./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b2136a9c10453b968eccf837dc70324a87bc3dbd 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-22 21:43:16,690 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-22 21:43:16,691 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-22 21:43:16,699 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-22 21:43:16,699 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-22 21:43:16,700 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-22 21:43:16,700 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-22 21:43:16,702 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-22 21:43:16,703 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-22 21:43:16,703 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-22 21:43:16,704 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-22 21:43:16,704 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-22 21:43:16,705 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-22 21:43:16,705 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-22 21:43:16,706 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-22 21:43:16,707 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-22 21:43:16,707 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-22 21:43:16,708 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-22 21:43:16,710 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-22 21:43:16,711 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-22 21:43:16,711 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-22 21:43:16,712 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-22 21:43:16,714 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-22 21:43:16,714 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-22 21:43:16,714 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-22 21:43:16,715 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-22 21:43:16,715 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-22 21:43:16,716 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-22 21:43:16,717 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-22 21:43:16,717 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-22 21:43:16,717 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-22 21:43:16,718 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-22 21:43:16,718 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-22 21:43:16,718 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-22 21:43:16,719 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-22 21:43:16,719 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-22 21:43:16,720 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-22 21:43:16,727 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-22 21:43:16,727 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-22 21:43:16,727 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-22 21:43:16,727 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-22 21:43:16,728 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-22 21:43:16,728 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-22 21:43:16,728 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-22 21:43:16,728 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-22 21:43:16,728 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-22 21:43:16,728 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-22 21:43:16,728 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-22 21:43:16,729 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-22 21:43:16,729 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-22 21:43:16,729 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-22 21:43:16,729 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-22 21:43:16,730 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-22 21:43:16,730 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-22 21:43:16,730 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-22 21:43:16,730 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-22 21:43:16,730 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-22 21:43:16,730 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-22 21:43:16,730 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-22 21:43:16,731 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-22 21:43:16,731 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-22 21:43:16,731 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-22 21:43:16,731 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-22 21:43:16,731 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-22 21:43:16,731 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-22 21:43:16,732 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-22 21:43:16,732 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 21:43:16,732 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-22 21:43:16,732 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-22 21:43:16,732 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-22 21:43:16,732 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-22 21:43:16,732 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-22 21:43:16,733 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-22 21:43:16,733 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-22 21:43:16,733 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b2136a9c10453b968eccf837dc70324a87bc3dbd [2018-11-22 21:43:16,757 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-22 21:43:16,766 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-22 21:43:16,768 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-22 21:43:16,769 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-22 21:43:16,770 INFO L276 PluginConnector]: CDTParser initialized [2018-11-22 21:43:16,770 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/../../sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i [2018-11-22 21:43:16,815 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/data/213608582/542ba8b0a4b94825bc0caafbe925225f/FLAG4866c3939 [2018-11-22 21:43:17,273 INFO L307 CDTParser]: Found 1 translation units. [2018-11-22 21:43:17,274 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i [2018-11-22 21:43:17,283 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/data/213608582/542ba8b0a4b94825bc0caafbe925225f/FLAG4866c3939 [2018-11-22 21:43:17,293 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/data/213608582/542ba8b0a4b94825bc0caafbe925225f [2018-11-22 21:43:17,295 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-22 21:43:17,296 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-22 21:43:17,296 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-22 21:43:17,296 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-22 21:43:17,299 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-22 21:43:17,299 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,301 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4d05c556 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17, skipping insertion in model container [2018-11-22 21:43:17,301 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,307 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-22 21:43:17,339 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-22 21:43:17,593 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 21:43:17,602 INFO L191 MainTranslator]: Completed pre-run [2018-11-22 21:43:17,687 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 21:43:17,728 INFO L195 MainTranslator]: Completed translation [2018-11-22 21:43:17,728 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17 WrapperNode [2018-11-22 21:43:17,728 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-22 21:43:17,729 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-22 21:43:17,729 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-22 21:43:17,729 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-22 21:43:17,736 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,746 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,762 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-22 21:43:17,762 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-22 21:43:17,762 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-22 21:43:17,762 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-22 21:43:17,768 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,768 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,772 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,772 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,779 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,782 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,784 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... [2018-11-22 21:43:17,786 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-22 21:43:17,786 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-22 21:43:17,786 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-22 21:43:17,786 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-22 21:43:17,787 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 21:43:17,828 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-22 21:43:17,829 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-22 21:43:17,829 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-22 21:43:17,829 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-22 21:43:17,829 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-22 21:43:17,829 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-22 21:43:17,829 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-22 21:43:17,829 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-22 21:43:17,830 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-22 21:43:17,831 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-22 21:43:17,831 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-22 21:43:17,831 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-22 21:43:17,831 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-22 21:43:17,832 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-22 21:43:18,374 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-22 21:43:18,374 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-22 21:43:18,375 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:43:18 BoogieIcfgContainer [2018-11-22 21:43:18,375 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-22 21:43:18,375 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-22 21:43:18,375 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-22 21:43:18,377 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-22 21:43:18,377 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.11 09:43:17" (1/3) ... [2018-11-22 21:43:18,378 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5964cbe4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 09:43:18, skipping insertion in model container [2018-11-22 21:43:18,378 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:43:17" (2/3) ... [2018-11-22 21:43:18,378 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5964cbe4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 09:43:18, skipping insertion in model container [2018-11-22 21:43:18,378 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:43:18" (3/3) ... [2018-11-22 21:43:18,379 INFO L112 eAbstractionObserver]: Analyzing ICFG safe006_power.opt_false-unreach-call.i [2018-11-22 21:43:18,406 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,407 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,407 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,407 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,407 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,407 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,407 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,408 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,408 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,408 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,408 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,408 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,408 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~mem3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,408 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,409 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,409 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~mem3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,411 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,411 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,411 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,411 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,412 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,412 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,412 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,412 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,412 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,412 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,412 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,413 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,413 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,413 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,413 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,413 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,413 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,413 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,414 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,414 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,414 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,414 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,414 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,414 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,415 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,415 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,416 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,416 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,416 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,416 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,416 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,416 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,416 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,417 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,418 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,418 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,418 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,418 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,418 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,419 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,420 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,420 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,420 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,420 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,420 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,421 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,421 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,421 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,421 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,421 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,421 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,421 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,422 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,422 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,422 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,422 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,422 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,423 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,423 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,423 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,423 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,423 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,423 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,424 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,424 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,424 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,424 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,424 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,424 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,424 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,425 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,425 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,425 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,425 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,425 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,425 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,425 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,426 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,426 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,426 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,426 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,426 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,426 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,427 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,427 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,427 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,427 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,427 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,427 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,428 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,428 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,428 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,428 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,428 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,428 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,429 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,429 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,429 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,429 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,429 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,429 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,429 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,430 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,430 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,430 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,430 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,430 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,430 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,432 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,433 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,433 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,433 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,433 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,433 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,433 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,433 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,436 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,437 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,441 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,441 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,441 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,441 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,441 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,441 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,442 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,442 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,442 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,442 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,442 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,442 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,443 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,443 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,443 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,443 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,443 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,443 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:43:18,468 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-22 21:43:18,468 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-22 21:43:18,477 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-22 21:43:18,488 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-22 21:43:18,505 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-22 21:43:18,506 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-22 21:43:18,506 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-22 21:43:18,506 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-22 21:43:18,506 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-22 21:43:18,506 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-22 21:43:18,506 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-22 21:43:18,506 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-22 21:43:18,516 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 200places, 259 transitions [2018-11-22 21:43:21,782 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 65314 states. [2018-11-22 21:43:21,783 INFO L276 IsEmpty]: Start isEmpty. Operand 65314 states. [2018-11-22 21:43:21,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-22 21:43:21,790 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:21,791 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:21,792 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:21,795 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:21,796 INFO L82 PathProgramCache]: Analyzing trace with hash -1016272846, now seen corresponding path program 1 times [2018-11-22 21:43:21,797 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:21,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:21,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:21,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:21,834 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:21,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:21,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:21,977 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:21,977 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:21,977 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:21,980 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:21,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:21,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:21,991 INFO L87 Difference]: Start difference. First operand 65314 states. Second operand 4 states. [2018-11-22 21:43:23,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:23,222 INFO L93 Difference]: Finished difference Result 113402 states and 445073 transitions. [2018-11-22 21:43:23,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 21:43:23,223 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-22 21:43:23,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:23,532 INFO L225 Difference]: With dead ends: 113402 [2018-11-22 21:43:23,532 INFO L226 Difference]: Without dead ends: 86242 [2018-11-22 21:43:23,533 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:23,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86242 states. [2018-11-22 21:43:25,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86242 to 53058. [2018-11-22 21:43:25,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53058 states. [2018-11-22 21:43:25,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53058 states to 53058 states and 208767 transitions. [2018-11-22 21:43:25,256 INFO L78 Accepts]: Start accepts. Automaton has 53058 states and 208767 transitions. Word has length 49 [2018-11-22 21:43:25,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:25,257 INFO L480 AbstractCegarLoop]: Abstraction has 53058 states and 208767 transitions. [2018-11-22 21:43:25,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:25,257 INFO L276 IsEmpty]: Start isEmpty. Operand 53058 states and 208767 transitions. [2018-11-22 21:43:25,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-22 21:43:25,264 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:25,264 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:25,264 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:25,265 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:25,265 INFO L82 PathProgramCache]: Analyzing trace with hash -267205330, now seen corresponding path program 1 times [2018-11-22 21:43:25,265 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:25,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:25,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:25,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:25,269 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:25,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:25,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:25,329 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:25,329 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:43:25,329 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:25,330 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:43:25,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:43:25,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:25,331 INFO L87 Difference]: Start difference. First operand 53058 states and 208767 transitions. Second operand 3 states. [2018-11-22 21:43:25,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:25,782 INFO L93 Difference]: Finished difference Result 53058 states and 208358 transitions. [2018-11-22 21:43:25,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:43:25,783 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2018-11-22 21:43:25,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:26,196 INFO L225 Difference]: With dead ends: 53058 [2018-11-22 21:43:26,196 INFO L226 Difference]: Without dead ends: 53058 [2018-11-22 21:43:26,197 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:26,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53058 states. [2018-11-22 21:43:26,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53058 to 53058. [2018-11-22 21:43:26,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53058 states. [2018-11-22 21:43:27,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53058 states to 53058 states and 208358 transitions. [2018-11-22 21:43:27,079 INFO L78 Accepts]: Start accepts. Automaton has 53058 states and 208358 transitions. Word has length 61 [2018-11-22 21:43:27,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:27,079 INFO L480 AbstractCegarLoop]: Abstraction has 53058 states and 208358 transitions. [2018-11-22 21:43:27,079 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:43:27,079 INFO L276 IsEmpty]: Start isEmpty. Operand 53058 states and 208358 transitions. [2018-11-22 21:43:27,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-22 21:43:27,082 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:27,082 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:27,083 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:27,083 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:27,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1475605005, now seen corresponding path program 1 times [2018-11-22 21:43:27,083 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:27,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:27,085 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:27,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:27,085 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:27,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:27,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:27,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:27,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:27,147 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:27,147 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:27,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:27,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:27,148 INFO L87 Difference]: Start difference. First operand 53058 states and 208358 transitions. Second operand 4 states. [2018-11-22 21:43:27,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:27,434 INFO L93 Difference]: Finished difference Result 14752 states and 50098 transitions. [2018-11-22 21:43:27,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:43:27,434 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 61 [2018-11-22 21:43:27,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:27,460 INFO L225 Difference]: With dead ends: 14752 [2018-11-22 21:43:27,460 INFO L226 Difference]: Without dead ends: 13006 [2018-11-22 21:43:27,461 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:27,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13006 states. [2018-11-22 21:43:27,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13006 to 13006. [2018-11-22 21:43:27,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13006 states. [2018-11-22 21:43:27,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13006 states to 13006 states and 43944 transitions. [2018-11-22 21:43:27,676 INFO L78 Accepts]: Start accepts. Automaton has 13006 states and 43944 transitions. Word has length 61 [2018-11-22 21:43:27,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:27,677 INFO L480 AbstractCegarLoop]: Abstraction has 13006 states and 43944 transitions. [2018-11-22 21:43:27,677 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:27,677 INFO L276 IsEmpty]: Start isEmpty. Operand 13006 states and 43944 transitions. [2018-11-22 21:43:27,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-22 21:43:27,678 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:27,678 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:27,679 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:27,679 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:27,679 INFO L82 PathProgramCache]: Analyzing trace with hash 1874201971, now seen corresponding path program 1 times [2018-11-22 21:43:27,679 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:27,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:27,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:27,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:27,681 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:27,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:27,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:27,799 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:27,799 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:43:27,799 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:27,799 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:43:27,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:43:27,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:27,800 INFO L87 Difference]: Start difference. First operand 13006 states and 43944 transitions. Second operand 6 states. [2018-11-22 21:43:28,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:28,194 INFO L93 Difference]: Finished difference Result 27890 states and 91756 transitions. [2018-11-22 21:43:28,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-22 21:43:28,195 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 62 [2018-11-22 21:43:28,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:28,236 INFO L225 Difference]: With dead ends: 27890 [2018-11-22 21:43:28,237 INFO L226 Difference]: Without dead ends: 27790 [2018-11-22 21:43:28,237 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2018-11-22 21:43:28,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27790 states. [2018-11-22 21:43:28,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27790 to 16773. [2018-11-22 21:43:28,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16773 states. [2018-11-22 21:43:28,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16773 states to 16773 states and 55428 transitions. [2018-11-22 21:43:28,479 INFO L78 Accepts]: Start accepts. Automaton has 16773 states and 55428 transitions. Word has length 62 [2018-11-22 21:43:28,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:28,480 INFO L480 AbstractCegarLoop]: Abstraction has 16773 states and 55428 transitions. [2018-11-22 21:43:28,480 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:43:28,480 INFO L276 IsEmpty]: Start isEmpty. Operand 16773 states and 55428 transitions. [2018-11-22 21:43:28,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-22 21:43:28,482 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:28,483 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:28,483 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:28,483 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:28,483 INFO L82 PathProgramCache]: Analyzing trace with hash -1781281892, now seen corresponding path program 1 times [2018-11-22 21:43:28,483 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:28,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:28,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:28,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:28,485 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:28,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:28,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:28,527 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:28,527 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:43:28,527 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:28,527 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:43:28,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:43:28,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:28,528 INFO L87 Difference]: Start difference. First operand 16773 states and 55428 transitions. Second operand 3 states. [2018-11-22 21:43:28,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:28,607 INFO L93 Difference]: Finished difference Result 23727 states and 77133 transitions. [2018-11-22 21:43:28,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:43:28,608 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2018-11-22 21:43:28,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:28,635 INFO L225 Difference]: With dead ends: 23727 [2018-11-22 21:43:28,636 INFO L226 Difference]: Without dead ends: 23727 [2018-11-22 21:43:28,636 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:28,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23727 states. [2018-11-22 21:43:28,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23727 to 18701. [2018-11-22 21:43:28,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18701 states. [2018-11-22 21:43:28,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18701 states to 18701 states and 60885 transitions. [2018-11-22 21:43:28,851 INFO L78 Accepts]: Start accepts. Automaton has 18701 states and 60885 transitions. Word has length 64 [2018-11-22 21:43:28,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:28,852 INFO L480 AbstractCegarLoop]: Abstraction has 18701 states and 60885 transitions. [2018-11-22 21:43:28,852 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:43:28,852 INFO L276 IsEmpty]: Start isEmpty. Operand 18701 states and 60885 transitions. [2018-11-22 21:43:28,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 21:43:28,855 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:28,855 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:28,855 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:28,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:28,856 INFO L82 PathProgramCache]: Analyzing trace with hash -571649263, now seen corresponding path program 1 times [2018-11-22 21:43:28,856 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:28,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:28,858 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:28,858 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:28,858 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:28,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:28,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:28,983 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:28,983 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-22 21:43:28,983 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:28,984 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-22 21:43:28,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-22 21:43:28,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-11-22 21:43:28,984 INFO L87 Difference]: Start difference. First operand 18701 states and 60885 transitions. Second operand 10 states. [2018-11-22 21:43:29,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:29,901 INFO L93 Difference]: Finished difference Result 26205 states and 83034 transitions. [2018-11-22 21:43:29,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-22 21:43:29,901 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 68 [2018-11-22 21:43:29,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:29,934 INFO L225 Difference]: With dead ends: 26205 [2018-11-22 21:43:29,934 INFO L226 Difference]: Without dead ends: 26086 [2018-11-22 21:43:29,935 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=200, Invalid=556, Unknown=0, NotChecked=0, Total=756 [2018-11-22 21:43:29,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26086 states. [2018-11-22 21:43:30,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26086 to 20328. [2018-11-22 21:43:30,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20328 states. [2018-11-22 21:43:30,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20328 states to 20328 states and 65644 transitions. [2018-11-22 21:43:30,261 INFO L78 Accepts]: Start accepts. Automaton has 20328 states and 65644 transitions. Word has length 68 [2018-11-22 21:43:30,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:30,261 INFO L480 AbstractCegarLoop]: Abstraction has 20328 states and 65644 transitions. [2018-11-22 21:43:30,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-22 21:43:30,261 INFO L276 IsEmpty]: Start isEmpty. Operand 20328 states and 65644 transitions. [2018-11-22 21:43:30,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-22 21:43:30,268 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:30,268 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:30,268 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:30,268 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:30,268 INFO L82 PathProgramCache]: Analyzing trace with hash 1407972401, now seen corresponding path program 1 times [2018-11-22 21:43:30,268 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:30,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:30,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:30,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:30,270 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:30,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:30,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:30,329 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:30,329 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:30,329 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:30,329 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:30,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:30,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:30,330 INFO L87 Difference]: Start difference. First operand 20328 states and 65644 transitions. Second operand 4 states. [2018-11-22 21:43:30,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:30,475 INFO L93 Difference]: Finished difference Result 22000 states and 70954 transitions. [2018-11-22 21:43:30,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:43:30,475 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2018-11-22 21:43:30,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:30,500 INFO L225 Difference]: With dead ends: 22000 [2018-11-22 21:43:30,500 INFO L226 Difference]: Without dead ends: 22000 [2018-11-22 21:43:30,501 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:30,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22000 states. [2018-11-22 21:43:30,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22000 to 21472. [2018-11-22 21:43:30,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21472 states. [2018-11-22 21:43:30,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21472 states to 21472 states and 69230 transitions. [2018-11-22 21:43:30,721 INFO L78 Accepts]: Start accepts. Automaton has 21472 states and 69230 transitions. Word has length 76 [2018-11-22 21:43:30,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:30,722 INFO L480 AbstractCegarLoop]: Abstraction has 21472 states and 69230 transitions. [2018-11-22 21:43:30,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:30,722 INFO L276 IsEmpty]: Start isEmpty. Operand 21472 states and 69230 transitions. [2018-11-22 21:43:30,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-22 21:43:30,726 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:30,726 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:30,727 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:30,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:30,727 INFO L82 PathProgramCache]: Analyzing trace with hash -1144184560, now seen corresponding path program 1 times [2018-11-22 21:43:30,727 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:30,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:30,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:30,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:30,729 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:30,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:30,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:30,820 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:30,820 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 21:43:30,820 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:30,820 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 21:43:30,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 21:43:30,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:30,821 INFO L87 Difference]: Start difference. First operand 21472 states and 69230 transitions. Second operand 7 states. [2018-11-22 21:43:31,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:31,348 INFO L93 Difference]: Finished difference Result 37517 states and 120136 transitions. [2018-11-22 21:43:31,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-22 21:43:31,349 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 76 [2018-11-22 21:43:31,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:31,393 INFO L225 Difference]: With dead ends: 37517 [2018-11-22 21:43:31,393 INFO L226 Difference]: Without dead ends: 37446 [2018-11-22 21:43:31,393 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-11-22 21:43:31,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37446 states. [2018-11-22 21:43:31,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37446 to 24138. [2018-11-22 21:43:31,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24138 states. [2018-11-22 21:43:31,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24138 states to 24138 states and 77250 transitions. [2018-11-22 21:43:31,702 INFO L78 Accepts]: Start accepts. Automaton has 24138 states and 77250 transitions. Word has length 76 [2018-11-22 21:43:31,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:31,702 INFO L480 AbstractCegarLoop]: Abstraction has 24138 states and 77250 transitions. [2018-11-22 21:43:31,702 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 21:43:31,702 INFO L276 IsEmpty]: Start isEmpty. Operand 24138 states and 77250 transitions. [2018-11-22 21:43:31,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-22 21:43:31,710 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:31,710 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:31,710 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:31,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:31,710 INFO L82 PathProgramCache]: Analyzing trace with hash -457594562, now seen corresponding path program 1 times [2018-11-22 21:43:31,710 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:31,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:31,712 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:31,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:31,712 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:31,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:31,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:31,757 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:31,757 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:43:31,757 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:31,758 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:43:31,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:43:31,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:31,758 INFO L87 Difference]: Start difference. First operand 24138 states and 77250 transitions. Second operand 3 states. [2018-11-22 21:43:31,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:31,963 INFO L93 Difference]: Finished difference Result 25009 states and 79558 transitions. [2018-11-22 21:43:31,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:43:31,964 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 82 [2018-11-22 21:43:31,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:31,992 INFO L225 Difference]: With dead ends: 25009 [2018-11-22 21:43:31,993 INFO L226 Difference]: Without dead ends: 25009 [2018-11-22 21:43:31,993 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:32,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25009 states. [2018-11-22 21:43:32,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25009 to 24700. [2018-11-22 21:43:32,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24700 states. [2018-11-22 21:43:32,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24700 states to 24700 states and 78706 transitions. [2018-11-22 21:43:32,305 INFO L78 Accepts]: Start accepts. Automaton has 24700 states and 78706 transitions. Word has length 82 [2018-11-22 21:43:32,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:32,305 INFO L480 AbstractCegarLoop]: Abstraction has 24700 states and 78706 transitions. [2018-11-22 21:43:32,305 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:43:32,305 INFO L276 IsEmpty]: Start isEmpty. Operand 24700 states and 78706 transitions. [2018-11-22 21:43:32,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-22 21:43:32,313 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:32,314 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:32,314 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:32,314 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:32,314 INFO L82 PathProgramCache]: Analyzing trace with hash -1806342675, now seen corresponding path program 1 times [2018-11-22 21:43:32,314 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:32,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:32,315 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:32,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:32,315 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:32,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:32,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:32,387 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:32,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:32,387 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:32,387 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:32,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:32,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:32,388 INFO L87 Difference]: Start difference. First operand 24700 states and 78706 transitions. Second operand 4 states. [2018-11-22 21:43:32,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:32,646 INFO L93 Difference]: Finished difference Result 32283 states and 100846 transitions. [2018-11-22 21:43:32,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 21:43:32,647 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 82 [2018-11-22 21:43:32,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:32,683 INFO L225 Difference]: With dead ends: 32283 [2018-11-22 21:43:32,683 INFO L226 Difference]: Without dead ends: 32283 [2018-11-22 21:43:32,683 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:32,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32283 states. [2018-11-22 21:43:32,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32283 to 28601. [2018-11-22 21:43:32,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28601 states. [2018-11-22 21:43:32,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28601 states to 28601 states and 90017 transitions. [2018-11-22 21:43:32,988 INFO L78 Accepts]: Start accepts. Automaton has 28601 states and 90017 transitions. Word has length 82 [2018-11-22 21:43:32,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:32,989 INFO L480 AbstractCegarLoop]: Abstraction has 28601 states and 90017 transitions. [2018-11-22 21:43:32,989 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:32,989 INFO L276 IsEmpty]: Start isEmpty. Operand 28601 states and 90017 transitions. [2018-11-22 21:43:33,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 21:43:33,000 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:33,000 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:33,000 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:33,001 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:33,001 INFO L82 PathProgramCache]: Analyzing trace with hash 1307367553, now seen corresponding path program 1 times [2018-11-22 21:43:33,001 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:33,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:33,002 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:33,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:33,002 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:33,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:33,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:33,072 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:33,072 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:43:33,072 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:33,072 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:43:33,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:43:33,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:33,073 INFO L87 Difference]: Start difference. First operand 28601 states and 90017 transitions. Second operand 6 states. [2018-11-22 21:43:33,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:33,853 INFO L93 Difference]: Finished difference Result 37655 states and 116057 transitions. [2018-11-22 21:43:33,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:43:33,854 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 84 [2018-11-22 21:43:33,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:33,896 INFO L225 Difference]: With dead ends: 37655 [2018-11-22 21:43:33,896 INFO L226 Difference]: Without dead ends: 37600 [2018-11-22 21:43:33,897 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:33,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37600 states. [2018-11-22 21:43:34,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37600 to 31640. [2018-11-22 21:43:34,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31640 states. [2018-11-22 21:43:34,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31640 states to 31640 states and 98637 transitions. [2018-11-22 21:43:34,238 INFO L78 Accepts]: Start accepts. Automaton has 31640 states and 98637 transitions. Word has length 84 [2018-11-22 21:43:34,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:34,238 INFO L480 AbstractCegarLoop]: Abstraction has 31640 states and 98637 transitions. [2018-11-22 21:43:34,238 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:43:34,238 INFO L276 IsEmpty]: Start isEmpty. Operand 31640 states and 98637 transitions. [2018-11-22 21:43:34,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 21:43:34,250 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:34,250 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:34,251 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:34,251 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:34,251 INFO L82 PathProgramCache]: Analyzing trace with hash -2025985726, now seen corresponding path program 1 times [2018-11-22 21:43:34,251 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:34,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:34,252 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:34,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:34,253 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:34,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:34,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:34,357 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:34,357 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:43:34,357 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:34,358 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:43:34,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:43:34,358 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:34,358 INFO L87 Difference]: Start difference. First operand 31640 states and 98637 transitions. Second operand 6 states. [2018-11-22 21:43:34,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:34,775 INFO L93 Difference]: Finished difference Result 35112 states and 106384 transitions. [2018-11-22 21:43:34,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 21:43:34,776 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 84 [2018-11-22 21:43:34,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:34,821 INFO L225 Difference]: With dead ends: 35112 [2018-11-22 21:43:34,822 INFO L226 Difference]: Without dead ends: 35112 [2018-11-22 21:43:34,822 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-22 21:43:34,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35112 states. [2018-11-22 21:43:35,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35112 to 32373. [2018-11-22 21:43:35,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32373 states. [2018-11-22 21:43:35,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32373 states to 32373 states and 99374 transitions. [2018-11-22 21:43:35,305 INFO L78 Accepts]: Start accepts. Automaton has 32373 states and 99374 transitions. Word has length 84 [2018-11-22 21:43:35,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:35,305 INFO L480 AbstractCegarLoop]: Abstraction has 32373 states and 99374 transitions. [2018-11-22 21:43:35,305 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:43:35,305 INFO L276 IsEmpty]: Start isEmpty. Operand 32373 states and 99374 transitions. [2018-11-22 21:43:35,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 21:43:35,318 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:35,318 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:35,318 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:35,318 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:35,318 INFO L82 PathProgramCache]: Analyzing trace with hash -781221245, now seen corresponding path program 1 times [2018-11-22 21:43:35,318 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:35,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:35,319 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:35,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:35,319 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:35,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:35,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:35,375 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:35,375 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:35,375 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:35,375 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:35,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:35,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:35,376 INFO L87 Difference]: Start difference. First operand 32373 states and 99374 transitions. Second operand 5 states. [2018-11-22 21:43:35,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:35,728 INFO L93 Difference]: Finished difference Result 39225 states and 118481 transitions. [2018-11-22 21:43:35,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:43:35,729 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-11-22 21:43:35,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:35,771 INFO L225 Difference]: With dead ends: 39225 [2018-11-22 21:43:35,771 INFO L226 Difference]: Without dead ends: 39225 [2018-11-22 21:43:35,771 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:35,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39225 states. [2018-11-22 21:43:36,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39225 to 35801. [2018-11-22 21:43:36,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35801 states. [2018-11-22 21:43:36,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35801 states to 35801 states and 108276 transitions. [2018-11-22 21:43:36,135 INFO L78 Accepts]: Start accepts. Automaton has 35801 states and 108276 transitions. Word has length 84 [2018-11-22 21:43:36,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:36,135 INFO L480 AbstractCegarLoop]: Abstraction has 35801 states and 108276 transitions. [2018-11-22 21:43:36,135 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:36,135 INFO L276 IsEmpty]: Start isEmpty. Operand 35801 states and 108276 transitions. [2018-11-22 21:43:36,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 21:43:36,147 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:36,147 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:36,147 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:36,147 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:36,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1778293598, now seen corresponding path program 1 times [2018-11-22 21:43:36,147 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:36,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:36,148 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:36,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:36,148 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:36,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:36,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:36,217 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:36,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:36,217 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:36,217 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:36,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:36,218 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:36,218 INFO L87 Difference]: Start difference. First operand 35801 states and 108276 transitions. Second operand 5 states. [2018-11-22 21:43:36,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:36,861 INFO L93 Difference]: Finished difference Result 53698 states and 161639 transitions. [2018-11-22 21:43:36,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:43:36,862 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-11-22 21:43:36,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:36,950 INFO L225 Difference]: With dead ends: 53698 [2018-11-22 21:43:36,950 INFO L226 Difference]: Without dead ends: 53698 [2018-11-22 21:43:36,951 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:43:37,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53698 states. [2018-11-22 21:43:37,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53698 to 45753. [2018-11-22 21:43:37,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45753 states. [2018-11-22 21:43:37,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45753 states to 45753 states and 137727 transitions. [2018-11-22 21:43:37,600 INFO L78 Accepts]: Start accepts. Automaton has 45753 states and 137727 transitions. Word has length 84 [2018-11-22 21:43:37,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:37,600 INFO L480 AbstractCegarLoop]: Abstraction has 45753 states and 137727 transitions. [2018-11-22 21:43:37,600 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:37,601 INFO L276 IsEmpty]: Start isEmpty. Operand 45753 states and 137727 transitions. [2018-11-22 21:43:37,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 21:43:37,614 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:37,614 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:37,614 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:37,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:37,614 INFO L82 PathProgramCache]: Analyzing trace with hash 719722339, now seen corresponding path program 1 times [2018-11-22 21:43:37,614 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:37,615 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:37,616 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:37,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:37,616 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:37,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:37,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:37,686 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:37,686 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:37,686 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:37,686 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:37,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:37,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:37,686 INFO L87 Difference]: Start difference. First operand 45753 states and 137727 transitions. Second operand 4 states. [2018-11-22 21:43:38,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:38,571 INFO L93 Difference]: Finished difference Result 60113 states and 180825 transitions. [2018-11-22 21:43:38,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:43:38,572 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 84 [2018-11-22 21:43:38,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:38,675 INFO L225 Difference]: With dead ends: 60113 [2018-11-22 21:43:38,675 INFO L226 Difference]: Without dead ends: 59685 [2018-11-22 21:43:38,675 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:38,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59685 states. [2018-11-22 21:43:39,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59685 to 55877. [2018-11-22 21:43:39,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55877 states. [2018-11-22 21:43:39,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55877 states to 55877 states and 168476 transitions. [2018-11-22 21:43:39,401 INFO L78 Accepts]: Start accepts. Automaton has 55877 states and 168476 transitions. Word has length 84 [2018-11-22 21:43:39,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:39,401 INFO L480 AbstractCegarLoop]: Abstraction has 55877 states and 168476 transitions. [2018-11-22 21:43:39,401 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:39,401 INFO L276 IsEmpty]: Start isEmpty. Operand 55877 states and 168476 transitions. [2018-11-22 21:43:39,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 21:43:39,416 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:39,416 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:39,416 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:39,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:39,417 INFO L82 PathProgramCache]: Analyzing trace with hash 426319332, now seen corresponding path program 1 times [2018-11-22 21:43:39,417 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:39,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:39,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:39,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:39,418 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:39,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:39,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:39,460 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:39,460 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:39,460 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:39,460 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:39,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:39,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:39,461 INFO L87 Difference]: Start difference. First operand 55877 states and 168476 transitions. Second operand 5 states. [2018-11-22 21:43:39,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:39,509 INFO L93 Difference]: Finished difference Result 12621 states and 29962 transitions. [2018-11-22 21:43:39,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:43:39,510 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-11-22 21:43:39,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:39,518 INFO L225 Difference]: With dead ends: 12621 [2018-11-22 21:43:39,518 INFO L226 Difference]: Without dead ends: 10165 [2018-11-22 21:43:39,518 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:39,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10165 states. [2018-11-22 21:43:39,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10165 to 8860. [2018-11-22 21:43:39,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8860 states. [2018-11-22 21:43:39,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8860 states to 8860 states and 20404 transitions. [2018-11-22 21:43:39,595 INFO L78 Accepts]: Start accepts. Automaton has 8860 states and 20404 transitions. Word has length 84 [2018-11-22 21:43:39,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:39,595 INFO L480 AbstractCegarLoop]: Abstraction has 8860 states and 20404 transitions. [2018-11-22 21:43:39,596 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:39,596 INFO L276 IsEmpty]: Start isEmpty. Operand 8860 states and 20404 transitions. [2018-11-22 21:43:39,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-11-22 21:43:39,601 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:39,601 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:39,601 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:39,601 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:39,601 INFO L82 PathProgramCache]: Analyzing trace with hash -371203702, now seen corresponding path program 1 times [2018-11-22 21:43:39,601 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:39,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:39,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:39,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:39,603 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:39,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:39,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:39,646 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:39,646 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:39,646 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:39,646 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:39,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:39,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:39,646 INFO L87 Difference]: Start difference. First operand 8860 states and 20404 transitions. Second operand 5 states. [2018-11-22 21:43:39,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:39,747 INFO L93 Difference]: Finished difference Result 10299 states and 23671 transitions. [2018-11-22 21:43:39,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 21:43:39,748 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 88 [2018-11-22 21:43:39,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:39,755 INFO L225 Difference]: With dead ends: 10299 [2018-11-22 21:43:39,755 INFO L226 Difference]: Without dead ends: 10299 [2018-11-22 21:43:39,755 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-22 21:43:39,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10299 states. [2018-11-22 21:43:39,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10299 to 9297. [2018-11-22 21:43:39,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9297 states. [2018-11-22 21:43:39,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9297 states to 9297 states and 21406 transitions. [2018-11-22 21:43:39,825 INFO L78 Accepts]: Start accepts. Automaton has 9297 states and 21406 transitions. Word has length 88 [2018-11-22 21:43:39,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:39,825 INFO L480 AbstractCegarLoop]: Abstraction has 9297 states and 21406 transitions. [2018-11-22 21:43:39,825 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:39,825 INFO L276 IsEmpty]: Start isEmpty. Operand 9297 states and 21406 transitions. [2018-11-22 21:43:39,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-11-22 21:43:39,831 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:39,831 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:39,831 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:39,831 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:39,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1371606633, now seen corresponding path program 1 times [2018-11-22 21:43:39,831 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:39,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:39,833 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:39,833 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:39,833 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:39,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:39,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:39,919 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:39,919 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:39,919 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:39,919 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:39,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:39,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:39,920 INFO L87 Difference]: Start difference. First operand 9297 states and 21406 transitions. Second operand 5 states. [2018-11-22 21:43:39,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:39,963 INFO L93 Difference]: Finished difference Result 12160 states and 27850 transitions. [2018-11-22 21:43:39,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:43:39,963 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 88 [2018-11-22 21:43:39,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:39,972 INFO L225 Difference]: With dead ends: 12160 [2018-11-22 21:43:39,972 INFO L226 Difference]: Without dead ends: 12079 [2018-11-22 21:43:39,972 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:39,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12079 states. [2018-11-22 21:43:40,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12079 to 8791. [2018-11-22 21:43:40,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8791 states. [2018-11-22 21:43:40,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8791 states to 8791 states and 19961 transitions. [2018-11-22 21:43:40,069 INFO L78 Accepts]: Start accepts. Automaton has 8791 states and 19961 transitions. Word has length 88 [2018-11-22 21:43:40,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:40,069 INFO L480 AbstractCegarLoop]: Abstraction has 8791 states and 19961 transitions. [2018-11-22 21:43:40,069 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:40,069 INFO L276 IsEmpty]: Start isEmpty. Operand 8791 states and 19961 transitions. [2018-11-22 21:43:40,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-11-22 21:43:40,074 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:40,074 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:40,074 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:40,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:40,075 INFO L82 PathProgramCache]: Analyzing trace with hash -425344726, now seen corresponding path program 1 times [2018-11-22 21:43:40,075 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:40,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:40,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:40,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:40,076 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:40,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:40,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:40,157 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:40,157 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 21:43:40,157 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:40,157 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 21:43:40,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 21:43:40,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:40,158 INFO L87 Difference]: Start difference. First operand 8791 states and 19961 transitions. Second operand 7 states. [2018-11-22 21:43:40,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:40,468 INFO L93 Difference]: Finished difference Result 13227 states and 30329 transitions. [2018-11-22 21:43:40,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-22 21:43:40,468 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 88 [2018-11-22 21:43:40,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:40,477 INFO L225 Difference]: With dead ends: 13227 [2018-11-22 21:43:40,477 INFO L226 Difference]: Without dead ends: 13108 [2018-11-22 21:43:40,477 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 9 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=106, Invalid=236, Unknown=0, NotChecked=0, Total=342 [2018-11-22 21:43:40,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13108 states. [2018-11-22 21:43:40,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13108 to 8754. [2018-11-22 21:43:40,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8754 states. [2018-11-22 21:43:40,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8754 states to 8754 states and 19814 transitions. [2018-11-22 21:43:40,556 INFO L78 Accepts]: Start accepts. Automaton has 8754 states and 19814 transitions. Word has length 88 [2018-11-22 21:43:40,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:40,556 INFO L480 AbstractCegarLoop]: Abstraction has 8754 states and 19814 transitions. [2018-11-22 21:43:40,556 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 21:43:40,556 INFO L276 IsEmpty]: Start isEmpty. Operand 8754 states and 19814 transitions. [2018-11-22 21:43:40,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-22 21:43:40,562 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:40,562 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:40,562 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:40,562 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:40,562 INFO L82 PathProgramCache]: Analyzing trace with hash -1024178531, now seen corresponding path program 1 times [2018-11-22 21:43:40,562 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:40,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:40,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:40,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:40,563 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:40,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:40,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:40,615 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:40,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:40,615 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:40,615 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:40,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:40,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:40,616 INFO L87 Difference]: Start difference. First operand 8754 states and 19814 transitions. Second operand 4 states. [2018-11-22 21:43:40,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:40,803 INFO L93 Difference]: Finished difference Result 12754 states and 28548 transitions. [2018-11-22 21:43:40,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 21:43:40,803 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-22 21:43:40,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:40,812 INFO L225 Difference]: With dead ends: 12754 [2018-11-22 21:43:40,812 INFO L226 Difference]: Without dead ends: 12754 [2018-11-22 21:43:40,812 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:40,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12754 states. [2018-11-22 21:43:40,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12754 to 10443. [2018-11-22 21:43:40,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10443 states. [2018-11-22 21:43:40,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10443 states to 10443 states and 23241 transitions. [2018-11-22 21:43:40,898 INFO L78 Accepts]: Start accepts. Automaton has 10443 states and 23241 transitions. Word has length 109 [2018-11-22 21:43:40,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:40,898 INFO L480 AbstractCegarLoop]: Abstraction has 10443 states and 23241 transitions. [2018-11-22 21:43:40,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:40,898 INFO L276 IsEmpty]: Start isEmpty. Operand 10443 states and 23241 transitions. [2018-11-22 21:43:40,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-22 21:43:40,905 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:40,905 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:40,905 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:40,905 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:40,905 INFO L82 PathProgramCache]: Analyzing trace with hash -974628703, now seen corresponding path program 2 times [2018-11-22 21:43:40,905 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:40,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:40,906 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:40,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:40,906 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:40,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:40,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:40,957 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:40,957 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:40,957 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:40,957 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:40,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:40,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:40,957 INFO L87 Difference]: Start difference. First operand 10443 states and 23241 transitions. Second operand 4 states. [2018-11-22 21:43:41,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:41,144 INFO L93 Difference]: Finished difference Result 10520 states and 23305 transitions. [2018-11-22 21:43:41,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 21:43:41,145 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-22 21:43:41,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:41,152 INFO L225 Difference]: With dead ends: 10520 [2018-11-22 21:43:41,152 INFO L226 Difference]: Without dead ends: 10520 [2018-11-22 21:43:41,153 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:41,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10520 states. [2018-11-22 21:43:41,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10520 to 10013. [2018-11-22 21:43:41,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10013 states. [2018-11-22 21:43:41,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10013 states to 10013 states and 22206 transitions. [2018-11-22 21:43:41,232 INFO L78 Accepts]: Start accepts. Automaton has 10013 states and 22206 transitions. Word has length 109 [2018-11-22 21:43:41,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:41,232 INFO L480 AbstractCegarLoop]: Abstraction has 10013 states and 22206 transitions. [2018-11-22 21:43:41,232 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:41,232 INFO L276 IsEmpty]: Start isEmpty. Operand 10013 states and 22206 transitions. [2018-11-22 21:43:41,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-22 21:43:41,239 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:41,239 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:41,240 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:41,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:41,240 INFO L82 PathProgramCache]: Analyzing trace with hash -925297252, now seen corresponding path program 1 times [2018-11-22 21:43:41,240 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:41,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:41,241 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:43:41,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:41,241 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:41,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:41,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:41,284 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:41,284 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:41,284 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:41,284 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:41,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:41,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:41,285 INFO L87 Difference]: Start difference. First operand 10013 states and 22206 transitions. Second operand 4 states. [2018-11-22 21:43:41,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:41,359 INFO L93 Difference]: Finished difference Result 10519 states and 23181 transitions. [2018-11-22 21:43:41,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 21:43:41,360 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-22 21:43:41,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:41,367 INFO L225 Difference]: With dead ends: 10519 [2018-11-22 21:43:41,368 INFO L226 Difference]: Without dead ends: 10519 [2018-11-22 21:43:41,368 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:41,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10519 states. [2018-11-22 21:43:41,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10519 to 9946. [2018-11-22 21:43:41,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9946 states. [2018-11-22 21:43:41,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9946 states to 9946 states and 21984 transitions. [2018-11-22 21:43:41,445 INFO L78 Accepts]: Start accepts. Automaton has 9946 states and 21984 transitions. Word has length 109 [2018-11-22 21:43:41,445 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:41,445 INFO L480 AbstractCegarLoop]: Abstraction has 9946 states and 21984 transitions. [2018-11-22 21:43:41,445 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:41,445 INFO L276 IsEmpty]: Start isEmpty. Operand 9946 states and 21984 transitions. [2018-11-22 21:43:41,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-22 21:43:41,452 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:41,452 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:41,452 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:41,453 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:41,453 INFO L82 PathProgramCache]: Analyzing trace with hash 2126539237, now seen corresponding path program 1 times [2018-11-22 21:43:41,453 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:41,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:41,454 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:41,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:41,454 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:41,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:41,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:41,512 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:41,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:41,512 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:41,513 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:41,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:41,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:41,515 INFO L87 Difference]: Start difference. First operand 9946 states and 21984 transitions. Second operand 5 states. [2018-11-22 21:43:41,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:41,742 INFO L93 Difference]: Finished difference Result 12974 states and 28550 transitions. [2018-11-22 21:43:41,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:43:41,743 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2018-11-22 21:43:41,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:41,756 INFO L225 Difference]: With dead ends: 12974 [2018-11-22 21:43:41,757 INFO L226 Difference]: Without dead ends: 12974 [2018-11-22 21:43:41,758 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:43:41,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12974 states. [2018-11-22 21:43:41,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12974 to 10352. [2018-11-22 21:43:41,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10352 states. [2018-11-22 21:43:41,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10352 states to 10352 states and 22841 transitions. [2018-11-22 21:43:41,877 INFO L78 Accepts]: Start accepts. Automaton has 10352 states and 22841 transitions. Word has length 111 [2018-11-22 21:43:41,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:41,877 INFO L480 AbstractCegarLoop]: Abstraction has 10352 states and 22841 transitions. [2018-11-22 21:43:41,878 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:41,878 INFO L276 IsEmpty]: Start isEmpty. Operand 10352 states and 22841 transitions. [2018-11-22 21:43:41,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-22 21:43:41,885 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:41,885 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:41,885 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:41,886 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:41,886 INFO L82 PathProgramCache]: Analyzing trace with hash 2137855364, now seen corresponding path program 1 times [2018-11-22 21:43:41,886 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:41,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:41,887 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:41,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:41,887 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:41,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:41,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:41,947 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:41,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:41,947 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:41,948 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:41,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:41,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:41,948 INFO L87 Difference]: Start difference. First operand 10352 states and 22841 transitions. Second operand 5 states. [2018-11-22 21:43:42,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:42,297 INFO L93 Difference]: Finished difference Result 17041 states and 38055 transitions. [2018-11-22 21:43:42,297 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:43:42,297 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2018-11-22 21:43:42,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:42,308 INFO L225 Difference]: With dead ends: 17041 [2018-11-22 21:43:42,308 INFO L226 Difference]: Without dead ends: 17041 [2018-11-22 21:43:42,308 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:42,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17041 states. [2018-11-22 21:43:42,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17041 to 11201. [2018-11-22 21:43:42,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11201 states. [2018-11-22 21:43:42,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11201 states to 11201 states and 24621 transitions. [2018-11-22 21:43:42,427 INFO L78 Accepts]: Start accepts. Automaton has 11201 states and 24621 transitions. Word has length 111 [2018-11-22 21:43:42,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:42,427 INFO L480 AbstractCegarLoop]: Abstraction has 11201 states and 24621 transitions. [2018-11-22 21:43:42,427 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:42,428 INFO L276 IsEmpty]: Start isEmpty. Operand 11201 states and 24621 transitions. [2018-11-22 21:43:42,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-22 21:43:42,436 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:42,436 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:42,437 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:42,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:42,437 INFO L82 PathProgramCache]: Analyzing trace with hash 60646021, now seen corresponding path program 1 times [2018-11-22 21:43:42,437 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:42,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:42,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:42,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:42,438 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:42,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:42,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:42,537 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:42,537 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-22 21:43:42,537 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:42,537 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 21:43:42,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 21:43:42,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:43:42,538 INFO L87 Difference]: Start difference. First operand 11201 states and 24621 transitions. Second operand 8 states. [2018-11-22 21:43:42,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:42,901 INFO L93 Difference]: Finished difference Result 14428 states and 31675 transitions. [2018-11-22 21:43:42,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-22 21:43:42,901 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 111 [2018-11-22 21:43:42,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:42,911 INFO L225 Difference]: With dead ends: 14428 [2018-11-22 21:43:42,911 INFO L226 Difference]: Without dead ends: 14396 [2018-11-22 21:43:42,911 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2018-11-22 21:43:42,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14396 states. [2018-11-22 21:43:43,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14396 to 12605. [2018-11-22 21:43:43,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12605 states. [2018-11-22 21:43:43,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12605 states to 12605 states and 27658 transitions. [2018-11-22 21:43:43,027 INFO L78 Accepts]: Start accepts. Automaton has 12605 states and 27658 transitions. Word has length 111 [2018-11-22 21:43:43,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:43,027 INFO L480 AbstractCegarLoop]: Abstraction has 12605 states and 27658 transitions. [2018-11-22 21:43:43,027 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 21:43:43,027 INFO L276 IsEmpty]: Start isEmpty. Operand 12605 states and 27658 transitions. [2018-11-22 21:43:43,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-22 21:43:43,038 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:43,039 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:43,039 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:43,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:43,039 INFO L82 PathProgramCache]: Analyzing trace with hash -232756986, now seen corresponding path program 1 times [2018-11-22 21:43:43,039 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:43,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:43,040 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:43,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:43,040 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:43,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:43,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:43,127 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:43,128 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-22 21:43:43,128 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:43,128 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 21:43:43,128 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 21:43:43,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:43:43,129 INFO L87 Difference]: Start difference. First operand 12605 states and 27658 transitions. Second operand 8 states. [2018-11-22 21:43:43,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:43,514 INFO L93 Difference]: Finished difference Result 20154 states and 45274 transitions. [2018-11-22 21:43:43,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-22 21:43:43,515 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 111 [2018-11-22 21:43:43,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:43,529 INFO L225 Difference]: With dead ends: 20154 [2018-11-22 21:43:43,529 INFO L226 Difference]: Without dead ends: 20154 [2018-11-22 21:43:43,530 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-11-22 21:43:43,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20154 states. [2018-11-22 21:43:43,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20154 to 14019. [2018-11-22 21:43:43,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14019 states. [2018-11-22 21:43:43,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14019 states to 14019 states and 31052 transitions. [2018-11-22 21:43:43,703 INFO L78 Accepts]: Start accepts. Automaton has 14019 states and 31052 transitions. Word has length 111 [2018-11-22 21:43:43,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:43,704 INFO L480 AbstractCegarLoop]: Abstraction has 14019 states and 31052 transitions. [2018-11-22 21:43:43,704 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 21:43:43,704 INFO L276 IsEmpty]: Start isEmpty. Operand 14019 states and 31052 transitions. [2018-11-22 21:43:43,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-22 21:43:43,713 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:43,713 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:43,714 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:43,714 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:43,714 INFO L82 PathProgramCache]: Analyzing trace with hash -2040211449, now seen corresponding path program 1 times [2018-11-22 21:43:43,714 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:43,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:43,715 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:43,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:43,715 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:43,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:43,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:43,792 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:43,792 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:43:43,793 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:43,793 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:43:43,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:43:43,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:43,793 INFO L87 Difference]: Start difference. First operand 14019 states and 31052 transitions. Second operand 6 states. [2018-11-22 21:43:43,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:43,843 INFO L93 Difference]: Finished difference Result 17132 states and 38017 transitions. [2018-11-22 21:43:43,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:43:43,843 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 111 [2018-11-22 21:43:43,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:43,854 INFO L225 Difference]: With dead ends: 17132 [2018-11-22 21:43:43,854 INFO L226 Difference]: Without dead ends: 17132 [2018-11-22 21:43:43,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:43,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17132 states. [2018-11-22 21:43:43,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17132 to 14207. [2018-11-22 21:43:43,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14207 states. [2018-11-22 21:43:43,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14207 states to 14207 states and 31263 transitions. [2018-11-22 21:43:43,967 INFO L78 Accepts]: Start accepts. Automaton has 14207 states and 31263 transitions. Word has length 111 [2018-11-22 21:43:43,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:43,968 INFO L480 AbstractCegarLoop]: Abstraction has 14207 states and 31263 transitions. [2018-11-22 21:43:43,968 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:43:43,968 INFO L276 IsEmpty]: Start isEmpty. Operand 14207 states and 31263 transitions. [2018-11-22 21:43:43,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-22 21:43:43,977 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:43,977 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:43,977 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:43,977 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:43,977 INFO L82 PathProgramCache]: Analyzing trace with hash -578631450, now seen corresponding path program 1 times [2018-11-22 21:43:43,977 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:43,978 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:43,978 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:43,978 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:43,978 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:43,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:44,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:44,028 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:44,028 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:43:44,029 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:44,029 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:43:44,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:43:44,029 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:44,029 INFO L87 Difference]: Start difference. First operand 14207 states and 31263 transitions. Second operand 3 states. [2018-11-22 21:43:44,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:44,060 INFO L93 Difference]: Finished difference Result 13951 states and 30431 transitions. [2018-11-22 21:43:44,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:43:44,061 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 111 [2018-11-22 21:43:44,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:44,070 INFO L225 Difference]: With dead ends: 13951 [2018-11-22 21:43:44,071 INFO L226 Difference]: Without dead ends: 13919 [2018-11-22 21:43:44,071 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:44,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13919 states. [2018-11-22 21:43:44,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13919 to 11260. [2018-11-22 21:43:44,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11260 states. [2018-11-22 21:43:44,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11260 states to 11260 states and 24224 transitions. [2018-11-22 21:43:44,167 INFO L78 Accepts]: Start accepts. Automaton has 11260 states and 24224 transitions. Word has length 111 [2018-11-22 21:43:44,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:44,168 INFO L480 AbstractCegarLoop]: Abstraction has 11260 states and 24224 transitions. [2018-11-22 21:43:44,168 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:43:44,168 INFO L276 IsEmpty]: Start isEmpty. Operand 11260 states and 24224 transitions. [2018-11-22 21:43:44,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-22 21:43:44,175 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:44,175 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:44,176 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:44,176 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:44,176 INFO L82 PathProgramCache]: Analyzing trace with hash -671278334, now seen corresponding path program 1 times [2018-11-22 21:43:44,176 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:44,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:44,177 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:44,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:44,177 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:44,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:44,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:44,230 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:44,230 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:43:44,230 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:44,230 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:43:44,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:43:44,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:44,231 INFO L87 Difference]: Start difference. First operand 11260 states and 24224 transitions. Second operand 6 states. [2018-11-22 21:43:44,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:44,462 INFO L93 Difference]: Finished difference Result 12827 states and 27502 transitions. [2018-11-22 21:43:44,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 21:43:44,462 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 113 [2018-11-22 21:43:44,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:44,470 INFO L225 Difference]: With dead ends: 12827 [2018-11-22 21:43:44,470 INFO L226 Difference]: Without dead ends: 12827 [2018-11-22 21:43:44,470 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-11-22 21:43:44,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12827 states. [2018-11-22 21:43:44,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12827 to 11484. [2018-11-22 21:43:44,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11484 states. [2018-11-22 21:43:44,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11484 states to 11484 states and 24704 transitions. [2018-11-22 21:43:44,556 INFO L78 Accepts]: Start accepts. Automaton has 11484 states and 24704 transitions. Word has length 113 [2018-11-22 21:43:44,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:44,556 INFO L480 AbstractCegarLoop]: Abstraction has 11484 states and 24704 transitions. [2018-11-22 21:43:44,556 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:43:44,556 INFO L276 IsEmpty]: Start isEmpty. Operand 11484 states and 24704 transitions. [2018-11-22 21:43:44,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-22 21:43:44,562 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:44,562 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:44,563 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:44,563 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:44,563 INFO L82 PathProgramCache]: Analyzing trace with hash 1613585121, now seen corresponding path program 1 times [2018-11-22 21:43:44,563 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:44,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:44,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:44,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:44,564 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:44,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:44,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:44,618 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:44,618 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:43:44,619 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:44,619 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:43:44,619 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:43:44,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:43:44,619 INFO L87 Difference]: Start difference. First operand 11484 states and 24704 transitions. Second operand 4 states. [2018-11-22 21:43:44,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:44,819 INFO L93 Difference]: Finished difference Result 13496 states and 29034 transitions. [2018-11-22 21:43:44,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:43:44,819 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 113 [2018-11-22 21:43:44,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:44,827 INFO L225 Difference]: With dead ends: 13496 [2018-11-22 21:43:44,827 INFO L226 Difference]: Without dead ends: 13433 [2018-11-22 21:43:44,828 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:44,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13433 states. [2018-11-22 21:43:44,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13433 to 11974. [2018-11-22 21:43:44,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11974 states. [2018-11-22 21:43:44,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11974 states to 11974 states and 25808 transitions. [2018-11-22 21:43:44,918 INFO L78 Accepts]: Start accepts. Automaton has 11974 states and 25808 transitions. Word has length 113 [2018-11-22 21:43:44,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:44,918 INFO L480 AbstractCegarLoop]: Abstraction has 11974 states and 25808 transitions. [2018-11-22 21:43:44,918 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:43:44,918 INFO L276 IsEmpty]: Start isEmpty. Operand 11974 states and 25808 transitions. [2018-11-22 21:43:44,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-22 21:43:44,926 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:44,927 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:44,927 INFO L423 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:44,927 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:44,927 INFO L82 PathProgramCache]: Analyzing trace with hash -429292798, now seen corresponding path program 1 times [2018-11-22 21:43:44,927 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:44,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:44,928 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:44,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:44,928 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:44,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:44,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:45,000 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:45,000 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 21:43:45,000 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:45,000 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 21:43:45,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 21:43:45,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:45,000 INFO L87 Difference]: Start difference. First operand 11974 states and 25808 transitions. Second operand 7 states. [2018-11-22 21:43:45,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:45,275 INFO L93 Difference]: Finished difference Result 13243 states and 28447 transitions. [2018-11-22 21:43:45,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-22 21:43:45,275 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 113 [2018-11-22 21:43:45,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:45,283 INFO L225 Difference]: With dead ends: 13243 [2018-11-22 21:43:45,283 INFO L226 Difference]: Without dead ends: 13243 [2018-11-22 21:43:45,284 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-11-22 21:43:45,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13243 states. [2018-11-22 21:43:45,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13243 to 11388. [2018-11-22 21:43:45,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11388 states. [2018-11-22 21:43:45,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11388 states to 11388 states and 24568 transitions. [2018-11-22 21:43:45,375 INFO L78 Accepts]: Start accepts. Automaton has 11388 states and 24568 transitions. Word has length 113 [2018-11-22 21:43:45,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:45,376 INFO L480 AbstractCegarLoop]: Abstraction has 11388 states and 24568 transitions. [2018-11-22 21:43:45,376 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 21:43:45,376 INFO L276 IsEmpty]: Start isEmpty. Operand 11388 states and 24568 transitions. [2018-11-22 21:43:45,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-22 21:43:45,383 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:45,383 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:45,383 INFO L423 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:45,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:45,383 INFO L82 PathProgramCache]: Analyzing trace with hash -1719768158, now seen corresponding path program 1 times [2018-11-22 21:43:45,383 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:45,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:45,384 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:45,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:45,384 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:45,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:45,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:45,459 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:45,459 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 21:43:45,459 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:45,460 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 21:43:45,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 21:43:45,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:45,460 INFO L87 Difference]: Start difference. First operand 11388 states and 24568 transitions. Second operand 7 states. [2018-11-22 21:43:45,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:45,587 INFO L93 Difference]: Finished difference Result 13837 states and 30118 transitions. [2018-11-22 21:43:45,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:43:45,588 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 113 [2018-11-22 21:43:45,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:45,596 INFO L225 Difference]: With dead ends: 13837 [2018-11-22 21:43:45,596 INFO L226 Difference]: Without dead ends: 13837 [2018-11-22 21:43:45,596 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-11-22 21:43:45,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13837 states. [2018-11-22 21:43:45,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13837 to 11644. [2018-11-22 21:43:45,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11644 states. [2018-11-22 21:43:45,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11644 states to 11644 states and 25019 transitions. [2018-11-22 21:43:45,690 INFO L78 Accepts]: Start accepts. Automaton has 11644 states and 25019 transitions. Word has length 113 [2018-11-22 21:43:45,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:45,691 INFO L480 AbstractCegarLoop]: Abstraction has 11644 states and 25019 transitions. [2018-11-22 21:43:45,691 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 21:43:45,691 INFO L276 IsEmpty]: Start isEmpty. Operand 11644 states and 25019 transitions. [2018-11-22 21:43:45,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-22 21:43:45,699 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:45,699 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:45,699 INFO L423 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:45,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:45,700 INFO L82 PathProgramCache]: Analyzing trace with hash -475003677, now seen corresponding path program 1 times [2018-11-22 21:43:45,700 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:45,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:45,701 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:45,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:45,701 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:45,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:45,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:45,777 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:45,777 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:43:45,777 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:45,778 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:43:45,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:43:45,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:43:45,778 INFO L87 Difference]: Start difference. First operand 11644 states and 25019 transitions. Second operand 5 states. [2018-11-22 21:43:45,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:45,808 INFO L93 Difference]: Finished difference Result 11564 states and 24771 transitions. [2018-11-22 21:43:45,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:43:45,808 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-22 21:43:45,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:45,816 INFO L225 Difference]: With dead ends: 11564 [2018-11-22 21:43:45,816 INFO L226 Difference]: Without dead ends: 11564 [2018-11-22 21:43:45,816 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:45,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11564 states. [2018-11-22 21:43:45,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11564 to 9848. [2018-11-22 21:43:45,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9848 states. [2018-11-22 21:43:45,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9848 states to 9848 states and 21132 transitions. [2018-11-22 21:43:45,890 INFO L78 Accepts]: Start accepts. Automaton has 9848 states and 21132 transitions. Word has length 113 [2018-11-22 21:43:45,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:45,890 INFO L480 AbstractCegarLoop]: Abstraction has 9848 states and 21132 transitions. [2018-11-22 21:43:45,890 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:43:45,890 INFO L276 IsEmpty]: Start isEmpty. Operand 9848 states and 21132 transitions. [2018-11-22 21:43:45,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-22 21:43:45,897 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:45,897 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:45,898 INFO L423 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:45,898 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:45,898 INFO L82 PathProgramCache]: Analyzing trace with hash 2012509156, now seen corresponding path program 1 times [2018-11-22 21:43:45,898 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:45,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:45,899 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:45,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:45,899 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:45,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:45,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:45,943 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:45,943 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:43:45,943 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:45,943 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:43:45,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:43:45,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:45,944 INFO L87 Difference]: Start difference. First operand 9848 states and 21132 transitions. Second operand 3 states. [2018-11-22 21:43:45,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:45,966 INFO L93 Difference]: Finished difference Result 9848 states and 21116 transitions. [2018-11-22 21:43:45,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:43:45,966 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2018-11-22 21:43:45,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:45,973 INFO L225 Difference]: With dead ends: 9848 [2018-11-22 21:43:45,973 INFO L226 Difference]: Without dead ends: 9848 [2018-11-22 21:43:45,973 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:43:45,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9848 states. [2018-11-22 21:43:46,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9848 to 9848. [2018-11-22 21:43:46,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9848 states. [2018-11-22 21:43:46,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9848 states to 9848 states and 21116 transitions. [2018-11-22 21:43:46,042 INFO L78 Accepts]: Start accepts. Automaton has 9848 states and 21116 transitions. Word has length 113 [2018-11-22 21:43:46,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:46,042 INFO L480 AbstractCegarLoop]: Abstraction has 9848 states and 21116 transitions. [2018-11-22 21:43:46,042 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:43:46,042 INFO L276 IsEmpty]: Start isEmpty. Operand 9848 states and 21116 transitions. [2018-11-22 21:43:46,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-22 21:43:46,049 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:46,049 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:46,049 INFO L423 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:46,049 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:46,050 INFO L82 PathProgramCache]: Analyzing trace with hash -2009478936, now seen corresponding path program 1 times [2018-11-22 21:43:46,050 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:46,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,051 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:46,051 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,051 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:46,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:46,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:46,123 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:46,123 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-22 21:43:46,123 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:46,123 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-22 21:43:46,124 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-22 21:43:46,124 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-11-22 21:43:46,124 INFO L87 Difference]: Start difference. First operand 9848 states and 21116 transitions. Second operand 9 states. [2018-11-22 21:43:46,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:46,377 INFO L93 Difference]: Finished difference Result 12111 states and 26147 transitions. [2018-11-22 21:43:46,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 21:43:46,377 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 115 [2018-11-22 21:43:46,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:46,379 INFO L225 Difference]: With dead ends: 12111 [2018-11-22 21:43:46,379 INFO L226 Difference]: Without dead ends: 2409 [2018-11-22 21:43:46,379 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2018-11-22 21:43:46,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2409 states. [2018-11-22 21:43:46,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2409 to 2409. [2018-11-22 21:43:46,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2409 states. [2018-11-22 21:43:46,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2409 states to 2409 states and 5339 transitions. [2018-11-22 21:43:46,393 INFO L78 Accepts]: Start accepts. Automaton has 2409 states and 5339 transitions. Word has length 115 [2018-11-22 21:43:46,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:46,393 INFO L480 AbstractCegarLoop]: Abstraction has 2409 states and 5339 transitions. [2018-11-22 21:43:46,393 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-22 21:43:46,394 INFO L276 IsEmpty]: Start isEmpty. Operand 2409 states and 5339 transitions. [2018-11-22 21:43:46,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-22 21:43:46,395 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:46,395 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:46,395 INFO L423 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:46,395 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:46,395 INFO L82 PathProgramCache]: Analyzing trace with hash 686518171, now seen corresponding path program 1 times [2018-11-22 21:43:46,395 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:46,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,396 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:46,397 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,397 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:46,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:46,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:46,450 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:46,450 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:43:46,450 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:46,450 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:43:46,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:43:46,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:46,451 INFO L87 Difference]: Start difference. First operand 2409 states and 5339 transitions. Second operand 6 states. [2018-11-22 21:43:46,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:46,585 INFO L93 Difference]: Finished difference Result 2369 states and 5156 transitions. [2018-11-22 21:43:46,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:43:46,585 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 115 [2018-11-22 21:43:46,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:46,587 INFO L225 Difference]: With dead ends: 2369 [2018-11-22 21:43:46,587 INFO L226 Difference]: Without dead ends: 2369 [2018-11-22 21:43:46,587 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:46,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2369 states. [2018-11-22 21:43:46,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2369 to 1937. [2018-11-22 21:43:46,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1937 states. [2018-11-22 21:43:46,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1937 states to 1937 states and 4208 transitions. [2018-11-22 21:43:46,600 INFO L78 Accepts]: Start accepts. Automaton has 1937 states and 4208 transitions. Word has length 115 [2018-11-22 21:43:46,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:46,601 INFO L480 AbstractCegarLoop]: Abstraction has 1937 states and 4208 transitions. [2018-11-22 21:43:46,601 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:43:46,601 INFO L276 IsEmpty]: Start isEmpty. Operand 1937 states and 4208 transitions. [2018-11-22 21:43:46,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-22 21:43:46,602 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:46,603 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:46,603 INFO L423 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:46,603 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:46,603 INFO L82 PathProgramCache]: Analyzing trace with hash 1865893307, now seen corresponding path program 1 times [2018-11-22 21:43:46,603 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:46,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:46,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,604 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:46,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:46,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:46,668 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:46,668 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:43:46,668 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:46,669 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:43:46,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:43:46,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:43:46,669 INFO L87 Difference]: Start difference. First operand 1937 states and 4208 transitions. Second operand 6 states. [2018-11-22 21:43:46,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:46,737 INFO L93 Difference]: Finished difference Result 2162 states and 4657 transitions. [2018-11-22 21:43:46,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:43:46,738 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 115 [2018-11-22 21:43:46,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:46,739 INFO L225 Difference]: With dead ends: 2162 [2018-11-22 21:43:46,740 INFO L226 Difference]: Without dead ends: 2131 [2018-11-22 21:43:46,740 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:43:46,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2131 states. [2018-11-22 21:43:46,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2131 to 1835. [2018-11-22 21:43:46,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1835 states. [2018-11-22 21:43:46,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1835 states to 1835 states and 3985 transitions. [2018-11-22 21:43:46,752 INFO L78 Accepts]: Start accepts. Automaton has 1835 states and 3985 transitions. Word has length 115 [2018-11-22 21:43:46,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:46,752 INFO L480 AbstractCegarLoop]: Abstraction has 1835 states and 3985 transitions. [2018-11-22 21:43:46,753 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:43:46,753 INFO L276 IsEmpty]: Start isEmpty. Operand 1835 states and 3985 transitions. [2018-11-22 21:43:46,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-22 21:43:46,754 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:46,755 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:46,755 INFO L423 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:46,755 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:46,755 INFO L82 PathProgramCache]: Analyzing trace with hash -1735972292, now seen corresponding path program 2 times [2018-11-22 21:43:46,755 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:46,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,756 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:46,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:46,756 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:46,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:47,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:47,089 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:47,089 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-11-22 21:43:47,089 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:47,089 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-22 21:43:47,089 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-22 21:43:47,090 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=232, Unknown=0, NotChecked=0, Total=272 [2018-11-22 21:43:47,090 INFO L87 Difference]: Start difference. First operand 1835 states and 3985 transitions. Second operand 17 states. [2018-11-22 21:43:47,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:47,384 INFO L93 Difference]: Finished difference Result 1991 states and 4323 transitions. [2018-11-22 21:43:47,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-22 21:43:47,384 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 115 [2018-11-22 21:43:47,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:47,385 INFO L225 Difference]: With dead ends: 1991 [2018-11-22 21:43:47,385 INFO L226 Difference]: Without dead ends: 1895 [2018-11-22 21:43:47,386 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=144, Invalid=612, Unknown=0, NotChecked=0, Total=756 [2018-11-22 21:43:47,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1895 states. [2018-11-22 21:43:47,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1895 to 1835. [2018-11-22 21:43:47,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1835 states. [2018-11-22 21:43:47,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1835 states to 1835 states and 3969 transitions. [2018-11-22 21:43:47,396 INFO L78 Accepts]: Start accepts. Automaton has 1835 states and 3969 transitions. Word has length 115 [2018-11-22 21:43:47,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:47,396 INFO L480 AbstractCegarLoop]: Abstraction has 1835 states and 3969 transitions. [2018-11-22 21:43:47,396 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-22 21:43:47,396 INFO L276 IsEmpty]: Start isEmpty. Operand 1835 states and 3969 transitions. [2018-11-22 21:43:47,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-22 21:43:47,397 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:47,398 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:47,398 INFO L423 AbstractCegarLoop]: === Iteration 39 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:47,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:47,398 INFO L82 PathProgramCache]: Analyzing trace with hash 816184669, now seen corresponding path program 1 times [2018-11-22 21:43:47,398 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:47,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:47,399 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:43:47,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:47,399 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:47,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:43:47,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:43:47,753 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:43:47,753 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [25] imperfect sequences [] total 25 [2018-11-22 21:43:47,753 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 21:43:47,753 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-22 21:43:47,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-22 21:43:47,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=539, Unknown=0, NotChecked=0, Total=600 [2018-11-22 21:43:47,754 INFO L87 Difference]: Start difference. First operand 1835 states and 3969 transitions. Second operand 25 states. [2018-11-22 21:43:48,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:43:48,544 INFO L93 Difference]: Finished difference Result 2619 states and 5695 transitions. [2018-11-22 21:43:48,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-22 21:43:48,544 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 115 [2018-11-22 21:43:48,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:43:48,546 INFO L225 Difference]: With dead ends: 2619 [2018-11-22 21:43:48,546 INFO L226 Difference]: Without dead ends: 2022 [2018-11-22 21:43:48,547 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 358 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=351, Invalid=1811, Unknown=0, NotChecked=0, Total=2162 [2018-11-22 21:43:48,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2022 states. [2018-11-22 21:43:48,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2022 to 1856. [2018-11-22 21:43:48,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1856 states. [2018-11-22 21:43:48,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1856 states to 1856 states and 4008 transitions. [2018-11-22 21:43:48,560 INFO L78 Accepts]: Start accepts. Automaton has 1856 states and 4008 transitions. Word has length 115 [2018-11-22 21:43:48,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:43:48,560 INFO L480 AbstractCegarLoop]: Abstraction has 1856 states and 4008 transitions. [2018-11-22 21:43:48,560 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-22 21:43:48,560 INFO L276 IsEmpty]: Start isEmpty. Operand 1856 states and 4008 transitions. [2018-11-22 21:43:48,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-22 21:43:48,562 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:43:48,562 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:43:48,562 INFO L423 AbstractCegarLoop]: === Iteration 40 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:43:48,562 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:43:48,562 INFO L82 PathProgramCache]: Analyzing trace with hash 1119572719, now seen corresponding path program 2 times [2018-11-22 21:43:48,562 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 21:43:48,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:48,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:43:48,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:43:48,564 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 21:43:48,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:43:48,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:43:48,619 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [596] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [520] L-1-->L671: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [632] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_5 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [680] L673-->L675: Formula: (= v_~__unbuffered_p0_EAX~0_2 0) InVars {} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 [570] L675-->L676: Formula: (= v_~__unbuffered_p1_EAX~0_2 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [513] L676-->L677: Formula: (= v_~__unbuffered_p1_EAX$flush_delayed~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$flush_delayed~0=v_~__unbuffered_p1_EAX$flush_delayed~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [603] L677-->L678: Formula: (= v_~__unbuffered_p1_EAX$mem_tmp~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$mem_tmp~0=v_~__unbuffered_p1_EAX$mem_tmp~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [709] L678-->L679: Formula: (= v_~__unbuffered_p1_EAX$r_buff0_thd0~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff0_thd0~0=v_~__unbuffered_p1_EAX$r_buff0_thd0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [767] L679-->L680: Formula: (= v_~__unbuffered_p1_EAX$r_buff0_thd1~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff0_thd1~0=v_~__unbuffered_p1_EAX$r_buff0_thd1~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [727] L680-->L681: Formula: (= v_~__unbuffered_p1_EAX$r_buff0_thd2~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff0_thd2~0=v_~__unbuffered_p1_EAX$r_buff0_thd2~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [536] L681-->L682: Formula: (= v_~__unbuffered_p1_EAX$r_buff1_thd0~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff1_thd0~0=v_~__unbuffered_p1_EAX$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [629] L682-->L683: Formula: (= v_~__unbuffered_p1_EAX$r_buff1_thd1~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff1_thd1~0=v_~__unbuffered_p1_EAX$r_buff1_thd1~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [576] L683-->L684: Formula: (= v_~__unbuffered_p1_EAX$r_buff1_thd2~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$r_buff1_thd2~0=v_~__unbuffered_p1_EAX$r_buff1_thd2~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [679] L684-->L685: Formula: (= v_~__unbuffered_p1_EAX$read_delayed~0_2 0) InVars {} OutVars{~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_2} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [744] L685-->L686: Formula: (and (= v_~__unbuffered_p1_EAX$read_delayed_var~0.base_2 0) (= v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_2 0)) InVars {} OutVars{~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_2, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_2} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [569] L686-->L687: Formula: (= v_~__unbuffered_p1_EAX$w_buff0~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff0~0=v_~__unbuffered_p1_EAX$w_buff0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [533] L687-->L688: Formula: (= v_~__unbuffered_p1_EAX$w_buff0_used~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff0_used~0=v_~__unbuffered_p1_EAX$w_buff0_used~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [602] L688-->L689: Formula: (= v_~__unbuffered_p1_EAX$w_buff1~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff1~0=v_~__unbuffered_p1_EAX$w_buff1~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [707] L689-->L690: Formula: (= v_~__unbuffered_p1_EAX$w_buff1_used~0_1 0) InVars {} OutVars{~__unbuffered_p1_EAX$w_buff1_used~0=v_~__unbuffered_p1_EAX$w_buff1_used~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [766] L690-->L691: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 [725] L691-->L693: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [627] L693-->L693-1: Formula: (and (= |v_#length_1| (store |v_#length_2| |v_~#x~0.base_13| 4)) (= |v_~#x~0.offset_13| 0) (not (= 0 |v_~#x~0.base_13|)) (= (store |v_#valid_4| |v_~#x~0.base_13| 1) |v_#valid_3|) (= 0 (select |v_#valid_4| |v_~#x~0.base_13|))) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#x~0.base=|v_~#x~0.base_13|, #length=|v_#length_1|, ~#x~0.offset=|v_~#x~0.offset_13|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#x~0.offset, #valid, ~#x~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [611] L693-1-->L693-2: Formula: (= (select (select |v_#memory_int_17| |v_~#x~0.base_14|) |v_~#x~0.offset_14|) 0) InVars {~#x~0.base=|v_~#x~0.base_14|, #memory_int=|v_#memory_int_17|, ~#x~0.offset=|v_~#x~0.offset_14|} OutVars{~#x~0.base=|v_~#x~0.base_14|, #memory_int=|v_#memory_int_17|, ~#x~0.offset=|v_~#x~0.offset_14|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [614] L693-2-->L695: Formula: (= v_~x$flush_delayed~0_5 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_5} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [?] -1 [678] L695-->L696: Formula: (= v_~x$mem_tmp~0_3 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_3} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [?] -1 [743] L696-->L697: Formula: (= v_~x$r_buff0_thd0~0_2 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [?] -1 [566] L697-->L698: Formula: (= v_~x$r_buff0_thd1~0_14 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [?] -1 [532] L698-->L699: Formula: (= v_~x$r_buff0_thd2~0_58 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_58} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [?] -1 [601] L699-->L700: Formula: (= v_~x$r_buff1_thd0~0_2 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [?] -1 [706] L700-->L701: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [?] -1 [765] L701-->L702: Formula: (= v_~x$r_buff1_thd2~0_41 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_41} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [?] -1 [724] L702-->L703: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [?] -1 [560] L703-->L704: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [?] -1 [624] L704-->L705: Formula: (= v_~x$w_buff0~0_16 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_16} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [?] -1 [575] L705-->L706: Formula: (= v_~x$w_buff0_used~0_83 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_83} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [?] -1 [676] L706-->L707: Formula: (= v_~x$w_buff1~0_13 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_13} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [?] -1 [742] L707-->L709: Formula: (= v_~x$w_buff1_used~0_47 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_47} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [?] -1 [531] L709-->L710: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [600] L710-->L711: Formula: (= v_~weak$$choice0~0_14 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_14} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [705] L711-->L712: Formula: (= v_~weak$$choice1~0_5 0) InVars {} OutVars{~weak$$choice1~0=v_~weak$$choice1~0_5} AuxVars[] AssignedVars[~weak$$choice1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [764] L712-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [628] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [623] L-1-2-->L788: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_1|, ULTIMATE.start_main_~#t1926~0.offset=|v_ULTIMATE.start_main_~#t1926~0.offset_1|, ULTIMATE.start_main_#t~nondet69=|v_ULTIMATE.start_main_#t~nondet69_1|, ULTIMATE.start_main_#t~nondet68=|v_ULTIMATE.start_main_#t~nondet68_1|, ULTIMATE.start_main_#t~mem70=|v_ULTIMATE.start_main_#t~mem70_1|, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_1|, ULTIMATE.start_main_~#t1926~0.base=|v_ULTIMATE.start_main_~#t1926~0.base_1|, ULTIMATE.start_main_~#t1925~0.base=|v_ULTIMATE.start_main_~#t1925~0.base_1|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_1|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_1|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_1|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_1|, ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_1|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_1|, ULTIMATE.start_main_~#t1925~0.offset=|v_ULTIMATE.start_main_~#t1925~0.offset_1|, ULTIMATE.start_main_#t~nondet77.offset=|v_ULTIMATE.start_main_#t~nondet77.offset_1|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_1|, ULTIMATE.start_main_#t~nondet77.base=|v_ULTIMATE.start_main_#t~nondet77.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_~#t1926~0.offset, ULTIMATE.start_main_#t~nondet69, ULTIMATE.start_main_#t~nondet68, ULTIMATE.start_main_#t~mem70, ULTIMATE.start_main_#t~ite79, ULTIMATE.start_main_~#t1926~0.base, ULTIMATE.start_main_~#t1925~0.base, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite71, ULTIMATE.start_main_#t~ite72, ULTIMATE.start_main_~#t1925~0.offset, ULTIMATE.start_main_#t~nondet77.offset, ULTIMATE.start_main_#t~ite80, ULTIMATE.start_main_#t~nondet77.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [701] L788-->L788-1: Formula: (and (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1925~0.base_2| 4)) (= |v_ULTIMATE.start_main_~#t1925~0.offset_2| 0) (= |v_#valid_5| (store |v_#valid_6| |v_ULTIMATE.start_main_~#t1925~0.base_2| 1)) (not (= |v_ULTIMATE.start_main_~#t1925~0.base_2| 0)) (= (select |v_#valid_6| |v_ULTIMATE.start_main_~#t1925~0.base_2|) 0)) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t1925~0.offset=|v_ULTIMATE.start_main_~#t1925~0.offset_2|, ULTIMATE.start_main_~#t1925~0.base=|v_ULTIMATE.start_main_~#t1925~0.base_2|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1925~0.offset, #valid, #length, ULTIMATE.start_main_~#t1925~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [702] L788-1-->L789: Formula: (= (store |v_#memory_int_19| |v_ULTIMATE.start_main_~#t1925~0.base_3| (store (select |v_#memory_int_19| |v_ULTIMATE.start_main_~#t1925~0.base_3|) |v_ULTIMATE.start_main_~#t1925~0.offset_3| 0)) |v_#memory_int_18|) InVars {#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#t1925~0.offset=|v_ULTIMATE.start_main_~#t1925~0.offset_3|, ULTIMATE.start_main_~#t1925~0.base=|v_ULTIMATE.start_main_~#t1925~0.base_3|} OutVars{#memory_int=|v_#memory_int_18|, ULTIMATE.start_main_~#t1925~0.offset=|v_ULTIMATE.start_main_~#t1925~0.offset_3|, ULTIMATE.start_main_~#t1925~0.base=|v_ULTIMATE.start_main_~#t1925~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 [942] L789-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [760] L789-1-->L790: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet68=|v_ULTIMATE.start_main_#t~nondet68_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet68] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [738] L790-->L790-1: Formula: (and (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t1926~0.base_2| 4)) (not (= |v_ULTIMATE.start_main_~#t1926~0.base_2| 0)) (= |v_ULTIMATE.start_main_~#t1926~0.offset_2| 0) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1926~0.base_2|) 0) (= |v_#valid_7| (store |v_#valid_8| |v_ULTIMATE.start_main_~#t1926~0.base_2| 1))) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#t1926~0.offset=|v_ULTIMATE.start_main_~#t1926~0.offset_2|, ULTIMATE.start_main_~#t1926~0.base=|v_ULTIMATE.start_main_~#t1926~0.base_2|, #length=|v_#length_5|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1926~0.offset, #valid, ULTIMATE.start_main_~#t1926~0.base, #length] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 [739] L790-1-->L791: Formula: (= (store |v_#memory_int_21| |v_ULTIMATE.start_main_~#t1926~0.base_3| (store (select |v_#memory_int_21| |v_ULTIMATE.start_main_~#t1926~0.base_3|) |v_ULTIMATE.start_main_~#t1926~0.offset_3| 1)) |v_#memory_int_20|) InVars {#memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t1926~0.offset=|v_ULTIMATE.start_main_~#t1926~0.offset_3|, ULTIMATE.start_main_~#t1926~0.base=|v_ULTIMATE.start_main_~#t1926~0.base_3|} OutVars{#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_~#t1926~0.offset=|v_ULTIMATE.start_main_~#t1926~0.offset_3|, ULTIMATE.start_main_~#t1926~0.base=|v_ULTIMATE.start_main_~#t1926~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 [941] L791-->P1ENTRY: Formula: (and (= 0 |v_Thread0_P1_#in~arg.offset_3|) (= 1 v_Thread0_P1_thidvar0_2) (= 0 |v_Thread0_P1_#in~arg.base_3|)) InVars {} OutVars{Thread0_P1_thidvar0=v_Thread0_P1_thidvar0_2, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_3|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P1_thidvar0, Thread0_P1_#in~arg.base, Thread0_P1_#in~arg.offset] VAL [Thread0_P1_thidvar0=1, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [799] P1ENTRY-->L749: Formula: (and (= v_Thread0_P1_~arg.offset_1 |v_Thread0_P1_#in~arg.offset_1|) (= v_~weak$$choice0~0_3 (ite (= (+ |v_Thread0_P1_#t~nondet11.offset_1| |v_Thread0_P1_#t~nondet11.base_1|) 0) 0 1)) (= v_~x$flush_delayed~0_1 v_~weak$$choice2~0_5) (= v_~weak$$choice2~0_5 (ite (= (+ |v_Thread0_P1_#t~nondet12.offset_1| |v_Thread0_P1_#t~nondet12.base_1|) 0) 0 1)) (= v_~x$mem_tmp~0_1 (select (select |v_#memory_int_4| |v_~#x~0.base_3|) |v_~#x~0.offset_3|)) (= v_Thread0_P1_~arg.base_1 |v_Thread0_P1_#in~arg.base_1|) (= v_~weak$$choice1~0_1 (ite (= (+ |v_Thread0_P1_#t~nondet14.offset_1| |v_Thread0_P1_#t~nondet14.base_1|) 0) 0 1))) InVars {Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_#t~nondet12.offset=|v_Thread0_P1_#t~nondet12.offset_1|, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_1|, ~#x~0.offset=|v_~#x~0.offset_3|, Thread0_P1_#t~nondet14.base=|v_Thread0_P1_#t~nondet14.base_1|, Thread0_P1_#t~nondet14.offset=|v_Thread0_P1_#t~nondet14.offset_1|, ~#x~0.base=|v_~#x~0.base_3|, #memory_int=|v_#memory_int_4|, Thread0_P1_#t~nondet12.base=|v_Thread0_P1_#t~nondet12.base_1|, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_1|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|} OutVars{Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_~arg.offset=v_Thread0_P1_~arg.offset_1, Thread0_P1_#t~nondet12.offset=|v_Thread0_P1_#t~nondet12.offset_2|, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_2|, ~#x~0.offset=|v_~#x~0.offset_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_1, Thread0_P1_#t~nondet14.offset=|v_Thread0_P1_#t~nondet14.offset_2|, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|, ~weak$$choice0~0=v_~weak$$choice0~0_3, ~weak$$choice1~0=v_~weak$$choice1~0_1, Thread0_P1_#t~nondet14.base=|v_Thread0_P1_#t~nondet14.base_2|, Thread0_P1_~arg.base=v_Thread0_P1_~arg.base_1, Thread0_P1_#t~mem13=|v_Thread0_P1_#t~mem13_1|, ~#x~0.base=|v_~#x~0.base_3|, #memory_int=|v_#memory_int_4|, Thread0_P1_#t~nondet12.base=|v_Thread0_P1_#t~nondet12.base_2|, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_2|, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread0_P1_~arg.offset, Thread0_P1_#t~nondet12.offset, Thread0_P1_#t~nondet11.base, ~x$flush_delayed~0, Thread0_P1_#t~nondet14.offset, ~x$mem_tmp~0, ~weak$$choice0~0, ~weak$$choice1~0, Thread0_P1_#t~nondet14.base, Thread0_P1_~arg.base, Thread0_P1_#t~mem13, Thread0_P1_#t~nondet12.base, Thread0_P1_#t~nondet11.offset, ~weak$$choice2~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [800] L749-->L749-23: Formula: (and (= 0 (mod v_~x$w_buff0_used~0_28 256)) (= |v_Thread0_P1_#t~ite25_1| |v_Thread0_P1_#t~mem15_1|) (= |v_Thread0_P1_#t~mem15_1| (select (select |v_#memory_int_5| |v_~#x~0.base_4|) |v_~#x~0.offset_4|))) InVars {~#x~0.base=|v_~#x~0.base_4|, #memory_int=|v_#memory_int_5|, ~#x~0.offset=|v_~#x~0.offset_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_28} OutVars{~#x~0.offset=|v_~#x~0.offset_4|, ~#x~0.base=|v_~#x~0.base_4|, #memory_int=|v_#memory_int_5|, Thread0_P1_#t~mem15=|v_Thread0_P1_#t~mem15_1|, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_28} AuxVars[] AssignedVars[Thread0_P1_#t~mem15, Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite25|=0, |Thread0_P1_#t~mem15|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [802] L749-23-->L750: Formula: (= (store |v_#memory_int_16| |v_~#x~0.base_12| (store (select |v_#memory_int_16| |v_~#x~0.base_12|) |v_~#x~0.offset_12| |v_Thread0_P1_#t~ite25_2|)) |v_#memory_int_15|) InVars {#memory_int=|v_#memory_int_16|, ~#x~0.base=|v_~#x~0.base_12|, ~#x~0.offset=|v_~#x~0.offset_12|, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_2|} OutVars{~#x~0.offset=|v_~#x~0.offset_12|, Thread0_P1_#t~mem16=|v_Thread0_P1_#t~mem16_1|, Thread0_P1_#t~mem15=|v_Thread0_P1_#t~mem15_2|, Thread0_P1_#t~mem20=|v_Thread0_P1_#t~mem20_1|, Thread0_P1_#t~ite18=|v_Thread0_P1_#t~ite18_1|, Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_1|, Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_1|, #memory_int=|v_#memory_int_15|, ~#x~0.base=|v_~#x~0.base_12|, Thread0_P1_#t~ite21=|v_Thread0_P1_#t~ite21_1|, Thread0_P1_#t~ite24=|v_Thread0_P1_#t~ite24_1|, Thread0_P1_#t~ite23=|v_Thread0_P1_#t~ite23_1|, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_3|, Thread0_P1_#t~ite17=|v_Thread0_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread0_P1_#t~mem20, Thread0_P1_#t~ite18, Thread0_P1_#t~ite19, Thread0_P1_#t~mem16, Thread0_P1_#t~ite22, #memory_int, Thread0_P1_#t~mem15, Thread0_P1_#t~ite21, Thread0_P1_#t~ite24, Thread0_P1_#t~ite23, Thread0_P1_#t~ite25, Thread0_P1_#t~ite17] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [805] L750-->L750-14: Formula: (and (= |v_Thread0_P1_#t~ite30_1| v_~x$w_buff0~0_9) (not (= (mod v_~weak$$choice2~0_6 256) 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_6} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_6, Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite30] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite30|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [810] L750-14-->L751: Formula: (= v_~x$w_buff0~0_15 |v_Thread0_P1_#t~ite30_2|) InVars {Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_2|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_15, Thread0_P1_#t~ite29=|v_Thread0_P1_#t~ite29_1|, Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_3|, Thread0_P1_#t~ite26=|v_Thread0_P1_#t~ite26_1|, Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_1|, Thread0_P1_#t~ite27=|v_Thread0_P1_#t~ite27_1|} AuxVars[] AssignedVars[~x$w_buff0~0, Thread0_P1_#t~ite29, Thread0_P1_#t~ite30, Thread0_P1_#t~ite26, Thread0_P1_#t~ite28, Thread0_P1_#t~ite27] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [817] L751-->L751-14: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread0_P1_#t~ite35_1| v_~x$w_buff1~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_8, ~x$w_buff1~0=v_~x$w_buff1~0_6} OutVars{Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_1|, ~weak$$choice2~0=v_~weak$$choice2~0_8, ~x$w_buff1~0=v_~x$w_buff1~0_6} AuxVars[] AssignedVars[Thread0_P1_#t~ite35] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite35|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [829] L751-14-->L752: Formula: (= v_~x$w_buff1~0_12 |v_Thread0_P1_#t~ite35_2|) InVars {Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_2|} OutVars{Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_1|, ~x$w_buff1~0=v_~x$w_buff1~0_12, Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_1|, Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_1|, Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_3|, Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite31, ~x$w_buff1~0, Thread0_P1_#t~ite33, Thread0_P1_#t~ite32, Thread0_P1_#t~ite35, Thread0_P1_#t~ite34] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [839] L752-->L752-14: Formula: (and (not (= (mod v_~weak$$choice2~0_10 256) 0)) (= |v_Thread0_P1_#t~ite40_1| (mod v_~x$w_buff0_used~0_65 256))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_65} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_10, Thread0_P1_#t~ite40=|v_Thread0_P1_#t~ite40_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_65} AuxVars[] AssignedVars[Thread0_P1_#t~ite40] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite40|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [848] L752-14-->L753: Formula: (= v_~x$w_buff0_used~0_74 (ite (= |v_Thread0_P1_#t~ite40_2| 0) 0 1)) InVars {Thread0_P1_#t~ite40=|v_Thread0_P1_#t~ite40_2|} OutVars{Thread0_P1_#t~ite40=|v_Thread0_P1_#t~ite40_3|, Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_1|, Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_1|, Thread0_P1_#t~ite39=|v_Thread0_P1_#t~ite39_1|, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_74} AuxVars[] AssignedVars[Thread0_P1_#t~ite40, Thread0_P1_#t~ite37, Thread0_P1_#t~ite36, Thread0_P1_#t~ite39, Thread0_P1_#t~ite38, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [855] L753-->L753-14: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread0_P1_#t~ite45_1| v_~x$w_buff1_used~0_40)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_40} OutVars{Thread0_P1_#t~ite45=|v_Thread0_P1_#t~ite45_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_40, ~weak$$choice2~0=v_~weak$$choice2~0_12} AuxVars[] AssignedVars[Thread0_P1_#t~ite45] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite45|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [863] L753-14-->L754: Formula: (= v_~x$w_buff1_used~0_46 |v_Thread0_P1_#t~ite45_2|) InVars {Thread0_P1_#t~ite45=|v_Thread0_P1_#t~ite45_2|} OutVars{Thread0_P1_#t~ite41=|v_Thread0_P1_#t~ite41_1|, Thread0_P1_#t~ite42=|v_Thread0_P1_#t~ite42_1|, Thread0_P1_#t~ite45=|v_Thread0_P1_#t~ite45_3|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_46, Thread0_P1_#t~ite43=|v_Thread0_P1_#t~ite43_1|, Thread0_P1_#t~ite44=|v_Thread0_P1_#t~ite44_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite41, Thread0_P1_#t~ite42, Thread0_P1_#t~ite45, ~x$w_buff1_used~0, Thread0_P1_#t~ite43, Thread0_P1_#t~ite44] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [870] L754-->L754-14: Formula: (and (= |v_Thread0_P1_#t~ite50_1| v_~x$r_buff0_thd2~0_2) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_1} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_1, Thread0_P1_#t~ite50=|v_Thread0_P1_#t~ite50_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite50] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite50|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [878] L754-14-->L755: Formula: (= v_~x$r_buff0_thd2~0_10 |v_Thread0_P1_#t~ite50_2|) InVars {Thread0_P1_#t~ite50=|v_Thread0_P1_#t~ite50_2|} OutVars{Thread0_P1_#t~ite50=|v_Thread0_P1_#t~ite50_3|, Thread0_P1_#t~ite46=|v_Thread0_P1_#t~ite46_1|, Thread0_P1_#t~ite49=|v_Thread0_P1_#t~ite49_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_10, Thread0_P1_#t~ite47=|v_Thread0_P1_#t~ite47_1|, Thread0_P1_#t~ite48=|v_Thread0_P1_#t~ite48_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite50, Thread0_P1_#t~ite46, Thread0_P1_#t~ite49, ~x$r_buff0_thd2~0, Thread0_P1_#t~ite47, Thread0_P1_#t~ite48] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [885] L755-->L755-17: Formula: (and (= |v_Thread0_P1_#t~ite56_1| v_~x$r_buff1_thd2~0_6) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6} OutVars{Thread0_P1_#t~ite56=|v_Thread0_P1_#t~ite56_1|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_3} AuxVars[] AssignedVars[Thread0_P1_#t~ite56] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite56|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [893] L755-17-->L759: Formula: (and (= v_~x$r_buff1_thd2~0_14 |v_Thread0_P1_#t~ite56_2|) (= v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_1 |v_~#x~0.offset_6|) (= v_~__unbuffered_p1_EAX$read_delayed~0_1 1) (= v_~__unbuffered_p1_EAX$read_delayed_var~0.base_1 |v_~#x~0.base_6|) (= (select (select |v_#memory_int_7| |v_~#x~0.base_6|) |v_~#x~0.offset_6|) v_~__unbuffered_p1_EAX~0_1)) InVars {~#x~0.base=|v_~#x~0.base_6|, #memory_int=|v_#memory_int_7|, Thread0_P1_#t~ite56=|v_Thread0_P1_#t~ite56_2|, ~#x~0.offset=|v_~#x~0.offset_6|} OutVars{Thread0_P1_#t~ite52=|v_Thread0_P1_#t~ite52_1|, ~#x~0.offset=|v_~#x~0.offset_6|, ~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_1, Thread0_P1_#t~ite53=|v_Thread0_P1_#t~ite53_1|, Thread0_P1_#t~ite51=|v_Thread0_P1_#t~ite51_1|, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_14, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread0_P1_#t~mem57=|v_Thread0_P1_#t~mem57_1|, Thread0_P1_#t~ite56=|v_Thread0_P1_#t~ite56_3|, ~#x~0.base=|v_~#x~0.base_6|, #memory_int=|v_#memory_int_7|, ~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_1, Thread0_P1_#t~ite54=|v_Thread0_P1_#t~ite54_1|, Thread0_P1_#t~ite55=|v_Thread0_P1_#t~ite55_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite52, ~__unbuffered_p1_EAX~0, ~__unbuffered_p1_EAX$read_delayed~0, Thread0_P1_#t~ite53, Thread0_P1_#t~mem57, Thread0_P1_#t~ite51, Thread0_P1_#t~ite56, ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, ~x$r_buff1_thd2~0, Thread0_P1_#t~ite54, Thread0_P1_#t~ite55] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [900] L759-->L759-2: Formula: (and (not (= (mod v_~x$flush_delayed~0_2 256) 0)) (= |v_Thread0_P1_#t~ite59_1| v_~x$mem_tmp~0_2)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_2, ~x$mem_tmp~0=v_~x$mem_tmp~0_2} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_2, Thread0_P1_#t~ite59=|v_Thread0_P1_#t~ite59_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite59] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite59|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 [908] L759-2-->L766: Formula: (and (= |v_#memory_int_9| (store |v_#memory_int_10| |v_~#x~0.base_8| (store (select |v_#memory_int_10| |v_~#x~0.base_8|) |v_~#x~0.offset_8| |v_Thread0_P1_#t~ite59_3|))) (= v_~x$flush_delayed~0_4 0) (= v_~y~0_2 1)) InVars {#memory_int=|v_#memory_int_10|, ~#x~0.base=|v_~#x~0.base_8|, ~#x~0.offset=|v_~#x~0.offset_8|, Thread0_P1_#t~ite59=|v_Thread0_P1_#t~ite59_3|} OutVars{Thread0_P1_#t~mem58=|v_Thread0_P1_#t~mem58_2|, ~x$flush_delayed~0=v_~x$flush_delayed~0_4, ~#x~0.offset=|v_~#x~0.offset_8|, #memory_int=|v_#memory_int_9|, ~#x~0.base=|v_~#x~0.base_8|, ~y~0=v_~y~0_2, Thread0_P1_#t~ite59=|v_Thread0_P1_#t~ite59_4|} AuxVars[] AssignedVars[Thread0_P1_#t~mem58, ~x$flush_delayed~0, #memory_int, ~y~0, Thread0_P1_#t~ite59] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [914] L766-->L766-2: Formula: (or (= 0 (mod v_~x$r_buff0_thd2~0_22 256)) (= 0 (mod v_~x$w_buff0_used~0_37 256))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_22, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_37} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_22, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_37} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [772] P0ENTRY-->L4: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~x$w_buff0~0_1 1) (= v_Thread1_P0___VERIFIER_assert_~expression_1 |v_Thread1_P0___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_1 v_~x$w_buff0~0_2) (= v_~x$w_buff1_used~0_1 v_~x$w_buff0_used~0_2) (= v_~x$w_buff0_used~0_1 1) (= v_~__unbuffered_p0_EAX~0_1 v_~y~0_1) (= |v_Thread1_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff1_used~0_1 256))) (not (= (mod v_~x$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_2, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~y~0=v_~y~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_2} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_1, Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_1, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~x$w_buff1~0=v_~x$w_buff1~0_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_1, Thread1_P0___VERIFIER_assert_#in~expression=|v_Thread1_P0___VERIFIER_assert_#in~expression_1|, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, ~y~0=v_~y~0_1} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P0___VERIFIER_assert_~expression, ~__unbuffered_p0_EAX~0, Thread1_P0_~arg.offset, Thread1_P0___VERIFIER_assert_#in~expression, ~x$w_buff1~0, Thread1_P0_~arg.base, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [774] L4-->L4-3: Formula: (not (= 0 v_Thread1_P0___VERIFIER_assert_~expression_3)) InVars {Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} OutVars{Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [921] L766-2-->L766-4: Formula: (and (= |v_Thread0_P1_#t~ite61_3| |v_Thread0_P1_#t~mem60_2|) (or (= 0 (mod v_~x$r_buff1_thd2~0_18 256)) (= (mod v_~x$w_buff1_used~0_21 256) 0)) (= (select (select |v_#memory_int_11| |v_~#x~0.base_9|) |v_~#x~0.offset_9|) |v_Thread0_P1_#t~mem60_2|)) InVars {~#x~0.base=|v_~#x~0.base_9|, #memory_int=|v_#memory_int_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_21, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_18, ~#x~0.offset=|v_~#x~0.offset_9|} OutVars{~#x~0.offset=|v_~#x~0.offset_9|, Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_3|, ~#x~0.base=|v_~#x~0.base_9|, #memory_int=|v_#memory_int_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_21, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_18, Thread0_P1_#t~mem60=|v_Thread0_P1_#t~mem60_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite61, Thread0_P1_#t~mem60] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [777] L4-3-->L730: Formula: (and (= v_~x$r_buff0_thd1~0_1 1) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff1_thd2~0_1 v_~x$r_buff0_thd2~0_1) (= v_~x$r_buff1_thd1~0_1 v_~x$r_buff0_thd1~0_2)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_1, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~x$r_buff1_thd0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [778] L730-->L730-5: Formula: (and (not (= 0 (mod v_~x$w_buff0_used~0_3 256))) (= |v_Thread1_P0_#t~ite5_1| v_~x$w_buff0~0_3) (not (= 0 (mod v_~x$r_buff0_thd1~0_3 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [926] L766-4-->L766-5: Formula: (= |v_Thread0_P1_#t~ite62_4| |v_Thread0_P1_#t~ite61_4|) InVars {Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_4|} OutVars{Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_4|, Thread0_P1_#t~ite62=|v_Thread0_P1_#t~ite62_4|} AuxVars[] AssignedVars[Thread0_P1_#t~ite62] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite61|=0, |Thread0_P1_#t~ite62|=0, |Thread0_P1_#t~mem60|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [919] L766-5-->L767: Formula: (= |v_#memory_int_12| (store |v_#memory_int_13| |v_~#x~0.base_10| (store (select |v_#memory_int_13| |v_~#x~0.base_10|) |v_~#x~0.offset_10| |v_Thread0_P1_#t~ite62_2|))) InVars {#memory_int=|v_#memory_int_13|, ~#x~0.base=|v_~#x~0.base_10|, ~#x~0.offset=|v_~#x~0.offset_10|, Thread0_P1_#t~ite62=|v_Thread0_P1_#t~ite62_2|} OutVars{~#x~0.offset=|v_~#x~0.offset_10|, Thread0_P1_#t~ite61=|v_Thread0_P1_#t~ite61_1|, Thread0_P1_#t~ite62=|v_Thread0_P1_#t~ite62_3|, #memory_int=|v_#memory_int_12|, ~#x~0.base=|v_~#x~0.base_10|, Thread0_P1_#t~mem60=|v_Thread0_P1_#t~mem60_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite61, Thread0_P1_#t~ite62, #memory_int, Thread0_P1_#t~mem60] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [780] L730-5-->L731: Formula: (= |v_#memory_int_2| (store |v_#memory_int_3| |v_~#x~0.base_2| (store (select |v_#memory_int_3| |v_~#x~0.base_2|) |v_~#x~0.offset_2| |v_Thread1_P0_#t~ite5_2|))) InVars {#memory_int=|v_#memory_int_3|, ~#x~0.base=|v_~#x~0.base_2|, ~#x~0.offset=|v_~#x~0.offset_2|, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_2|} OutVars{Thread1_P0_#t~mem3=|v_Thread1_P0_#t~mem3_1|, ~#x~0.offset=|v_~#x~0.offset_2|, #memory_int=|v_#memory_int_2|, ~#x~0.base=|v_~#x~0.base_2|, Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_1|, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_3|} AuxVars[] AssignedVars[Thread1_P0_#t~mem3, #memory_int, Thread1_P0_#t~ite4, Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [925] L767-->L767-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_41 256)) (= 0 (mod v_~x$r_buff0_thd2~0_26 256))) (= |v_Thread0_P1_#t~ite63_2| v_~x$w_buff0_used~0_41)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_26, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_41} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_26, Thread0_P1_#t~ite63=|v_Thread0_P1_#t~ite63_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_41} AuxVars[] AssignedVars[Thread0_P1_#t~ite63] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite63|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [928] L767-2-->L768: Formula: (= v_~x$w_buff0_used~0_42 |v_Thread0_P1_#t~ite63_3|) InVars {Thread0_P1_#t~ite63=|v_Thread0_P1_#t~ite63_3|} OutVars{Thread0_P1_#t~ite63=|v_Thread0_P1_#t~ite63_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} AuxVars[] AssignedVars[Thread0_P1_#t~ite63, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [930] L768-->L768-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd2~0_28 256)) (= (mod v_~x$w_buff0_used~0_44 256) 0)) (= |v_Thread0_P1_#t~ite64_2| v_~x$w_buff1_used~0_24) (or (= (mod v_~x$r_buff1_thd2~0_21 256) 0) (= (mod v_~x$w_buff1_used~0_24 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_24, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_24, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, Thread0_P1_#t~ite64=|v_Thread0_P1_#t~ite64_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} AuxVars[] AssignedVars[Thread0_P1_#t~ite64] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite64|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [931] L768-2-->L769: Formula: (= v_~x$w_buff1_used~0_25 |v_Thread0_P1_#t~ite64_3|) InVars {Thread0_P1_#t~ite64=|v_Thread0_P1_#t~ite64_3|} OutVars{Thread0_P1_#t~ite64=|v_Thread0_P1_#t~ite64_4|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_25} AuxVars[] AssignedVars[Thread0_P1_#t~ite64, ~x$w_buff1_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [933] L769-->L769-2: Formula: (and (or (= (mod v_~x$r_buff0_thd2~0_30 256) 0) (= 0 (mod v_~x$w_buff0_used~0_46 256))) (= |v_Thread0_P1_#t~ite65_2| v_~x$r_buff0_thd2~0_30)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_30, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_46} OutVars{Thread0_P1_#t~ite65=|v_Thread0_P1_#t~ite65_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_30, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_46} AuxVars[] AssignedVars[Thread0_P1_#t~ite65] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite65|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [934] L769-2-->L770: Formula: (= v_~x$r_buff0_thd2~0_31 |v_Thread0_P1_#t~ite65_3|) InVars {Thread0_P1_#t~ite65=|v_Thread0_P1_#t~ite65_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_31, Thread0_P1_#t~ite65=|v_Thread0_P1_#t~ite65_4|} AuxVars[] AssignedVars[Thread0_P1_#t~ite65, ~x$r_buff0_thd2~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [936] L770-->L770-2: Formula: (and (= |v_Thread0_P1_#t~ite66_2| v_~x$r_buff1_thd2~0_23) (or (= 0 (mod v_~x$w_buff1_used~0_27 256)) (= (mod v_~x$r_buff1_thd2~0_23 256) 0)) (or (= (mod v_~x$w_buff0_used~0_49 256) 0) (= 0 (mod v_~x$r_buff0_thd2~0_33 256)))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_23, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_33, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_23, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, Thread0_P1_#t~ite66=|v_Thread0_P1_#t~ite66_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_33, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} AuxVars[] AssignedVars[Thread0_P1_#t~ite66] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite66|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 [937] L770-2-->L775: Formula: (and (= v_~x$r_buff1_thd2~0_24 |v_Thread0_P1_#t~ite66_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread0_P1_#t~ite66=|v_Thread0_P1_#t~ite66_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_24, Thread0_P1_#t~ite66=|v_Thread0_P1_#t~ite66_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, Thread0_P1_#t~ite66, ~__unbuffered_cnt~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [783] L731-->L731-2: Formula: (and (not (= 0 (mod v_~x$r_buff0_thd1~0_5 256))) (not (= (mod v_~x$w_buff0_used~0_5 256) 0)) (= |v_Thread1_P0_#t~ite6_1| 0)) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread1_P0_#t~ite6] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite6|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [786] L731-2-->L732: Formula: (= v_~x$w_buff0_used~0_7 |v_Thread1_P0_#t~ite6_3|) InVars {Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_3|} OutVars{Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread1_P0_#t~ite6, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [788] L732-->L732-2: Formula: (and (or (= 0 (mod v_~x$r_buff1_thd1~0_5 256)) (= 0 (mod v_~x$w_buff1_used~0_5 256))) (= |v_Thread1_P0_#t~ite7_2| v_~x$w_buff1_used~0_5) (or (= (mod v_~x$w_buff0_used~0_9 256) 0) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} AuxVars[] AssignedVars[Thread1_P0_#t~ite7] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite7|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [789] L732-2-->L733: Formula: (= v_~x$w_buff1_used~0_6 |v_Thread1_P0_#t~ite7_3|) InVars {Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_3|} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_4|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_6} AuxVars[] AssignedVars[Thread1_P0_#t~ite7, ~x$w_buff1_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [791] L733-->L733-2: Formula: (and (= |v_Thread1_P0_#t~ite8_2| v_~x$r_buff0_thd1~0_10) (or (= (mod v_~x$w_buff0_used~0_11 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} OutVars{Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread1_P0_#t~ite8] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite8|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [792] L733-2-->L734: Formula: (= v_~x$r_buff0_thd1~0_11 |v_Thread1_P0_#t~ite8_3|) InVars {Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_3|} OutVars{Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_11} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread1_P0_#t~ite8] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [794] L734-->L734-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_13 256)) (= (mod v_~x$r_buff0_thd1~0_13 256) 0)) (or (= (mod v_~x$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~x$w_buff1_used~0_8 256))) (= |v_Thread1_P0_#t~ite9_2| v_~x$r_buff1_thd1~0_7)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread1_P0_#t~ite9=|v_Thread1_P0_#t~ite9_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} AuxVars[] AssignedVars[Thread1_P0_#t~ite9] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite9|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 [795] L734-2-->L739: Formula: (and (= v_~x$r_buff1_thd1~0_8 |v_Thread1_P0_#t~ite9_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread1_P0_#t~ite9=|v_Thread1_P0_#t~ite9_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, Thread1_P0_#t~ite9=|v_Thread1_P0_#t~ite9_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread1_P0_#t~ite9] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [557] L791-1-->L795: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_6 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2, ULTIMATE.start_main_#t~nondet69=|v_ULTIMATE.start_main_#t~nondet69_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet69, ~main$tmp_guard0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [751] L795-->L797: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [523] L797-->L797-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_85 256)) (= (mod v_~x$r_buff0_thd0~0_4 256) 0)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_85} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_85} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [530] L797-2-->L797-4: Formula: (and (= |v_ULTIMATE.start_main_#t~mem70_2| (select (select |v_#memory_int_22| |v_~#x~0.base_15|) |v_~#x~0.offset_15|)) (= |v_ULTIMATE.start_main_#t~ite71_3| |v_ULTIMATE.start_main_#t~mem70_2|) (or (= 0 (mod v_~x$r_buff1_thd0~0_4 256)) (= (mod v_~x$w_buff1_used~0_49 256) 0))) InVars {~#x~0.base=|v_~#x~0.base_15|, #memory_int=|v_#memory_int_22|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_49, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ~#x~0.offset=|v_~#x~0.offset_15|} OutVars{ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_3|, ~#x~0.offset=|v_~#x~0.offset_15|, ~#x~0.base=|v_~#x~0.base_15|, #memory_int=|v_#memory_int_22|, ULTIMATE.start_main_#t~mem70=|v_ULTIMATE.start_main_#t~mem70_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_49, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite71, ULTIMATE.start_main_#t~mem70] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [514] L797-4-->L797-5: Formula: (= |v_ULTIMATE.start_main_#t~ite72_3| |v_ULTIMATE.start_main_#t~ite71_4|) InVars {ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_4|} OutVars{ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_4|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite72] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~ite72|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [518] L797-5-->L798: Formula: (= (store |v_#memory_int_24| |v_~#x~0.base_16| (store (select |v_#memory_int_24| |v_~#x~0.base_16|) |v_~#x~0.offset_16| |v_ULTIMATE.start_main_#t~ite72_5|)) |v_#memory_int_23|) InVars {#memory_int=|v_#memory_int_24|, ~#x~0.base=|v_~#x~0.base_16|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_5|, ~#x~0.offset=|v_~#x~0.offset_16|} OutVars{ULTIMATE.start_main_#t~ite71=|v_ULTIMATE.start_main_#t~ite71_5|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_4|, ~#x~0.offset=|v_~#x~0.offset_16|, #memory_int=|v_#memory_int_23|, ~#x~0.base=|v_~#x~0.base_16|, ULTIMATE.start_main_#t~mem70=|v_ULTIMATE.start_main_#t~mem70_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite71, ULTIMATE.start_main_#t~ite72, #memory_int, ULTIMATE.start_main_#t~mem70] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [595] L798-->L798-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite73_3| v_~x$w_buff0_used~0_87) (or (= (mod v_~x$r_buff0_thd0~0_6 256) 0) (= (mod v_~x$w_buff0_used~0_87 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_87} OutVars{ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_87} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite73] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite73|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [599] L798-2-->L799: Formula: (= v_~x$w_buff0_used~0_88 |v_ULTIMATE.start_main_#t~ite73_5|) InVars {ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_5|} OutVars{ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_88} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite73, ~x$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [711] L799-->L799-2: Formula: (and (or (= 0 (mod v_~x$w_buff1_used~0_51 256)) (= (mod v_~x$r_buff1_thd0~0_6 256) 0)) (= |v_ULTIMATE.start_main_#t~ite74_3| v_~x$w_buff1_used~0_51) (or (= (mod v_~x$r_buff0_thd0~0_8 256) 0) (= (mod v_~x$w_buff0_used~0_90 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_51, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_90} OutVars{ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_51, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_90} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite74] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite74|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [703] L799-2-->L800: Formula: (= v_~x$w_buff1_used~0_52 |v_ULTIMATE.start_main_#t~ite74_5|) InVars {ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_5|} OutVars{ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_4|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_52} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite74, ~x$w_buff1_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [659] L800-->L800-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_92 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_10 256))) (= |v_ULTIMATE.start_main_#t~ite75_3| v_~x$r_buff0_thd0~0_10)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_92} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_92} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite75] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite75|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [763] L800-2-->L801: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite75_5|) InVars {ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite75] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [737] L801-->L801-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite76_3| v_~x$r_buff1_thd0~0_8) (or (= 0 (mod v_~x$r_buff0_thd0~0_13 256)) (= 0 (mod v_~x$w_buff0_used~0_94 256))) (or (= 0 (mod v_~x$r_buff1_thd0~0_8 256)) (= 0 (mod v_~x$w_buff1_used~0_54 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_54, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_94} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_54, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_94} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite76] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite76|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [741] L801-2-->L805: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite76_5|) (= v_~weak$$choice1~0_6 (ite (= (+ |v_ULTIMATE.start_main_#t~nondet77.base_3| |v_ULTIMATE.start_main_#t~nondet77.offset_3|) 0) 0 1))) InVars {ULTIMATE.start_main_#t~nondet77.offset=|v_ULTIMATE.start_main_#t~nondet77.offset_3|, ULTIMATE.start_main_#t~nondet77.base=|v_ULTIMATE.start_main_#t~nondet77.base_3|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_5|} OutVars{~weak$$choice1~0=v_~weak$$choice1~0_6, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9, ULTIMATE.start_main_#t~nondet77.offset=|v_ULTIMATE.start_main_#t~nondet77.offset_2|, ULTIMATE.start_main_#t~nondet77.base=|v_ULTIMATE.start_main_#t~nondet77.base_2|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_4|} AuxVars[] AssignedVars[~weak$$choice1~0, ULTIMATE.start_main_#t~nondet77.offset, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet77.base, ULTIMATE.start_main_#t~ite76] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [689] L805-->L805-1: Formula: (not (= (mod v_~__unbuffered_p1_EAX$read_delayed~0_3 256) 0)) InVars {~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_3} OutVars{~__unbuffered_p1_EAX$read_delayed~0=v_~__unbuffered_p1_EAX$read_delayed~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [671] L805-1-->L805-3: Formula: (and (= |v_ULTIMATE.start_main_#t~ite79_2| |v_ULTIMATE.start_main_#t~mem78_2|) (not (= 0 (mod v_~weak$$choice1~0_7 256))) (= |v_ULTIMATE.start_main_#t~mem78_2| (select (select |v_#memory_int_25| v_~__unbuffered_p1_EAX$read_delayed_var~0.base_3) v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_3))) InVars {~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_3, #memory_int=|v_#memory_int_25|, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_3, ~weak$$choice1~0=v_~weak$$choice1~0_7} OutVars{ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_2|, ~weak$$choice1~0=v_~weak$$choice1~0_7, ~__unbuffered_p1_EAX$read_delayed_var~0.base=v_~__unbuffered_p1_EAX$read_delayed_var~0.base_3, #memory_int=|v_#memory_int_25|, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=v_~__unbuffered_p1_EAX$read_delayed_var~0.offset_3, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite79] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [677] L805-3-->L805-5: Formula: (= |v_ULTIMATE.start_main_#t~ite80_2| |v_ULTIMATE.start_main_#t~ite79_4|) InVars {ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_4|} OutVars{ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_2|, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite80] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~ite80|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [683] L805-5-->L808: Formula: (and (= v_~main$tmp_guard1~0_2 (ite (= 0 (ite (not (and (= 1 v_~__unbuffered_p1_EAX~0_5) (= v_~__unbuffered_p0_EAX~0_3 1))) 1 0)) 0 1)) (= v_~__unbuffered_p1_EAX~0_5 |v_ULTIMATE.start_main_#t~ite80_5|)) InVars {ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_5|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3} OutVars{ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_3|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_5, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem78, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_#t~ite80, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite79] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [521] L808-->L808-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [526] L808-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [551] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [549] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 [545] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); srcloc: L693 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); srcloc: L693-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0.base, main_~#t1925~0.offset, main_~#t1926~0.base, main_~#t1926~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1925~0.base, main_~#t1925~0.offset := #Ultimate.alloc(4); srcloc: L788 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1925~0.base, main_~#t1925~0.offset, 4); srcloc: L788-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1926~0.base, main_~#t1926~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1926~0.base, main_~#t1926~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1);havoc #t~nondet12.base, #t~nondet12.offset;~x$flush_delayed~0 := ~weak$$choice2~0;call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4);~x$mem_tmp~0 := #t~mem13;havoc #t~mem13;~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1);havoc #t~nondet14.base, #t~nondet14.offset; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 == ~x$w_buff0_used~0 % 256;call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite25 := #t~mem15; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P1_#t~mem15|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4);havoc #t~mem16;havoc #t~mem15;havoc #t~ite18;havoc #t~ite17;havoc #t~ite22;havoc #t~ite19;havoc #t~ite24;havoc #t~ite23;havoc #t~ite21;havoc #t~mem20;havoc #t~ite25; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite30 := ~x$w_buff0~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite30|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0~0 := #t~ite30;havoc #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite30;havoc #t~ite29; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite35 := ~x$w_buff1~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1~0 := #t~ite35;havoc #t~ite35;havoc #t~ite34;havoc #t~ite31;havoc #t~ite32;havoc #t~ite33; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~x$w_buff0_used~0 % 256; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite40|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1);havoc #t~ite38;havoc #t~ite37;havoc #t~ite39;havoc #t~ite36;havoc #t~ite40; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite45 := ~x$w_buff1_used~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite45|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1_used~0 := #t~ite45;havoc #t~ite41;havoc #t~ite44;havoc #t~ite43;havoc #t~ite42;havoc #t~ite45; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite50 := ~x$r_buff0_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite50|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff0_thd2~0 := #t~ite50;havoc #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite50;havoc #t~ite46; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite56 := ~x$r_buff1_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite56|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd2~0 := #t~ite56;havoc #t~ite52;havoc #t~ite54;havoc #t~ite56;havoc #t~ite55;havoc #t~ite51;havoc #t~ite53;~__unbuffered_p1_EAX$read_delayed~0 := 1;~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset;call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4);~__unbuffered_p1_EAX~0 := #t~mem57;havoc #t~mem57; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~x$flush_delayed~0 % 256;#t~ite59 := ~x$mem_tmp~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite59|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4);havoc #t~mem58;havoc #t~ite59;~x$flush_delayed~0 := 0;~y~0 := 1; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~__unbuffered_p0_EAX~0 := ~y~0;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite61 := #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 #t~ite62 := #t~ite61; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~ite62|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite62;havoc #t~ite61;havoc #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite5;havoc #t~mem3;havoc #t~ite4; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite63 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite63|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite63;havoc #t~ite63; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite64 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite64|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite64;havoc #t~ite64; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite65 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite65|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite65;havoc #t~ite65; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite66 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite66|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite66;havoc #t~ite66;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite6 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite7 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite8 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite8;havoc #t~ite8; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite9 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite9|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite9;havoc #t~ite9;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc main_#t~nondet69;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4);main_#t~ite71 := main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite72 := main_#t~ite71; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~ite72|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4);havoc main_#t~ite71;havoc main_#t~ite72;havoc main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite73 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite73|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite73;havoc main_#t~ite73; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite74 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite74|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite74;havoc main_#t~ite74; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite75|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite75;havoc main_#t~ite75; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite76|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite76;havoc main_#t~ite76;~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1);havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~weak$$choice1~0 % 256;call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4);main_#t~ite79 := main_#t~mem78; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite80 := main_#t~ite79; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~ite80|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80;havoc main_#t~ite79;havoc main_#t~ite80;havoc main_#t~mem78;~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); srcloc: L693 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 SUMMARY for call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); srcloc: L693-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0.base, main_~#t1925~0.offset, main_~#t1926~0.base, main_~#t1926~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1925~0.base, main_~#t1925~0.offset := #Ultimate.alloc(4); srcloc: L788 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1925~0.base, main_~#t1925~0.offset, 4); srcloc: L788-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1926~0.base, main_~#t1926~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1926~0.base, main_~#t1926~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1);havoc #t~nondet12.base, #t~nondet12.offset;~x$flush_delayed~0 := ~weak$$choice2~0;call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4);~x$mem_tmp~0 := #t~mem13;havoc #t~mem13;~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1);havoc #t~nondet14.base, #t~nondet14.offset; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 == ~x$w_buff0_used~0 % 256;call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite25 := #t~mem15; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P1_#t~mem15|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4);havoc #t~mem16;havoc #t~mem15;havoc #t~ite18;havoc #t~ite17;havoc #t~ite22;havoc #t~ite19;havoc #t~ite24;havoc #t~ite23;havoc #t~ite21;havoc #t~mem20;havoc #t~ite25; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite30 := ~x$w_buff0~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite30|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0~0 := #t~ite30;havoc #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite30;havoc #t~ite29; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite35 := ~x$w_buff1~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1~0 := #t~ite35;havoc #t~ite35;havoc #t~ite34;havoc #t~ite31;havoc #t~ite32;havoc #t~ite33; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~x$w_buff0_used~0 % 256; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite40|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1);havoc #t~ite38;havoc #t~ite37;havoc #t~ite39;havoc #t~ite36;havoc #t~ite40; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite45 := ~x$w_buff1_used~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite45|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$w_buff1_used~0 := #t~ite45;havoc #t~ite41;havoc #t~ite44;havoc #t~ite43;havoc #t~ite42;havoc #t~ite45; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite50 := ~x$r_buff0_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite50|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff0_thd2~0 := #t~ite50;havoc #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite50;havoc #t~ite46; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite56 := ~x$r_buff1_thd2~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite56|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd2~0 := #t~ite56;havoc #t~ite52;havoc #t~ite54;havoc #t~ite56;havoc #t~ite55;havoc #t~ite51;havoc #t~ite53;~__unbuffered_p1_EAX$read_delayed~0 := 1;~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset;call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4);~__unbuffered_p1_EAX~0 := #t~mem57;havoc #t~mem57; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 assume 0 != ~x$flush_delayed~0 % 256;#t~ite59 := ~x$mem_tmp~0; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite59|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4);havoc #t~mem58;havoc #t~ite59;~x$flush_delayed~0 := 0;~y~0 := 1; VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~__unbuffered_p0_EAX~0 := ~y~0;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4);#t~ite61 := #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 #t~ite62 := #t~ite61; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite61|=0, |P1_#t~ite62|=0, |P1_#t~mem60|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite62;havoc #t~ite61;havoc #t~mem60; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4);havoc #t~ite5;havoc #t~mem3;havoc #t~ite4; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite63 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite63|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite63;havoc #t~ite63; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite64 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite64|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite64;havoc #t~ite64; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite65 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite65|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite65;havoc #t~ite65; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite66 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite66|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite66;havoc #t~ite66;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite6 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite7 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite8 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite8;havoc #t~ite8; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite9 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite9|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite9;havoc #t~ite9;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc main_#t~nondet69;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4);main_#t~ite71 := main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite72 := main_#t~ite71; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite71|=1, |ULTIMATE.start_main_#t~ite72|=1, |ULTIMATE.start_main_#t~mem70|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4);havoc main_#t~ite71;havoc main_#t~ite72;havoc main_#t~mem70; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite73 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite73|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite73;havoc main_#t~ite73; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite74 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite74|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite74;havoc main_#t~ite74; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite75|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite75;havoc main_#t~ite75; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite76|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite76;havoc main_#t~ite76;~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1);havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 != ~weak$$choice1~0 % 256;call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4);main_#t~ite79 := main_#t~mem78; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 main_#t~ite80 := main_#t~ite79; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite79|=1, |ULTIMATE.start_main_#t~ite80|=1, |ULTIMATE.start_main_#t~mem78|=1, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80;havoc main_#t~ite79;havoc main_#t~ite80;havoc main_#t~mem78;~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1925~0.base|=7, |ULTIMATE.start_main_~#t1925~0.offset|=0, |ULTIMATE.start_main_~#t1926~0.base|=5, |ULTIMATE.start_main_~#t1926~0.offset|=0, |~#x~0.base|=6, |~#x~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0.base, main_~#t1925~0.offset, main_~#t1926~0.base, main_~#t1926~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t1925~0.base, main_~#t1925~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t1925~0.base, main_~#t1925~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t1926~0.base, main_~#t1926~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t1926~0.base, main_~#t1926~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4); [L759] 0 havoc #t~mem58; [L759] 0 havoc #t~ite59; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L766] 0 call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4); [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; [L730] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L731] 1 #t~ite6 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L797] -1 call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1); [L804] -1 havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~weak$$choice1~0 % 256; [L805] -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite79; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0.base, main_~#t1925~0.offset, main_~#t1926~0.base, main_~#t1926~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t1925~0.base, main_~#t1925~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t1925~0.base, main_~#t1925~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t1926~0.base, main_~#t1926~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t1926~0.base, main_~#t1926~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0.base, main_~#t1925~0.offset, main_~#t1926~0.base, main_~#t1926~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t1925~0.base, main_~#t1925~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t1925~0.base, main_~#t1925~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t1926~0.base, main_~#t1926~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t1926~0.base, main_~#t1926~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4); [L759] 0 havoc #t~mem58; [L759] 0 havoc #t~ite59; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L766] 0 call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4); [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; [L730] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L731] 1 #t~ite6 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L797] -1 call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1); [L804] -1 havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~weak$$choice1~0 % 256; [L805] -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite79; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call ~#x~0.base, ~#x~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] -1 call write~init~int(0, ~#x~0.base, ~#x~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77.base, main_#t~nondet77.offset, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0.base, main_~#t1925~0.offset, main_~#t1926~0.base, main_~#t1926~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] -1 call main_~#t1925~0.base, main_~#t1925~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 call write~int(0, main_~#t1925~0.base, main_~#t1925~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] -1 call main_~#t1926~0.base, main_~#t1926~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] -1 call write~int(1, main_~#t1926~0.base, main_~#t1926~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L744] 0 havoc #t~nondet11.base, #t~nondet11.offset; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12.base + #t~nondet12.offset then 0 else 1); [L745] 0 havoc #t~nondet12.base, #t~nondet12.offset; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] 0 call #t~mem13 := read~int(~#x~0.base, ~#x~0.offset, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14.base + #t~nondet14.offset then 0 else 1); [L748] 0 havoc #t~nondet14.base, #t~nondet14.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 assume 0 == ~x$w_buff0_used~0 % 256; [L749] 0 call #t~mem15 := read~int(~#x~0.base, ~#x~0.offset, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~mem15=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] 0 call write~int(#t~ite25, ~#x~0.base, ~#x~0.offset, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 assume 0 != ~weak$$choice2~0 % 256; [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 assume 0 != ~weak$$choice2~0 % 256; [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 assume 0 != ~weak$$choice2~0 % 256; [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 assume 0 != ~weak$$choice2~0 % 256; [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite45=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 assume 0 != ~weak$$choice2~0 % 256; [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 assume 0 != ~weak$$choice2~0 % 256; [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=0, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset := ~#x~0.base, ~#x~0.offset; [L758] 0 call #t~mem57 := read~int(~#x~0.base, ~#x~0.offset, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 assume 0 != ~x$flush_delayed~0 % 256; [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite59=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] 0 call write~int(#t~ite59, ~#x~0.base, ~#x~0.offset, 4); [L759] 0 havoc #t~mem58; [L759] 0 havoc #t~ite59; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] 1 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L766] 0 call #t~mem60 := read~int(~#x~0.base, ~#x~0.offset, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 call write~int(#t~ite62, ~#x~0.base, ~#x~0.offset, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] 1 call write~int(#t~ite5, ~#x~0.base, ~#x~0.offset, 4); [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; [L730] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L731] 1 #t~ite6 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L797] -1 call main_#t~mem70 := read~int(~#x~0.base, ~#x~0.offset, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 call write~int(main_#t~ite72, ~#x~0.base, ~#x~0.offset, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77.base + main_#t~nondet77.offset then 0 else 1); [L804] -1 havoc main_#t~nondet77.base, main_#t~nondet77.offset; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 assume 0 != ~weak$$choice1~0 % 256; [L805] -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0.base, ~__unbuffered_p1_EAX$read_delayed_var~0.offset, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite79; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0.base=7, main_~#t1925~0.offset=0, main_~#t1926~0.base=5, main_~#t1926~0.offset=0, ~#x~0.base=6, ~#x~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0.base=6, ~__unbuffered_p1_EAX$read_delayed_var~0.offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0, main_~#t1926~0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call main_~#t1925~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, main_~#t1925~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call main_~#t1926~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, main_~#t1926~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~mem58; [L759] 0 havoc #t~ite59; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; [L730] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call main_#t~mem70 := read~int(~#x~0, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(main_#t~ite72, ~#x~0, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77!base + main_#t~nondet77!offset then 0 else 1); [L804] -1 havoc main_#t~nondet77; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite79; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet68, main_#t~nondet69, main_#t~ite72, main_#t~ite71, main_#t~mem70, main_#t~ite73, main_#t~ite74, main_#t~ite75, main_#t~ite76, main_#t~nondet77, main_#t~ite80, main_#t~ite79, main_#t~mem78, main_~#t1925~0, main_~#t1926~0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call main_~#t1925~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, main_~#t1925~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc main_#t~nondet68; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call main_~#t1926~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, main_~#t1926~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~mem58; [L759] 0 havoc #t~ite59; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L723] 1 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 1 havoc __VERIFIER_assert_~expression; [L4] 1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, #t~ite61=0, #t~ite62=0, #t~mem60=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; [L730] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite9=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc main_#t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call main_#t~mem70 := read~int(~#x~0, 4); [L797] -1 main_#t~ite71 := main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~mem70=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 main_#t~ite72 := main_#t~ite71; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite71=1, main_#t~ite72=1, main_#t~mem70=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(main_#t~ite72, ~#x~0, 4); [L797] -1 havoc main_#t~ite71; [L797] -1 havoc main_#t~ite72; [L797] -1 havoc main_#t~mem70; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 main_#t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite73=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := main_#t~ite73; [L798] -1 havoc main_#t~ite73; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 main_#t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite74=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := main_#t~ite74; [L799] -1 havoc main_#t~ite74; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite75=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := main_#t~ite75; [L800] -1 havoc main_#t~ite75; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite76=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := main_#t~ite76; [L801] -1 havoc main_#t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == main_#t~nondet77!base + main_#t~nondet77!offset then 0 else 1); [L804] -1 havoc main_#t~nondet77; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call main_#t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 main_#t~ite79 := main_#t~mem78; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~mem78=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 main_#t~ite80 := main_#t~ite79; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite79=1, main_#t~ite80=1, main_#t~mem78=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := main_#t~ite80; [L805] -1 havoc main_#t~ite79; [L805] -1 havoc main_#t~ite80; [L805] -1 havoc main_#t~mem78; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t1925~0!base=7, main_~#t1925~0!offset=0, main_~#t1926~0!base=5, main_~#t1926~0!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call ~#t1925~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, ~#t1925~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc #t~nondet68; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call ~#t1926~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, ~#t1926~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~mem58; [L759] 0 havoc #t~ite59; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L4] 1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~ite62=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; [L730] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc #t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call #t~mem70 := read~int(~#x~0, 4); [L797] -1 #t~ite71 := #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 #t~ite72 := #t~ite71; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(#t~ite72, ~#x~0, 4); [L797] -1 havoc #t~ite71; [L797] -1 havoc #t~ite72; [L797] -1 havoc #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 #t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := #t~ite73; [L798] -1 havoc #t~ite73; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 #t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := #t~ite74; [L799] -1 havoc #t~ite74; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 #t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := #t~ite75; [L800] -1 havoc #t~ite75; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := #t~ite76; [L801] -1 havoc #t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == #t~nondet77!base + #t~nondet77!offset then 0 else 1); [L804] -1 havoc #t~nondet77; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call #t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 #t~ite79 := #t~mem78; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 #t~ite80 := #t~ite79; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := #t~ite80; [L805] -1 havoc #t~ite79; [L805] -1 havoc #t~ite80; [L805] -1 havoc #t~mem78; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EAX$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EAX$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX~0=0] [L678] -1 ~__unbuffered_p1_EAX$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EAX$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p1_EAX$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L681] -1 ~__unbuffered_p1_EAX$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX~0=0] [L682] -1 ~__unbuffered_p1_EAX$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX~0=0] [L683] -1 ~__unbuffered_p1_EAX$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX~0=0] [L684] -1 ~__unbuffered_p1_EAX$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L685] -1 ~__unbuffered_p1_EAX$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX~0=0] [L686] -1 ~__unbuffered_p1_EAX$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L687] -1 ~__unbuffered_p1_EAX$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX~0=0] [L688] -1 ~__unbuffered_p1_EAX$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L689] -1 ~__unbuffered_p1_EAX$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0] [L690] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L691] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call ~#x~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L693] FCALL -1 call write~init~int(0, ~#x~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L694] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0] [L695] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0] [L696] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0] [L697] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0] [L698] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0] [L699] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0] [L700] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0] [L701] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0] [L702] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0] [L703] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0] [L704] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0] [L705] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0] [L706] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0] [L707] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0] [L709] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L710] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L711] -1 ~weak$$choice1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L712] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L788] FCALL -1 call ~#t1925~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FCALL -1 call write~int(0, ~#t1925~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L789] -1 havoc #t~nondet68; VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L790] FCALL -1 call ~#t1926~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FCALL -1 call write~int(1, ~#t1926~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L791] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice1~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L741-L776] 0 ~arg := #in~arg; [L744] 0 ~weak$$choice0~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L744] 0 havoc #t~nondet11; [L745] 0 ~weak$$choice2~0 := (if 0 == #t~nondet12!base + #t~nondet12!offset then 0 else 1); [L745] 0 havoc #t~nondet12; [L746] 0 ~x$flush_delayed~0 := ~weak$$choice2~0; [L747] FCALL 0 call #t~mem13 := read~int(~#x~0, 4); [L747] 0 ~x$mem_tmp~0 := #t~mem13; [L747] 0 havoc #t~mem13; [L748] 0 ~weak$$choice1~0 := (if 0 == #t~nondet14!base + #t~nondet14!offset then 0 else 1); [L748] 0 havoc #t~nondet14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] COND TRUE 0 0 == ~x$w_buff0_used~0 % 256 [L749] FCALL 0 call #t~mem15 := read~int(~#x~0, 4); [L749] 0 #t~ite25 := #t~mem15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~mem15=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L749] FCALL 0 call write~int(#t~ite25, ~#x~0, 4); [L749] 0 havoc #t~mem16; [L749] 0 havoc #t~mem15; [L749] 0 havoc #t~ite18; [L749] 0 havoc #t~ite17; [L749] 0 havoc #t~ite22; [L749] 0 havoc #t~ite19; [L749] 0 havoc #t~ite24; [L749] 0 havoc #t~ite23; [L749] 0 havoc #t~ite21; [L749] 0 havoc #t~mem20; [L749] 0 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L750] 0 #t~ite30 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L750] 0 ~x$w_buff0~0 := #t~ite30; [L750] 0 havoc #t~ite28; [L750] 0 havoc #t~ite26; [L750] 0 havoc #t~ite27; [L750] 0 havoc #t~ite30; [L750] 0 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L751] 0 #t~ite35 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L751] 0 ~x$w_buff1~0 := #t~ite35; [L751] 0 havoc #t~ite35; [L751] 0 havoc #t~ite34; [L751] 0 havoc #t~ite31; [L751] 0 havoc #t~ite32; [L751] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L752] 0 #t~ite40 := ~x$w_buff0_used~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L752] 0 ~x$w_buff0_used~0 := (if 0 == #t~ite40 then 0 else 1); [L752] 0 havoc #t~ite38; [L752] 0 havoc #t~ite37; [L752] 0 havoc #t~ite39; [L752] 0 havoc #t~ite36; [L752] 0 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L753] 0 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite45=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L753] 0 ~x$w_buff1_used~0 := #t~ite45; [L753] 0 havoc #t~ite41; [L753] 0 havoc #t~ite44; [L753] 0 havoc #t~ite43; [L753] 0 havoc #t~ite42; [L753] 0 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L754] 0 #t~ite50 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L754] 0 ~x$r_buff0_thd2~0 := #t~ite50; [L754] 0 havoc #t~ite49; [L754] 0 havoc #t~ite48; [L754] 0 havoc #t~ite47; [L754] 0 havoc #t~ite50; [L754] 0 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L755] 0 #t~ite56 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=0, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=0, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L755] 0 ~x$r_buff1_thd2~0 := #t~ite56; [L755] 0 havoc #t~ite52; [L755] 0 havoc #t~ite54; [L755] 0 havoc #t~ite56; [L755] 0 havoc #t~ite55; [L755] 0 havoc #t~ite51; [L755] 0 havoc #t~ite53; [L756] 0 ~__unbuffered_p1_EAX$read_delayed~0 := 1; [L757] 0 ~__unbuffered_p1_EAX$read_delayed_var~0 := ~#x~0; [L758] FCALL 0 call #t~mem57 := read~int(~#x~0, 4); [L758] 0 ~__unbuffered_p1_EAX~0 := #t~mem57; [L758] 0 havoc #t~mem57; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] COND TRUE 0 0 != ~x$flush_delayed~0 % 256 [L759] 0 #t~ite59 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite59=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=0] [L759] FCALL 0 call write~int(#t~ite59, ~#x~0, 4); [L759] 0 havoc #t~mem58; [L759] 0 havoc #t~ite59; [L760] 0 ~x$flush_delayed~0 := 0; [L763] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L713-L740] 1 ~arg := #in~arg; [L716] 1 ~__unbuffered_p0_EAX~0 := ~y~0; [L719] 1 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 1 ~x$w_buff0~0 := 1; [L721] 1 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 1 ~x$w_buff0_used~0 := 1; [L4] 1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND FALSE 1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] COND FALSE 0 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L766] FCALL 0 call #t~mem60 := read~int(~#x~0, 4); [L766] 0 #t~ite61 := #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L724] 1 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 1 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 1 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 1 ~x$r_buff0_thd1~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L730] 1 #t~ite5 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] 0 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite61=0, #t~ite62=0, #t~mem60=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L766] FCALL 0 call write~int(#t~ite62, ~#x~0, 4); [L766] 0 havoc #t~ite62; [L766] 0 havoc #t~ite61; [L766] 0 havoc #t~mem60; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L730] FCALL 1 call write~int(#t~ite5, ~#x~0, 4); [L730] 1 havoc #t~ite5; [L730] 1 havoc #t~mem3; [L730] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L767] 0 #t~ite63 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite63=1, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L767] 0 ~x$w_buff0_used~0 := #t~ite63; [L767] 0 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L768] 0 #t~ite64 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite64=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L768] 0 ~x$w_buff1_used~0 := #t~ite64; [L768] 0 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L769] 0 #t~ite65 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite65=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L769] 0 ~x$r_buff0_thd2~0 := #t~ite65; [L769] 0 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L770] 0 #t~ite66 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite66=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L770] 0 ~x$r_buff1_thd2~0 := #t~ite66; [L770] 0 havoc #t~ite66; [L773] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] COND TRUE 1 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L731] 1 #t~ite6 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L731] 1 ~x$w_buff0_used~0 := #t~ite6; [L731] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L732] 1 #t~ite7 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L732] 1 ~x$w_buff1_used~0 := #t~ite7; [L732] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L733] 1 #t~ite8 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L733] 1 ~x$r_buff0_thd1~0 := #t~ite8; [L733] 1 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L734] 1 #t~ite9 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L734] 1 ~x$r_buff1_thd1~0 := #t~ite9; [L734] 1 havoc #t~ite9; [L737] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L791] -1 havoc #t~nondet69; [L793] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L795] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L797] FCALL -1 call #t~mem70 := read~int(~#x~0, 4); [L797] -1 #t~ite71 := #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] -1 #t~ite72 := #t~ite71; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L797] FCALL -1 call write~int(#t~ite72, ~#x~0, 4); [L797] -1 havoc #t~ite71; [L797] -1 havoc #t~ite72; [L797] -1 havoc #t~mem70; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L798] -1 #t~ite73 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L798] -1 ~x$w_buff0_used~0 := #t~ite73; [L798] -1 havoc #t~ite73; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L799] -1 #t~ite74 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L799] -1 ~x$w_buff1_used~0 := #t~ite74; [L799] -1 havoc #t~ite74; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L800] -1 #t~ite75 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L800] -1 ~x$r_buff0_thd0~0 := #t~ite75; [L800] -1 havoc #t~ite75; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite76 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L801] -1 ~x$r_buff1_thd0~0 := #t~ite76; [L801] -1 havoc #t~ite76; [L804] -1 ~weak$$choice1~0 := (if 0 == #t~nondet77!base + #t~nondet77!offset then 0 else 1); [L804] -1 havoc #t~nondet77; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~__unbuffered_p1_EAX$read_delayed~0 % 256 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] COND TRUE -1 0 != ~weak$$choice1~0 % 256 [L805] FCALL -1 call #t~mem78 := read~int(~__unbuffered_p1_EAX$read_delayed_var~0, 4); [L805] -1 #t~ite79 := #t~mem78; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 #t~ite80 := #t~ite79; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L805] -1 ~__unbuffered_p1_EAX~0 := #t~ite80; [L805] -1 havoc #t~ite79; [L805] -1 havoc #t~ite80; [L805] -1 havoc #t~mem78; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(1 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#x~0!base=6, ~#x~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p1_EAX$flush_delayed~0=0, ~__unbuffered_p1_EAX$mem_tmp~0=0, ~__unbuffered_p1_EAX$r_buff0_thd0~0=0, ~__unbuffered_p1_EAX$r_buff0_thd1~0=0, ~__unbuffered_p1_EAX$r_buff0_thd2~0=0, ~__unbuffered_p1_EAX$r_buff1_thd0~0=0, ~__unbuffered_p1_EAX$r_buff1_thd1~0=0, ~__unbuffered_p1_EAX$r_buff1_thd2~0=0, ~__unbuffered_p1_EAX$read_delayed_var~0!base=6, ~__unbuffered_p1_EAX$read_delayed_var~0!offset=0, ~__unbuffered_p1_EAX$read_delayed~0=1, ~__unbuffered_p1_EAX$w_buff0_used~0=0, ~__unbuffered_p1_EAX$w_buff0~0=0, ~__unbuffered_p1_EAX$w_buff1_used~0=0, ~__unbuffered_p1_EAX$w_buff1~0=0, ~__unbuffered_p1_EAX~0=1, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice1~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~y~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L676] -1 _Bool __unbuffered_p1_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0] [L677] -1 int __unbuffered_p1_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0] [L678] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0] [L679] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0] [L680] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0] [L681] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0] [L682] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0] [L683] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0] [L684] -1 _Bool __unbuffered_p1_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0] [L685] -1 int *__unbuffered_p1_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}] [L686] -1 int __unbuffered_p1_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0] [L687] -1 _Bool __unbuffered_p1_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0] [L688] -1 int __unbuffered_p1_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0] [L689] -1 _Bool __unbuffered_p1_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0] [L690] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0] [L691] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L693] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}] [L694] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0] [L695] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0] [L696] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L697] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L698] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L699] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L700] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L701] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L702] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L703] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L704] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L705] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L706] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L707] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L709] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L710] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L711] -1 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L712] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L788] -1 pthread_t t1925; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L789] FCALL, FORK -1 pthread_create(&t1925, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L790] -1 pthread_t t1926; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L791] FCALL, FORK -1 pthread_create(&t1926, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L744] 0 weak$$choice0 = __VERIFIER_nondet_pointer() [L745] 0 weak$$choice2 = __VERIFIER_nondet_pointer() [L746] 0 x$flush_delayed = weak$$choice2 [L747] EXPR 0 \read(x) [L747] 0 x$mem_tmp = x [L748] 0 weak$$choice1 = __VERIFIER_nondet_pointer() [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L749] EXPR 0 \read(x) [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) VAL [!x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x))))=0, \read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L749] 0 x = !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L750] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L750] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) [L751] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L751] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) [L752] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) [L753] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L754] EXPR 0 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] 0 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L755] EXPR 0 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] 0 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L756] 0 __unbuffered_p1_EAX$read_delayed = (_Bool)1 [L757] 0 __unbuffered_p1_EAX$read_delayed_var = &x [L758] EXPR 0 \read(x) [L758] 0 __unbuffered_p1_EAX = x [L759] EXPR 0 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L759] 0 x = x$flush_delayed ? x$mem_tmp : x [L760] 0 x$flush_delayed = (_Bool)0 [L763] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L716] 1 __unbuffered_p0_EAX = y [L719] 1 x$w_buff1 = x$w_buff0 [L720] 1 x$w_buff0 = 1 [L721] 1 x$w_buff1_used = x$w_buff0_used [L722] 1 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 1 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x [L766] EXPR 0 \read(x) [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L724] 1 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 1 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 1 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 1 x$r_buff0_thd1 = (_Bool)1 VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L730] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L730] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L767] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L768] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L769] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L769] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L770] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L770] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L773] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L732] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L732] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L734] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L737] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L793] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x [L797] EXPR -1 \read(x) [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L798] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L798] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L799] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L799] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L800] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L800] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L801] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L801] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L804] -1 weak$$choice1 = __VERIFIER_nondet_pointer() [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX [L805] EXPR -1 \read(*__unbuffered_p1_EAX$read_delayed_var) [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] -1 __unbuffered_p1_EAX = __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p1_EAX == 1) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] ----- [2018-11-22 21:44:04,152 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_dc06346c-44cb-454a-90e9-92af9c9eb6bd/bin-2019/utaipan/witness.graphml [2018-11-22 21:44:04,152 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-22 21:44:04,153 INFO L168 Benchmark]: Toolchain (without parser) took 46857.51 ms. Allocated memory was 1.0 GB in the beginning and 4.5 GB in the end (delta: 3.5 GB). Free memory was 957.6 MB in the beginning and 3.6 GB in the end (delta: -2.6 GB). Peak memory consumption was 849.9 MB. Max. memory is 11.5 GB. [2018-11-22 21:44:04,154 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 21:44:04,154 INFO L168 Benchmark]: CACSL2BoogieTranslator took 432.52 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -154.5 MB). Peak memory consumption was 35.8 MB. Max. memory is 11.5 GB. [2018-11-22 21:44:04,154 INFO L168 Benchmark]: Boogie Procedure Inliner took 32.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-22 21:44:04,154 INFO L168 Benchmark]: Boogie Preprocessor took 23.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-22 21:44:04,154 INFO L168 Benchmark]: RCFGBuilder took 588.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 63.8 MB). Peak memory consumption was 63.8 MB. Max. memory is 11.5 GB. [2018-11-22 21:44:04,154 INFO L168 Benchmark]: TraceAbstraction took 34796.91 ms. Allocated memory was 1.2 GB in the beginning and 4.5 GB in the end (delta: 3.3 GB). Free memory was 1.0 GB in the beginning and 3.8 GB in the end (delta: -2.7 GB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. [2018-11-22 21:44:04,154 INFO L168 Benchmark]: Witness Printer took 10979.77 ms. Allocated memory is still 4.5 GB. Free memory was 3.8 GB in the beginning and 3.6 GB in the end (delta: 203.4 MB). Peak memory consumption was 203.4 MB. Max. memory is 11.5 GB. [2018-11-22 21:44:04,156 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 432.52 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -154.5 MB). Peak memory consumption was 35.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 32.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 23.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 588.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 63.8 MB). Peak memory consumption was 63.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 34796.91 ms. Allocated memory was 1.2 GB in the beginning and 4.5 GB in the end (delta: 3.3 GB). Free memory was 1.0 GB in the beginning and 3.8 GB in the end (delta: -2.7 GB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. * Witness Printer took 10979.77 ms. Allocated memory is still 4.5 GB. Free memory was 3.8 GB in the beginning and 3.6 GB in the end (delta: 203.4 MB). Peak memory consumption was 203.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L676] -1 _Bool __unbuffered_p1_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0] [L677] -1 int __unbuffered_p1_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0] [L678] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0] [L679] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0] [L680] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0] [L681] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0] [L682] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0] [L683] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0] [L684] -1 _Bool __unbuffered_p1_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0] [L685] -1 int *__unbuffered_p1_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}] [L686] -1 int __unbuffered_p1_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0] [L687] -1 _Bool __unbuffered_p1_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0] [L688] -1 int __unbuffered_p1_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0] [L689] -1 _Bool __unbuffered_p1_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0] [L690] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0] [L691] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L693] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}] [L694] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0] [L695] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0] [L696] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L697] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L698] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L699] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L700] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L701] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L702] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L703] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L704] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L705] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L706] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L707] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L709] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L710] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L711] -1 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L712] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L788] -1 pthread_t t1925; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L789] FCALL, FORK -1 pthread_create(&t1925, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L790] -1 pthread_t t1926; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L791] FCALL, FORK -1 pthread_create(&t1926, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L744] 0 weak$$choice0 = __VERIFIER_nondet_pointer() [L745] 0 weak$$choice2 = __VERIFIER_nondet_pointer() [L746] 0 x$flush_delayed = weak$$choice2 [L747] EXPR 0 \read(x) [L747] 0 x$mem_tmp = x [L748] 0 weak$$choice1 = __VERIFIER_nondet_pointer() [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L749] EXPR 0 \read(x) [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) VAL [!x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x))))=0, \read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L749] 0 x = !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L750] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L750] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) [L751] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L751] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) [L752] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) [L753] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L754] EXPR 0 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] 0 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L755] EXPR 0 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] 0 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L756] 0 __unbuffered_p1_EAX$read_delayed = (_Bool)1 [L757] 0 __unbuffered_p1_EAX$read_delayed_var = &x [L758] EXPR 0 \read(x) [L758] 0 __unbuffered_p1_EAX = x [L759] EXPR 0 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L759] 0 x = x$flush_delayed ? x$mem_tmp : x [L760] 0 x$flush_delayed = (_Bool)0 [L763] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L716] 1 __unbuffered_p0_EAX = y [L719] 1 x$w_buff1 = x$w_buff0 [L720] 1 x$w_buff0 = 1 [L721] 1 x$w_buff1_used = x$w_buff0_used [L722] 1 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 1 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x [L766] EXPR 0 \read(x) [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L724] 1 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 1 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 1 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 1 x$r_buff0_thd1 = (_Bool)1 VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L730] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L730] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L767] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L768] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L769] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L769] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L770] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L770] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L773] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L732] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L732] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L734] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L737] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L793] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x [L797] EXPR -1 \read(x) [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L798] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L798] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L799] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L799] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L800] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L800] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L801] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L801] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L804] -1 weak$$choice1 = __VERIFIER_nondet_pointer() [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX [L805] EXPR -1 \read(*__unbuffered_p1_EAX$read_delayed_var) [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] -1 __unbuffered_p1_EAX = __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p1_EAX == 1) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 318 locations, 3 error locations. UNSAFE Result, 34.6s OverallTime, 40 OverallIterations, 1 TraceHistogramMax, 13.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 13318 SDtfs, 16029 SDslu, 31909 SDs, 0 SdLazy, 11815 SolverSat, 825 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 437 GetRequests, 103 SyntacticMatches, 34 SemanticMatches, 300 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 802 ImplicationChecksByTransitivity, 3.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=65314occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 9.1s AutomataMinimizationTime, 39 MinimizatonAttempts, 141520 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.7s InterpolantComputationTime, 3810 NumberOfCodeBlocks, 3810 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 3656 ConstructedInterpolants, 0 QuantifiedInterpolants, 1008669 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 39 InterpolantComputations, 39 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...