./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ee05cb2d66f71fb2277986b04bb223cfc634fed1 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ee05cb2d66f71fb2277986b04bb223cfc634fed1 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Result: TRUE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-22 22:07:31,043 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-22 22:07:31,044 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-22 22:07:31,051 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-22 22:07:31,051 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-22 22:07:31,052 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-22 22:07:31,052 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-22 22:07:31,054 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-22 22:07:31,055 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-22 22:07:31,055 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-22 22:07:31,056 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-22 22:07:31,056 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-22 22:07:31,057 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-22 22:07:31,057 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-22 22:07:31,058 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-22 22:07:31,058 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-22 22:07:31,059 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-22 22:07:31,060 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-22 22:07:31,061 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-22 22:07:31,062 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-22 22:07:31,063 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-22 22:07:31,063 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-22 22:07:31,065 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-22 22:07:31,065 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-22 22:07:31,065 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-22 22:07:31,065 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-22 22:07:31,066 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-22 22:07:31,066 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-22 22:07:31,067 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-22 22:07:31,067 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-22 22:07:31,068 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-22 22:07:31,068 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-22 22:07:31,068 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-22 22:07:31,068 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-22 22:07:31,069 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-22 22:07:31,070 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-22 22:07:31,070 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-22 22:07:31,077 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-22 22:07:31,077 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-22 22:07:31,078 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-22 22:07:31,078 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-22 22:07:31,078 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-22 22:07:31,078 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-22 22:07:31,078 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-22 22:07:31,078 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-22 22:07:31,078 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-22 22:07:31,079 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-22 22:07:31,079 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-22 22:07:31,079 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-22 22:07:31,079 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-22 22:07:31,079 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-22 22:07:31,080 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-22 22:07:31,080 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-22 22:07:31,080 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-22 22:07:31,080 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-22 22:07:31,080 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-22 22:07:31,080 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-22 22:07:31,080 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-22 22:07:31,081 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-22 22:07:31,081 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-22 22:07:31,081 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-22 22:07:31,081 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-22 22:07:31,081 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-22 22:07:31,081 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-22 22:07:31,081 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-22 22:07:31,081 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-22 22:07:31,082 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 22:07:31,082 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-22 22:07:31,082 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-22 22:07:31,082 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-22 22:07:31,082 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-22 22:07:31,082 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-22 22:07:31,082 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-22 22:07:31,083 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-22 22:07:31,083 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ee05cb2d66f71fb2277986b04bb223cfc634fed1 [2018-11-22 22:07:31,106 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-22 22:07:31,115 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-22 22:07:31,118 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-22 22:07:31,119 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-22 22:07:31,119 INFO L276 PluginConnector]: CDTParser initialized [2018-11-22 22:07:31,120 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-22 22:07:31,164 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/bf2ea8a0f/dbdf4be750164b7ca4eed300ed353461/FLAGcfb93377b [2018-11-22 22:07:31,500 INFO L307 CDTParser]: Found 1 translation units. [2018-11-22 22:07:31,501 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-22 22:07:31,507 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/bf2ea8a0f/dbdf4be750164b7ca4eed300ed353461/FLAGcfb93377b [2018-11-22 22:07:31,925 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/bf2ea8a0f/dbdf4be750164b7ca4eed300ed353461 [2018-11-22 22:07:31,926 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-22 22:07:31,927 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-22 22:07:31,928 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-22 22:07:31,928 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-22 22:07:31,930 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-22 22:07:31,931 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 10:07:31" (1/1) ... [2018-11-22 22:07:31,932 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58152ec2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:31, skipping insertion in model container [2018-11-22 22:07:31,932 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 10:07:31" (1/1) ... [2018-11-22 22:07:31,940 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-22 22:07:31,960 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-22 22:07:32,084 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 22:07:32,086 INFO L191 MainTranslator]: Completed pre-run [2018-11-22 22:07:32,109 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 22:07:32,117 INFO L195 MainTranslator]: Completed translation [2018-11-22 22:07:32,118 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32 WrapperNode [2018-11-22 22:07:32,118 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-22 22:07:32,118 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-22 22:07:32,118 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-22 22:07:32,118 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-22 22:07:32,123 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,128 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,132 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-22 22:07:32,132 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-22 22:07:32,132 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-22 22:07:32,132 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-22 22:07:32,174 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,174 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,174 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,175 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,178 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,182 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,183 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... [2018-11-22 22:07:32,184 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-22 22:07:32,184 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-22 22:07:32,184 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-22 22:07:32,184 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-22 22:07:32,185 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 22:07:32,219 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-22 22:07:32,219 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-22 22:07:32,219 INFO L130 BoogieDeclarations]: Found specification of procedure base2flt [2018-11-22 22:07:32,219 INFO L138 BoogieDeclarations]: Found implementation of procedure base2flt [2018-11-22 22:07:32,220 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-22 22:07:32,220 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-22 22:07:32,220 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-22 22:07:32,220 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-22 22:07:32,220 INFO L130 BoogieDeclarations]: Found specification of procedure addflt [2018-11-22 22:07:32,220 INFO L138 BoogieDeclarations]: Found implementation of procedure addflt [2018-11-22 22:07:32,220 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-22 22:07:32,220 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-22 22:07:32,420 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-22 22:07:32,420 INFO L280 CfgBuilder]: Removed 2 assue(true) statements. [2018-11-22 22:07:32,420 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 10:07:32 BoogieIcfgContainer [2018-11-22 22:07:32,420 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-22 22:07:32,421 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-22 22:07:32,421 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-22 22:07:32,423 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-22 22:07:32,423 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.11 10:07:31" (1/3) ... [2018-11-22 22:07:32,423 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6983ff3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 10:07:32, skipping insertion in model container [2018-11-22 22:07:32,423 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:32" (2/3) ... [2018-11-22 22:07:32,424 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6983ff3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 10:07:32, skipping insertion in model container [2018-11-22 22:07:32,424 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 10:07:32" (3/3) ... [2018-11-22 22:07:32,425 INFO L112 eAbstractionObserver]: Analyzing ICFG soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-22 22:07:32,431 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-22 22:07:32,436 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-22 22:07:32,446 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-22 22:07:32,465 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-22 22:07:32,465 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-22 22:07:32,465 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-22 22:07:32,466 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-22 22:07:32,466 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-22 22:07:32,466 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-22 22:07:32,466 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-22 22:07:32,466 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-22 22:07:32,480 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states. [2018-11-22 22:07:32,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-22 22:07:32,485 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:32,485 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:32,486 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:32,489 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:32,490 INFO L82 PathProgramCache]: Analyzing trace with hash 1457053844, now seen corresponding path program 1 times [2018-11-22 22:07:32,491 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:32,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:32,527 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:32,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:32,527 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:32,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:32,769 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:32,771 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:32,771 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-22 22:07:32,772 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 35 with the following transitions: [2018-11-22 22:07:32,773 INFO L202 CegarAbsIntRunner]: [0], [1], [4], [62], [63], [67], [69], [71], [73], [94], [97], [105], [129], [132], [134], [140], [141], [142], [144], [145], [146], [147], [148], [149], [150], [156] [2018-11-22 22:07:32,797 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-22 22:07:32,797 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-22 22:07:32,893 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-22 22:07:32,894 INFO L272 AbstractInterpreter]: Visited 21 different actions 29 times. Never merged. Never widened. Performed 79 root evaluator evaluations with a maximum evaluation depth of 3. Performed 79 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 19 variables. [2018-11-22 22:07:32,904 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:32,904 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-22 22:07:32,964 INFO L227 lantSequenceWeakener]: Weakened 16 states. On average, predicates are now at 62.81% of their original sizes. [2018-11-22 22:07:32,965 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-22 22:07:33,042 INFO L415 sIntCurrentIteration]: We unified 33 AI predicates to 33 [2018-11-22 22:07:33,042 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-22 22:07:33,042 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-22 22:07:33,043 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [9] total 20 [2018-11-22 22:07:33,043 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 22:07:33,046 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-22 22:07:33,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-22 22:07:33,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2018-11-22 22:07:33,050 INFO L87 Difference]: Start difference. First operand 56 states. Second operand 13 states. [2018-11-22 22:07:33,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:07:33,549 INFO L93 Difference]: Finished difference Result 146 states and 218 transitions. [2018-11-22 22:07:33,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-22 22:07:33,550 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 34 [2018-11-22 22:07:33,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:07:33,558 INFO L225 Difference]: With dead ends: 146 [2018-11-22 22:07:33,558 INFO L226 Difference]: Without dead ends: 85 [2018-11-22 22:07:33,562 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 38 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=254, Unknown=0, NotChecked=0, Total=306 [2018-11-22 22:07:33,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-11-22 22:07:33,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 71. [2018-11-22 22:07:33,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-11-22 22:07:33,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 91 transitions. [2018-11-22 22:07:33,598 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 91 transitions. Word has length 34 [2018-11-22 22:07:33,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:07:33,599 INFO L480 AbstractCegarLoop]: Abstraction has 71 states and 91 transitions. [2018-11-22 22:07:33,599 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-22 22:07:33,599 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 91 transitions. [2018-11-22 22:07:33,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-22 22:07:33,602 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:33,602 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:33,602 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:33,602 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:33,603 INFO L82 PathProgramCache]: Analyzing trace with hash 1691151941, now seen corresponding path program 1 times [2018-11-22 22:07:33,603 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:33,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:33,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:33,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:33,604 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:33,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:33,741 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:33,742 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:33,742 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-22 22:07:33,742 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 39 with the following transitions: [2018-11-22 22:07:33,742 INFO L202 CegarAbsIntRunner]: [0], [1], [4], [6], [35], [44], [48], [54], [62], [63], [67], [69], [71], [73], [94], [97], [105], [129], [132], [134], [140], [141], [142], [144], [145], [146], [147], [148], [149], [150], [156] [2018-11-22 22:07:33,745 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-22 22:07:33,745 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-22 22:07:33,804 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-22 22:07:33,804 INFO L272 AbstractInterpreter]: Visited 31 different actions 84 times. Merged at 7 different actions 17 times. Never widened. Performed 279 root evaluator evaluations with a maximum evaluation depth of 6. Performed 279 inverse root evaluator evaluations with a maximum inverse evaluation depth of 6. Never found a fixpoint. Largest state had 19 variables. [2018-11-22 22:07:33,809 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:33,810 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-22 22:07:33,810 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:33,810 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:07:33,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:33,827 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-22 22:07:33,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:33,853 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:07:33,913 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-22 22:07:33,913 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:07:34,054 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:34,070 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-22 22:07:34,070 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11, 9] total 19 [2018-11-22 22:07:34,070 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-22 22:07:34,071 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-22 22:07:34,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-22 22:07:34,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=298, Unknown=0, NotChecked=0, Total=342 [2018-11-22 22:07:34,073 INFO L87 Difference]: Start difference. First operand 71 states and 91 transitions. Second operand 12 states. [2018-11-22 22:07:34,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:07:34,371 INFO L93 Difference]: Finished difference Result 144 states and 192 transitions. [2018-11-22 22:07:34,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-22 22:07:34,372 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2018-11-22 22:07:34,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:07:34,373 INFO L225 Difference]: With dead ends: 144 [2018-11-22 22:07:34,373 INFO L226 Difference]: Without dead ends: 118 [2018-11-22 22:07:34,374 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 66 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=102, Invalid=600, Unknown=0, NotChecked=0, Total=702 [2018-11-22 22:07:34,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-11-22 22:07:34,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 93. [2018-11-22 22:07:34,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-11-22 22:07:34,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 119 transitions. [2018-11-22 22:07:34,383 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 119 transitions. Word has length 38 [2018-11-22 22:07:34,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:07:34,383 INFO L480 AbstractCegarLoop]: Abstraction has 93 states and 119 transitions. [2018-11-22 22:07:34,383 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-22 22:07:34,383 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 119 transitions. [2018-11-22 22:07:34,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-22 22:07:34,384 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:34,385 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:34,385 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:34,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:34,385 INFO L82 PathProgramCache]: Analyzing trace with hash 1748410243, now seen corresponding path program 1 times [2018-11-22 22:07:34,385 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:34,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:34,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:34,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:34,386 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:34,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:34,511 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:34,511 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:34,511 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-22 22:07:34,511 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 39 with the following transitions: [2018-11-22 22:07:34,511 INFO L202 CegarAbsIntRunner]: [0], [1], [4], [6], [35], [44], [48], [54], [62], [63], [67], [69], [71], [73], [94], [99], [105], [129], [132], [134], [140], [141], [142], [144], [145], [146], [147], [148], [149], [150], [156] [2018-11-22 22:07:34,513 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-22 22:07:34,513 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-22 22:07:34,548 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-22 22:07:34,548 INFO L272 AbstractInterpreter]: Visited 31 different actions 81 times. Merged at 7 different actions 17 times. Never widened. Performed 246 root evaluator evaluations with a maximum evaluation depth of 6. Performed 246 inverse root evaluator evaluations with a maximum inverse evaluation depth of 6. Never found a fixpoint. Largest state had 19 variables. [2018-11-22 22:07:34,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:34,550 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-22 22:07:34,550 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:34,550 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:07:34,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:34,566 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-22 22:07:34,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:34,582 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:07:34,671 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-22 22:07:34,671 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:07:34,828 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:34,850 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-22 22:07:34,850 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11, 9] total 20 [2018-11-22 22:07:34,850 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-22 22:07:34,850 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-22 22:07:34,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-22 22:07:34,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=331, Unknown=0, NotChecked=0, Total=380 [2018-11-22 22:07:34,851 INFO L87 Difference]: Start difference. First operand 93 states and 119 transitions. Second operand 13 states. [2018-11-22 22:07:35,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:07:35,072 INFO L93 Difference]: Finished difference Result 150 states and 198 transitions. [2018-11-22 22:07:35,076 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-22 22:07:35,076 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2018-11-22 22:07:35,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:07:35,078 INFO L225 Difference]: With dead ends: 150 [2018-11-22 22:07:35,078 INFO L226 Difference]: Without dead ends: 114 [2018-11-22 22:07:35,079 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=119, Invalid=693, Unknown=0, NotChecked=0, Total=812 [2018-11-22 22:07:35,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-22 22:07:35,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 85. [2018-11-22 22:07:35,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-11-22 22:07:35,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 105 transitions. [2018-11-22 22:07:35,090 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 105 transitions. Word has length 38 [2018-11-22 22:07:35,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:07:35,090 INFO L480 AbstractCegarLoop]: Abstraction has 85 states and 105 transitions. [2018-11-22 22:07:35,090 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-22 22:07:35,090 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 105 transitions. [2018-11-22 22:07:35,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-22 22:07:35,091 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:35,091 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:35,091 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:35,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:35,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1790976707, now seen corresponding path program 2 times [2018-11-22 22:07:35,092 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:35,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:35,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:35,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:35,095 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:35,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:35,170 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:35,170 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:35,171 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-22 22:07:35,171 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-22 22:07:35,171 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-22 22:07:35,171 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:35,171 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:07:35,180 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-22 22:07:35,180 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-22 22:07:35,199 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2018-11-22 22:07:35,200 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:07:35,202 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:07:35,249 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:35,249 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:07:35,347 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:07:35,361 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-22 22:07:35,362 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [8] total 20 [2018-11-22 22:07:35,362 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 22:07:35,362 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 22:07:35,362 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 22:07:35,362 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=337, Unknown=0, NotChecked=0, Total=380 [2018-11-22 22:07:35,362 INFO L87 Difference]: Start difference. First operand 85 states and 105 transitions. Second operand 8 states. [2018-11-22 22:07:35,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:07:35,405 INFO L93 Difference]: Finished difference Result 126 states and 160 transitions. [2018-11-22 22:07:35,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 22:07:35,406 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 38 [2018-11-22 22:07:35,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:07:35,407 INFO L225 Difference]: With dead ends: 126 [2018-11-22 22:07:35,407 INFO L226 Difference]: Without dead ends: 100 [2018-11-22 22:07:35,408 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=407, Unknown=0, NotChecked=0, Total=462 [2018-11-22 22:07:35,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-11-22 22:07:35,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 93. [2018-11-22 22:07:35,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-11-22 22:07:35,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 113 transitions. [2018-11-22 22:07:35,417 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 113 transitions. Word has length 38 [2018-11-22 22:07:35,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:07:35,418 INFO L480 AbstractCegarLoop]: Abstraction has 93 states and 113 transitions. [2018-11-22 22:07:35,418 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 22:07:35,418 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 113 transitions. [2018-11-22 22:07:35,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:07:35,419 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:35,419 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:35,419 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:35,419 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:35,419 INFO L82 PathProgramCache]: Analyzing trace with hash -774274828, now seen corresponding path program 3 times [2018-11-22 22:07:35,420 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:35,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:35,420 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:07:35,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:35,420 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:35,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:35,512 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:07:35,512 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:07:35,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-22 22:07:35,512 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 22:07:35,513 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-22 22:07:35,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-22 22:07:35,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-11-22 22:07:35,513 INFO L87 Difference]: Start difference. First operand 93 states and 113 transitions. Second operand 10 states. [2018-11-22 22:07:52,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:07:52,655 INFO L93 Difference]: Finished difference Result 160 states and 211 transitions. [2018-11-22 22:07:52,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-22 22:07:52,655 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-11-22 22:07:52,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:07:52,656 INFO L225 Difference]: With dead ends: 160 [2018-11-22 22:07:52,656 INFO L226 Difference]: Without dead ends: 134 [2018-11-22 22:07:52,657 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2018-11-22 22:07:52,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-22 22:07:52,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 115. [2018-11-22 22:07:52,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-11-22 22:07:52,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 147 transitions. [2018-11-22 22:07:52,668 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 147 transitions. Word has length 42 [2018-11-22 22:07:52,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:07:52,668 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 147 transitions. [2018-11-22 22:07:52,668 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-22 22:07:52,668 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 147 transitions. [2018-11-22 22:07:52,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:07:52,670 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:52,671 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:52,671 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:52,671 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:52,671 INFO L82 PathProgramCache]: Analyzing trace with hash -717016526, now seen corresponding path program 2 times [2018-11-22 22:07:52,671 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:52,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:52,672 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:07:52,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:52,672 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:52,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:52,835 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:07:52,836 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:07:52,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-22 22:07:52,836 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 22:07:52,836 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-22 22:07:52,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-22 22:07:52,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2018-11-22 22:07:52,837 INFO L87 Difference]: Start difference. First operand 115 states and 147 transitions. Second operand 13 states. [2018-11-22 22:07:52,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:07:52,982 INFO L93 Difference]: Finished difference Result 140 states and 179 transitions. [2018-11-22 22:07:52,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-22 22:07:52,983 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 42 [2018-11-22 22:07:52,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:07:52,983 INFO L225 Difference]: With dead ends: 140 [2018-11-22 22:07:52,983 INFO L226 Difference]: Without dead ends: 138 [2018-11-22 22:07:52,984 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:07:52,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-22 22:07:52,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 119. [2018-11-22 22:07:52,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-11-22 22:07:52,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 150 transitions. [2018-11-22 22:07:52,994 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 150 transitions. Word has length 42 [2018-11-22 22:07:52,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:07:52,995 INFO L480 AbstractCegarLoop]: Abstraction has 119 states and 150 transitions. [2018-11-22 22:07:52,995 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-22 22:07:52,995 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 150 transitions. [2018-11-22 22:07:52,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:07:52,996 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:52,996 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:52,996 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:52,996 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:52,997 INFO L82 PathProgramCache]: Analyzing trace with hash 749157176, now seen corresponding path program 1 times [2018-11-22 22:07:52,997 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:52,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:52,997 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:07:52,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:52,998 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:53,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:53,069 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:07:53,070 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:53,070 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-22 22:07:53,070 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 43 with the following transitions: [2018-11-22 22:07:53,070 INFO L202 CegarAbsIntRunner]: [0], [1], [4], [6], [35], [44], [48], [50], [54], [60], [62], [63], [67], [69], [71], [73], [94], [97], [105], [129], [132], [134], [140], [141], [142], [144], [145], [146], [147], [148], [149], [150], [156] [2018-11-22 22:07:53,071 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-22 22:07:53,071 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-22 22:07:53,128 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-22 22:07:53,128 INFO L272 AbstractInterpreter]: Visited 33 different actions 138 times. Merged at 8 different actions 40 times. Never widened. Performed 458 root evaluator evaluations with a maximum evaluation depth of 6. Performed 458 inverse root evaluator evaluations with a maximum inverse evaluation depth of 6. Found 2 fixpoints after 1 different actions. Largest state had 19 variables. [2018-11-22 22:07:53,133 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:53,133 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-22 22:07:53,133 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:07:53,133 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:07:53,146 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:53,146 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-22 22:07:53,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:07:53,163 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:07:53,189 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:07:53,189 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:07:53,946 WARN L180 SmtUtils]: Spent 737.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-11-22 22:07:54,689 WARN L180 SmtUtils]: Spent 733.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-11-22 22:07:55,437 WARN L180 SmtUtils]: Spent 734.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-11-22 22:07:56,219 WARN L180 SmtUtils]: Spent 757.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-11-22 22:07:56,993 WARN L180 SmtUtils]: Spent 736.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-11-22 22:07:57,748 WARN L180 SmtUtils]: Spent 738.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-11-22 22:07:57,753 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:07:57,768 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-22 22:07:57,768 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 9] total 15 [2018-11-22 22:07:57,768 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-22 22:07:57,768 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 22:07:57,769 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 22:07:57,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2018-11-22 22:07:57,769 INFO L87 Difference]: Start difference. First operand 119 states and 150 transitions. Second operand 8 states. [2018-11-22 22:07:57,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:07:57,850 INFO L93 Difference]: Finished difference Result 188 states and 243 transitions. [2018-11-22 22:07:57,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 22:07:57,852 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-11-22 22:07:57,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:07:57,853 INFO L225 Difference]: With dead ends: 188 [2018-11-22 22:07:57,854 INFO L226 Difference]: Without dead ends: 162 [2018-11-22 22:07:57,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 76 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=45, Invalid=227, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:07:57,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-11-22 22:07:57,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 147. [2018-11-22 22:07:57,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-11-22 22:07:57,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 189 transitions. [2018-11-22 22:07:57,868 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 189 transitions. Word has length 42 [2018-11-22 22:07:57,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:07:57,868 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 189 transitions. [2018-11-22 22:07:57,868 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 22:07:57,868 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 189 transitions. [2018-11-22 22:07:57,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:07:57,869 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:07:57,869 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:07:57,869 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:07:57,870 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:07:57,870 INFO L82 PathProgramCache]: Analyzing trace with hash 806415478, now seen corresponding path program 1 times [2018-11-22 22:07:57,870 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 22:07:57,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:57,870 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:07:57,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 22:07:57,871 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 22:07:57,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 22:07:57,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 22:07:57,901 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); [?] assume true; [?] RET #141#return; [?] CALL call #t~ret9 := main(); [?] havoc ~a~0;~ma~2 := #t~nondet0;havoc #t~nondet0;assume -128 <= #t~nondet1 && #t~nondet1 <= 127;~ea~2 := #t~nondet1;havoc #t~nondet1;havoc ~b~0;~mb~2 := #t~nondet2;havoc #t~nondet2;assume -128 <= #t~nondet3 && #t~nondet3 <= 127;~eb~2 := #t~nondet3;havoc #t~nondet3;havoc ~r_add1~0;havoc ~r_add2~0;havoc ~zero~0;havoc ~tmp~2;havoc ~tmp___0~0;havoc ~__retres14~0; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216] [?] CALL call #t~ret4 := base2flt(0, 0); VAL [|base2flt_#in~e|=0, |base2flt_#in~m|=0] [?] ~m := #in~m;~e := #in~e;havoc ~res~0;havoc ~__retres4~0; VAL [base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0] [?] assume 0 == ~m % 4294967296;~__retres4~0 := 0; VAL [base2flt_~__retres4~0=0, base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0] [?] #res := ~__retres4~0; VAL [base2flt_~__retres4~0=0, base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0, |base2flt_#res|=0] [?] assume true; VAL [base2flt_~__retres4~0=0, base2flt_~e=0, base2flt_~m=0, |base2flt_#in~e|=0, |base2flt_#in~m|=0, |base2flt_#res|=0] [?] RET #145#return; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, |main_#t~ret4|=0] [?] ~zero~0 := #t~ret4;havoc #t~ret4; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0] [?] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [|base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] ~m := #in~m;~e := #in~e;havoc ~res~0;havoc ~__retres4~0; VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume !(0 == ~m % 4294967296); VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume !(~m % 4294967296 < 16777216); VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume !false; VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume ~m % 4294967296 >= 33554432; VAL [base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] assume ~e >= 127;~__retres4~0 := 4294967295; VAL [base2flt_~__retres4~0=4294967295, base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432] [?] #res := ~__retres4~0; VAL [base2flt_~__retres4~0=4294967295, base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432, |base2flt_#res|=4294967295] [?] assume true; VAL [base2flt_~__retres4~0=4294967295, base2flt_~e=127, base2flt_~m=33554432, |base2flt_#in~e|=127, |base2flt_#in~m|=33554432, |base2flt_#res|=4294967295] [?] RET #147#return; VAL [main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0, |main_#t~ret5|=4294967295] [?] ~a~0 := #t~ret5;havoc #t~ret5; VAL [main_~a~0=4294967295, main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0] [?] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [|base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] ~m := #in~m;~e := #in~e;havoc ~res~0;havoc ~__retres4~0; VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !(0 == ~m % 4294967296); VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !(~m % 4294967296 < 16777216); VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !false; VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] assume !(~m % 4294967296 >= 33554432); VAL [base2flt_~e=0, base2flt_~m=16777216, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216));~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e));~__retres4~0 := ~res~0; VAL [base2flt_~__retres4~0=36028797002186752, base2flt_~e=0, base2flt_~res~0=36028797002186752, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216] [?] #res := ~__retres4~0; VAL [base2flt_~__retres4~0=36028797002186752, base2flt_~e=0, base2flt_~res~0=36028797002186752, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216, |base2flt_#res|=36028797002186752] [?] assume true; VAL [base2flt_~__retres4~0=36028797002186752, base2flt_~e=0, base2flt_~res~0=36028797002186752, |base2flt_#in~e|=0, |base2flt_#in~m|=16777216, |base2flt_#res|=36028797002186752] [?] RET #149#return; VAL [main_~a~0=4294967295, main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0, |main_#t~ret6|=36028797002186752] [?] ~b~0 := #t~ret6;havoc #t~ret6; VAL [main_~a~0=4294967295, main_~b~0=36028797002186752, main_~ea~2=127, main_~eb~2=0, main_~ma~2=33554432, main_~mb~2=16777216, main_~zero~0=0] [?] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [|addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] ~a := #in~a;~b := #in~b;havoc ~res~1;havoc ~ma~0;havoc ~mb~0;havoc ~delta~0;havoc ~ea~0;havoc ~eb~0;havoc ~tmp~0;havoc ~__retres10~0; VAL [addflt_~a=4294967295, addflt_~b=36028797002186752, |addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] assume !(~a % 4294967296 < ~b % 4294967296); VAL [addflt_~a=4294967295, addflt_~b=36028797002186752, |addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] assume !(0 == ~b % 4294967296);~ma~0 := ~bitwiseAnd(~a, 16777215);~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128;~ma~0 := ~bitwiseOr(~ma~0, 16777216);~mb~0 := ~bitwiseAnd(~b, 16777215);~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128;~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [addflt_~a=4294967295, addflt_~b=36028797002186752, addflt_~ea~0=127, addflt_~eb~0=2147483519, |addflt_#in~a|=4294967295, |addflt_#in~b|=36028797002186752] [?] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [|__VERIFIER_assert_#in~cond|=0] [?] ~cond := #in~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume 0 == ~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume !false; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19-L24] assume 0 == ~m % 4294967296; [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L14-L72] ensures true; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] assume !false; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49-L53] assume ~m % 4294967296 >= 33554432; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54-L59] assume ~e >= 127; [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L14-L72] ensures true; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] assume !false; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49-L53] assume !(~m % 4294967296 >= 33554432); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L14-L72] ensures true; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84-L90] assume !(~a % 4294967296 < ~b % 4294967296); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91-L96] assume !(0 == ~b % 4294967296); [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6-L8] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19-L24] assume 0 == ~m % 4294967296; [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L14-L72] ensures true; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] assume !false; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49-L53] assume ~m % 4294967296 >= 33554432; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54-L59] assume ~e >= 127; [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L14-L72] ensures true; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19-L24] assume !(0 == ~m % 4294967296); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25-L65] assume !(~m % 4294967296 < 16777216); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] assume !false; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49-L53] assume !(~m % 4294967296 >= 33554432); VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L14-L72] ensures true; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84-L90] assume !(~a % 4294967296 < ~b % 4294967296); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91-L96] assume !(0 == ~b % 4294967296); [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6-L8] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret9 := main(); [L215] havoc ~a~0; [L216] ~ma~2 := #t~nondet0; [L216] havoc #t~nondet0; [L217] assume -128 <= #t~nondet1 && #t~nondet1 <= 127; [L217] ~ea~2 := #t~nondet1; [L217] havoc #t~nondet1; [L218] havoc ~b~0; [L219] ~mb~2 := #t~nondet2; [L219] havoc #t~nondet2; [L220] assume -128 <= #t~nondet3 && #t~nondet3 <= 127; [L220] ~eb~2 := #t~nondet3; [L220] havoc #t~nondet3; [L221] havoc ~r_add1~0; [L222] havoc ~r_add2~0; [L223] havoc ~zero~0; [L224] havoc ~tmp~2; [L225] havoc ~tmp___0~0; [L226] havoc ~__retres14~0; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] CALL call #t~ret4 := base2flt(0, 0); VAL [#in~e=0, #in~m=0] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=0, ~e=0, ~m=0] [L19] COND TRUE 0 == ~m % 4294967296 [L20] ~__retres4~0 := 0; VAL [#in~e=0, #in~m=0, ~__retres4~0=0, ~e=0, ~m=0] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=0, #res=0, ~__retres4~0=0, ~e=0, ~m=0] [L230] RET call #t~ret4 := base2flt(0, 0); VAL [#t~ret4=0, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216] [L230] ~zero~0 := #t~ret4; [L230] havoc #t~ret4; VAL [~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] CALL call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#in~e=127, #in~m=33554432] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L47-L62] COND FALSE !(false) VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L49] COND TRUE ~m % 4294967296 >= 33554432 VAL [#in~e=127, #in~m=33554432, ~e=127, ~m=33554432] [L54] COND TRUE ~e >= 127 [L55] ~__retres4~0 := 4294967295; VAL [#in~e=127, #in~m=33554432, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L70] #res := ~__retres4~0; VAL [#in~e=127, #in~m=33554432, #res=4294967295, ~__retres4~0=4294967295, ~e=127, ~m=33554432] [L231] RET call #t~ret5 := base2flt(~ma~2, ~ea~2); VAL [#t~ret5=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L231] ~a~0 := #t~ret5; [L231] havoc #t~ret5; VAL [~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] CALL call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#in~e=0, #in~m=16777216] [L14-L72] ~m := #in~m; [L14-L72] ~e := #in~e; [L15] havoc ~res~0; [L16] havoc ~__retres4~0; VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L19] COND FALSE !(0 == ~m % 4294967296) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L25] COND FALSE !(~m % 4294967296 < 16777216) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L47-L62] COND FALSE !(false) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L49] COND FALSE !(~m % 4294967296 >= 33554432) VAL [#in~e=0, #in~m=16777216, ~e=0, ~m=16777216] [L66] ~m := ~bitwiseAnd(~m, ~bitwiseComplement(16777216)); [L67] ~res~0 := ~bitwiseOr(~m, 16777216 * (128 + ~e)); [L68] ~__retres4~0 := ~res~0; VAL [#in~e=0, #in~m=16777216, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L70] #res := ~__retres4~0; VAL [#in~e=0, #in~m=16777216, #res=36028797002186752, ~__retres4~0=36028797002186752, ~e=0, ~res~0=36028797002186752] [L232] RET call #t~ret6 := base2flt(~mb~2, ~eb~2); VAL [#t~ret6=36028797002186752, ~a~0=4294967295, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L232] ~b~0 := #t~ret6; [L232] havoc #t~ret6; VAL [~a~0=4294967295, ~b~0=36028797002186752, ~ea~2=127, ~eb~2=0, ~ma~2=33554432, ~mb~2=16777216, ~zero~0=0] [L233] CALL call #t~ret7 := addflt(~a~0, ~b~0); VAL [#in~a=4294967295, #in~b=36028797002186752] [L73-L136] ~a := #in~a; [L73-L136] ~b := #in~b; [L74] havoc ~res~1; [L75] havoc ~ma~0; [L76] havoc ~mb~0; [L77] havoc ~delta~0; [L78] havoc ~ea~0; [L79] havoc ~eb~0; [L80] havoc ~tmp~0; [L81] havoc ~__retres10~0; VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L84] COND FALSE !(~a % 4294967296 < ~b % 4294967296) VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752] [L91] COND FALSE !(0 == ~b % 4294967296) [L98] ~ma~0 := ~bitwiseAnd(~a, 16777215); [L99] ~ea~0 := (if ~a / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~a / 16777216 % 4294967296 % 4294967296 else ~a / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L100] ~ma~0 := ~bitwiseOr(~ma~0, 16777216); [L101] ~mb~0 := ~bitwiseAnd(~b, 16777215); [L102] ~eb~0 := (if ~b / 16777216 % 4294967296 % 4294967296 <= 2147483647 then ~b / 16777216 % 4294967296 % 4294967296 else ~b / 16777216 % 4294967296 % 4294967296 - 4294967296) - 128; [L103] ~mb~0 := ~bitwiseOr(~mb~0, 16777216); VAL [#in~a=4294967295, #in~b=36028797002186752, ~a=4294967295, ~b=36028797002186752, ~ea~0=127, ~eb~0=2147483519] [L104] CALL call __VERIFIER_assert((if ~ea~0 >= ~eb~0 then 1 else 0)); VAL [#in~cond=0] [L5-L10] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L6] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L7] assert false; VAL [#in~cond=0, ~cond=0] [L215] unsigned int a ; [L216] unsigned int ma = __VERIFIER_nondet_uint(); [L217] signed char ea = __VERIFIER_nondet_char(); [L218] unsigned int b ; [L219] unsigned int mb = __VERIFIER_nondet_uint(); [L220] signed char eb = __VERIFIER_nondet_char(); [L221] unsigned int r_add1 ; [L222] unsigned int r_add2 ; [L223] unsigned int zero ; [L224] int tmp ; [L225] int tmp___0 ; [L226] int __retres14 ; VAL [ea=127, eb=0, ma=33554432, mb=16777216] [L230] CALL, EXPR base2flt(0, 0) VAL [\old(e)=0, \old(m)=0] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=0, e=0, m=0] [L19] COND TRUE ! m [L20] __retres4 = 0U VAL [\old(e)=0, \old(m)=0, __retres4=0, e=0, m=0] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=0, \result=0, __retres4=0, e=0, m=0] [L230] RET, EXPR base2flt(0, 0) VAL [base2flt(0, 0)=0, ea=127, eb=0, ma=33554432, mb=16777216] [L230] zero = base2flt(0, 0) [L231] CALL, EXPR base2flt(ma, ea) VAL [\old(e)=127, \old(m)=33554432] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L19] COND FALSE !(! m) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L47] COND TRUE 1 VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L49] COND TRUE m >= 1U << 25U VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L54] COND TRUE e >= 127 [L55] __retres4 = 4294967295U VAL [\old(e)=127, \old(m)=33554432, __retres4=4294967295, e=127, m=33554432] [L70] return (__retres4); VAL [\old(e)=127, \old(m)=33554432, \result=4294967295, __retres4=4294967295, e=127, m=33554432] [L231] RET, EXPR base2flt(ma, ea) VAL [base2flt(ma, ea)=4294967295, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L231] a = base2flt(ma, ea) [L232] CALL, EXPR base2flt(mb, eb) VAL [\old(e)=0, \old(m)=16777216] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L19] COND FALSE !(! m) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L47] COND TRUE 1 VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L49] COND FALSE !(m >= 1U << 25U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L66] m = m & ~ (1U << 24U) [L67] res = m | (unsigned int )((e + 128) << 24U) [L68] __retres4 = res VAL [\old(e)=0, \old(m)=16777216, __retres4=4278190080, e=0, res=4278190080] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=16777216, \result=36028797002186752, __retres4=4278190080, e=0, res=4278190080] [L232] RET, EXPR base2flt(mb, eb) VAL [a=4294967295, base2flt(mb, eb)=36028797002186752, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L232] b = base2flt(mb, eb) [L233] CALL addflt(a, b) VAL [\old(a)=4294967295, \old(b)=4278190080] [L74] unsigned int res ; [L75] unsigned int ma ; [L76] unsigned int mb ; [L77] unsigned int delta ; [L78] int ea ; [L79] int eb ; [L80] unsigned int tmp ; [L81] unsigned int __retres10 ; VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L84] COND FALSE !(a < b) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L91] COND FALSE !(! b) [L98] ma = a & ((1U << 24U) - 1U) [L99] ea = (int )(a >> 24U) - 128 [L100] ma = ma | (1U << 24U) [L101] mb = b & ((1U << 24U) - 1U) [L102] eb = (int )(b >> 24U) - 128 [L103] mb = mb | (1U << 24U) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080, ea=127, eb=2147483519] [L104] CALL __VERIFIER_assert(ea >= eb) VAL [\old(cond)=0] [L6] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L7] __VERIFIER_error() VAL [\old(cond)=0, cond=0] ----- [2018-11-22 22:07:57,955 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.11 10:07:57 BoogieIcfgContainer [2018-11-22 22:07:57,955 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-22 22:07:57,955 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-22 22:07:57,955 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-22 22:07:57,955 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-22 22:07:57,956 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 10:07:32" (3/4) ... [2018-11-22 22:07:57,960 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-22 22:07:57,960 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-22 22:07:57,968 INFO L168 Benchmark]: Toolchain (without parser) took 26041.56 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 172.0 MB). Free memory was 960.8 MB in the beginning and 969.7 MB in the end (delta: -8.9 MB). Peak memory consumption was 163.1 MB. Max. memory is 11.5 GB. [2018-11-22 22:07:57,969 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 22:07:57,969 INFO L168 Benchmark]: CACSL2BoogieTranslator took 190.33 ms. Allocated memory is still 1.0 GB. Free memory was 960.8 MB in the beginning and 944.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-22 22:07:57,970 INFO L168 Benchmark]: Boogie Procedure Inliner took 13.40 ms. Allocated memory is still 1.0 GB. Free memory is still 944.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 22:07:57,970 INFO L168 Benchmark]: Boogie Preprocessor took 52.11 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -187.1 MB). Peak memory consumption was 14.1 MB. Max. memory is 11.5 GB. [2018-11-22 22:07:57,971 INFO L168 Benchmark]: RCFGBuilder took 236.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.7 MB). Peak memory consumption was 19.7 MB. Max. memory is 11.5 GB. [2018-11-22 22:07:57,971 INFO L168 Benchmark]: TraceAbstraction took 25533.98 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 35.1 MB). Free memory was 1.1 GB in the beginning and 969.7 MB in the end (delta: 142.4 MB). Peak memory consumption was 177.5 MB. Max. memory is 11.5 GB. [2018-11-22 22:07:57,971 INFO L168 Benchmark]: Witness Printer took 4.64 ms. Allocated memory is still 1.2 GB. Free memory is still 969.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 22:07:57,974 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 190.33 ms. Allocated memory is still 1.0 GB. Free memory was 960.8 MB in the beginning and 944.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 13.40 ms. Allocated memory is still 1.0 GB. Free memory is still 944.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 52.11 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -187.1 MB). Peak memory consumption was 14.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 236.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.7 MB). Peak memory consumption was 19.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 25533.98 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 35.1 MB). Free memory was 1.1 GB in the beginning and 969.7 MB in the end (delta: 142.4 MB). Peak memory consumption was 177.5 MB. Max. memory is 11.5 GB. * Witness Printer took 4.64 ms. Allocated memory is still 1.2 GB. Free memory is still 969.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 7]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseOr at line 100, overapproximation of bitwiseAnd at line 98. Possible FailurePath: [L215] unsigned int a ; [L216] unsigned int ma = __VERIFIER_nondet_uint(); [L217] signed char ea = __VERIFIER_nondet_char(); [L218] unsigned int b ; [L219] unsigned int mb = __VERIFIER_nondet_uint(); [L220] signed char eb = __VERIFIER_nondet_char(); [L221] unsigned int r_add1 ; [L222] unsigned int r_add2 ; [L223] unsigned int zero ; [L224] int tmp ; [L225] int tmp___0 ; [L226] int __retres14 ; VAL [ea=127, eb=0, ma=33554432, mb=16777216] [L230] CALL, EXPR base2flt(0, 0) VAL [\old(e)=0, \old(m)=0] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=0, e=0, m=0] [L19] COND TRUE ! m [L20] __retres4 = 0U VAL [\old(e)=0, \old(m)=0, __retres4=0, e=0, m=0] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=0, \result=0, __retres4=0, e=0, m=0] [L230] RET, EXPR base2flt(0, 0) VAL [base2flt(0, 0)=0, ea=127, eb=0, ma=33554432, mb=16777216] [L230] zero = base2flt(0, 0) [L231] CALL, EXPR base2flt(ma, ea) VAL [\old(e)=127, \old(m)=33554432] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L19] COND FALSE !(! m) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L47] COND TRUE 1 VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L49] COND TRUE m >= 1U << 25U VAL [\old(e)=127, \old(m)=33554432, e=127, m=33554432] [L54] COND TRUE e >= 127 [L55] __retres4 = 4294967295U VAL [\old(e)=127, \old(m)=33554432, __retres4=4294967295, e=127, m=33554432] [L70] return (__retres4); VAL [\old(e)=127, \old(m)=33554432, \result=4294967295, __retres4=4294967295, e=127, m=33554432] [L231] RET, EXPR base2flt(ma, ea) VAL [base2flt(ma, ea)=4294967295, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L231] a = base2flt(ma, ea) [L232] CALL, EXPR base2flt(mb, eb) VAL [\old(e)=0, \old(m)=16777216] [L15] unsigned int res ; [L16] unsigned int __retres4 ; VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L19] COND FALSE !(! m) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L25] COND FALSE !(m < 1U << 24U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L47] COND TRUE 1 VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L49] COND FALSE !(m >= 1U << 25U) VAL [\old(e)=0, \old(m)=16777216, e=0, m=16777216] [L66] m = m & ~ (1U << 24U) [L67] res = m | (unsigned int )((e + 128) << 24U) [L68] __retres4 = res VAL [\old(e)=0, \old(m)=16777216, __retres4=4278190080, e=0, res=4278190080] [L70] return (__retres4); VAL [\old(e)=0, \old(m)=16777216, \result=36028797002186752, __retres4=4278190080, e=0, res=4278190080] [L232] RET, EXPR base2flt(mb, eb) VAL [a=4294967295, base2flt(mb, eb)=36028797002186752, ea=127, eb=0, ma=33554432, mb=16777216, zero=0] [L232] b = base2flt(mb, eb) [L233] CALL addflt(a, b) VAL [\old(a)=4294967295, \old(b)=4278190080] [L74] unsigned int res ; [L75] unsigned int ma ; [L76] unsigned int mb ; [L77] unsigned int delta ; [L78] int ea ; [L79] int eb ; [L80] unsigned int tmp ; [L81] unsigned int __retres10 ; VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L84] COND FALSE !(a < b) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080] [L91] COND FALSE !(! b) [L98] ma = a & ((1U << 24U) - 1U) [L99] ea = (int )(a >> 24U) - 128 [L100] ma = ma | (1U << 24U) [L101] mb = b & ((1U << 24U) - 1U) [L102] eb = (int )(b >> 24U) - 128 [L103] mb = mb | (1U << 24U) VAL [\old(a)=4294967295, \old(b)=4278190080, a=4294967295, b=4278190080, ea=127, eb=2147483519] [L104] CALL __VERIFIER_assert(ea >= eb) VAL [\old(cond)=0] [L6] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L7] __VERIFIER_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 56 locations, 1 error locations. UNSAFE Result, 25.4s OverallTime, 8 OverallIterations, 3 TraceHistogramMax, 18.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 539 SDtfs, 304 SDslu, 4251 SDs, 0 SdLazy, 859 SolverSat, 42 SolverUnsat, 8 SolverUnknown, 0 SolverNotchecked, 16.8s Time, PredicateUnifierStatistics: 2 DeclaredPredicates, 436 GetRequests, 302 SyntacticMatches, 4 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 247 ImplicationChecksByTransitivity, 5.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=147occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.3s AbstIntTime, 4 AbstIntIterations, 1 AbstIntStrong, 0.5444444444444445 AbsIntWeakeningRatio, 1.8484848484848484 AbsIntAvgWeakeningVarsNumRemoved, 1.0 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 7 MinimizatonAttempts, 128 StatesRemovedByMinimization, 7 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 5.9s InterpolantComputationTime, 472 NumberOfCodeBlocks, 454 NumberOfCodeBlocksAsserted, 12 NumberOfCheckSat, 571 ConstructedInterpolants, 26 QuantifiedInterpolants, 62844 SizeOfPredicates, 20 NumberOfNonLiveVariables, 427 ConjunctsInSsa, 76 ConjunctsInUnsatCore, 15 InterpolantComputations, 4 PerfectInterpolantSequences, 193/242 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-aa41828 [2018-11-22 22:07:59,357 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-22 22:07:59,359 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-22 22:07:59,367 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2018-11-22 22:07:59,373 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-22 22:07:59,373 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-22 22:07:59,374 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-22 22:07:59,375 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-22 22:07:59,375 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-22 22:07:59,376 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-22 22:07:59,377 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-22 22:07:59,378 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-22 22:07:59,379 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-22 22:07:59,380 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-22 22:07:59,381 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-22 22:07:59,383 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-22 22:07:59,383 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-22 22:07:59,383 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-22 22:07:59,384 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-22 22:07:59,385 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-22 22:07:59,386 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-22 22:07:59,386 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-22 22:07:59,387 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-22 22:07:59,387 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-22 22:07:59,388 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-22 22:07:59,388 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-22 22:07:59,388 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-22 22:07:59,389 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-22 22:07:59,390 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-22 22:07:59,390 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Bitvector.epf [2018-11-22 22:07:59,400 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-22 22:07:59,400 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-22 22:07:59,401 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-22 22:07:59,401 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-22 22:07:59,401 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-22 22:07:59,401 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-22 22:07:59,401 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-22 22:07:59,402 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-22 22:07:59,402 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-22 22:07:59,402 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-22 22:07:59,402 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-22 22:07:59,403 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-22 22:07:59,403 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-22 22:07:59,403 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-22 22:07:59,403 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-22 22:07:59,403 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-22 22:07:59,403 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-22 22:07:59,403 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-22 22:07:59,404 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-22 22:07:59,404 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-22 22:07:59,404 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-22 22:07:59,406 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-22 22:07:59,406 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-22 22:07:59,406 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-22 22:07:59,406 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-22 22:07:59,406 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-22 22:07:59,407 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-22 22:07:59,407 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 22:07:59,407 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-22 22:07:59,407 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-22 22:07:59,407 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-22 22:07:59,407 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-11-22 22:07:59,407 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-22 22:07:59,407 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-22 22:07:59,408 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-22 22:07:59,408 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ee05cb2d66f71fb2277986b04bb223cfc634fed1 [2018-11-22 22:07:59,438 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-22 22:07:59,447 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-22 22:07:59,450 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-22 22:07:59,451 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-22 22:07:59,451 INFO L276 PluginConnector]: CDTParser initialized [2018-11-22 22:07:59,452 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/../../sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-22 22:07:59,497 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/5bf320643/ae0df5a8603642beab58982e425d7f07/FLAG3d86f93b6 [2018-11-22 22:07:59,827 INFO L307 CDTParser]: Found 1 translation units. [2018-11-22 22:07:59,828 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/sv-benchmarks/c/bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-22 22:07:59,832 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/5bf320643/ae0df5a8603642beab58982e425d7f07/FLAG3d86f93b6 [2018-11-22 22:07:59,841 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/data/5bf320643/ae0df5a8603642beab58982e425d7f07 [2018-11-22 22:07:59,843 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-22 22:07:59,844 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-22 22:07:59,844 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-22 22:07:59,845 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-22 22:07:59,847 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-22 22:07:59,848 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 10:07:59" (1/1) ... [2018-11-22 22:07:59,850 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@29d0518e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:07:59, skipping insertion in model container [2018-11-22 22:07:59,850 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 10:07:59" (1/1) ... [2018-11-22 22:07:59,856 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-22 22:07:59,880 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-22 22:08:00,052 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 22:08:00,055 INFO L191 MainTranslator]: Completed pre-run [2018-11-22 22:08:00,090 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 22:08:00,101 INFO L195 MainTranslator]: Completed translation [2018-11-22 22:08:00,102 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00 WrapperNode [2018-11-22 22:08:00,102 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-22 22:08:00,102 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-22 22:08:00,103 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-22 22:08:00,103 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-22 22:08:00,109 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,116 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,122 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-22 22:08:00,122 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-22 22:08:00,122 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-22 22:08:00,122 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-22 22:08:00,171 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,172 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,173 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,173 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,178 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,181 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,183 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... [2018-11-22 22:08:00,184 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-22 22:08:00,185 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-22 22:08:00,185 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-22 22:08:00,185 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-22 22:08:00,185 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 22:08:00,218 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-22 22:08:00,218 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-22 22:08:00,218 INFO L130 BoogieDeclarations]: Found specification of procedure base2flt [2018-11-22 22:08:00,218 INFO L138 BoogieDeclarations]: Found implementation of procedure base2flt [2018-11-22 22:08:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-22 22:08:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-22 22:08:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-22 22:08:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-22 22:08:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure addflt [2018-11-22 22:08:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure addflt [2018-11-22 22:08:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-22 22:08:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-22 22:08:00,415 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-22 22:08:00,415 INFO L280 CfgBuilder]: Removed 2 assue(true) statements. [2018-11-22 22:08:00,416 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 10:08:00 BoogieIcfgContainer [2018-11-22 22:08:00,416 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-22 22:08:00,417 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-22 22:08:00,417 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-22 22:08:00,419 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-22 22:08:00,419 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.11 10:07:59" (1/3) ... [2018-11-22 22:08:00,420 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7df02b06 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 10:08:00, skipping insertion in model container [2018-11-22 22:08:00,420 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 10:08:00" (2/3) ... [2018-11-22 22:08:00,420 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7df02b06 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 10:08:00, skipping insertion in model container [2018-11-22 22:08:00,420 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 10:08:00" (3/3) ... [2018-11-22 22:08:00,421 INFO L112 eAbstractionObserver]: Analyzing ICFG soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c [2018-11-22 22:08:00,427 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-22 22:08:00,431 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-22 22:08:00,442 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-22 22:08:00,462 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-22 22:08:00,463 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-22 22:08:00,463 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-22 22:08:00,463 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-22 22:08:00,463 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-22 22:08:00,463 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-22 22:08:00,463 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-22 22:08:00,463 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-22 22:08:00,463 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-22 22:08:00,474 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states. [2018-11-22 22:08:00,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-22 22:08:00,478 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:00,479 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:00,480 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:00,483 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:00,483 INFO L82 PathProgramCache]: Analyzing trace with hash 1457053844, now seen corresponding path program 1 times [2018-11-22 22:08:00,486 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:00,486 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:00,499 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:00,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:00,544 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:00,654 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:00,654 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:00,699 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:00,702 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:00,702 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:00,713 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:00,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:00,735 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:00,742 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:00,742 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:00,811 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:00,827 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:08:00,827 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9] total 9 [2018-11-22 22:08:00,831 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-22 22:08:00,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-22 22:08:00,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-22 22:08:00,844 INFO L87 Difference]: Start difference. First operand 56 states. Second operand 9 states. [2018-11-22 22:08:01,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:01,002 INFO L93 Difference]: Finished difference Result 136 states and 204 transitions. [2018-11-22 22:08:01,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 22:08:01,004 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-11-22 22:08:01,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:01,014 INFO L225 Difference]: With dead ends: 136 [2018-11-22 22:08:01,014 INFO L226 Difference]: Without dead ends: 78 [2018-11-22 22:08:01,017 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-11-22 22:08:01,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-11-22 22:08:01,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 64. [2018-11-22 22:08:01,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-11-22 22:08:01,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 86 transitions. [2018-11-22 22:08:01,052 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 86 transitions. Word has length 34 [2018-11-22 22:08:01,052 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:01,052 INFO L480 AbstractCegarLoop]: Abstraction has 64 states and 86 transitions. [2018-11-22 22:08:01,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-22 22:08:01,053 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 86 transitions. [2018-11-22 22:08:01,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-22 22:08:01,054 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:01,054 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:01,054 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:01,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:01,055 INFO L82 PathProgramCache]: Analyzing trace with hash 1790976707, now seen corresponding path program 1 times [2018-11-22 22:08:01,055 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:01,055 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:01,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:01,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:01,089 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:01,149 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:01,149 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:01,219 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:01,220 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:01,220 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:01,232 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:01,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:01,251 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:01,337 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-22 22:08:01,338 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:01,454 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:01,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 3 imperfect interpolant sequences. [2018-11-22 22:08:01,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [8, 8, 12] total 18 [2018-11-22 22:08:01,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-22 22:08:01,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-22 22:08:01,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=259, Unknown=0, NotChecked=0, Total=306 [2018-11-22 22:08:01,473 INFO L87 Difference]: Start difference. First operand 64 states and 86 transitions. Second operand 18 states. [2018-11-22 22:08:01,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:01,858 INFO L93 Difference]: Finished difference Result 169 states and 234 transitions. [2018-11-22 22:08:01,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-22 22:08:01,860 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 38 [2018-11-22 22:08:01,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:01,862 INFO L225 Difference]: With dead ends: 169 [2018-11-22 22:08:01,862 INFO L226 Difference]: Without dead ends: 139 [2018-11-22 22:08:01,863 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 130 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=86, Invalid=466, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:08:01,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-11-22 22:08:01,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 92. [2018-11-22 22:08:01,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-11-22 22:08:01,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 126 transitions. [2018-11-22 22:08:01,879 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 126 transitions. Word has length 38 [2018-11-22 22:08:01,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:01,880 INFO L480 AbstractCegarLoop]: Abstraction has 92 states and 126 transitions. [2018-11-22 22:08:01,880 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-22 22:08:01,880 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 126 transitions. [2018-11-22 22:08:01,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-11-22 22:08:01,881 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:01,881 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:01,881 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:01,882 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:01,882 INFO L82 PathProgramCache]: Analyzing trace with hash -182008515, now seen corresponding path program 1 times [2018-11-22 22:08:01,882 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:01,882 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:01,894 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:01,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:01,910 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:01,937 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:01,937 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:01,941 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:01,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-22 22:08:01,942 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 22:08:01,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 22:08:01,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-22 22:08:01,942 INFO L87 Difference]: Start difference. First operand 92 states and 126 transitions. Second operand 8 states. [2018-11-22 22:08:02,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:02,010 INFO L93 Difference]: Finished difference Result 149 states and 202 transitions. [2018-11-22 22:08:02,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 22:08:02,010 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 38 [2018-11-22 22:08:02,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:02,011 INFO L225 Difference]: With dead ends: 149 [2018-11-22 22:08:02,011 INFO L226 Difference]: Without dead ends: 113 [2018-11-22 22:08:02,012 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-22 22:08:02,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-11-22 22:08:02,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 92. [2018-11-22 22:08:02,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-11-22 22:08:02,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 126 transitions. [2018-11-22 22:08:02,022 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 126 transitions. Word has length 38 [2018-11-22 22:08:02,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:02,023 INFO L480 AbstractCegarLoop]: Abstraction has 92 states and 126 transitions. [2018-11-22 22:08:02,023 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 22:08:02,023 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 126 transitions. [2018-11-22 22:08:02,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:08:02,025 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:02,025 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:02,026 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:02,026 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:02,026 INFO L82 PathProgramCache]: Analyzing trace with hash -977604237, now seen corresponding path program 1 times [2018-11-22 22:08:02,026 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:02,026 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:02,037 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:02,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:02,055 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:02,095 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 22:08:02,095 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:02,096 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:02,096 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-22 22:08:02,096 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-22 22:08:02,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-22 22:08:02,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-22 22:08:02,096 INFO L87 Difference]: Start difference. First operand 92 states and 126 transitions. Second operand 9 states. [2018-11-22 22:08:02,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:02,198 INFO L93 Difference]: Finished difference Result 136 states and 182 transitions. [2018-11-22 22:08:02,199 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 22:08:02,199 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 42 [2018-11-22 22:08:02,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:02,200 INFO L225 Difference]: With dead ends: 136 [2018-11-22 22:08:02,200 INFO L226 Difference]: Without dead ends: 115 [2018-11-22 22:08:02,200 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-11-22 22:08:02,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-11-22 22:08:02,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 100. [2018-11-22 22:08:02,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-11-22 22:08:02,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 135 transitions. [2018-11-22 22:08:02,210 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 135 transitions. Word has length 42 [2018-11-22 22:08:02,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:02,210 INFO L480 AbstractCegarLoop]: Abstraction has 100 states and 135 transitions. [2018-11-22 22:08:02,210 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-22 22:08:02,210 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 135 transitions. [2018-11-22 22:08:02,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:08:02,211 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:02,212 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:02,212 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:02,212 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:02,212 INFO L82 PathProgramCache]: Analyzing trace with hash -717016526, now seen corresponding path program 1 times [2018-11-22 22:08:02,212 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:02,212 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:02,224 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:02,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:02,250 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:02,344 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:08:02,344 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:02,345 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:02,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-22 22:08:02,346 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-22 22:08:02,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-22 22:08:02,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2018-11-22 22:08:02,346 INFO L87 Difference]: Start difference. First operand 100 states and 135 transitions. Second operand 13 states. [2018-11-22 22:08:02,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:02,515 INFO L93 Difference]: Finished difference Result 181 states and 246 transitions. [2018-11-22 22:08:02,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-22 22:08:02,515 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 42 [2018-11-22 22:08:02,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:02,516 INFO L225 Difference]: With dead ends: 181 [2018-11-22 22:08:02,516 INFO L226 Difference]: Without dead ends: 150 [2018-11-22 22:08:02,517 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:08:02,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-22 22:08:02,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 134. [2018-11-22 22:08:02,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-22 22:08:02,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 176 transitions. [2018-11-22 22:08:02,529 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 176 transitions. Word has length 42 [2018-11-22 22:08:02,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:02,529 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 176 transitions. [2018-11-22 22:08:02,530 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-22 22:08:02,530 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 176 transitions. [2018-11-22 22:08:02,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:08:02,531 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:02,531 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:02,531 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:02,531 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:02,532 INFO L82 PathProgramCache]: Analyzing trace with hash 806415478, now seen corresponding path program 1 times [2018-11-22 22:08:02,532 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:02,532 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:02,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:02,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:02,571 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:02,634 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:08:02,635 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:02,788 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:02,788 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:02,794 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:02,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:02,804 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:02,817 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:08:02,817 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:02,842 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:08:02,842 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-11-22 22:08:02,842 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 22:08:02,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 22:08:02,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:08:02,843 INFO L87 Difference]: Start difference. First operand 134 states and 176 transitions. Second operand 11 states. [2018-11-22 22:08:03,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:03,053 INFO L93 Difference]: Finished difference Result 193 states and 247 transitions. [2018-11-22 22:08:03,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 22:08:03,054 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 42 [2018-11-22 22:08:03,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:03,055 INFO L225 Difference]: With dead ends: 193 [2018-11-22 22:08:03,055 INFO L226 Difference]: Without dead ends: 162 [2018-11-22 22:08:03,056 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=62, Invalid=358, Unknown=0, NotChecked=0, Total=420 [2018-11-22 22:08:03,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-11-22 22:08:03,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 142. [2018-11-22 22:08:03,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-22 22:08:03,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 181 transitions. [2018-11-22 22:08:03,071 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 181 transitions. Word has length 42 [2018-11-22 22:08:03,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:03,071 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 181 transitions. [2018-11-22 22:08:03,072 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 22:08:03,072 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 181 transitions. [2018-11-22 22:08:03,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:08:03,072 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:03,073 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:03,073 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:03,073 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:03,073 INFO L82 PathProgramCache]: Analyzing trace with hash -1035766736, now seen corresponding path program 1 times [2018-11-22 22:08:03,073 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:03,073 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:03,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:03,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:03,125 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:03,209 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:08:03,209 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:03,211 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:03,211 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-22 22:08:03,211 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-22 22:08:03,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-22 22:08:03,211 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=111, Unknown=0, NotChecked=0, Total=132 [2018-11-22 22:08:03,212 INFO L87 Difference]: Start difference. First operand 142 states and 181 transitions. Second operand 12 states. [2018-11-22 22:08:03,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:03,502 INFO L93 Difference]: Finished difference Result 220 states and 285 transitions. [2018-11-22 22:08:03,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-22 22:08:03,503 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 42 [2018-11-22 22:08:03,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:03,504 INFO L225 Difference]: With dead ends: 220 [2018-11-22 22:08:03,504 INFO L226 Difference]: Without dead ends: 190 [2018-11-22 22:08:03,505 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2018-11-22 22:08:03,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states. [2018-11-22 22:08:03,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 170. [2018-11-22 22:08:03,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-11-22 22:08:03,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 214 transitions. [2018-11-22 22:08:03,520 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 214 transitions. Word has length 42 [2018-11-22 22:08:03,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:03,521 INFO L480 AbstractCegarLoop]: Abstraction has 170 states and 214 transitions. [2018-11-22 22:08:03,521 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-22 22:08:03,521 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 214 transitions. [2018-11-22 22:08:03,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:08:03,522 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:03,522 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:03,522 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:03,522 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:03,522 INFO L82 PathProgramCache]: Analyzing trace with hash 487665268, now seen corresponding path program 1 times [2018-11-22 22:08:03,522 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:03,522 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:03,538 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:03,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:03,572 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:03,603 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:08:03,603 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:03,605 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:03,605 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 22:08:03,605 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 22:08:03,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 22:08:03,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 22:08:03,605 INFO L87 Difference]: Start difference. First operand 170 states and 214 transitions. Second operand 6 states. [2018-11-22 22:08:04,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:04,901 INFO L93 Difference]: Finished difference Result 215 states and 269 transitions. [2018-11-22 22:08:04,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 22:08:04,902 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-11-22 22:08:04,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:04,903 INFO L225 Difference]: With dead ends: 215 [2018-11-22 22:08:04,903 INFO L226 Difference]: Without dead ends: 213 [2018-11-22 22:08:04,904 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-22 22:08:04,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-11-22 22:08:04,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 176. [2018-11-22 22:08:04,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-11-22 22:08:04,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 221 transitions. [2018-11-22 22:08:04,920 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 221 transitions. Word has length 42 [2018-11-22 22:08:04,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:04,921 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 221 transitions. [2018-11-22 22:08:04,921 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 22:08:04,921 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 221 transitions. [2018-11-22 22:08:04,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-22 22:08:04,922 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:04,922 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:04,922 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:04,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:04,922 INFO L82 PathProgramCache]: Analyzing trace with hash 544923570, now seen corresponding path program 2 times [2018-11-22 22:08:04,922 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:04,923 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:04,934 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:08:04,953 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-22 22:08:04,953 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:08:04,956 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:04,985 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:08:04,985 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:04,987 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:04,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 22:08:04,987 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 22:08:04,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 22:08:04,987 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 22:08:04,987 INFO L87 Difference]: Start difference. First operand 176 states and 221 transitions. Second operand 6 states. [2018-11-22 22:08:07,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:07,078 INFO L93 Difference]: Finished difference Result 182 states and 226 transitions. [2018-11-22 22:08:07,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 22:08:07,079 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-11-22 22:08:07,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:07,080 INFO L225 Difference]: With dead ends: 182 [2018-11-22 22:08:07,080 INFO L226 Difference]: Without dead ends: 180 [2018-11-22 22:08:07,080 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-22 22:08:07,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-11-22 22:08:07,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 174. [2018-11-22 22:08:07,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-11-22 22:08:07,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 217 transitions. [2018-11-22 22:08:07,095 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 217 transitions. Word has length 42 [2018-11-22 22:08:07,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:07,095 INFO L480 AbstractCegarLoop]: Abstraction has 174 states and 217 transitions. [2018-11-22 22:08:07,095 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 22:08:07,095 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 217 transitions. [2018-11-22 22:08:07,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-22 22:08:07,096 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:07,096 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:07,096 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:07,096 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:07,097 INFO L82 PathProgramCache]: Analyzing trace with hash -1597355174, now seen corresponding path program 1 times [2018-11-22 22:08:07,097 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:07,097 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:07,109 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:08:07,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:07,125 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:07,171 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:07,171 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:07,224 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:07,225 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:07,225 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:07,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:07,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:07,242 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:07,266 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:07,266 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:07,315 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:07,330 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:08:07,330 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8] total 10 [2018-11-22 22:08:07,331 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-22 22:08:07,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-22 22:08:07,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-11-22 22:08:07,331 INFO L87 Difference]: Start difference. First operand 174 states and 217 transitions. Second operand 10 states. [2018-11-22 22:08:07,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:07,478 INFO L93 Difference]: Finished difference Result 231 states and 295 transitions. [2018-11-22 22:08:07,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 22:08:07,478 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 47 [2018-11-22 22:08:07,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:07,480 INFO L225 Difference]: With dead ends: 231 [2018-11-22 22:08:07,480 INFO L226 Difference]: Without dead ends: 220 [2018-11-22 22:08:07,480 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 191 GetRequests, 174 SyntacticMatches, 7 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-11-22 22:08:07,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-11-22 22:08:07,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 188. [2018-11-22 22:08:07,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-11-22 22:08:07,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 236 transitions. [2018-11-22 22:08:07,499 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 236 transitions. Word has length 47 [2018-11-22 22:08:07,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:07,499 INFO L480 AbstractCegarLoop]: Abstraction has 188 states and 236 transitions. [2018-11-22 22:08:07,499 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-22 22:08:07,499 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 236 transitions. [2018-11-22 22:08:07,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-22 22:08:07,501 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:07,501 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:07,501 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:07,501 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:07,502 INFO L82 PathProgramCache]: Analyzing trace with hash -896290596, now seen corresponding path program 1 times [2018-11-22 22:08:07,502 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:07,502 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:07,518 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:07,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:07,535 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:07,603 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:07,604 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:07,711 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:07,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:07,712 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:07,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:07,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:07,737 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:07,782 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:07,782 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:07,797 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:08:07,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [10, 10] total 17 [2018-11-22 22:08:07,798 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-22 22:08:07,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-22 22:08:07,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:08:07,798 INFO L87 Difference]: Start difference. First operand 188 states and 236 transitions. Second operand 17 states. [2018-11-22 22:08:08,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:08,110 INFO L93 Difference]: Finished difference Result 257 states and 326 transitions. [2018-11-22 22:08:08,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-22 22:08:08,110 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 47 [2018-11-22 22:08:08,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:08,112 INFO L225 Difference]: With dead ends: 257 [2018-11-22 22:08:08,113 INFO L226 Difference]: Without dead ends: 250 [2018-11-22 22:08:08,114 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 124 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=111, Invalid=539, Unknown=0, NotChecked=0, Total=650 [2018-11-22 22:08:08,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2018-11-22 22:08:08,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 207. [2018-11-22 22:08:08,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-22 22:08:08,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 262 transitions. [2018-11-22 22:08:08,134 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 262 transitions. Word has length 47 [2018-11-22 22:08:08,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:08,134 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 262 transitions. [2018-11-22 22:08:08,134 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-22 22:08:08,134 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 262 transitions. [2018-11-22 22:08:08,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-22 22:08:08,135 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:08,136 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:08,136 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:08,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:08,136 INFO L82 PathProgramCache]: Analyzing trace with hash 1716473666, now seen corresponding path program 1 times [2018-11-22 22:08:08,137 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:08,137 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:08,150 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:08,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:08,164 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:08,211 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:08,211 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:08,336 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:08,337 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:08,337 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:08,344 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:08,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:08,355 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:08,414 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:08,414 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:08,462 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:08,476 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:08:08,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 11, 11] total 21 [2018-11-22 22:08:08,477 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-22 22:08:08,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-22 22:08:08,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=372, Unknown=0, NotChecked=0, Total=420 [2018-11-22 22:08:08,477 INFO L87 Difference]: Start difference. First operand 207 states and 262 transitions. Second operand 21 states. [2018-11-22 22:08:08,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:08,955 INFO L93 Difference]: Finished difference Result 304 states and 389 transitions. [2018-11-22 22:08:08,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-22 22:08:08,956 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 49 [2018-11-22 22:08:08,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:08,957 INFO L225 Difference]: With dead ends: 304 [2018-11-22 22:08:08,957 INFO L226 Difference]: Without dead ends: 271 [2018-11-22 22:08:08,958 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 205 GetRequests, 174 SyntacticMatches, 2 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=132, Invalid=798, Unknown=0, NotChecked=0, Total=930 [2018-11-22 22:08:08,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-11-22 22:08:08,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 228. [2018-11-22 22:08:08,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-22 22:08:08,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 289 transitions. [2018-11-22 22:08:08,975 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 289 transitions. Word has length 49 [2018-11-22 22:08:08,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:08,975 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 289 transitions. [2018-11-22 22:08:08,975 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-22 22:08:08,975 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 289 transitions. [2018-11-22 22:08:08,976 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-22 22:08:08,976 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:08,977 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:08,977 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:08,977 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:08,977 INFO L82 PathProgramCache]: Analyzing trace with hash 1773731968, now seen corresponding path program 1 times [2018-11-22 22:08:08,977 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:08,978 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:08,998 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:09,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:09,033 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:09,057 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-11-22 22:08:09,057 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:09,060 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:09,060 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 22:08:09,061 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 22:08:09,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 22:08:09,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 22:08:09,061 INFO L87 Difference]: Start difference. First operand 228 states and 289 transitions. Second operand 6 states. [2018-11-22 22:08:09,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:09,094 INFO L93 Difference]: Finished difference Result 236 states and 296 transitions. [2018-11-22 22:08:09,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 22:08:09,095 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 49 [2018-11-22 22:08:09,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:09,096 INFO L225 Difference]: With dead ends: 236 [2018-11-22 22:08:09,096 INFO L226 Difference]: Without dead ends: 209 [2018-11-22 22:08:09,096 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-22 22:08:09,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-11-22 22:08:09,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 201. [2018-11-22 22:08:09,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-11-22 22:08:09,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 253 transitions. [2018-11-22 22:08:09,109 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 253 transitions. Word has length 49 [2018-11-22 22:08:09,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:09,110 INFO L480 AbstractCegarLoop]: Abstraction has 201 states and 253 transitions. [2018-11-22 22:08:09,110 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 22:08:09,110 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 253 transitions. [2018-11-22 22:08:09,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-22 22:08:09,111 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:09,111 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:09,111 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:09,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:09,111 INFO L82 PathProgramCache]: Analyzing trace with hash 2005355055, now seen corresponding path program 1 times [2018-11-22 22:08:09,111 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:09,111 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:09,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:09,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:09,167 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:09,248 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:08:09,248 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:09,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:09,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-22 22:08:09,250 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-22 22:08:09,250 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-22 22:08:09,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2018-11-22 22:08:09,251 INFO L87 Difference]: Start difference. First operand 201 states and 253 transitions. Second operand 13 states. [2018-11-22 22:08:09,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:09,475 INFO L93 Difference]: Finished difference Result 256 states and 323 transitions. [2018-11-22 22:08:09,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-22 22:08:09,476 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 50 [2018-11-22 22:08:09,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:09,477 INFO L225 Difference]: With dead ends: 256 [2018-11-22 22:08:09,477 INFO L226 Difference]: Without dead ends: 221 [2018-11-22 22:08:09,477 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=225, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:08:09,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states. [2018-11-22 22:08:09,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 197. [2018-11-22 22:08:09,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-11-22 22:08:09,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 243 transitions. [2018-11-22 22:08:09,492 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 243 transitions. Word has length 50 [2018-11-22 22:08:09,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:09,492 INFO L480 AbstractCegarLoop]: Abstraction has 197 states and 243 transitions. [2018-11-22 22:08:09,492 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-22 22:08:09,492 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 243 transitions. [2018-11-22 22:08:09,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-22 22:08:09,493 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:09,493 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:09,493 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:09,494 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:09,494 INFO L82 PathProgramCache]: Analyzing trace with hash -802652045, now seen corresponding path program 1 times [2018-11-22 22:08:09,494 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:09,494 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:09,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:09,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:09,537 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:09,630 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:08:09,630 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:09,738 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:09,738 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:09,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:09,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:09,767 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:09,828 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:08:09,828 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:09,905 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:08:09,905 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-11-22 22:08:09,905 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 22:08:09,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 22:08:09,905 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2018-11-22 22:08:09,905 INFO L87 Difference]: Start difference. First operand 197 states and 243 transitions. Second operand 11 states. [2018-11-22 22:08:10,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:10,254 INFO L93 Difference]: Finished difference Result 265 states and 330 transitions. [2018-11-22 22:08:10,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 22:08:10,255 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 50 [2018-11-22 22:08:10,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:10,256 INFO L225 Difference]: With dead ends: 265 [2018-11-22 22:08:10,256 INFO L226 Difference]: Without dead ends: 220 [2018-11-22 22:08:10,257 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=65, Invalid=277, Unknown=0, NotChecked=0, Total=342 [2018-11-22 22:08:10,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-11-22 22:08:10,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 195. [2018-11-22 22:08:10,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-11-22 22:08:10,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 239 transitions. [2018-11-22 22:08:10,270 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 239 transitions. Word has length 50 [2018-11-22 22:08:10,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:10,270 INFO L480 AbstractCegarLoop]: Abstraction has 195 states and 239 transitions. [2018-11-22 22:08:10,271 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 22:08:10,271 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 239 transitions. [2018-11-22 22:08:10,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-22 22:08:10,272 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:10,272 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:10,272 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:10,272 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:10,272 INFO L82 PathProgramCache]: Analyzing trace with hash -526602707, now seen corresponding path program 1 times [2018-11-22 22:08:10,272 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:10,272 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:10,290 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:10,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:10,323 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:10,833 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-22 22:08:10,833 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:10,834 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:10,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-22 22:08:10,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-22 22:08:10,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-22 22:08:10,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2018-11-22 22:08:10,835 INFO L87 Difference]: Start difference. First operand 195 states and 239 transitions. Second operand 12 states. [2018-11-22 22:08:17,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:17,864 INFO L93 Difference]: Finished difference Result 270 states and 332 transitions. [2018-11-22 22:08:17,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-22 22:08:17,864 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 50 [2018-11-22 22:08:17,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:17,865 INFO L225 Difference]: With dead ends: 270 [2018-11-22 22:08:17,865 INFO L226 Difference]: Without dead ends: 225 [2018-11-22 22:08:17,866 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=93, Invalid=368, Unknown=1, NotChecked=0, Total=462 [2018-11-22 22:08:17,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-11-22 22:08:17,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 193. [2018-11-22 22:08:17,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. [2018-11-22 22:08:17,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 235 transitions. [2018-11-22 22:08:17,884 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 235 transitions. Word has length 50 [2018-11-22 22:08:17,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:17,885 INFO L480 AbstractCegarLoop]: Abstraction has 193 states and 235 transitions. [2018-11-22 22:08:17,885 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-22 22:08:17,885 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 235 transitions. [2018-11-22 22:08:17,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-22 22:08:17,886 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:17,886 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:17,886 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:17,886 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:17,886 INFO L82 PathProgramCache]: Analyzing trace with hash 960357489, now seen corresponding path program 1 times [2018-11-22 22:08:17,887 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:17,887 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:17,915 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:17,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:17,965 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:26,180 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:08:26,180 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:26,192 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:26,192 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-22 22:08:26,193 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 22:08:26,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 22:08:26,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=37, Unknown=4, NotChecked=0, Total=56 [2018-11-22 22:08:26,193 INFO L87 Difference]: Start difference. First operand 193 states and 235 transitions. Second operand 8 states. [2018-11-22 22:08:29,801 WARN L180 SmtUtils]: Spent 1.60 s on a formula simplification. DAG size of input: 25 DAG size of output: 15 [2018-11-22 22:08:40,262 WARN L180 SmtUtils]: Spent 2.04 s on a formula simplification that was a NOOP. DAG size: 21 [2018-11-22 22:08:41,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:41,027 INFO L93 Difference]: Finished difference Result 213 states and 261 transitions. [2018-11-22 22:08:41,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 22:08:41,028 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 50 [2018-11-22 22:08:41,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:41,029 INFO L225 Difference]: With dead ends: 213 [2018-11-22 22:08:41,029 INFO L226 Difference]: Without dead ends: 211 [2018-11-22 22:08:41,030 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 14.4s TimeCoverageRelationStatistics Valid=30, Invalid=75, Unknown=5, NotChecked=0, Total=110 [2018-11-22 22:08:41,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-11-22 22:08:41,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 198. [2018-11-22 22:08:41,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-11-22 22:08:41,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 240 transitions. [2018-11-22 22:08:41,049 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 240 transitions. Word has length 50 [2018-11-22 22:08:41,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:41,050 INFO L480 AbstractCegarLoop]: Abstraction has 198 states and 240 transitions. [2018-11-22 22:08:41,050 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 22:08:41,050 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 240 transitions. [2018-11-22 22:08:41,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-22 22:08:41,051 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:41,051 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:41,051 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:41,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:41,051 INFO L82 PathProgramCache]: Analyzing trace with hash -614439095, now seen corresponding path program 1 times [2018-11-22 22:08:41,051 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:41,051 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:41,071 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:41,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:41,086 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:41,138 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:41,138 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:41,257 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:41,258 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:41,259 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:41,267 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:41,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:41,279 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:41,282 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:41,282 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:41,364 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:41,379 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:08:41,379 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12] total 16 [2018-11-22 22:08:41,379 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-22 22:08:41,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-22 22:08:41,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-11-22 22:08:41,380 INFO L87 Difference]: Start difference. First operand 198 states and 240 transitions. Second operand 16 states. [2018-11-22 22:08:42,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:42,233 INFO L93 Difference]: Finished difference Result 245 states and 319 transitions. [2018-11-22 22:08:42,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-22 22:08:42,233 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 51 [2018-11-22 22:08:42,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:42,234 INFO L225 Difference]: With dead ends: 245 [2018-11-22 22:08:42,235 INFO L226 Difference]: Without dead ends: 236 [2018-11-22 22:08:42,235 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 184 SyntacticMatches, 6 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=96, Invalid=554, Unknown=0, NotChecked=0, Total=650 [2018-11-22 22:08:42,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-11-22 22:08:42,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 206. [2018-11-22 22:08:42,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-11-22 22:08:42,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 255 transitions. [2018-11-22 22:08:42,252 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 255 transitions. Word has length 51 [2018-11-22 22:08:42,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:42,253 INFO L480 AbstractCegarLoop]: Abstraction has 206 states and 255 transitions. [2018-11-22 22:08:42,253 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-22 22:08:42,253 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 255 transitions. [2018-11-22 22:08:42,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-22 22:08:42,254 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:42,254 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:42,254 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:42,254 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:42,254 INFO L82 PathProgramCache]: Analyzing trace with hash 1494907781, now seen corresponding path program 1 times [2018-11-22 22:08:42,254 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:42,254 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:42,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:42,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:42,297 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:42,365 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:42,365 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:42,619 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:42,620 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:42,620 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:42,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:08:42,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:42,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:42,644 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:42,644 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:42,724 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:42,738 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:08:42,739 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13] total 24 [2018-11-22 22:08:42,739 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-22 22:08:42,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-22 22:08:42,739 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:08:42,739 INFO L87 Difference]: Start difference. First operand 206 states and 255 transitions. Second operand 24 states. [2018-11-22 22:08:43,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:43,567 INFO L93 Difference]: Finished difference Result 269 states and 366 transitions. [2018-11-22 22:08:43,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-22 22:08:43,568 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 51 [2018-11-22 22:08:43,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:43,569 INFO L225 Difference]: With dead ends: 269 [2018-11-22 22:08:43,569 INFO L226 Difference]: Without dead ends: 235 [2018-11-22 22:08:43,569 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 177 SyntacticMatches, 3 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 173 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=199, Invalid=1361, Unknown=0, NotChecked=0, Total=1560 [2018-11-22 22:08:43,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2018-11-22 22:08:43,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 195. [2018-11-22 22:08:43,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-11-22 22:08:43,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 254 transitions. [2018-11-22 22:08:43,584 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 254 transitions. Word has length 51 [2018-11-22 22:08:43,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:43,585 INFO L480 AbstractCegarLoop]: Abstraction has 195 states and 254 transitions. [2018-11-22 22:08:43,585 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-22 22:08:43,585 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 254 transitions. [2018-11-22 22:08:43,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-22 22:08:43,585 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:43,585 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:43,586 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:43,586 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:43,586 INFO L82 PathProgramCache]: Analyzing trace with hash 32918923, now seen corresponding path program 2 times [2018-11-22 22:08:43,586 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:43,586 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:43,609 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:08:43,625 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:08:43,625 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:08:43,628 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:43,685 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:43,685 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:43,829 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:43,831 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:43,831 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:43,845 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:08:43,859 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:08:43,859 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:08:43,860 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:43,863 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:43,863 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:43,930 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-22 22:08:43,944 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:08:43,945 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11] total 14 [2018-11-22 22:08:43,945 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-22 22:08:43,945 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-22 22:08:43,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2018-11-22 22:08:43,945 INFO L87 Difference]: Start difference. First operand 195 states and 254 transitions. Second operand 14 states. [2018-11-22 22:08:44,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:44,245 INFO L93 Difference]: Finished difference Result 233 states and 325 transitions. [2018-11-22 22:08:44,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-22 22:08:44,246 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 51 [2018-11-22 22:08:44,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:44,247 INFO L225 Difference]: With dead ends: 233 [2018-11-22 22:08:44,247 INFO L226 Difference]: Without dead ends: 226 [2018-11-22 22:08:44,247 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 188 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=422, Unknown=0, NotChecked=0, Total=506 [2018-11-22 22:08:44,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-11-22 22:08:44,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 199. [2018-11-22 22:08:44,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-11-22 22:08:44,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 260 transitions. [2018-11-22 22:08:44,263 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 260 transitions. Word has length 51 [2018-11-22 22:08:44,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:44,263 INFO L480 AbstractCegarLoop]: Abstraction has 199 states and 260 transitions. [2018-11-22 22:08:44,263 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-22 22:08:44,263 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 260 transitions. [2018-11-22 22:08:44,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-22 22:08:44,264 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:44,264 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:44,264 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:44,265 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:44,265 INFO L82 PathProgramCache]: Analyzing trace with hash 1866743247, now seen corresponding path program 2 times [2018-11-22 22:08:44,265 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:44,265 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:44,278 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:08:44,295 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:08:44,295 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:08:44,298 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:44,381 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:44,381 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:44,638 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:44,639 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:08:44,639 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:08:44,645 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:08:44,663 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:08:44,664 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:08:44,665 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:44,667 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:44,667 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:08:44,749 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-22 22:08:44,764 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:08:44,764 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13] total 24 [2018-11-22 22:08:44,764 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-22 22:08:44,764 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-22 22:08:44,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:08:44,765 INFO L87 Difference]: Start difference. First operand 199 states and 260 transitions. Second operand 24 states. [2018-11-22 22:08:45,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:08:45,802 INFO L93 Difference]: Finished difference Result 247 states and 329 transitions. [2018-11-22 22:08:45,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-22 22:08:45,803 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 51 [2018-11-22 22:08:45,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:08:45,804 INFO L225 Difference]: With dead ends: 247 [2018-11-22 22:08:45,804 INFO L226 Difference]: Without dead ends: 214 [2018-11-22 22:08:45,805 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 177 SyntacticMatches, 3 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=184, Invalid=1298, Unknown=0, NotChecked=0, Total=1482 [2018-11-22 22:08:45,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2018-11-22 22:08:45,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 179. [2018-11-22 22:08:45,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-11-22 22:08:45,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 234 transitions. [2018-11-22 22:08:45,830 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 234 transitions. Word has length 51 [2018-11-22 22:08:45,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:08:45,830 INFO L480 AbstractCegarLoop]: Abstraction has 179 states and 234 transitions. [2018-11-22 22:08:45,831 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-22 22:08:45,831 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 234 transitions. [2018-11-22 22:08:45,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-11-22 22:08:45,831 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:08:45,832 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:08:45,832 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:08:45,832 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:08:45,832 INFO L82 PathProgramCache]: Analyzing trace with hash -528325640, now seen corresponding path program 1 times [2018-11-22 22:08:45,832 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:08:45,832 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:08:45,851 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:08:45,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:08:45,902 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:08:54,045 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:08:54,046 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:08:54,047 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:08:54,047 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-22 22:08:54,047 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 22:08:54,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 22:08:54,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=37, Unknown=4, NotChecked=0, Total=56 [2018-11-22 22:08:54,047 INFO L87 Difference]: Start difference. First operand 179 states and 234 transitions. Second operand 8 states. [2018-11-22 22:09:09,073 WARN L180 SmtUtils]: Spent 422.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 17 [2018-11-22 22:09:22,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:22,039 INFO L93 Difference]: Finished difference Result 195 states and 254 transitions. [2018-11-22 22:09:22,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 22:09:22,039 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-11-22 22:09:22,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:22,040 INFO L225 Difference]: With dead ends: 195 [2018-11-22 22:09:22,040 INFO L226 Difference]: Without dead ends: 191 [2018-11-22 22:09:22,041 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=30, Invalid=74, Unknown=6, NotChecked=0, Total=110 [2018-11-22 22:09:22,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-11-22 22:09:22,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 176. [2018-11-22 22:09:22,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-11-22 22:09:22,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 230 transitions. [2018-11-22 22:09:22,058 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 230 transitions. Word has length 51 [2018-11-22 22:09:22,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:22,058 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 230 transitions. [2018-11-22 22:09:22,058 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 22:09:22,059 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 230 transitions. [2018-11-22 22:09:22,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-22 22:09:22,059 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:22,060 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:22,060 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:22,060 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:22,060 INFO L82 PathProgramCache]: Analyzing trace with hash -1162373086, now seen corresponding path program 1 times [2018-11-22 22:09:22,060 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:22,060 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:22,079 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:22,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:22,096 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:22,136 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:09:22,136 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:09:22,137 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:09:22,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-22 22:09:22,137 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-22 22:09:22,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-22 22:09:22,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-22 22:09:22,138 INFO L87 Difference]: Start difference. First operand 176 states and 230 transitions. Second operand 9 states. [2018-11-22 22:09:22,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:22,264 INFO L93 Difference]: Finished difference Result 215 states and 303 transitions. [2018-11-22 22:09:22,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 22:09:22,265 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 57 [2018-11-22 22:09:22,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:22,266 INFO L225 Difference]: With dead ends: 215 [2018-11-22 22:09:22,266 INFO L226 Difference]: Without dead ends: 206 [2018-11-22 22:09:22,266 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-11-22 22:09:22,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-11-22 22:09:22,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 181. [2018-11-22 22:09:22,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181 states. [2018-11-22 22:09:22,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181 states to 181 states and 244 transitions. [2018-11-22 22:09:22,282 INFO L78 Accepts]: Start accepts. Automaton has 181 states and 244 transitions. Word has length 57 [2018-11-22 22:09:22,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:22,282 INFO L480 AbstractCegarLoop]: Abstraction has 181 states and 244 transitions. [2018-11-22 22:09:22,282 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-22 22:09:22,282 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 244 transitions. [2018-11-22 22:09:22,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-22 22:09:22,283 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:22,284 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:22,284 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:22,284 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:22,284 INFO L82 PathProgramCache]: Analyzing trace with hash -1304588962, now seen corresponding path program 1 times [2018-11-22 22:09:22,284 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:22,284 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:22,297 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:22,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:22,314 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:22,331 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:09:22,331 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:09:22,332 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:09:22,332 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 22:09:22,332 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 22:09:22,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 22:09:22,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 22:09:22,333 INFO L87 Difference]: Start difference. First operand 181 states and 244 transitions. Second operand 5 states. [2018-11-22 22:09:22,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:22,396 INFO L93 Difference]: Finished difference Result 220 states and 326 transitions. [2018-11-22 22:09:22,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 22:09:22,396 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-22 22:09:22,397 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:22,397 INFO L225 Difference]: With dead ends: 220 [2018-11-22 22:09:22,397 INFO L226 Difference]: Without dead ends: 209 [2018-11-22 22:09:22,398 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 22:09:22,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-11-22 22:09:22,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 202. [2018-11-22 22:09:22,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-11-22 22:09:22,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 289 transitions. [2018-11-22 22:09:22,417 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 289 transitions. Word has length 57 [2018-11-22 22:09:22,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:22,418 INFO L480 AbstractCegarLoop]: Abstraction has 202 states and 289 transitions. [2018-11-22 22:09:22,418 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 22:09:22,418 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 289 transitions. [2018-11-22 22:09:22,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-22 22:09:22,419 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:22,419 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:22,419 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:22,419 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:22,419 INFO L82 PathProgramCache]: Analyzing trace with hash 1712427967, now seen corresponding path program 1 times [2018-11-22 22:09:22,420 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:22,420 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:22,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:22,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:22,454 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:22,504 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:09:22,504 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:22,656 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 5 proven. 8 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:09:22,657 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:22,657 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:22,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:22,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:22,677 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:22,681 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:09:22,681 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:22,750 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 5 proven. 8 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-22 22:09:22,765 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:22,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11] total 18 [2018-11-22 22:09:22,765 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-22 22:09:22,765 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-22 22:09:22,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=257, Unknown=0, NotChecked=0, Total=306 [2018-11-22 22:09:22,765 INFO L87 Difference]: Start difference. First operand 202 states and 289 transitions. Second operand 18 states. [2018-11-22 22:09:22,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:22,995 INFO L93 Difference]: Finished difference Result 231 states and 327 transitions. [2018-11-22 22:09:22,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-22 22:09:22,996 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 64 [2018-11-22 22:09:22,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:22,997 INFO L225 Difference]: With dead ends: 231 [2018-11-22 22:09:22,997 INFO L226 Difference]: Without dead ends: 222 [2018-11-22 22:09:22,997 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 236 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=71, Invalid=349, Unknown=0, NotChecked=0, Total=420 [2018-11-22 22:09:22,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-11-22 22:09:23,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 207. [2018-11-22 22:09:23,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-22 22:09:23,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 295 transitions. [2018-11-22 22:09:23,018 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 295 transitions. Word has length 64 [2018-11-22 22:09:23,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:23,018 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 295 transitions. [2018-11-22 22:09:23,018 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-22 22:09:23,019 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 295 transitions. [2018-11-22 22:09:23,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-22 22:09:23,020 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:23,020 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:23,020 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:23,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:23,020 INFO L82 PathProgramCache]: Analyzing trace with hash -1835326830, now seen corresponding path program 1 times [2018-11-22 22:09:23,020 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:23,020 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:23,042 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:23,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:23,061 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:23,085 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,085 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:23,144 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,145 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:23,145 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:23,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:23,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:23,173 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:23,175 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,175 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:23,213 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,227 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:23,227 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8] total 11 [2018-11-22 22:09:23,228 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 22:09:23,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 22:09:23,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-22 22:09:23,228 INFO L87 Difference]: Start difference. First operand 207 states and 295 transitions. Second operand 11 states. [2018-11-22 22:09:23,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:23,364 INFO L93 Difference]: Finished difference Result 225 states and 317 transitions. [2018-11-22 22:09:23,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 22:09:23,365 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 64 [2018-11-22 22:09:23,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:23,366 INFO L225 Difference]: With dead ends: 225 [2018-11-22 22:09:23,366 INFO L226 Difference]: Without dead ends: 207 [2018-11-22 22:09:23,366 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 245 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-11-22 22:09:23,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-11-22 22:09:23,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2018-11-22 22:09:23,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-22 22:09:23,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 293 transitions. [2018-11-22 22:09:23,395 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 293 transitions. Word has length 64 [2018-11-22 22:09:23,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:23,396 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 293 transitions. [2018-11-22 22:09:23,396 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 22:09:23,396 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 293 transitions. [2018-11-22 22:09:23,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-22 22:09:23,397 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:23,397 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:23,397 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:23,397 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:23,397 INFO L82 PathProgramCache]: Analyzing trace with hash -1527151470, now seen corresponding path program 2 times [2018-11-22 22:09:23,398 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:23,398 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:23,417 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:23,465 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:23,465 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:23,469 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:23,517 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,517 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:23,606 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,607 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:23,607 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:23,614 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:23,628 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:23,628 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:23,630 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:23,634 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,634 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:23,676 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-22 22:09:23,701 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:23,701 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8] total 11 [2018-11-22 22:09:23,701 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 22:09:23,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 22:09:23,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-22 22:09:23,701 INFO L87 Difference]: Start difference. First operand 207 states and 293 transitions. Second operand 11 states. [2018-11-22 22:09:23,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:23,868 INFO L93 Difference]: Finished difference Result 220 states and 311 transitions. [2018-11-22 22:09:23,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 22:09:23,869 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 64 [2018-11-22 22:09:23,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:23,870 INFO L225 Difference]: With dead ends: 220 [2018-11-22 22:09:23,870 INFO L226 Difference]: Without dead ends: 202 [2018-11-22 22:09:23,871 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 245 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=174, Unknown=0, NotChecked=0, Total=240 [2018-11-22 22:09:23,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-11-22 22:09:23,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 202. [2018-11-22 22:09:23,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-11-22 22:09:23,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 284 transitions. [2018-11-22 22:09:23,899 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 284 transitions. Word has length 64 [2018-11-22 22:09:23,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:23,899 INFO L480 AbstractCegarLoop]: Abstraction has 202 states and 284 transitions. [2018-11-22 22:09:23,899 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 22:09:23,899 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 284 transitions. [2018-11-22 22:09:23,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-22 22:09:23,900 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:23,900 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:23,901 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:23,901 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:23,901 INFO L82 PathProgramCache]: Analyzing trace with hash 218346458, now seen corresponding path program 1 times [2018-11-22 22:09:23,901 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:23,901 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:23,922 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:09:23,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:23,951 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:23,989 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:23,989 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:24,051 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:24,052 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:24,052 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:24,058 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:24,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:24,071 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:24,073 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:24,073 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:24,120 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:24,145 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:24,145 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8] total 11 [2018-11-22 22:09:24,145 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 22:09:24,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 22:09:24,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-22 22:09:24,146 INFO L87 Difference]: Start difference. First operand 202 states and 284 transitions. Second operand 11 states. [2018-11-22 22:09:24,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:24,299 INFO L93 Difference]: Finished difference Result 213 states and 295 transitions. [2018-11-22 22:09:24,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 22:09:24,299 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2018-11-22 22:09:24,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:24,300 INFO L225 Difference]: With dead ends: 213 [2018-11-22 22:09:24,300 INFO L226 Difference]: Without dead ends: 199 [2018-11-22 22:09:24,300 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 253 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-11-22 22:09:24,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-11-22 22:09:24,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 199. [2018-11-22 22:09:24,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-11-22 22:09:24,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 278 transitions. [2018-11-22 22:09:24,324 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 278 transitions. Word has length 66 [2018-11-22 22:09:24,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:24,325 INFO L480 AbstractCegarLoop]: Abstraction has 199 states and 278 transitions. [2018-11-22 22:09:24,325 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 22:09:24,325 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 278 transitions. [2018-11-22 22:09:24,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-22 22:09:24,326 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:24,326 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:24,326 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:24,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:24,327 INFO L82 PathProgramCache]: Analyzing trace with hash 166673046, now seen corresponding path program 2 times [2018-11-22 22:09:24,327 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:24,327 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:24,351 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:24,382 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:24,382 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:24,385 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:24,447 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:24,447 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:24,538 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:24,540 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:24,540 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:24,546 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:24,564 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:24,565 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:24,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:24,570 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:24,570 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:24,618 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:09:24,632 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:24,633 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8] total 11 [2018-11-22 22:09:24,633 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 22:09:24,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 22:09:24,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-22 22:09:24,633 INFO L87 Difference]: Start difference. First operand 199 states and 278 transitions. Second operand 11 states. [2018-11-22 22:09:24,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:24,764 INFO L93 Difference]: Finished difference Result 210 states and 289 transitions. [2018-11-22 22:09:24,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 22:09:24,765 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2018-11-22 22:09:24,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:24,766 INFO L225 Difference]: With dead ends: 210 [2018-11-22 22:09:24,766 INFO L226 Difference]: Without dead ends: 196 [2018-11-22 22:09:24,766 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 253 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=174, Unknown=0, NotChecked=0, Total=240 [2018-11-22 22:09:24,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-11-22 22:09:24,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2018-11-22 22:09:24,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-11-22 22:09:24,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 261 transitions. [2018-11-22 22:09:24,785 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 261 transitions. Word has length 66 [2018-11-22 22:09:24,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:24,785 INFO L480 AbstractCegarLoop]: Abstraction has 194 states and 261 transitions. [2018-11-22 22:09:24,785 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 22:09:24,785 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 261 transitions. [2018-11-22 22:09:24,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-22 22:09:24,786 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:24,786 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:24,786 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:24,787 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:24,787 INFO L82 PathProgramCache]: Analyzing trace with hash -1109140964, now seen corresponding path program 1 times [2018-11-22 22:09:24,787 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:24,787 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:24,801 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:09:24,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:24,823 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:24,906 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 15 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-22 22:09:24,906 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:25,071 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 15 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-22 22:09:25,072 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:25,072 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:25,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:25,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:25,095 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:25,106 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 15 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-22 22:09:25,106 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:25,206 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 15 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-22 22:09:25,231 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:25,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12] total 16 [2018-11-22 22:09:25,232 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-22 22:09:25,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-22 22:09:25,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-11-22 22:09:25,232 INFO L87 Difference]: Start difference. First operand 194 states and 261 transitions. Second operand 16 states. [2018-11-22 22:09:25,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:25,549 INFO L93 Difference]: Finished difference Result 212 states and 289 transitions. [2018-11-22 22:09:25,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-22 22:09:25,550 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 71 [2018-11-22 22:09:25,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:25,550 INFO L225 Difference]: With dead ends: 212 [2018-11-22 22:09:25,550 INFO L226 Difference]: Without dead ends: 169 [2018-11-22 22:09:25,551 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 265 SyntacticMatches, 6 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=90, Invalid=462, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:09:25,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-11-22 22:09:25,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 159. [2018-11-22 22:09:25,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-11-22 22:09:25,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 227 transitions. [2018-11-22 22:09:25,566 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 227 transitions. Word has length 71 [2018-11-22 22:09:25,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:25,566 INFO L480 AbstractCegarLoop]: Abstraction has 159 states and 227 transitions. [2018-11-22 22:09:25,566 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-22 22:09:25,567 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 227 transitions. [2018-11-22 22:09:25,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-22 22:09:25,567 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:25,567 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:25,567 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:25,567 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:25,568 INFO L82 PathProgramCache]: Analyzing trace with hash 1251533860, now seen corresponding path program 2 times [2018-11-22 22:09:25,568 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:25,568 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:25,579 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:25,610 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:25,610 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:25,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:25,774 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 10 proven. 8 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-22 22:09:25,774 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:26,160 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:26,160 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:26,181 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:26,204 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:26,204 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:26,207 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:26,315 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-22 22:09:26,315 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:09:26,339 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-22 22:09:26,339 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [15] total 20 [2018-11-22 22:09:26,340 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-22 22:09:26,340 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-22 22:09:26,340 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=454, Unknown=0, NotChecked=0, Total=506 [2018-11-22 22:09:26,340 INFO L87 Difference]: Start difference. First operand 159 states and 227 transitions. Second operand 20 states. [2018-11-22 22:09:27,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:27,036 INFO L93 Difference]: Finished difference Result 214 states and 282 transitions. [2018-11-22 22:09:27,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-22 22:09:27,036 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 71 [2018-11-22 22:09:27,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:27,037 INFO L225 Difference]: With dead ends: 214 [2018-11-22 22:09:27,037 INFO L226 Difference]: Without dead ends: 174 [2018-11-22 22:09:27,038 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 170 GetRequests, 134 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 2 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=171, Invalid=1089, Unknown=0, NotChecked=0, Total=1260 [2018-11-22 22:09:27,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-11-22 22:09:27,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 151. [2018-11-22 22:09:27,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-22 22:09:27,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 206 transitions. [2018-11-22 22:09:27,052 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 206 transitions. Word has length 71 [2018-11-22 22:09:27,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:27,053 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 206 transitions. [2018-11-22 22:09:27,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-22 22:09:27,053 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 206 transitions. [2018-11-22 22:09:27,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-22 22:09:27,054 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:27,054 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:27,054 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:27,054 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:27,054 INFO L82 PathProgramCache]: Analyzing trace with hash 1043562547, now seen corresponding path program 1 times [2018-11-22 22:09:27,054 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:27,054 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:27,072 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:09:27,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:27,137 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:27,428 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:09:27,428 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:28,493 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:09:28,494 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:28,494 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:28,500 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:28,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:28,531 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:29,064 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:09:29,064 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:29,166 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 44 [2018-11-22 22:09:31,101 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:09:31,116 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:31,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 13, 14] total 38 [2018-11-22 22:09:31,116 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-11-22 22:09:31,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-11-22 22:09:31,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=174, Invalid=1232, Unknown=0, NotChecked=0, Total=1406 [2018-11-22 22:09:31,117 INFO L87 Difference]: Start difference. First operand 151 states and 206 transitions. Second operand 38 states. [2018-11-22 22:09:31,778 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 48 [2018-11-22 22:09:32,397 WARN L180 SmtUtils]: Spent 191.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 45 [2018-11-22 22:09:32,743 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 46 [2018-11-22 22:09:33,033 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 43 [2018-11-22 22:09:33,440 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 45 [2018-11-22 22:09:33,699 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 47 [2018-11-22 22:09:34,746 WARN L180 SmtUtils]: Spent 258.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 55 [2018-11-22 22:09:35,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:35,867 INFO L93 Difference]: Finished difference Result 200 states and 283 transitions. [2018-11-22 22:09:35,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-22 22:09:35,869 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 71 [2018-11-22 22:09:35,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:35,870 INFO L225 Difference]: With dead ends: 200 [2018-11-22 22:09:35,870 INFO L226 Difference]: Without dead ends: 189 [2018-11-22 22:09:35,871 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 296 GetRequests, 240 SyntacticMatches, 6 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 502 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=446, Invalid=2206, Unknown=0, NotChecked=0, Total=2652 [2018-11-22 22:09:35,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-11-22 22:09:35,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 163. [2018-11-22 22:09:35,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-11-22 22:09:35,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 230 transitions. [2018-11-22 22:09:35,903 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 230 transitions. Word has length 71 [2018-11-22 22:09:35,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:35,903 INFO L480 AbstractCegarLoop]: Abstraction has 163 states and 230 transitions. [2018-11-22 22:09:35,903 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-11-22 22:09:35,904 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 230 transitions. [2018-11-22 22:09:35,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-22 22:09:35,907 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:35,907 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:35,907 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:35,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:35,908 INFO L82 PathProgramCache]: Analyzing trace with hash 1017205495, now seen corresponding path program 2 times [2018-11-22 22:09:35,908 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:35,908 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:35,927 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:36,007 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:36,007 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:36,018 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:36,340 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:09:36,340 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:37,366 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:09:37,367 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:37,368 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:37,383 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:09:37,416 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:09:37,416 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:09:37,418 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:37,931 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:09:37,931 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:39,927 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:09:39,941 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:09:39,942 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 13, 14] total 38 [2018-11-22 22:09:39,942 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-11-22 22:09:39,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-11-22 22:09:39,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=1235, Unknown=0, NotChecked=0, Total=1406 [2018-11-22 22:09:39,942 INFO L87 Difference]: Start difference. First operand 163 states and 230 transitions. Second operand 38 states. [2018-11-22 22:09:40,591 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 47 [2018-11-22 22:09:41,358 WARN L180 SmtUtils]: Spent 207.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 44 [2018-11-22 22:09:41,957 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 43 [2018-11-22 22:09:42,180 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 38 [2018-11-22 22:09:42,529 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 46 [2018-11-22 22:09:42,881 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 45 [2018-11-22 22:09:43,218 WARN L180 SmtUtils]: Spent 209.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 50 [2018-11-22 22:09:44,093 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 36 [2018-11-22 22:09:44,922 WARN L180 SmtUtils]: Spent 249.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 55 [2018-11-22 22:09:45,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:45,648 INFO L93 Difference]: Finished difference Result 205 states and 290 transitions. [2018-11-22 22:09:45,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-22 22:09:45,649 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 71 [2018-11-22 22:09:45,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:45,650 INFO L225 Difference]: With dead ends: 205 [2018-11-22 22:09:45,651 INFO L226 Difference]: Without dead ends: 194 [2018-11-22 22:09:45,651 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 296 GetRequests, 242 SyntacticMatches, 4 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 505 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=449, Invalid=2203, Unknown=0, NotChecked=0, Total=2652 [2018-11-22 22:09:45,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-11-22 22:09:45,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 173. [2018-11-22 22:09:45,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-11-22 22:09:45,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 247 transitions. [2018-11-22 22:09:45,681 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 247 transitions. Word has length 71 [2018-11-22 22:09:45,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:45,681 INFO L480 AbstractCegarLoop]: Abstraction has 173 states and 247 transitions. [2018-11-22 22:09:45,681 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-11-22 22:09:45,681 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 247 transitions. [2018-11-22 22:09:45,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-22 22:09:45,682 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:45,682 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:45,682 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:45,682 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:45,682 INFO L82 PathProgramCache]: Analyzing trace with hash 1098580064, now seen corresponding path program 1 times [2018-11-22 22:09:45,682 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:45,682 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:45,695 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:09:45,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:45,713 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:45,802 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:09:45,802 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:45,880 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:45,880 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:45,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:45,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:45,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:47,017 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-22 22:09:47,018 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:09:47,032 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-22 22:09:47,033 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [13] total 29 [2018-11-22 22:09:47,033 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-22 22:09:47,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-22 22:09:47,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=785, Unknown=0, NotChecked=0, Total=870 [2018-11-22 22:09:47,033 INFO L87 Difference]: Start difference. First operand 173 states and 247 transitions. Second operand 29 states. [2018-11-22 22:09:48,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:48,660 INFO L93 Difference]: Finished difference Result 200 states and 276 transitions. [2018-11-22 22:09:48,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-22 22:09:48,660 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 71 [2018-11-22 22:09:48,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:48,661 INFO L225 Difference]: With dead ends: 200 [2018-11-22 22:09:48,661 INFO L226 Difference]: Without dead ends: 191 [2018-11-22 22:09:48,662 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 118 SyntacticMatches, 3 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 303 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=204, Invalid=1518, Unknown=0, NotChecked=0, Total=1722 [2018-11-22 22:09:48,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-11-22 22:09:48,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 173. [2018-11-22 22:09:48,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-11-22 22:09:48,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 246 transitions. [2018-11-22 22:09:48,695 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 246 transitions. Word has length 71 [2018-11-22 22:09:48,695 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:48,695 INFO L480 AbstractCegarLoop]: Abstraction has 173 states and 246 transitions. [2018-11-22 22:09:48,695 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-22 22:09:48,695 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 246 transitions. [2018-11-22 22:09:48,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-22 22:09:48,696 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:48,696 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:48,696 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:48,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:48,696 INFO L82 PathProgramCache]: Analyzing trace with hash -1669060429, now seen corresponding path program 1 times [2018-11-22 22:09:48,697 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:48,697 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:48,714 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:48,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:48,790 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:49,057 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-22 22:09:49,058 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:49,177 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 43 [2018-11-22 22:09:50,447 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 9 proven. 11 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-22 22:09:50,448 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:09:50,448 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:09:50,454 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:50,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:50,532 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:09:51,864 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 12 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-22 22:09:51,865 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:09:52,331 WARN L180 SmtUtils]: Spent 234.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 63 [2018-11-22 22:09:53,638 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-22 22:09:53,638 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 18] total 34 [2018-11-22 22:09:53,638 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-11-22 22:09:53,638 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-11-22 22:09:53,638 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=1350, Unknown=0, NotChecked=0, Total=1560 [2018-11-22 22:09:53,639 INFO L87 Difference]: Start difference. First operand 173 states and 246 transitions. Second operand 34 states. [2018-11-22 22:09:54,919 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 39 [2018-11-22 22:09:55,201 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 39 [2018-11-22 22:09:55,564 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 41 [2018-11-22 22:09:56,943 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 43 [2018-11-22 22:09:57,200 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 45 [2018-11-22 22:09:58,118 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification that was a NOOP. DAG size: 72 [2018-11-22 22:09:59,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:09:59,917 INFO L93 Difference]: Finished difference Result 242 states and 323 transitions. [2018-11-22 22:09:59,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-22 22:09:59,918 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 76 [2018-11-22 22:09:59,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:09:59,919 INFO L225 Difference]: With dead ends: 242 [2018-11-22 22:09:59,919 INFO L226 Difference]: Without dead ends: 213 [2018-11-22 22:09:59,920 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 254 GetRequests, 194 SyntacticMatches, 6 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 877 ImplicationChecksByTransitivity, 7.7s TimeCoverageRelationStatistics Valid=490, Invalid=2590, Unknown=0, NotChecked=0, Total=3080 [2018-11-22 22:09:59,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-11-22 22:09:59,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 174. [2018-11-22 22:09:59,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-11-22 22:09:59,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 227 transitions. [2018-11-22 22:09:59,941 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 227 transitions. Word has length 76 [2018-11-22 22:09:59,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:09:59,941 INFO L480 AbstractCegarLoop]: Abstraction has 174 states and 227 transitions. [2018-11-22 22:09:59,941 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-11-22 22:09:59,941 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 227 transitions. [2018-11-22 22:09:59,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-22 22:09:59,941 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:09:59,941 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:09:59,942 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:09:59,942 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:09:59,942 INFO L82 PathProgramCache]: Analyzing trace with hash 1038546648, now seen corresponding path program 1 times [2018-11-22 22:09:59,942 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:09:59,942 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:09:59,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:09:59,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:09:59,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:00,026 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-22 22:10:00,027 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:00,069 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-22 22:10:00,070 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:00,070 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:00,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:00,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:00,092 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:00,095 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-22 22:10:00,095 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:00,132 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-22 22:10:00,156 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:10:00,156 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6] total 6 [2018-11-22 22:10:00,157 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 22:10:00,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 22:10:00,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 22:10:00,157 INFO L87 Difference]: Start difference. First operand 174 states and 227 transitions. Second operand 6 states. [2018-11-22 22:10:00,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:00,200 INFO L93 Difference]: Finished difference Result 191 states and 245 transitions. [2018-11-22 22:10:00,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 22:10:00,200 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-11-22 22:10:00,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:00,201 INFO L225 Difference]: With dead ends: 191 [2018-11-22 22:10:00,201 INFO L226 Difference]: Without dead ends: 186 [2018-11-22 22:10:00,201 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 291 GetRequests, 282 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-22 22:10:00,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-11-22 22:10:00,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 174. [2018-11-22 22:10:00,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-11-22 22:10:00,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 227 transitions. [2018-11-22 22:10:00,223 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 227 transitions. Word has length 73 [2018-11-22 22:10:00,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:00,223 INFO L480 AbstractCegarLoop]: Abstraction has 174 states and 227 transitions. [2018-11-22 22:10:00,223 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 22:10:00,224 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 227 transitions. [2018-11-22 22:10:00,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-22 22:10:00,224 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:00,224 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:00,224 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:00,225 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:00,225 INFO L82 PathProgramCache]: Analyzing trace with hash 1937569667, now seen corresponding path program 1 times [2018-11-22 22:10:00,225 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:00,225 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:00,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:00,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:00,312 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:00,595 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:00,595 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:01,591 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:10:01,592 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:01,592 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:01,601 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:01,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:01,643 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:01,657 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:01,657 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:01,997 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:10:02,011 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:10:02,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12, 13] total 22 [2018-11-22 22:10:02,012 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-22 22:10:02,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-22 22:10:02,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=386, Unknown=0, NotChecked=0, Total=462 [2018-11-22 22:10:02,012 INFO L87 Difference]: Start difference. First operand 174 states and 227 transitions. Second operand 22 states. [2018-11-22 22:10:02,501 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 41 [2018-11-22 22:10:02,952 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 38 [2018-11-22 22:10:03,261 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-22 22:10:03,628 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 43 [2018-11-22 22:10:04,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:04,381 INFO L93 Difference]: Finished difference Result 203 states and 261 transitions. [2018-11-22 22:10:04,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-22 22:10:04,382 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 73 [2018-11-22 22:10:04,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:04,383 INFO L225 Difference]: With dead ends: 203 [2018-11-22 22:10:04,383 INFO L226 Difference]: Without dead ends: 192 [2018-11-22 22:10:04,383 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 300 GetRequests, 268 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=196, Invalid=796, Unknown=0, NotChecked=0, Total=992 [2018-11-22 22:10:04,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states. [2018-11-22 22:10:04,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 174. [2018-11-22 22:10:04,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-11-22 22:10:04,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 225 transitions. [2018-11-22 22:10:04,416 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 225 transitions. Word has length 73 [2018-11-22 22:10:04,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:04,416 INFO L480 AbstractCegarLoop]: Abstraction has 174 states and 225 transitions. [2018-11-22 22:10:04,416 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-22 22:10:04,416 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 225 transitions. [2018-11-22 22:10:04,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-22 22:10:04,417 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:04,417 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:04,417 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:04,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:04,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1573324402, now seen corresponding path program 1 times [2018-11-22 22:10:04,417 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:04,417 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:04,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:04,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:04,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:04,839 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-22 22:10:04,839 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:05,455 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 47 [2018-11-22 22:10:06,314 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-22 22:10:06,315 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:06,315 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:06,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:06,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:06,409 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:06,443 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-22 22:10:06,443 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:06,737 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 46 [2018-11-22 22:10:06,952 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-22 22:10:06,968 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:10:06,968 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 15, 13, 15] total 24 [2018-11-22 22:10:06,969 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-22 22:10:06,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-22 22:10:06,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=473, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:10:06,969 INFO L87 Difference]: Start difference. First operand 174 states and 225 transitions. Second operand 24 states. [2018-11-22 22:10:09,256 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 29 [2018-11-22 22:10:09,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:09,860 INFO L93 Difference]: Finished difference Result 242 states and 301 transitions. [2018-11-22 22:10:09,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-22 22:10:09,862 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 77 [2018-11-22 22:10:09,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:09,863 INFO L225 Difference]: With dead ends: 242 [2018-11-22 22:10:09,863 INFO L226 Difference]: Without dead ends: 183 [2018-11-22 22:10:09,864 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 321 GetRequests, 281 SyntacticMatches, 3 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=262, Invalid=1220, Unknown=0, NotChecked=0, Total=1482 [2018-11-22 22:10:09,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-11-22 22:10:09,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 172. [2018-11-22 22:10:09,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-11-22 22:10:09,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 220 transitions. [2018-11-22 22:10:09,888 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 220 transitions. Word has length 77 [2018-11-22 22:10:09,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:09,889 INFO L480 AbstractCegarLoop]: Abstraction has 172 states and 220 transitions. [2018-11-22 22:10:09,889 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-22 22:10:09,889 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 220 transitions. [2018-11-22 22:10:09,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-22 22:10:09,889 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:09,889 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:09,889 INFO L423 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:09,889 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:09,890 INFO L82 PathProgramCache]: Analyzing trace with hash -880217657, now seen corresponding path program 2 times [2018-11-22 22:10:09,890 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:09,890 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:09,902 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:10:09,970 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:10:09,970 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:10:09,981 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:10,272 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:10,273 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:11,300 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:10:11,301 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:11,301 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:11,310 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:10:11,343 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:10:11,343 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:10:11,345 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:11,354 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:11,354 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:11,654 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 8 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-22 22:10:11,669 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:10:11,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12, 13] total 22 [2018-11-22 22:10:11,669 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-22 22:10:11,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-22 22:10:11,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=388, Unknown=0, NotChecked=0, Total=462 [2018-11-22 22:10:11,670 INFO L87 Difference]: Start difference. First operand 172 states and 220 transitions. Second operand 22 states. [2018-11-22 22:10:12,129 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 41 [2018-11-22 22:10:12,588 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 38 [2018-11-22 22:10:12,853 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-22 22:10:13,065 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 43 [2018-11-22 22:10:13,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:13,913 INFO L93 Difference]: Finished difference Result 193 states and 242 transitions. [2018-11-22 22:10:13,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-22 22:10:13,914 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 73 [2018-11-22 22:10:13,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:13,915 INFO L225 Difference]: With dead ends: 193 [2018-11-22 22:10:13,915 INFO L226 Difference]: Without dead ends: 179 [2018-11-22 22:10:13,915 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 300 GetRequests, 268 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=192, Invalid=800, Unknown=0, NotChecked=0, Total=992 [2018-11-22 22:10:13,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-11-22 22:10:13,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 169. [2018-11-22 22:10:13,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-11-22 22:10:13,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 215 transitions. [2018-11-22 22:10:13,935 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 215 transitions. Word has length 73 [2018-11-22 22:10:13,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:13,935 INFO L480 AbstractCegarLoop]: Abstraction has 169 states and 215 transitions. [2018-11-22 22:10:13,936 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-22 22:10:13,936 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 215 transitions. [2018-11-22 22:10:13,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-11-22 22:10:13,936 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:13,936 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:13,936 INFO L423 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:13,936 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:13,936 INFO L82 PathProgramCache]: Analyzing trace with hash 237463554, now seen corresponding path program 1 times [2018-11-22 22:10:13,937 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:13,937 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:13,957 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:10:13,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:13,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:14,021 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-22 22:10:14,021 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:10:14,023 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:10:14,023 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 22:10:14,024 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 22:10:14,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 22:10:14,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 22:10:14,024 INFO L87 Difference]: Start difference. First operand 169 states and 215 transitions. Second operand 6 states. [2018-11-22 22:10:14,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:14,063 INFO L93 Difference]: Finished difference Result 181 states and 227 transitions. [2018-11-22 22:10:14,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 22:10:14,063 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 75 [2018-11-22 22:10:14,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:14,064 INFO L225 Difference]: With dead ends: 181 [2018-11-22 22:10:14,064 INFO L226 Difference]: Without dead ends: 172 [2018-11-22 22:10:14,065 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 70 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-22 22:10:14,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-11-22 22:10:14,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 169. [2018-11-22 22:10:14,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-11-22 22:10:14,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 209 transitions. [2018-11-22 22:10:14,086 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 209 transitions. Word has length 75 [2018-11-22 22:10:14,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:14,086 INFO L480 AbstractCegarLoop]: Abstraction has 169 states and 209 transitions. [2018-11-22 22:10:14,086 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 22:10:14,086 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 209 transitions. [2018-11-22 22:10:14,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-22 22:10:14,087 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:14,087 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:14,087 INFO L423 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:14,087 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:14,087 INFO L82 PathProgramCache]: Analyzing trace with hash 1637188566, now seen corresponding path program 1 times [2018-11-22 22:10:14,087 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:14,087 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:14,100 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:14,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:14,154 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:14,334 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 18 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:14,334 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:14,462 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:14,462 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:14,468 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:14,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:14,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:14,663 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification that was a NOOP. DAG size: 22 [2018-11-22 22:10:14,786 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 24 proven. 3 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-22 22:10:14,786 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:14,993 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:10:14,993 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15] total 15 [2018-11-22 22:10:14,993 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-22 22:10:14,994 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-22 22:10:14,994 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-11-22 22:10:14,994 INFO L87 Difference]: Start difference. First operand 169 states and 209 transitions. Second operand 15 states. [2018-11-22 22:10:20,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:20,826 INFO L93 Difference]: Finished difference Result 192 states and 237 transitions. [2018-11-22 22:10:20,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-22 22:10:20,827 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 80 [2018-11-22 22:10:20,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:20,828 INFO L225 Difference]: With dead ends: 192 [2018-11-22 22:10:20,828 INFO L226 Difference]: Without dead ends: 183 [2018-11-22 22:10:20,828 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 185 GetRequests, 162 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=67, Invalid=439, Unknown=0, NotChecked=0, Total=506 [2018-11-22 22:10:20,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-11-22 22:10:20,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 176. [2018-11-22 22:10:20,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-11-22 22:10:20,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 221 transitions. [2018-11-22 22:10:20,851 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 221 transitions. Word has length 80 [2018-11-22 22:10:20,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:20,852 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 221 transitions. [2018-11-22 22:10:20,852 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-22 22:10:20,852 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 221 transitions. [2018-11-22 22:10:20,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-22 22:10:20,852 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:20,853 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:20,853 INFO L423 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:20,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:20,853 INFO L82 PathProgramCache]: Analyzing trace with hash -1107258990, now seen corresponding path program 2 times [2018-11-22 22:10:20,853 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:20,853 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:20,866 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:10:20,922 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:10:20,922 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:10:20,932 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:21,077 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:21,077 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-22 22:10:21,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 22:10:21,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-11-22 22:10:21,079 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 22:10:21,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 22:10:21,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2018-11-22 22:10:21,079 INFO L87 Difference]: Start difference. First operand 176 states and 221 transitions. Second operand 11 states. [2018-11-22 22:10:23,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:23,632 INFO L93 Difference]: Finished difference Result 190 states and 234 transitions. [2018-11-22 22:10:23,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-22 22:10:23,633 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 80 [2018-11-22 22:10:23,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:23,633 INFO L225 Difference]: With dead ends: 190 [2018-11-22 22:10:23,634 INFO L226 Difference]: Without dead ends: 181 [2018-11-22 22:10:23,634 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=49, Invalid=223, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:10:23,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-11-22 22:10:23,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 165. [2018-11-22 22:10:23,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-11-22 22:10:23,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 207 transitions. [2018-11-22 22:10:23,655 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 207 transitions. Word has length 80 [2018-11-22 22:10:23,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:23,655 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 207 transitions. [2018-11-22 22:10:23,655 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 22:10:23,655 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 207 transitions. [2018-11-22 22:10:23,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-22 22:10:23,656 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:23,656 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:23,656 INFO L423 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:23,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:23,656 INFO L82 PathProgramCache]: Analyzing trace with hash -1359709994, now seen corresponding path program 1 times [2018-11-22 22:10:23,656 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:23,656 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:23,670 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:10:23,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:23,765 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:24,329 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:10:24,329 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:26,523 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:26,524 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:26,524 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:26,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:26,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:26,705 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:27,362 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:10:27,362 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:28,425 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-22 22:10:28,425 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 16] total 31 [2018-11-22 22:10:28,425 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-22 22:10:28,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-22 22:10:28,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=937, Unknown=0, NotChecked=0, Total=1122 [2018-11-22 22:10:28,426 INFO L87 Difference]: Start difference. First operand 165 states and 207 transitions. Second operand 31 states. [2018-11-22 22:10:30,335 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 38 [2018-11-22 22:10:30,981 WARN L180 SmtUtils]: Spent 244.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 54 [2018-11-22 22:10:32,317 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 38 [2018-11-22 22:10:33,012 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 36 [2018-11-22 22:10:33,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:33,317 INFO L93 Difference]: Finished difference Result 219 states and 269 transitions. [2018-11-22 22:10:33,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-22 22:10:33,318 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 80 [2018-11-22 22:10:33,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:33,319 INFO L225 Difference]: With dead ends: 219 [2018-11-22 22:10:33,319 INFO L226 Difference]: Without dead ends: 194 [2018-11-22 22:10:33,320 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 264 GetRequests, 213 SyntacticMatches, 2 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 400 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=429, Invalid=2121, Unknown=0, NotChecked=0, Total=2550 [2018-11-22 22:10:33,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-11-22 22:10:33,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 165. [2018-11-22 22:10:33,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-11-22 22:10:33,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 207 transitions. [2018-11-22 22:10:33,343 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 207 transitions. Word has length 80 [2018-11-22 22:10:33,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:33,344 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 207 transitions. [2018-11-22 22:10:33,344 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-22 22:10:33,344 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 207 transitions. [2018-11-22 22:10:33,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-22 22:10:33,344 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:33,345 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:33,345 INFO L423 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:33,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:33,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1037358574, now seen corresponding path program 2 times [2018-11-22 22:10:33,345 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:33,345 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:33,358 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:10:33,458 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:10:33,458 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:10:33,474 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:34,035 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:10:34,035 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:36,208 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:36,209 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:36,209 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:36,214 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:10:36,370 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:10:36,370 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:10:36,372 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:37,588 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:10:37,588 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:37,920 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification that was a NOOP. DAG size: 62 [2018-11-22 22:10:39,833 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-22 22:10:39,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 18] total 35 [2018-11-22 22:10:39,833 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-22 22:10:39,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-22 22:10:39,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=218, Invalid=1422, Unknown=0, NotChecked=0, Total=1640 [2018-11-22 22:10:39,834 INFO L87 Difference]: Start difference. First operand 165 states and 207 transitions. Second operand 35 states. [2018-11-22 22:10:40,601 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 38 [2018-11-22 22:10:41,277 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 39 [2018-11-22 22:10:42,660 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 39 [2018-11-22 22:10:42,982 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 42 [2018-11-22 22:10:44,080 WARN L180 SmtUtils]: Spent 249.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 38 [2018-11-22 22:10:44,540 WARN L180 SmtUtils]: Spent 196.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 38 [2018-11-22 22:10:44,892 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 30 [2018-11-22 22:10:47,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:47,036 INFO L93 Difference]: Finished difference Result 219 states and 271 transitions. [2018-11-22 22:10:47,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-22 22:10:47,038 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 80 [2018-11-22 22:10:47,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:47,038 INFO L225 Difference]: With dead ends: 219 [2018-11-22 22:10:47,039 INFO L226 Difference]: Without dead ends: 199 [2018-11-22 22:10:47,039 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 270 GetRequests, 211 SyntacticMatches, 2 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 661 ImplicationChecksByTransitivity, 9.3s TimeCoverageRelationStatistics Valid=495, Invalid=2927, Unknown=0, NotChecked=0, Total=3422 [2018-11-22 22:10:47,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-11-22 22:10:47,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 185. [2018-11-22 22:10:47,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-11-22 22:10:47,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 232 transitions. [2018-11-22 22:10:47,077 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 232 transitions. Word has length 80 [2018-11-22 22:10:47,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:47,077 INFO L480 AbstractCegarLoop]: Abstraction has 185 states and 232 transitions. [2018-11-22 22:10:47,077 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-22 22:10:47,077 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 232 transitions. [2018-11-22 22:10:47,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-22 22:10:47,077 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:47,077 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:47,078 INFO L423 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:47,078 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:47,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1128172057, now seen corresponding path program 1 times [2018-11-22 22:10:47,078 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:47,078 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:47,092 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:10:47,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:47,112 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:47,167 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 17 proven. 5 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:47,167 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:47,309 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 19 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:47,310 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:47,310 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:47,316 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:47,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:47,333 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:47,338 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 19 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:47,338 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:47,399 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 19 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:47,414 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:10:47,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10, 10] total 18 [2018-11-22 22:10:47,414 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-22 22:10:47,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-22 22:10:47,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-11-22 22:10:47,415 INFO L87 Difference]: Start difference. First operand 185 states and 232 transitions. Second operand 18 states. [2018-11-22 22:10:47,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:47,876 INFO L93 Difference]: Finished difference Result 196 states and 244 transitions. [2018-11-22 22:10:47,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-22 22:10:47,876 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 81 [2018-11-22 22:10:47,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:47,877 INFO L225 Difference]: With dead ends: 196 [2018-11-22 22:10:47,877 INFO L226 Difference]: Without dead ends: 161 [2018-11-22 22:10:47,877 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 310 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2018-11-22 22:10:47,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-11-22 22:10:47,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 161. [2018-11-22 22:10:47,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-11-22 22:10:47,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 204 transitions. [2018-11-22 22:10:47,907 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 204 transitions. Word has length 81 [2018-11-22 22:10:47,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:47,907 INFO L480 AbstractCegarLoop]: Abstraction has 161 states and 204 transitions. [2018-11-22 22:10:47,907 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-22 22:10:47,907 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 204 transitions. [2018-11-22 22:10:47,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-22 22:10:47,907 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:47,907 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:47,908 INFO L423 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:47,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:47,908 INFO L82 PathProgramCache]: Analyzing trace with hash 1949643741, now seen corresponding path program 2 times [2018-11-22 22:10:47,908 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:47,908 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:47,923 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:10:47,956 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:10:47,956 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:10:47,959 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:48,014 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 20 proven. 2 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:48,014 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:48,152 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-22 22:10:48,153 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-22 22:10:48,153 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [11] total 17 [2018-11-22 22:10:48,153 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-22 22:10:48,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-22 22:10:48,153 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2018-11-22 22:10:48,153 INFO L87 Difference]: Start difference. First operand 161 states and 204 transitions. Second operand 17 states. [2018-11-22 22:10:48,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:48,588 INFO L93 Difference]: Finished difference Result 172 states and 215 transitions. [2018-11-22 22:10:48,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-22 22:10:48,589 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 81 [2018-11-22 22:10:48,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:48,590 INFO L225 Difference]: With dead ends: 172 [2018-11-22 22:10:48,590 INFO L226 Difference]: Without dead ends: 131 [2018-11-22 22:10:48,591 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 149 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=468, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:10:48,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-11-22 22:10:48,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 128. [2018-11-22 22:10:48,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-11-22 22:10:48,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 167 transitions. [2018-11-22 22:10:48,608 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 167 transitions. Word has length 81 [2018-11-22 22:10:48,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:48,609 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 167 transitions. [2018-11-22 22:10:48,609 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-22 22:10:48,609 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 167 transitions. [2018-11-22 22:10:48,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-22 22:10:48,610 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:48,610 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:48,610 INFO L423 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:48,610 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:48,610 INFO L82 PathProgramCache]: Analyzing trace with hash -1581370087, now seen corresponding path program 1 times [2018-11-22 22:10:48,610 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:48,610 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 78 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:48,630 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:10:48,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:48,654 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:48,717 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:48,717 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:48,883 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:48,885 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:48,885 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:48,894 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:48,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:48,913 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:48,921 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:48,921 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:49,052 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:49,077 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:10:49,077 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 15 [2018-11-22 22:10:49,077 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-22 22:10:49,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-22 22:10:49,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-11-22 22:10:49,078 INFO L87 Difference]: Start difference. First operand 128 states and 167 transitions. Second operand 15 states. [2018-11-22 22:10:49,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:10:49,537 INFO L93 Difference]: Finished difference Result 137 states and 175 transitions. [2018-11-22 22:10:49,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-22 22:10:49,538 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 81 [2018-11-22 22:10:49,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:10:49,538 INFO L225 Difference]: With dead ends: 137 [2018-11-22 22:10:49,538 INFO L226 Difference]: Without dead ends: 124 [2018-11-22 22:10:49,539 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 329 GetRequests, 305 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=99, Invalid=363, Unknown=0, NotChecked=0, Total=462 [2018-11-22 22:10:49,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-11-22 22:10:49,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 124. [2018-11-22 22:10:49,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-11-22 22:10:49,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 161 transitions. [2018-11-22 22:10:49,555 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 161 transitions. Word has length 81 [2018-11-22 22:10:49,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:10:49,555 INFO L480 AbstractCegarLoop]: Abstraction has 124 states and 161 transitions. [2018-11-22 22:10:49,555 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-22 22:10:49,555 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 161 transitions. [2018-11-22 22:10:49,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-22 22:10:49,556 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:10:49,556 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:10:49,556 INFO L423 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:10:49,556 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:10:49,556 INFO L82 PathProgramCache]: Analyzing trace with hash 1716375510, now seen corresponding path program 1 times [2018-11-22 22:10:49,556 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:10:49,556 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 80 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:10:49,571 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:49,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:49,662 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:50,238 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:10:50,238 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:52,332 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:52,333 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:10:52,333 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:10:52,340 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:10:52,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:10:52,497 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:10:53,894 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:10:53,894 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:10:55,469 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification that was a NOOP. DAG size: 62 [2018-11-22 22:10:57,764 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:10:57,778 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:10:57,779 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 18, 21] total 49 [2018-11-22 22:10:57,779 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-22 22:10:57,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-22 22:10:57,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=259, Invalid=2093, Unknown=0, NotChecked=0, Total=2352 [2018-11-22 22:10:57,780 INFO L87 Difference]: Start difference. First operand 124 states and 161 transitions. Second operand 49 states. [2018-11-22 22:10:58,823 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 44 [2018-11-22 22:11:03,064 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 41 [2018-11-22 22:11:03,496 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 43 [2018-11-22 22:11:04,614 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 41 [2018-11-22 22:11:05,597 WARN L180 SmtUtils]: Spent 280.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 41 [2018-11-22 22:11:06,257 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 42 [2018-11-22 22:11:08,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:11:08,963 INFO L93 Difference]: Finished difference Result 170 states and 213 transitions. [2018-11-22 22:11:08,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-11-22 22:11:08,965 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 78 [2018-11-22 22:11:08,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:11:08,966 INFO L225 Difference]: With dead ends: 170 [2018-11-22 22:11:08,966 INFO L226 Difference]: Without dead ends: 148 [2018-11-22 22:11:08,967 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 258 SyntacticMatches, 5 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1374 ImplicationChecksByTransitivity, 13.3s TimeCoverageRelationStatistics Valid=934, Invalid=5708, Unknown=0, NotChecked=0, Total=6642 [2018-11-22 22:11:08,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-11-22 22:11:08,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 132. [2018-11-22 22:11:08,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-11-22 22:11:08,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 169 transitions. [2018-11-22 22:11:08,985 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 169 transitions. Word has length 78 [2018-11-22 22:11:08,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:11:08,985 INFO L480 AbstractCegarLoop]: Abstraction has 132 states and 169 transitions. [2018-11-22 22:11:08,985 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-22 22:11:08,985 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 169 transitions. [2018-11-22 22:11:08,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-22 22:11:08,986 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:11:08,986 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:11:08,986 INFO L423 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:11:08,986 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:11:08,986 INFO L82 PathProgramCache]: Analyzing trace with hash -178410659, now seen corresponding path program 2 times [2018-11-22 22:11:08,986 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:11:08,986 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 82 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:11:09,002 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:09,038 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:09,038 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:09,041 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:09,109 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:11:09,109 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:09,229 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:11:09,230 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:11:09,230 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:11:09,238 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:09,256 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:09,257 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:09,258 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:09,264 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:11:09,264 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:09,328 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:11:09,343 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:11:09,343 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 15 [2018-11-22 22:11:09,343 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-22 22:11:09,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-22 22:11:09,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-11-22 22:11:09,344 INFO L87 Difference]: Start difference. First operand 132 states and 169 transitions. Second operand 15 states. [2018-11-22 22:11:09,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:11:09,718 INFO L93 Difference]: Finished difference Result 139 states and 175 transitions. [2018-11-22 22:11:09,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 22:11:09,719 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 81 [2018-11-22 22:11:09,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:11:09,720 INFO L225 Difference]: With dead ends: 139 [2018-11-22 22:11:09,720 INFO L226 Difference]: Without dead ends: 118 [2018-11-22 22:11:09,720 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 329 GetRequests, 304 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=102, Invalid=360, Unknown=0, NotChecked=0, Total=462 [2018-11-22 22:11:09,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-11-22 22:11:09,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 116. [2018-11-22 22:11:09,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-11-22 22:11:09,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 146 transitions. [2018-11-22 22:11:09,748 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 146 transitions. Word has length 81 [2018-11-22 22:11:09,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:11:09,749 INFO L480 AbstractCegarLoop]: Abstraction has 116 states and 146 transitions. [2018-11-22 22:11:09,749 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-22 22:11:09,749 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 146 transitions. [2018-11-22 22:11:09,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-22 22:11:09,749 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:11:09,749 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:11:09,749 INFO L423 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:11:09,750 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:11:09,750 INFO L82 PathProgramCache]: Analyzing trace with hash -1512796842, now seen corresponding path program 2 times [2018-11-22 22:11:09,750 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:11:09,750 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 84 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:11:09,773 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:09,928 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:09,928 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:09,952 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:10,650 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:11:10,650 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:12,971 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:11:12,973 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:11:12,973 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:11:12,979 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:13,140 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:13,140 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:13,143 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:14,578 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-11-22 22:11:14,578 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:18,088 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-22 22:11:18,103 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:11:18,103 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 18, 21] total 48 [2018-11-22 22:11:18,104 INFO L459 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-11-22 22:11:18,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-11-22 22:11:18,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=246, Invalid=2010, Unknown=0, NotChecked=0, Total=2256 [2018-11-22 22:11:18,104 INFO L87 Difference]: Start difference. First operand 116 states and 146 transitions. Second operand 48 states. [2018-11-22 22:11:18,959 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 55 [2018-11-22 22:11:19,952 WARN L180 SmtUtils]: Spent 245.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 68 [2018-11-22 22:11:20,674 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 54 [2018-11-22 22:11:21,354 WARN L180 SmtUtils]: Spent 264.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 41 [2018-11-22 22:11:22,102 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 41 [2018-11-22 22:11:22,830 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 42 [2018-11-22 22:11:23,679 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 45 [2018-11-22 22:11:24,528 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 41 [2018-11-22 22:11:24,924 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 43 [2018-11-22 22:11:26,021 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 41 [2018-11-22 22:11:26,410 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 41 [2018-11-22 22:11:26,928 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 42 [2018-11-22 22:11:27,708 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 42 [2018-11-22 22:11:28,700 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 45 [2018-11-22 22:11:29,044 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 48 [2018-11-22 22:11:29,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:11:29,964 INFO L93 Difference]: Finished difference Result 145 states and 181 transitions. [2018-11-22 22:11:29,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-22 22:11:29,965 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 78 [2018-11-22 22:11:29,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:11:29,965 INFO L225 Difference]: With dead ends: 145 [2018-11-22 22:11:29,965 INFO L226 Difference]: Without dead ends: 132 [2018-11-22 22:11:29,966 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 339 GetRequests, 260 SyntacticMatches, 4 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1164 ImplicationChecksByTransitivity, 13.8s TimeCoverageRelationStatistics Valid=828, Invalid=5024, Unknown=0, NotChecked=0, Total=5852 [2018-11-22 22:11:29,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-11-22 22:11:29,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 111. [2018-11-22 22:11:29,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-11-22 22:11:29,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 139 transitions. [2018-11-22 22:11:29,981 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 139 transitions. Word has length 78 [2018-11-22 22:11:29,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:11:29,981 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 139 transitions. [2018-11-22 22:11:29,981 INFO L481 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-11-22 22:11:29,981 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 139 transitions. [2018-11-22 22:11:29,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-22 22:11:29,982 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:11:29,982 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:11:29,982 INFO L423 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:11:29,982 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:11:29,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1912539214, now seen corresponding path program 1 times [2018-11-22 22:11:29,982 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:11:29,982 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 86 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:11:29,997 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:11:30,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:11:30,378 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:31,876 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:11:31,876 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:32,181 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification that was a NOOP. DAG size: 62 [2018-11-22 22:11:33,517 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:11:33,517 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:11:33,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:11:34,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:11:34,244 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:34,516 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 11 proven. 16 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-22 22:11:34,516 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:34,640 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification that was a NOOP. DAG size: 62 [2018-11-22 22:11:35,175 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:11:35,175 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22] total 22 [2018-11-22 22:11:35,175 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-22 22:11:35,175 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-22 22:11:35,175 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=695, Unknown=0, NotChecked=0, Total=756 [2018-11-22 22:11:35,175 INFO L87 Difference]: Start difference. First operand 111 states and 139 transitions. Second operand 22 states. [2018-11-22 22:11:39,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:11:39,089 INFO L93 Difference]: Finished difference Result 127 states and 156 transitions. [2018-11-22 22:11:39,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-22 22:11:39,089 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 83 [2018-11-22 22:11:39,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:11:39,090 INFO L225 Difference]: With dead ends: 127 [2018-11-22 22:11:39,090 INFO L226 Difference]: Without dead ends: 118 [2018-11-22 22:11:39,091 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 160 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 194 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=137, Invalid=1669, Unknown=0, NotChecked=0, Total=1806 [2018-11-22 22:11:39,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-11-22 22:11:39,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 109. [2018-11-22 22:11:39,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-11-22 22:11:39,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 134 transitions. [2018-11-22 22:11:39,107 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 134 transitions. Word has length 83 [2018-11-22 22:11:39,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:11:39,107 INFO L480 AbstractCegarLoop]: Abstraction has 109 states and 134 transitions. [2018-11-22 22:11:39,108 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-22 22:11:39,108 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 134 transitions. [2018-11-22 22:11:39,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 22:11:39,108 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:11:39,108 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:11:39,108 INFO L423 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:11:39,108 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:11:39,109 INFO L82 PathProgramCache]: Analyzing trace with hash -107585423, now seen corresponding path program 1 times [2018-11-22 22:11:39,109 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:11:39,109 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 88 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:11:39,125 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:11:39,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:11:39,236 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:39,698 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:11:39,698 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:39,831 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 48 [2018-11-22 22:11:41,593 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-22 22:11:41,595 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:11:41,595 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:11:41,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:11:41,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:11:41,815 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:41,833 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:11:41,833 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:41,978 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 48 [2018-11-22 22:11:42,395 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-22 22:11:42,419 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:11:42,419 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 13, 14] total 24 [2018-11-22 22:11:42,420 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-22 22:11:42,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-22 22:11:42,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=472, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:11:42,420 INFO L87 Difference]: Start difference. First operand 109 states and 134 transitions. Second operand 24 states. [2018-11-22 22:11:43,724 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification that was a NOOP. DAG size: 63 [2018-11-22 22:11:46,692 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 35 [2018-11-22 22:11:47,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:11:47,718 INFO L93 Difference]: Finished difference Result 153 states and 186 transitions. [2018-11-22 22:11:47,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-22 22:11:47,719 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 84 [2018-11-22 22:11:47,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:11:47,720 INFO L225 Difference]: With dead ends: 153 [2018-11-22 22:11:47,720 INFO L226 Difference]: Without dead ends: 96 [2018-11-22 22:11:47,721 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 356 GetRequests, 312 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 254 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2018-11-22 22:11:47,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-11-22 22:11:47,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 87. [2018-11-22 22:11:47,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-11-22 22:11:47,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 106 transitions. [2018-11-22 22:11:47,736 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 106 transitions. Word has length 84 [2018-11-22 22:11:47,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:11:47,736 INFO L480 AbstractCegarLoop]: Abstraction has 87 states and 106 transitions. [2018-11-22 22:11:47,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-22 22:11:47,736 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 106 transitions. [2018-11-22 22:11:47,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-22 22:11:47,737 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:11:47,737 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:11:47,737 INFO L423 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:11:47,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:11:47,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1418902222, now seen corresponding path program 2 times [2018-11-22 22:11:47,737 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:11:47,737 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 90 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:11:47,750 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:48,023 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:48,023 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:48,039 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:49,528 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:11:49,528 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:51,086 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:11:51,086 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:11:51,092 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:51,850 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:51,850 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:51,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:52,113 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 11 proven. 16 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-22 22:11:52,113 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:52,752 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:11:52,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22] total 22 [2018-11-22 22:11:52,752 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-22 22:11:52,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-22 22:11:52,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=695, Unknown=0, NotChecked=0, Total=756 [2018-11-22 22:11:52,752 INFO L87 Difference]: Start difference. First operand 87 states and 106 transitions. Second operand 22 states. [2018-11-22 22:11:56,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:11:56,494 INFO L93 Difference]: Finished difference Result 103 states and 123 transitions. [2018-11-22 22:11:56,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-22 22:11:56,494 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 83 [2018-11-22 22:11:56,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:11:56,495 INFO L225 Difference]: With dead ends: 103 [2018-11-22 22:11:56,495 INFO L226 Difference]: Without dead ends: 89 [2018-11-22 22:11:56,495 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 160 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 193 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=137, Invalid=1669, Unknown=0, NotChecked=0, Total=1806 [2018-11-22 22:11:56,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-11-22 22:11:56,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 82. [2018-11-22 22:11:56,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-11-22 22:11:56,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 99 transitions. [2018-11-22 22:11:56,505 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 99 transitions. Word has length 83 [2018-11-22 22:11:56,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:11:56,505 INFO L480 AbstractCegarLoop]: Abstraction has 82 states and 99 transitions. [2018-11-22 22:11:56,505 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-22 22:11:56,505 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 99 transitions. [2018-11-22 22:11:56,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-22 22:11:56,505 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:11:56,505 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:11:56,505 INFO L423 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:11:56,505 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:11:56,505 INFO L82 PathProgramCache]: Analyzing trace with hash -1984707855, now seen corresponding path program 2 times [2018-11-22 22:11:56,506 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:11:56,506 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 92 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:11:56,517 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:56,623 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:56,623 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:56,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:57,140 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:11:57,140 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:58,997 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-22 22:11:58,999 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:11:58,999 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:11:59,006 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:11:59,216 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:11:59,216 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:11:59,219 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:11:59,236 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 10 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:11:59,236 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:11:59,340 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-22 22:11:59,737 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-22 22:11:59,752 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-22 22:11:59,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 13, 14] total 24 [2018-11-22 22:11:59,752 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-22 22:11:59,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-22 22:11:59,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=470, Unknown=0, NotChecked=0, Total=552 [2018-11-22 22:11:59,753 INFO L87 Difference]: Start difference. First operand 82 states and 99 transitions. Second operand 24 states. [2018-11-22 22:12:02,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:12:02,924 INFO L93 Difference]: Finished difference Result 102 states and 120 transitions. [2018-11-22 22:12:02,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-22 22:12:02,924 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 84 [2018-11-22 22:12:02,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:12:02,925 INFO L225 Difference]: With dead ends: 102 [2018-11-22 22:12:02,925 INFO L226 Difference]: Without dead ends: 73 [2018-11-22 22:12:02,925 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 351 GetRequests, 312 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 169 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=291, Invalid=1349, Unknown=0, NotChecked=0, Total=1640 [2018-11-22 22:12:02,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-11-22 22:12:02,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-11-22 22:12:02,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-11-22 22:12:02,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 87 transitions. [2018-11-22 22:12:02,934 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 87 transitions. Word has length 84 [2018-11-22 22:12:02,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:12:02,935 INFO L480 AbstractCegarLoop]: Abstraction has 73 states and 87 transitions. [2018-11-22 22:12:02,935 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-22 22:12:02,935 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 87 transitions. [2018-11-22 22:12:02,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-22 22:12:02,935 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:12:02,935 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:12:02,935 INFO L423 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:12:02,936 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:12:02,936 INFO L82 PathProgramCache]: Analyzing trace with hash 593862840, now seen corresponding path program 1 times [2018-11-22 22:12:02,936 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:12:02,936 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 94 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:12:02,952 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 22:12:03,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:12:03,262 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:12:05,297 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:12:05,297 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:12:05,700 WARN L180 SmtUtils]: Spent 209.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 62 [2018-11-22 22:12:06,975 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:12:06,975 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 95 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:12:06,981 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 22:12:07,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 22:12:07,663 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:12:10,168 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 11 proven. 17 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-22 22:12:10,168 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:12:10,373 WARN L180 SmtUtils]: Spent 201.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 65 [2018-11-22 22:12:12,115 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:12:12,115 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 24] total 32 [2018-11-22 22:12:12,116 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-11-22 22:12:12,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-11-22 22:12:12,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=1612, Unknown=0, NotChecked=0, Total=1722 [2018-11-22 22:12:12,116 INFO L87 Difference]: Start difference. First operand 73 states and 87 transitions. Second operand 32 states. [2018-11-22 22:12:17,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:12:17,654 INFO L93 Difference]: Finished difference Result 82 states and 96 transitions. [2018-11-22 22:12:17,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-22 22:12:17,655 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 85 [2018-11-22 22:12:17,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:12:17,655 INFO L225 Difference]: With dead ends: 82 [2018-11-22 22:12:17,655 INFO L226 Difference]: Without dead ends: 71 [2018-11-22 22:12:17,656 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 151 SyntacticMatches, 1 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 516 ImplicationChecksByTransitivity, 10.3s TimeCoverageRelationStatistics Valid=210, Invalid=3212, Unknown=0, NotChecked=0, Total=3422 [2018-11-22 22:12:17,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-11-22 22:12:17,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-11-22 22:12:17,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-11-22 22:12:17,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 83 transitions. [2018-11-22 22:12:17,663 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 83 transitions. Word has length 85 [2018-11-22 22:12:17,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:12:17,663 INFO L480 AbstractCegarLoop]: Abstraction has 71 states and 83 transitions. [2018-11-22 22:12:17,663 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-11-22 22:12:17,663 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 83 transitions. [2018-11-22 22:12:17,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-22 22:12:17,663 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 22:12:17,663 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 22:12:17,664 INFO L423 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 22:12:17,664 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 22:12:17,664 INFO L82 PathProgramCache]: Analyzing trace with hash 516304508, now seen corresponding path program 2 times [2018-11-22 22:12:17,664 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-22 22:12:17,664 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/cvc4nyu Starting monitored process 96 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-22 22:12:17,679 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-22 22:12:17,945 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:12:17,945 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:12:17,961 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:12:19,945 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-22 22:12:19,945 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:12:20,350 WARN L180 SmtUtils]: Spent 217.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 68 [2018-11-22 22:12:21,661 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 22:12:21,661 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/z3 Starting monitored process 97 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 22:12:21,667 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-22 22:12:22,349 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-22 22:12:22,349 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-22 22:12:22,352 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 22:12:24,654 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 11 proven. 17 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-22 22:12:24,654 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-22 22:12:24,918 WARN L180 SmtUtils]: Spent 261.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 68 [2018-11-22 22:12:25,447 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 22:12:25,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 24] total 31 [2018-11-22 22:12:25,447 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-22 22:12:25,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-22 22:12:25,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=1243, Unknown=0, NotChecked=0, Total=1332 [2018-11-22 22:12:25,448 INFO L87 Difference]: Start difference. First operand 71 states and 83 transitions. Second operand 31 states. [2018-11-22 22:12:30,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 22:12:30,981 INFO L93 Difference]: Finished difference Result 71 states and 83 transitions. [2018-11-22 22:12:30,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-22 22:12:30,982 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 85 [2018-11-22 22:12:30,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 22:12:30,983 INFO L225 Difference]: With dead ends: 71 [2018-11-22 22:12:30,983 INFO L226 Difference]: Without dead ends: 0 [2018-11-22 22:12:30,983 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 155 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 8.8s TimeCoverageRelationStatistics Valid=181, Invalid=2681, Unknown=0, NotChecked=0, Total=2862 [2018-11-22 22:12:30,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-11-22 22:12:30,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-11-22 22:12:30,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-11-22 22:12:30,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-11-22 22:12:30,984 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 85 [2018-11-22 22:12:30,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 22:12:30,984 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-11-22 22:12:30,984 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-22 22:12:30,984 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-11-22 22:12:30,984 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-22 22:12:30,987 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-11-22 22:12:31,129 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:31,957 WARN L180 SmtUtils]: Spent 336.00 ms on a formula simplification. DAG size of input: 355 DAG size of output: 336 [2018-11-22 22:12:32,204 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:32,205 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:32,322 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 315 DAG size of output: 290 [2018-11-22 22:12:32,588 WARN L180 SmtUtils]: Spent 264.00 ms on a formula simplification. DAG size of input: 354 DAG size of output: 338 [2018-11-22 22:12:32,830 WARN L180 SmtUtils]: Spent 241.00 ms on a formula simplification. DAG size of input: 315 DAG size of output: 300 [2018-11-22 22:12:32,831 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:33,025 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 363 DAG size of output: 331 [2018-11-22 22:12:33,511 WARN L180 SmtUtils]: Spent 484.00 ms on a formula simplification. DAG size of input: 415 DAG size of output: 387 [2018-11-22 22:12:33,852 WARN L180 SmtUtils]: Spent 340.00 ms on a formula simplification. DAG size of input: 385 DAG size of output: 356 [2018-11-22 22:12:33,857 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:34,273 WARN L180 SmtUtils]: Spent 205.00 ms on a formula simplification. DAG size of input: 379 DAG size of output: 349 [2018-11-22 22:12:34,278 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:34,622 WARN L180 SmtUtils]: Spent 281.00 ms on a formula simplification. DAG size of input: 363 DAG size of output: 335 [2018-11-22 22:12:34,888 WARN L180 SmtUtils]: Spent 262.00 ms on a formula simplification. DAG size of input: 354 DAG size of output: 338 [2018-11-22 22:12:35,180 WARN L180 SmtUtils]: Spent 291.00 ms on a formula simplification. DAG size of input: 374 DAG size of output: 349 [2018-11-22 22:12:35,426 WARN L180 SmtUtils]: Spent 245.00 ms on a formula simplification. DAG size of input: 351 DAG size of output: 335 [2018-11-22 22:12:35,427 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:35,652 WARN L180 SmtUtils]: Spent 223.00 ms on a formula simplification. DAG size of input: 337 DAG size of output: 321 [2018-11-22 22:12:35,653 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:35,793 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2018-11-22 22:12:36,267 WARN L180 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 306 DAG size of output: 292 [2018-11-22 22:12:36,381 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 285 DAG size of output: 263 [2018-11-22 22:14:29,316 WARN L180 SmtUtils]: Spent 1.87 m on a formula simplification. DAG size of input: 329 DAG size of output: 57 [2018-11-22 22:14:29,457 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 1 [2018-11-22 22:16:23,262 WARN L180 SmtUtils]: Spent 1.90 m on a formula simplification. DAG size of input: 734 DAG size of output: 169 [2018-11-22 22:16:25,939 WARN L180 SmtUtils]: Spent 2.67 s on a formula simplification. DAG size of input: 174 DAG size of output: 96 [2018-11-22 22:19:34,963 WARN L180 SmtUtils]: Spent 3.15 m on a formula simplification. DAG size of input: 471 DAG size of output: 141 [2018-11-22 22:19:34,966 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.initFINAL(line -1) the Hoare annotation is: true [2018-11-22 22:19:34,966 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.initEXIT(line -1) no Hoare annotation was computed. [2018-11-22 22:19:34,966 INFO L448 ceAbstractionStarter]: For program point L19(lines 19 24) no Hoare annotation was computed. [2018-11-22 22:19:34,966 INFO L448 ceAbstractionStarter]: For program point L48(lines 47 62) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L451 ceAbstractionStarter]: At program point L69(lines 18 71) the Hoare annotation is: true [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point L28(lines 27 42) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point L49(lines 47 62) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point L37(lines 37 41) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L451 ceAbstractionStarter]: At program point L37-1(lines 27 42) the Hoare annotation is: true [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point L25(lines 25 65) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L451 ceAbstractionStarter]: At program point base2fltENTRY(lines 14 72) the Hoare annotation is: true [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point base2fltFINAL(lines 14 72) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L451 ceAbstractionStarter]: At program point L63(lines 25 65) the Hoare annotation is: true [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point base2fltEXIT(lines 14 72) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L451 ceAbstractionStarter]: At program point L47-2(lines 47 62) the Hoare annotation is: true [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L451 ceAbstractionStarter]: At program point L-1(line -1) the Hoare annotation is: true [2018-11-22 22:19:34,967 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point mainEXIT(lines 214 252) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point mainFINAL(lines 214 252) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L448 ceAbstractionStarter]: For program point L236(lines 236 245) no Hoare annotation was computed. [2018-11-22 22:19:34,967 INFO L444 ceAbstractionStarter]: At program point L234(line 234) the Hoare annotation is: (let ((.cse5 (bvlshr main_~b~0 (_ bv24 32)))) (let ((.cse7 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) main_~b~0))) (.cse8 (bvneg (bvadd .cse5 (_ bv4294967168 32)))) (.cse10 (bvlshr main_~a~0 (_ bv24 32)))) (let ((.cse24 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) main_~a~0))) (.cse22 (bvlshr .cse7 (bvadd .cse8 .cse10 (_ bv4294967168 32))))) (let ((.cse20 (bvadd .cse24 .cse22)) (.cse23 (bvlshr .cse24 (bvadd .cse5 (bvneg (bvadd .cse10 (_ bv4294967168 32))) (_ bv4294967168 32))))) (let ((.cse4 (bvadd .cse23 .cse7)) (.cse18 (= (bvadd .cse5 (_ bv4294967041 32)) (_ bv0 32))) (.cse15 (= (bvand (_ bv33554432 32) .cse20) (_ bv0 32)))) (let ((.cse9 (not .cse15)) (.cse0 (not .cse18)) (.cse19 (= main_~b~0 (_ bv0 32))) (.cse2 (bvult main_~a~0 main_~b~0)) (.cse14 (= (_ bv0 32) (bvand (_ bv33554432 32) .cse4))) (.cse17 (= main_~a~0 (_ bv0 32)))) (let ((.cse1 (not .cse17)) (.cse12 (= .cse23 (_ bv0 32))) (.cse13 (= main_~b~0 main_~r_add1~0)) (.cse3 (not .cse14)) (.cse11 (= (_ bv4294967295 32) main_~r_add1~0)) (.cse6 (= main_~a~0 main_~r_add1~0)) (.cse16 (let ((.cse21 (and .cse0 (not .cse19) (not .cse2)))) (or (and .cse21 (not (= (_ bv255 32) .cse10)) .cse9) (and .cse15 (= (bvor (bvand (_ bv16777215 32) .cse20) (bvshl .cse10 (_ bv24 32))) main_~r_add1~0) .cse21 (not (= .cse22 (_ bv0 32)))))))) (or (and .cse0 .cse1 .cse2 .cse3 (= main_~r_add1~0 (bvor (bvand (_ bv16777215 32) (bvlshr .cse4 (_ bv1 32))) (bvshl (bvadd .cse5 (_ bv1 32)) (_ bv24 32))))) (and .cse6 (= (bvlshr .cse7 (bvadd (bvlshr main_~r_add1~0 (_ bv24 32)) .cse8 (_ bv4294967168 32))) (_ bv0 32)) (not (bvult main_~r_add1~0 main_~b~0))) (and .cse9 (= (bvadd .cse10 (_ bv4294967041 32)) (_ bv0 32)) .cse11) (and .cse12 .cse2 .cse13) (and .cse14 .cse1 (= main_~r_add1~0 (bvor (bvand (_ bv16777215 32) .cse4) (bvshl .cse5 (_ bv24 32)))) (not .cse12)) (and .cse15 .cse16) (and .cse17 .cse13) (and .cse3 .cse18 .cse11) (and .cse19 .cse6) (and .cse16 (= main_~r_add1~0 (bvor (bvand (_ bv16777215 32) (bvlshr .cse20 (_ bv1 32))) (bvshl (bvadd .cse10 (_ bv1 32)) (_ bv24 32))))))))))))) [2018-11-22 22:19:34,968 INFO L444 ceAbstractionStarter]: At program point L236-2(lines 236 245) the Hoare annotation is: (and (= main_~tmp___0~0 (_ bv0 32)) (= main_~tmp~2 (_ bv0 32))) [2018-11-22 22:19:34,968 INFO L448 ceAbstractionStarter]: For program point L234-1(line 234) no Hoare annotation was computed. [2018-11-22 22:19:34,968 INFO L451 ceAbstractionStarter]: At program point L232(line 232) the Hoare annotation is: true [2018-11-22 22:19:34,968 INFO L448 ceAbstractionStarter]: For program point L232-1(line 232) no Hoare annotation was computed. [2018-11-22 22:19:34,968 INFO L451 ceAbstractionStarter]: At program point L230(line 230) the Hoare annotation is: true [2018-11-22 22:19:34,968 INFO L448 ceAbstractionStarter]: For program point L230-1(line 230) no Hoare annotation was computed. [2018-11-22 22:19:34,968 INFO L451 ceAbstractionStarter]: At program point mainENTRY(lines 214 252) the Hoare annotation is: true [2018-11-22 22:19:34,968 INFO L448 ceAbstractionStarter]: For program point L247(line 247) no Hoare annotation was computed. [2018-11-22 22:19:34,968 INFO L448 ceAbstractionStarter]: For program point L239(lines 239 243) no Hoare annotation was computed. [2018-11-22 22:19:34,968 INFO L448 ceAbstractionStarter]: For program point L239-2(lines 239 243) no Hoare annotation was computed. [2018-11-22 22:19:34,968 INFO L451 ceAbstractionStarter]: At program point L233(line 233) the Hoare annotation is: true [2018-11-22 22:19:34,968 INFO L448 ceAbstractionStarter]: For program point L233-1(line 233) no Hoare annotation was computed. [2018-11-22 22:19:34,969 INFO L451 ceAbstractionStarter]: At program point L231(line 231) the Hoare annotation is: true [2018-11-22 22:19:34,969 INFO L448 ceAbstractionStarter]: For program point L231-1(line 231) no Hoare annotation was computed. [2018-11-22 22:19:34,969 INFO L448 ceAbstractionStarter]: For program point L128(line 128) no Hoare annotation was computed. [2018-11-22 22:19:34,969 INFO L451 ceAbstractionStarter]: At program point addfltENTRY(lines 73 136) the Hoare annotation is: true [2018-11-22 22:19:34,969 INFO L448 ceAbstractionStarter]: For program point addfltFINAL(lines 73 136) no Hoare annotation was computed. [2018-11-22 22:19:34,969 INFO L448 ceAbstractionStarter]: For program point L116(lines 116 121) no Hoare annotation was computed. [2018-11-22 22:19:34,969 INFO L448 ceAbstractionStarter]: For program point L108(lines 108 113) no Hoare annotation was computed. [2018-11-22 22:19:34,969 INFO L444 ceAbstractionStarter]: At program point L104(line 104) the Hoare annotation is: (let ((.cse0 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~b|))) (.cse2 (bvadd (bvlshr |addflt_#in~a| (_ bv24 32)) (_ bv4294967168 32))) (.cse4 (= addflt_~a |addflt_#in~a|)) (.cse3 (bvadd (bvlshr |addflt_#in~b| (_ bv24 32)) (_ bv4294967168 32))) (.cse1 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~a|)))) (and (or (and (= .cse0 addflt_~ma~0) (= .cse1 addflt_~mb~0) (= .cse2 addflt_~eb~0) (= .cse3 addflt_~ea~0)) .cse4) (let ((.cse5 (and (not (= (_ bv0 32) |addflt_#in~b|)) (exists ((addflt_~b (_ BitVec 32)) (addflt_~a (_ BitVec 32))) (and (= (bvadd addflt_~eb~0 (_ bv128 32)) (bvlshr addflt_~b (_ bv24 32))) (not (bvult addflt_~a addflt_~b)) (= (bvadd (bvlshr addflt_~a (_ bv24 32)) (_ bv4294967168 32)) addflt_~ea~0))) (not (bvult addflt_~a addflt_~b))))) (or (and (and (= .cse0 addflt_~mb~0) .cse5) (= .cse2 addflt_~ea~0) .cse4 (= addflt_~b |addflt_#in~b|) (= .cse3 addflt_~eb~0) (= .cse1 addflt_~ma~0)) (and (bvult |addflt_#in~a| |addflt_#in~b|) (= addflt_~b |addflt_#in~a|) .cse5 (= addflt_~a |addflt_#in~b|)))) (not (= (_ bv0 32) |addflt_#in~a|)))) [2018-11-22 22:19:34,969 INFO L448 ceAbstractionStarter]: For program point L104-1(line 104) no Hoare annotation was computed. [2018-11-22 22:19:34,969 INFO L444 ceAbstractionStarter]: At program point L133(lines 83 135) the Hoare annotation is: (let ((.cse40 (bvlshr |addflt_#in~b| (_ bv24 32)))) (let ((.cse35 (bvlshr |addflt_#in~a| (_ bv24 32))) (.cse36 (bvadd .cse40 (_ bv4294967168 32)))) (let ((.cse10 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~b|))) (.cse11 (bvneg .cse36)) (.cse9 (bvadd .cse35 (_ bv4294967168 32)))) (let ((.cse28 (bvneg .cse9)) (.cse55 (bvlshr .cse10 (bvadd .cse35 .cse11 (_ bv4294967168 32)))) (.cse17 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~a|)))) (let ((.cse34 (bvadd .cse55 .cse17)) (.cse52 (= addflt_~a |addflt_#in~b|)) (.cse12 (= addflt_~b |addflt_#in~b|)) (.cse42 (= (_ bv0 32) |addflt_#in~b|)) (.cse49 (bvlshr .cse17 (bvadd .cse40 .cse28 (_ bv4294967168 32))))) (let ((.cse39 (bvadd .cse49 .cse10)) (.cse51 (not (= (bvadd |addflt_#in~a| (_ bv1 32)) (_ bv0 32)))) (.cse50 (let ((.cse56 (and (not .cse42) (not (bvult addflt_~a addflt_~b))))) (or (and .cse56 .cse52) (and .cse12 .cse56)))) (.cse15 (= addflt_~a |addflt_#in~a|)) (.cse32 (= (bvand (_ bv33554432 32) .cse34) (_ bv0 32)))) (let ((.cse45 (= (_ bv0 32) |addflt_#in~a|)) (.cse29 (not (= (_ bv127 32) addflt_~ea~0))) (.cse30 (= (_ bv0 32) (bvand (_ bv33554432 32) addflt_~ma~0))) (.cse43 (not .cse32)) (.cse20 (= (bvadd .cse35 (_ bv4294967041 32)) (_ bv0 32))) (.cse23 (= addflt_~b |addflt_#in~a|)) (.cse22 (and (or (= (bvadd addflt_~a (_ bv1 32)) (_ bv0 32)) .cse51) (or (and .cse50 .cse52) (and .cse50 .cse15)))) (.cse53 (not (bvult addflt_~a |addflt_#in~a|))) (.cse37 (= (bvand (_ bv33554432 32) .cse39) (_ bv0 32)))) (let ((.cse27 (not .cse37)) (.cse31 (= .cse55 (_ bv0 32))) (.cse47 (= .cse49 (_ bv0 32))) (.cse24 (bvult |addflt_#in~a| |addflt_#in~b|)) (.cse33 (let ((.cse54 (and .cse22 .cse53))) (or (and .cse54 .cse23) (and .cse54 .cse15)))) (.cse3 (not .cse20)) (.cse44 (or .cse29 .cse30 (and .cse43 .cse20))) (.cse48 (not .cse45))) (let ((.cse13 (= addflt_~__retres10~0 |addflt_#in~a|)) (.cse2 (= (bvadd .cse40 (_ bv4294967041 32)) (_ bv0 32))) (.cse41 (and (or .cse31 (not (= (_ bv0 32) addflt_~mb~0))) (not .cse47) (and .cse24 .cse33 .cse3 .cse44 .cse48))) (.cse38 (or .cse30 .cse27)) (.cse21 (= (bvlshr .cse10 (bvadd (bvlshr addflt_~a (_ bv24 32)) .cse11 (_ bv4294967168 32))) addflt_~mb~0)) (.cse25 (= .cse36 addflt_~ea~0)) (.cse46 (and .cse50 (or (= (bvadd |addflt_#res| (_ bv1 32)) (_ bv0 32)) .cse51) (= addflt_~__retres10~0 |addflt_#in~b|) .cse52 .cse53)) (.cse26 (= .cse49 addflt_~mb~0))) (let ((.cse4 (and (= .cse10 addflt_~ma~0) .cse47 .cse25 .cse23 .cse46 .cse26 .cse48)) (.cse0 (and .cse45 .cse46 .cse23)) (.cse5 (and .cse12 .cse43 .cse44 .cse38 .cse21 (= (bvor (bvand (_ bv16777215 32) (bvlshr .cse34 (_ bv1 32))) (bvshl (bvadd .cse35 (_ bv1 32)) (_ bv24 32))) addflt_~__retres10~0) .cse3 .cse33)) (.cse6 (and (= addflt_~__retres10~0 (bvor (bvand (_ bv16777215 32) (bvlshr .cse39 (_ bv1 32))) (bvshl (bvadd .cse40 (_ bv1 32)) (_ bv24 32)))) .cse26 .cse27 (not .cse2) (or .cse43 .cse30) .cse41)) (.cse1 (and .cse15 .cse42 .cse12 .cse13)) (.cse8 (bvlshr .cse10 (bvadd .cse11 addflt_~ea~0))) (.cse7 (and .cse37 .cse25 .cse38 .cse26 (= addflt_~__retres10~0 (bvor (bvand (_ bv16777215 32) .cse39) (bvshl .cse40 (_ bv24 32)))) .cse41))) (and (or .cse0 .cse1 (and .cse2 .cse3) .cse4 .cse5 .cse6 .cse7 (= addflt_~mb~0 .cse8)) (let ((.cse14 (not .cse24)) (.cse19 (= (bvadd addflt_~__retres10~0 (_ bv1 32)) (_ bv0 32))) (.cse16 (= .cse36 addflt_~eb~0))) (or .cse4 .cse0 .cse5 .cse6 .cse1 (and (= .cse9 addflt_~ea~0) (= (_ bv0 32) (bvlshr .cse10 (bvadd (bvlshr addflt_~__retres10~0 (_ bv24 32)) .cse11 (_ bv4294967168 32)))) .cse12 .cse13 .cse14 .cse15 .cse16 (= .cse17 addflt_~ma~0)) (let ((.cse18 (bvadd .cse8 .cse17))) (and (= .cse18 addflt_~ma~0) .cse19 .cse12 .cse20 .cse21 (not (= (_ bv0 32) (bvand (_ bv33554432 32) .cse18))) .cse14 .cse15 .cse16)) (and .cse19 (and .cse22 .cse23) .cse24 .cse25 .cse26 .cse27 (= (bvadd .cse10 (bvlshr .cse17 (bvadd .cse28 addflt_~ea~0))) addflt_~ma~0)) (and (or .cse29 (= (bvand (_ bv33554432 32) (bvadd addflt_~mb~0 addflt_~ma~0)) (_ bv0 32))) .cse30 .cse21 (not .cse31) .cse32 .cse33 .cse16 (= (bvor (bvand (_ bv16777215 32) .cse34) (bvshl .cse35 (_ bv24 32))) addflt_~__retres10~0)) .cse7))))))))))))) [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point addfltEXIT(lines 73 136) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point L84(lines 84 90) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point L115(lines 115 126) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point L84-2(lines 83 135) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L444 ceAbstractionStarter]: At program point L115-2(lines 115 126) the Hoare annotation is: (let ((.cse19 (bvlshr |addflt_#in~b| (_ bv24 32)))) (let ((.cse21 (bvlshr |addflt_#in~a| (_ bv24 32))) (.cse3 (bvadd .cse19 (_ bv4294967168 32)))) (let ((.cse16 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~b|))) (.cse17 (bvneg .cse3)) (.cse2 (bvadd .cse21 (_ bv4294967168 32)))) (let ((.cse27 (bvneg .cse2)) (.cse26 (bvlshr .cse16 (bvadd .cse21 .cse17 (_ bv4294967168 32)))) (.cse15 (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) |addflt_#in~a|)))) (let ((.cse20 (bvadd .cse26 .cse15)) (.cse25 (bvlshr .cse15 (bvadd .cse19 .cse27 (_ bv4294967168 32))))) (let ((.cse6 (= addflt_~a |addflt_#in~a|)) (.cse18 (bvadd .cse25 .cse16)) (.cse5 (= addflt_~b |addflt_#in~a|)) (.cse10 (= addflt_~b |addflt_#in~b|)) (.cse0 (= (bvand (_ bv33554432 32) .cse20) (_ bv0 32))) (.cse8 (= addflt_~a |addflt_#in~b|)) (.cse22 (= (bvadd .cse16 (bvlshr .cse15 (bvadd .cse27 addflt_~ea~0))) addflt_~ma~0)) (.cse1 (= .cse26 (_ bv0 32)))) (and (or (or (not .cse0) .cse1) (and (= .cse2 addflt_~ea~0) (= .cse3 addflt_~eb~0))) (let ((.cse4 (let ((.cse9 (and (not (= (_ bv0 32) addflt_~b)) (and (not (= (_ bv0 32) |addflt_#in~b|)) (not (bvult addflt_~a addflt_~b))))) (.cse11 (not (bvult addflt_~a |addflt_#in~a|)))) (or (and (exists ((addflt_~delta~0 (_ BitVec 32)) (addflt_~b (_ BitVec 32)) (addflt_~a (_ BitVec 32))) (= (bvlshr (bvadd (bvneg (bvneg (bvlshr (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~b)) addflt_~delta~0))) (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~a))) (_ bv1 32)) addflt_~ma~0)) (and (let ((.cse7 (or (and .cse9 .cse10) (and .cse9 .cse8)))) (or (and .cse7 .cse6) (and .cse7 .cse8))) .cse11)) (and (and (let ((.cse12 (let ((.cse13 (= (_ bv0 32) (bvand (_ bv33554432 32) addflt_~ma~0)))) (or (and .cse13 .cse9 .cse8) (and .cse13 .cse9 .cse10))))) (or (and .cse12 .cse8) (and .cse12 .cse6))) .cse11) (exists ((addflt_~delta~0 (_ BitVec 32)) (addflt_~b (_ BitVec 32)) (addflt_~a (_ BitVec 32))) (= (bvadd (bvneg (bvlshr (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~b)) addflt_~delta~0)) addflt_~ma~0) (bvor (_ bv16777216 32) (bvand (_ bv16777215 32) addflt_~a))))))))) (or (and .cse4 .cse5) (and .cse4 .cse6))) (or (let ((.cse14 (bvlshr .cse16 (bvadd .cse17 addflt_~ea~0)))) (and (= (bvadd .cse14 .cse15) addflt_~ma~0) .cse6 (= addflt_~mb~0 .cse14))) (and (= (bvlshr .cse18 (_ bv1 32)) addflt_~ma~0) (= (bvadd .cse19 (_ bv4294967169 32)) addflt_~ea~0) .cse8) (and (= (bvlshr .cse20 (_ bv1 32)) addflt_~ma~0) (= (bvadd .cse21 (_ bv4294967169 32)) addflt_~ea~0) .cse6) (and (= .cse3 addflt_~ea~0) .cse8 .cse22)) (let ((.cse24 (not .cse1)) (.cse23 (= .cse25 addflt_~mb~0))) (or (and .cse23 (not (= (bvand (_ bv33554432 32) .cse18) (_ bv0 32))) .cse5 (not (= (bvadd .cse19 (_ bv4294967041 32)) (_ bv0 32)))) (and .cse10 (= (bvlshr .cse16 (bvadd (bvlshr addflt_~a (_ bv24 32)) .cse17 (_ bv4294967168 32))) addflt_~mb~0) .cse24 (not (= (bvadd .cse21 (_ bv4294967041 32)) (_ bv0 32)))) (and .cse24 .cse0) (and .cse23 (not (= (_ bv0 32) (bvadd (bvneg .cse16) addflt_~ma~0))) .cse8 .cse22)))))))))) [2018-11-22 22:19:34,970 INFO L451 ceAbstractionStarter]: At program point __VERIFIER_assertENTRY(lines 5 10) the Hoare annotation is: true [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertEXIT(lines 5 10) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point L7(line 7) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point L6(lines 6 8) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point L6-2(lines 5 10) no Hoare annotation was computed. [2018-11-22 22:19:34,970 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION(line 7) no Hoare annotation was computed. [2018-11-22 22:19:35,017 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.11 10:19:35 BoogieIcfgContainer [2018-11-22 22:19:35,017 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-22 22:19:35,017 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-22 22:19:35,017 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-22 22:19:35,021 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-22 22:19:35,022 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 10:08:00" (3/4) ... [2018-11-22 22:19:35,026 INFO L144 WitnessPrinter]: Generating witness for correct program [2018-11-22 22:19:35,032 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure ULTIMATE.init [2018-11-22 22:19:35,032 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure base2flt [2018-11-22 22:19:35,033 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure main [2018-11-22 22:19:35,033 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure addflt [2018-11-22 22:19:35,033 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure __VERIFIER_assert [2018-11-22 22:19:35,038 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 11 nodes and edges [2018-11-22 22:19:35,038 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 4 nodes and edges [2018-11-22 22:19:35,038 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 1 nodes and edges [2018-11-22 22:19:35,063 WARN L221 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((0bv32 == \old(a) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && b == \old(a)) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || (~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32 && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) || ((((((~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))) == ma && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && b == \old(a)) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a)))) || (((((((b == \old(b) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a))))) || (((((__retres10 == ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(b), 24bv32), 1bv32), 24bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && !(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32)) && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) || (((((~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && __retres10 == ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))), ~bvshl32(~bvlshr64(\old(b), 24bv32), 24bv32))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) || mb == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea))) && (((((((((((((((~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))) == ma && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && b == \old(a)) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a))) || ((0bv32 == \old(a) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && b == \old(a))) || (((((((b == \old(b) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a))))) || (((((__retres10 == ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(b), 24bv32), 1bv32), 24bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && !(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32)) && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || (((((((~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32) == ea && 0bv32 == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(__retres10, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32))) && b == \old(b)) && __retres10 == \old(a)) && !~bvult64(\old(a), \old(b))) && a == \old(a)) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb) && ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))) == ma)) || ((((((((~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))) == ma && ~bvadd64(__retres10, 1bv32) == 0bv32) && b == \old(b)) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))))) && !~bvult64(\old(a), \old(b))) && a == \old(a)) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb)) || ((((((~bvadd64(__retres10, 1bv32) == 0bv32 && ((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && b == \old(a)) && ~bvult64(\old(a), \old(b))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && ~bvadd64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), ea))) == ma)) || ((((((((!(127bv32 == ea) || ~bvand64(33554432bv32, ~bvadd64(mb, ma)) == 0bv32) && 0bv32 == ~bvand64(33554432bv32, ma)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb) && ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))), ~bvshl32(~bvlshr64(\old(a), 24bv32), 24bv32)) == __retres10)) || (((((~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && __retres10 == ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))), ~bvshl32(~bvlshr64(\old(b), 24bv32), 24bv32))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) [2018-11-22 22:19:35,084 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_e44c7839-183f-43dc-8455-29097192982c/bin-2019/utaipan/witness.graphml [2018-11-22 22:19:35,084 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-22 22:19:35,087 INFO L168 Benchmark]: Toolchain (without parser) took 695244.44 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 227.0 MB). Free memory was 945.2 MB in the beginning and 884.9 MB in the end (delta: 60.2 MB). Peak memory consumption was 287.3 MB. Max. memory is 11.5 GB. [2018-11-22 22:19:35,088 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 22:19:35,088 INFO L168 Benchmark]: CACSL2BoogieTranslator took 257.71 ms. Allocated memory is still 1.0 GB. Free memory was 945.2 MB in the beginning and 929.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-22 22:19:35,088 INFO L168 Benchmark]: Boogie Procedure Inliner took 19.51 ms. Allocated memory is still 1.0 GB. Free memory is still 929.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 22:19:35,089 INFO L168 Benchmark]: Boogie Preprocessor took 62.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.8 MB). Free memory was 929.1 MB in the beginning and 1.1 GB in the end (delta: -206.2 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. [2018-11-22 22:19:35,089 INFO L168 Benchmark]: RCFGBuilder took 231.39 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 17.6 MB). Peak memory consumption was 17.6 MB. Max. memory is 11.5 GB. [2018-11-22 22:19:35,089 INFO L168 Benchmark]: TraceAbstraction took 694599.85 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 80.2 MB). Free memory was 1.1 GB in the beginning and 893.0 MB in the end (delta: 224.7 MB). Peak memory consumption was 455.7 MB. Max. memory is 11.5 GB. [2018-11-22 22:19:35,089 INFO L168 Benchmark]: Witness Printer took 66.62 ms. Allocated memory is still 1.3 GB. Free memory was 893.0 MB in the beginning and 884.9 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. [2018-11-22 22:19:35,091 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 257.71 ms. Allocated memory is still 1.0 GB. Free memory was 945.2 MB in the beginning and 929.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 19.51 ms. Allocated memory is still 1.0 GB. Free memory is still 929.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 62.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.8 MB). Free memory was 929.1 MB in the beginning and 1.1 GB in the end (delta: -206.2 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 231.39 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 17.6 MB). Peak memory consumption was 17.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 694599.85 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 80.2 MB). Free memory was 1.1 GB in the beginning and 893.0 MB in the end (delta: 224.7 MB). Peak memory consumption was 455.7 MB. Max. memory is 11.5 GB. * Witness Printer took 66.62 ms. Allocated memory is still 1.3 GB. Free memory was 893.0 MB in the beginning and 884.9 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 7]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 25]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 18]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 83]: Loop Invariant Derived loop invariant: (((((((((0bv32 == \old(a) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && b == \old(a)) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || (~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32 && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) || ((((((~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))) == ma && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && b == \old(a)) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a)))) || (((((((b == \old(b) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a))))) || (((((__retres10 == ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(b), 24bv32), 1bv32), 24bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && !(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32)) && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) || (((((~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && __retres10 == ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))), ~bvshl32(~bvlshr64(\old(b), 24bv32), 24bv32))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) || mb == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea))) && (((((((((((((((~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))) == ma && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && b == \old(a)) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == \old(a))) || ((0bv32 == \old(a) && ((((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && (~bvadd64(\result, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32))) && __retres10 == \old(b)) && a == \old(b)) && !~bvult64(a, \old(a))) && b == \old(a))) || (((((((b == \old(b) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(a), 24bv32), 1bv32), 24bv32)) == __retres10) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a))))) || (((((__retres10 == ~bvor32(~bvand64(16777215bv32, ~bvlshr64(~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b)))), 1bv32)), ~bvshl32(~bvadd64(~bvlshr64(\old(b), 24bv32), 1bv32), 24bv32)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && !(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967041bv32) == 0bv32)) && (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) || 0bv32 == ~bvand64(33554432bv32, ma))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) || (((a == \old(a) && 0bv32 == \old(b)) && b == \old(b)) && __retres10 == \old(a))) || (((((((~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32) == ea && 0bv32 == ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(__retres10, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32))) && b == \old(b)) && __retres10 == \old(a)) && !~bvult64(\old(a), \old(b))) && a == \old(a)) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb) && ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))) == ma)) || ((((((((~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a)))) == ma && ~bvadd64(__retres10, 1bv32) == 0bv32) && b == \old(b)) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(0bv32 == ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), ea)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))))) && !~bvult64(\old(a), \old(b))) && a == \old(a)) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb)) || ((((((~bvadd64(__retres10, 1bv32) == 0bv32 && ((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && b == \old(a)) && ~bvult64(\old(a), \old(b))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32)) && ~bvadd64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), ea))) == ma)) || ((((((((!(127bv32 == ea) || ~bvand64(33554432bv32, ~bvadd64(mb, ma)) == 0bv32) && 0bv32 == ~bvand64(33554432bv32, ma)) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(a, 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && ~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == eb) && ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))), ~bvshl32(~bvlshr64(\old(a), 24bv32), 24bv32)) == __retres10)) || (((((~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32 && ~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32) == ea) && (0bv32 == ~bvand64(33554432bv32, ma) || !(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))) == 0bv32))) && ~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == mb) && __retres10 == ~bvor32(~bvand64(16777215bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))))), ~bvshl32(~bvlshr64(\old(b), 24bv32), 24bv32))) && ((~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32 || !(0bv32 == mb)) && !(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))), ~bvadd64(~bvlshr64(\old(b), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967168bv32)), 4294967168bv32)) == 0bv32)) && (((~bvult64(\old(a), \old(b)) && (((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && b == \old(a)) || ((((~bvadd64(a, 1bv32) == 0bv32 || !(~bvadd64(\old(a), 1bv32) == 0bv32)) && (((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(b)) || ((((!(0bv32 == \old(b)) && !~bvult64(a, b)) && a == \old(b)) || (b == \old(b) && !(0bv32 == \old(b)) && !~bvult64(a, b))) && a == \old(a)))) && !~bvult64(a, \old(a))) && a == \old(a)))) && !(~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32)) && ((!(127bv32 == ea) || 0bv32 == ~bvand64(33554432bv32, ma)) || (!(~bvand64(33554432bv32, ~bvadd64(~bvlshr64(~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(b))), ~bvadd64(~bvlshr64(\old(a), 24bv32), ~bvneg32(~bvadd64(~bvlshr64(\old(b), 24bv32), 4294967168bv32)), 4294967168bv32)), ~bvor32(16777216bv32, ~bvand64(16777215bv32, \old(a))))) == 0bv32) && ~bvadd64(~bvlshr64(\old(a), 24bv32), 4294967041bv32) == 0bv32))) && !(0bv32 == \old(a)))) - InvariantResult [Line: 47]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 27]: Loop Invariant Derived loop invariant: 1 - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 56 locations, 1 error locations. SAFE Result, 694.5s OverallTime, 56 OverallIterations, 5 TraceHistogramMax, 159.7s AutomataDifference, 0.0s DeadEndRemovalTime, 423.9s HoareAnnotationTime, HoareTripleCheckerStatistics: 4108 SDtfs, 4444 SDslu, 41268 SDs, 0 SdLazy, 20149 SolverSat, 2014 SolverUnsat, 19 SolverUnknown, 0 SolverNotchecked, 82.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 10821 GetRequests, 9243 SyntacticMatches, 106 SemanticMatches, 1472 ConstructedPredicates, 0 IntricatePredicates, 3 DeprecatedPredicates, 9082 ImplicationChecksByTransitivity, 151.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=228occurred in iteration=12, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.0s AutomataMinimizationTime, 56 MinimizatonAttempts, 936 StatesRemovedByMinimization, 48 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 20 LocationsWithAnnotation, 337 PreInvPairs, 1516 NumberOfFragments, 5065 HoareAnnotationTreeSize, 337 FomulaSimplifications, 1644365796 FormulaSimplificationTreeSizeReduction, 5.9s HoareSimplificationTime, 20 FomulaSimplificationsInter, 80165464 FormulaSimplificationTreeSizeReductionInter, 418.0s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 7.3s SatisfiabilityAnalysisTime, 99.7s InterpolantComputationTime, 6258 NumberOfCodeBlocks, 6240 NumberOfCodeBlocksAsserted, 124 NumberOfCheckSat, 10011 ConstructedInterpolants, 111 QuantifiedInterpolants, 4684243 SizeOfPredicates, 960 NumberOfNonLiveVariables, 11160 ConjunctsInSsa, 1764 ConjunctsInUnsatCore, 155 InterpolantComputations, 20 PerfectInterpolantSequences, 4463/5395 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Received shutdown request...