./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 14:18:21,334 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 14:18:21,335 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 14:18:21,344 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 14:18:21,344 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 14:18:21,345 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 14:18:21,346 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 14:18:21,347 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 14:18:21,348 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 14:18:21,349 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 14:18:21,349 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 14:18:21,349 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 14:18:21,350 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 14:18:21,351 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 14:18:21,351 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 14:18:21,352 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 14:18:21,353 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 14:18:21,354 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 14:18:21,355 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 14:18:21,356 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 14:18:21,357 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 14:18:21,358 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 14:18:21,360 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 14:18:21,360 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 14:18:21,360 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 14:18:21,361 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 14:18:21,361 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 14:18:21,362 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 14:18:21,363 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 14:18:21,363 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 14:18:21,364 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 14:18:21,364 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 14:18:21,364 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 14:18:21,364 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 14:18:21,365 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 14:18:21,366 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 14:18:21,366 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-23 14:18:21,376 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 14:18:21,376 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 14:18:21,377 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 14:18:21,377 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 14:18:21,377 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 14:18:21,377 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 14:18:21,377 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 14:18:21,377 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-23 14:18:21,377 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 14:18:21,378 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 14:18:21,378 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-23 14:18:21,378 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-23 14:18:21,378 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 14:18:21,378 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 14:18:21,379 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 14:18:21,380 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 14:18:21,380 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 14:18:21,380 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 14:18:21,380 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 14:18:21,380 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 14:18:21,380 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 14:18:21,380 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 14:18:21,381 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 14:18:21,381 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 14:18:21,381 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 14:18:21,381 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 14:18:21,381 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-23 14:18:21,381 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 14:18:21,381 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 14:18:21,381 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 14:18:21,382 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2018-11-23 14:18:21,403 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 14:18:21,412 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 14:18:21,415 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 14:18:21,416 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 14:18:21,416 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 14:18:21,416 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-23 14:18:21,457 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/data/735ecdf43/57c88c06314f4ed094f47ec560888199/FLAGd85b3a3db [2018-11-23 14:18:21,824 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 14:18:21,824 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-23 14:18:21,833 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/data/735ecdf43/57c88c06314f4ed094f47ec560888199/FLAGd85b3a3db [2018-11-23 14:18:21,843 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/data/735ecdf43/57c88c06314f4ed094f47ec560888199 [2018-11-23 14:18:21,846 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 14:18:21,847 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 14:18:21,847 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 14:18:21,847 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 14:18:21,850 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 14:18:21,851 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:18:21" (1/1) ... [2018-11-23 14:18:21,853 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@399b955d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:21, skipping insertion in model container [2018-11-23 14:18:21,853 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:18:21" (1/1) ... [2018-11-23 14:18:21,860 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 14:18:21,888 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 14:18:22,053 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:18:22,058 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 14:18:22,094 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:18:22,107 INFO L195 MainTranslator]: Completed translation [2018-11-23 14:18:22,107 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22 WrapperNode [2018-11-23 14:18:22,107 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 14:18:22,108 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 14:18:22,108 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 14:18:22,108 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 14:18:22,113 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,117 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,163 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 14:18:22,163 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 14:18:22,163 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 14:18:22,163 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 14:18:22,170 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,170 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,173 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,174 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,183 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,194 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,196 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... [2018-11-23 14:18:22,199 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 14:18:22,200 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 14:18:22,200 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 14:18:22,200 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 14:18:22,201 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 14:18:22,245 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-11-23 14:18:22,245 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-11-23 14:18:22,245 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-11-23 14:18:22,245 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-11-23 14:18:22,245 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-11-23 14:18:22,245 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-11-23 14:18:22,245 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-11-23 14:18:22,245 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-11-23 14:18:22,246 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 14:18:22,246 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 14:18:22,246 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-23 14:18:22,246 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-23 14:18:22,246 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-23 14:18:22,246 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-23 14:18:22,246 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-11-23 14:18:22,246 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-11-23 14:18:22,246 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-23 14:18:22,246 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-23 14:18:22,246 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-11-23 14:18:22,247 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-11-23 14:18:22,247 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-23 14:18:22,247 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-23 14:18:22,247 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-11-23 14:18:22,247 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-11-23 14:18:22,247 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-23 14:18:22,247 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-23 14:18:22,247 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-23 14:18:22,248 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-23 14:18:22,248 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-23 14:18:22,248 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-23 14:18:22,248 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-23 14:18:22,248 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-23 14:18:22,248 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-11-23 14:18:22,248 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-11-23 14:18:22,248 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-23 14:18:22,248 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-23 14:18:22,249 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-11-23 14:18:22,249 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-11-23 14:18:22,249 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-23 14:18:22,249 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-23 14:18:22,249 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 14:18:22,249 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 14:18:22,249 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-23 14:18:22,249 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-23 14:18:22,250 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-11-23 14:18:22,250 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-11-23 14:18:22,250 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-23 14:18:22,250 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-23 14:18:22,250 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-23 14:18:22,250 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-23 14:18:22,250 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 14:18:22,250 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 14:18:22,251 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-23 14:18:22,251 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-23 14:18:22,793 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 14:18:22,793 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 14:18:22,794 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:18:22 BoogieIcfgContainer [2018-11-23 14:18:22,794 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 14:18:22,795 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 14:18:22,795 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 14:18:22,798 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 14:18:22,798 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 02:18:21" (1/3) ... [2018-11-23 14:18:22,799 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@52a4dbf4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:18:22, skipping insertion in model container [2018-11-23 14:18:22,799 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:18:22" (2/3) ... [2018-11-23 14:18:22,799 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@52a4dbf4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:18:22, skipping insertion in model container [2018-11-23 14:18:22,799 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:18:22" (3/3) ... [2018-11-23 14:18:22,801 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-23 14:18:22,813 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 14:18:22,820 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 14:18:22,834 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 14:18:22,865 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 14:18:22,865 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 14:18:22,865 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 14:18:22,865 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 14:18:22,865 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 14:18:22,865 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 14:18:22,865 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 14:18:22,866 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 14:18:22,885 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states. [2018-11-23 14:18:22,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:22,893 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:22,894 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:22,897 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:22,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:22,902 INFO L82 PathProgramCache]: Analyzing trace with hash -2019614736, now seen corresponding path program 1 times [2018-11-23 14:18:22,905 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:22,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:22,946 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:22,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:22,946 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:23,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:23,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:23,219 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:23,219 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:23,219 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:23,223 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:23,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:23,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:23,235 INFO L87 Difference]: Start difference. First operand 229 states. Second operand 5 states. [2018-11-23 14:18:23,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:23,807 INFO L93 Difference]: Finished difference Result 475 states and 713 transitions. [2018-11-23 14:18:23,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:23,809 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:23,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:23,821 INFO L225 Difference]: With dead ends: 475 [2018-11-23 14:18:23,821 INFO L226 Difference]: Without dead ends: 256 [2018-11-23 14:18:23,826 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:23,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-11-23 14:18:23,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-11-23 14:18:23,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:23,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 304 transitions. [2018-11-23 14:18:23,890 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 304 transitions. Word has length 120 [2018-11-23 14:18:23,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:23,891 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 304 transitions. [2018-11-23 14:18:23,891 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:23,891 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 304 transitions. [2018-11-23 14:18:23,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:23,894 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:23,894 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:23,895 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:23,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:23,895 INFO L82 PathProgramCache]: Analyzing trace with hash 1218621358, now seen corresponding path program 1 times [2018-11-23 14:18:23,896 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:23,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:23,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:23,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:23,897 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:23,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:24,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:24,005 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:24,005 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:24,005 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:24,007 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:24,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:24,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:24,007 INFO L87 Difference]: Start difference. First operand 220 states and 304 transitions. Second operand 5 states. [2018-11-23 14:18:24,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:24,388 INFO L93 Difference]: Finished difference Result 454 states and 646 transitions. [2018-11-23 14:18:24,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:24,389 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:24,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:24,392 INFO L225 Difference]: With dead ends: 454 [2018-11-23 14:18:24,392 INFO L226 Difference]: Without dead ends: 256 [2018-11-23 14:18:24,394 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:24,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-11-23 14:18:24,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-11-23 14:18:24,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:24,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 303 transitions. [2018-11-23 14:18:24,420 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 303 transitions. Word has length 120 [2018-11-23 14:18:24,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:24,421 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 303 transitions. [2018-11-23 14:18:24,421 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:24,421 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 303 transitions. [2018-11-23 14:18:24,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:24,424 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:24,424 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:24,424 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:24,426 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:24,426 INFO L82 PathProgramCache]: Analyzing trace with hash -1724960720, now seen corresponding path program 1 times [2018-11-23 14:18:24,426 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:24,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:24,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:24,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:24,427 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:24,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:24,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:24,533 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:24,534 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:24,534 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:24,534 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:24,535 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:24,535 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:24,535 INFO L87 Difference]: Start difference. First operand 220 states and 303 transitions. Second operand 5 states. [2018-11-23 14:18:24,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:24,857 INFO L93 Difference]: Finished difference Result 452 states and 640 transitions. [2018-11-23 14:18:24,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:24,858 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:24,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:24,860 INFO L225 Difference]: With dead ends: 452 [2018-11-23 14:18:24,861 INFO L226 Difference]: Without dead ends: 254 [2018-11-23 14:18:24,862 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:24,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states. [2018-11-23 14:18:24,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 220. [2018-11-23 14:18:24,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:24,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 302 transitions. [2018-11-23 14:18:24,883 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 302 transitions. Word has length 120 [2018-11-23 14:18:24,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:24,884 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 302 transitions. [2018-11-23 14:18:24,884 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:24,884 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 302 transitions. [2018-11-23 14:18:24,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:24,886 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:24,886 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:24,886 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:24,886 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:24,887 INFO L82 PathProgramCache]: Analyzing trace with hash 951031662, now seen corresponding path program 1 times [2018-11-23 14:18:24,887 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:24,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:24,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:24,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:24,888 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:24,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:24,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:24,965 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:24,965 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:24,965 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:24,965 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:24,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:24,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:24,966 INFO L87 Difference]: Start difference. First operand 220 states and 302 transitions. Second operand 5 states. [2018-11-23 14:18:25,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:25,355 INFO L93 Difference]: Finished difference Result 450 states and 634 transitions. [2018-11-23 14:18:25,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:25,355 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:25,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:25,357 INFO L225 Difference]: With dead ends: 450 [2018-11-23 14:18:25,357 INFO L226 Difference]: Without dead ends: 252 [2018-11-23 14:18:25,358 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:25,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-11-23 14:18:25,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 220. [2018-11-23 14:18:25,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:25,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 301 transitions. [2018-11-23 14:18:25,375 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 301 transitions. Word has length 120 [2018-11-23 14:18:25,375 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:25,375 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 301 transitions. [2018-11-23 14:18:25,375 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:25,375 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 301 transitions. [2018-11-23 14:18:25,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:25,376 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:25,377 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:25,377 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:25,377 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:25,377 INFO L82 PathProgramCache]: Analyzing trace with hash 67522672, now seen corresponding path program 1 times [2018-11-23 14:18:25,377 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:25,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:25,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:25,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:25,378 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:25,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:25,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:25,441 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:25,441 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:25,441 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:25,442 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:25,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:25,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:25,442 INFO L87 Difference]: Start difference. First operand 220 states and 301 transitions. Second operand 5 states. [2018-11-23 14:18:25,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:25,850 INFO L93 Difference]: Finished difference Result 471 states and 668 transitions. [2018-11-23 14:18:25,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:25,850 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:25,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:25,853 INFO L225 Difference]: With dead ends: 471 [2018-11-23 14:18:25,853 INFO L226 Difference]: Without dead ends: 273 [2018-11-23 14:18:25,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:25,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states. [2018-11-23 14:18:25,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 220. [2018-11-23 14:18:25,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:25,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 300 transitions. [2018-11-23 14:18:25,879 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 300 transitions. Word has length 120 [2018-11-23 14:18:25,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:25,879 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 300 transitions. [2018-11-23 14:18:25,879 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:25,879 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 300 transitions. [2018-11-23 14:18:25,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:25,885 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:25,885 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:25,886 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:25,886 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:25,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1873059342, now seen corresponding path program 1 times [2018-11-23 14:18:25,886 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:25,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:25,887 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:25,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:25,887 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:25,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:25,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:25,968 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:25,968 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:25,968 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:25,969 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:25,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:25,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:25,970 INFO L87 Difference]: Start difference. First operand 220 states and 300 transitions. Second operand 5 states. [2018-11-23 14:18:26,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:26,435 INFO L93 Difference]: Finished difference Result 469 states and 662 transitions. [2018-11-23 14:18:26,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:26,435 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:26,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:26,437 INFO L225 Difference]: With dead ends: 469 [2018-11-23 14:18:26,437 INFO L226 Difference]: Without dead ends: 271 [2018-11-23 14:18:26,438 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:26,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-11-23 14:18:26,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 220. [2018-11-23 14:18:26,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:26,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 299 transitions. [2018-11-23 14:18:26,460 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 299 transitions. Word has length 120 [2018-11-23 14:18:26,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:26,460 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 299 transitions. [2018-11-23 14:18:26,460 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:26,460 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 299 transitions. [2018-11-23 14:18:26,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:26,462 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:26,462 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:26,462 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:26,462 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:26,462 INFO L82 PathProgramCache]: Analyzing trace with hash 4003888, now seen corresponding path program 1 times [2018-11-23 14:18:26,462 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:26,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:26,463 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:26,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:26,464 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:26,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:26,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:26,524 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:26,524 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:26,525 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:26,525 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:26,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:26,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:26,526 INFO L87 Difference]: Start difference. First operand 220 states and 299 transitions. Second operand 5 states. [2018-11-23 14:18:26,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:26,853 INFO L93 Difference]: Finished difference Result 467 states and 656 transitions. [2018-11-23 14:18:26,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:26,854 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:26,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:26,856 INFO L225 Difference]: With dead ends: 467 [2018-11-23 14:18:26,856 INFO L226 Difference]: Without dead ends: 269 [2018-11-23 14:18:26,857 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:26,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-11-23 14:18:26,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 220. [2018-11-23 14:18:26,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:26,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 298 transitions. [2018-11-23 14:18:26,874 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 298 transitions. Word has length 120 [2018-11-23 14:18:26,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:26,874 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 298 transitions. [2018-11-23 14:18:26,874 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:26,875 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 298 transitions. [2018-11-23 14:18:26,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:26,876 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:26,876 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:26,876 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:26,876 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:26,877 INFO L82 PathProgramCache]: Analyzing trace with hash -766729678, now seen corresponding path program 1 times [2018-11-23 14:18:26,877 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:26,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:26,877 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:26,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:26,878 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:26,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:26,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:26,940 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:26,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:26,941 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:26,941 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:26,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:26,941 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:26,942 INFO L87 Difference]: Start difference. First operand 220 states and 298 transitions. Second operand 5 states. [2018-11-23 14:18:27,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:27,233 INFO L93 Difference]: Finished difference Result 465 states and 650 transitions. [2018-11-23 14:18:27,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:27,233 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-11-23 14:18:27,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:27,235 INFO L225 Difference]: With dead ends: 465 [2018-11-23 14:18:27,235 INFO L226 Difference]: Without dead ends: 267 [2018-11-23 14:18:27,236 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:27,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-11-23 14:18:27,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 220. [2018-11-23 14:18:27,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-11-23 14:18:27,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 297 transitions. [2018-11-23 14:18:27,253 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 297 transitions. Word has length 120 [2018-11-23 14:18:27,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:27,253 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 297 transitions. [2018-11-23 14:18:27,253 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:27,253 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 297 transitions. [2018-11-23 14:18:27,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:27,255 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:27,255 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:27,255 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:27,255 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:27,256 INFO L82 PathProgramCache]: Analyzing trace with hash -1761423376, now seen corresponding path program 1 times [2018-11-23 14:18:27,256 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:27,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:27,256 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:27,257 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:27,257 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:27,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:27,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:27,313 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:27,313 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:18:27,313 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:27,314 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:18:27,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:18:27,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:27,314 INFO L87 Difference]: Start difference. First operand 220 states and 297 transitions. Second operand 6 states. [2018-11-23 14:18:27,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:27,370 INFO L93 Difference]: Finished difference Result 436 states and 607 transitions. [2018-11-23 14:18:27,370 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:27,371 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-11-23 14:18:27,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:27,372 INFO L225 Difference]: With dead ends: 436 [2018-11-23 14:18:27,372 INFO L226 Difference]: Without dead ends: 239 [2018-11-23 14:18:27,373 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:27,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-11-23 14:18:27,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 225. [2018-11-23 14:18:27,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-11-23 14:18:27,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 302 transitions. [2018-11-23 14:18:27,400 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 302 transitions. Word has length 120 [2018-11-23 14:18:27,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:27,400 INFO L480 AbstractCegarLoop]: Abstraction has 225 states and 302 transitions. [2018-11-23 14:18:27,401 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:18:27,402 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 302 transitions. [2018-11-23 14:18:27,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:27,403 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:27,403 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:27,403 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:27,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:27,404 INFO L82 PathProgramCache]: Analyzing trace with hash -27318926, now seen corresponding path program 1 times [2018-11-23 14:18:27,404 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:27,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:27,405 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:27,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:27,405 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:27,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:27,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:27,488 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:27,488 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:18:27,488 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:27,488 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:18:27,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:18:27,489 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:18:27,489 INFO L87 Difference]: Start difference. First operand 225 states and 302 transitions. Second operand 4 states. [2018-11-23 14:18:27,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:27,727 INFO L93 Difference]: Finished difference Result 622 states and 862 transitions. [2018-11-23 14:18:27,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:18:27,728 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-11-23 14:18:27,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:27,730 INFO L225 Difference]: With dead ends: 622 [2018-11-23 14:18:27,730 INFO L226 Difference]: Without dead ends: 420 [2018-11-23 14:18:27,732 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:18:27,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-11-23 14:18:27,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 415. [2018-11-23 14:18:27,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 415 states. [2018-11-23 14:18:27,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 415 states to 415 states and 556 transitions. [2018-11-23 14:18:27,808 INFO L78 Accepts]: Start accepts. Automaton has 415 states and 556 transitions. Word has length 120 [2018-11-23 14:18:27,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:27,808 INFO L480 AbstractCegarLoop]: Abstraction has 415 states and 556 transitions. [2018-11-23 14:18:27,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:18:27,808 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 556 transitions. [2018-11-23 14:18:27,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:27,809 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:27,809 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:27,809 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:27,810 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:27,810 INFO L82 PathProgramCache]: Analyzing trace with hash -512734447, now seen corresponding path program 1 times [2018-11-23 14:18:27,810 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:27,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:27,811 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:27,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:27,811 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:27,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:27,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:27,886 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:27,886 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:18:27,886 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:27,886 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:18:27,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:18:27,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:27,887 INFO L87 Difference]: Start difference. First operand 415 states and 556 transitions. Second operand 6 states. [2018-11-23 14:18:27,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:27,967 INFO L93 Difference]: Finished difference Result 823 states and 1130 transitions. [2018-11-23 14:18:27,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:27,968 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-11-23 14:18:27,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:27,971 INFO L225 Difference]: With dead ends: 823 [2018-11-23 14:18:27,972 INFO L226 Difference]: Without dead ends: 431 [2018-11-23 14:18:27,974 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:27,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-11-23 14:18:28,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 420. [2018-11-23 14:18:28,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 420 states. [2018-11-23 14:18:28,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 560 transitions. [2018-11-23 14:18:28,021 INFO L78 Accepts]: Start accepts. Automaton has 420 states and 560 transitions. Word has length 120 [2018-11-23 14:18:28,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:28,021 INFO L480 AbstractCegarLoop]: Abstraction has 420 states and 560 transitions. [2018-11-23 14:18:28,021 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:18:28,021 INFO L276 IsEmpty]: Start isEmpty. Operand 420 states and 560 transitions. [2018-11-23 14:18:28,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:28,022 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:28,022 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:28,023 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:28,023 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:28,023 INFO L82 PathProgramCache]: Analyzing trace with hash -1244701873, now seen corresponding path program 1 times [2018-11-23 14:18:28,023 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:28,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,024 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:28,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,024 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:28,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:28,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:28,091 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:28,091 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:18:28,091 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:28,091 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:18:28,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:18:28,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:18:28,092 INFO L87 Difference]: Start difference. First operand 420 states and 560 transitions. Second operand 4 states. [2018-11-23 14:18:28,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:28,263 INFO L93 Difference]: Finished difference Result 1201 states and 1654 transitions. [2018-11-23 14:18:28,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:18:28,263 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-11-23 14:18:28,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:28,266 INFO L225 Difference]: With dead ends: 1201 [2018-11-23 14:18:28,266 INFO L226 Difference]: Without dead ends: 804 [2018-11-23 14:18:28,268 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:18:28,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 804 states. [2018-11-23 14:18:28,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 804 to 797. [2018-11-23 14:18:28,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 797 states. [2018-11-23 14:18:28,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 1060 transitions. [2018-11-23 14:18:28,317 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 1060 transitions. Word has length 120 [2018-11-23 14:18:28,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:28,318 INFO L480 AbstractCegarLoop]: Abstraction has 797 states and 1060 transitions. [2018-11-23 14:18:28,318 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:18:28,318 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 1060 transitions. [2018-11-23 14:18:28,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:28,319 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:28,319 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:28,320 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:28,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:28,320 INFO L82 PathProgramCache]: Analyzing trace with hash -667773232, now seen corresponding path program 1 times [2018-11-23 14:18:28,320 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:28,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,322 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:28,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,322 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:28,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:28,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:28,380 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:28,380 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:18:28,380 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:28,380 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:18:28,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:18:28,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:28,381 INFO L87 Difference]: Start difference. First operand 797 states and 1060 transitions. Second operand 6 states. [2018-11-23 14:18:28,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:28,442 INFO L93 Difference]: Finished difference Result 1597 states and 2175 transitions. [2018-11-23 14:18:28,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:28,442 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-11-23 14:18:28,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:28,445 INFO L225 Difference]: With dead ends: 1597 [2018-11-23 14:18:28,445 INFO L226 Difference]: Without dead ends: 823 [2018-11-23 14:18:28,447 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:28,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823 states. [2018-11-23 14:18:28,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823 to 807. [2018-11-23 14:18:28,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-11-23 14:18:28,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1068 transitions. [2018-11-23 14:18:28,497 INFO L78 Accepts]: Start accepts. Automaton has 807 states and 1068 transitions. Word has length 120 [2018-11-23 14:18:28,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:28,497 INFO L480 AbstractCegarLoop]: Abstraction has 807 states and 1068 transitions. [2018-11-23 14:18:28,497 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:18:28,497 INFO L276 IsEmpty]: Start isEmpty. Operand 807 states and 1068 transitions. [2018-11-23 14:18:28,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:28,499 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:28,499 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:28,499 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:28,499 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:28,499 INFO L82 PathProgramCache]: Analyzing trace with hash 593144018, now seen corresponding path program 1 times [2018-11-23 14:18:28,499 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:28,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,500 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:28,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,500 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:28,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:28,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:28,548 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:28,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:18:28,549 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:28,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:18:28,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:18:28,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:28,550 INFO L87 Difference]: Start difference. First operand 807 states and 1068 transitions. Second operand 6 states. [2018-11-23 14:18:28,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:28,614 INFO L93 Difference]: Finished difference Result 1631 states and 2212 transitions. [2018-11-23 14:18:28,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:28,614 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-11-23 14:18:28,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:28,617 INFO L225 Difference]: With dead ends: 1631 [2018-11-23 14:18:28,617 INFO L226 Difference]: Without dead ends: 847 [2018-11-23 14:18:28,620 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:28,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 847 states. [2018-11-23 14:18:28,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 847 to 827. [2018-11-23 14:18:28,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 827 states. [2018-11-23 14:18:28,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1088 transitions. [2018-11-23 14:18:28,673 INFO L78 Accepts]: Start accepts. Automaton has 827 states and 1088 transitions. Word has length 120 [2018-11-23 14:18:28,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:28,673 INFO L480 AbstractCegarLoop]: Abstraction has 827 states and 1088 transitions. [2018-11-23 14:18:28,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:18:28,674 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1088 transitions. [2018-11-23 14:18:28,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-11-23 14:18:28,675 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:28,675 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:28,675 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:28,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:28,675 INFO L82 PathProgramCache]: Analyzing trace with hash -1762661232, now seen corresponding path program 1 times [2018-11-23 14:18:28,676 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:28,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:28,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:28,677 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:28,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:28,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:18:28,730 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:28,730 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:18:28,730 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:28,730 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:18:28,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:18:28,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:18:28,731 INFO L87 Difference]: Start difference. First operand 827 states and 1088 transitions. Second operand 4 states. [2018-11-23 14:18:29,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:29,006 INFO L93 Difference]: Finished difference Result 2411 states and 3286 transitions. [2018-11-23 14:18:29,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:18:29,007 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-11-23 14:18:29,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:29,012 INFO L225 Difference]: With dead ends: 2411 [2018-11-23 14:18:29,013 INFO L226 Difference]: Without dead ends: 1607 [2018-11-23 14:18:29,015 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:18:29,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1607 states. [2018-11-23 14:18:29,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1607 to 1598. [2018-11-23 14:18:29,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1598 states. [2018-11-23 14:18:29,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1598 states to 1598 states and 2097 transitions. [2018-11-23 14:18:29,101 INFO L78 Accepts]: Start accepts. Automaton has 1598 states and 2097 transitions. Word has length 120 [2018-11-23 14:18:29,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:29,101 INFO L480 AbstractCegarLoop]: Abstraction has 1598 states and 2097 transitions. [2018-11-23 14:18:29,101 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:18:29,101 INFO L276 IsEmpty]: Start isEmpty. Operand 1598 states and 2097 transitions. [2018-11-23 14:18:29,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:29,103 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:29,104 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:29,104 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:29,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:29,104 INFO L82 PathProgramCache]: Analyzing trace with hash 1599710920, now seen corresponding path program 1 times [2018-11-23 14:18:29,104 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:29,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:29,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:29,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:29,105 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:29,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:29,150 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:29,150 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:29,150 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 14:18:29,150 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:29,150 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:18:29,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:18:29,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:29,151 INFO L87 Difference]: Start difference. First operand 1598 states and 2097 transitions. Second operand 6 states. [2018-11-23 14:18:29,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:29,268 INFO L93 Difference]: Finished difference Result 3201 states and 4303 transitions. [2018-11-23 14:18:29,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:29,270 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 141 [2018-11-23 14:18:29,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:29,275 INFO L225 Difference]: With dead ends: 3201 [2018-11-23 14:18:29,275 INFO L226 Difference]: Without dead ends: 1626 [2018-11-23 14:18:29,279 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:29,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states. [2018-11-23 14:18:29,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1618. [2018-11-23 14:18:29,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-11-23 14:18:29,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2113 transitions. [2018-11-23 14:18:29,367 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2113 transitions. Word has length 141 [2018-11-23 14:18:29,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:29,367 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2113 transitions. [2018-11-23 14:18:29,367 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:18:29,367 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2113 transitions. [2018-11-23 14:18:29,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:29,369 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:29,370 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:29,370 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:29,370 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:29,370 INFO L82 PathProgramCache]: Analyzing trace with hash 1801534854, now seen corresponding path program 1 times [2018-11-23 14:18:29,370 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:29,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:29,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:29,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:29,371 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:29,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:29,441 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:29,441 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:29,441 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:29,441 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:29,442 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:29,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:29,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:29,442 INFO L87 Difference]: Start difference. First operand 1618 states and 2113 transitions. Second operand 5 states. [2018-11-23 14:18:29,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:29,795 INFO L93 Difference]: Finished difference Result 3212 states and 4210 transitions. [2018-11-23 14:18:29,795 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:29,795 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-11-23 14:18:29,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:29,801 INFO L225 Difference]: With dead ends: 3212 [2018-11-23 14:18:29,802 INFO L226 Difference]: Without dead ends: 1618 [2018-11-23 14:18:29,805 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:29,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-11-23 14:18:29,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-11-23 14:18:29,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-11-23 14:18:29,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2097 transitions. [2018-11-23 14:18:29,916 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2097 transitions. Word has length 141 [2018-11-23 14:18:29,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:29,917 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2097 transitions. [2018-11-23 14:18:29,917 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:29,917 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2097 transitions. [2018-11-23 14:18:29,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:29,919 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:29,919 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:29,919 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:29,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:29,920 INFO L82 PathProgramCache]: Analyzing trace with hash -1106647032, now seen corresponding path program 1 times [2018-11-23 14:18:29,920 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:29,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:29,921 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:29,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:29,921 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:29,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:30,009 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:30,010 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:30,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:30,010 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:30,010 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:30,010 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:30,010 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:30,011 INFO L87 Difference]: Start difference. First operand 1618 states and 2097 transitions. Second operand 5 states. [2018-11-23 14:18:30,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:30,367 INFO L93 Difference]: Finished difference Result 3212 states and 4178 transitions. [2018-11-23 14:18:30,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:30,368 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-11-23 14:18:30,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:30,373 INFO L225 Difference]: With dead ends: 3212 [2018-11-23 14:18:30,373 INFO L226 Difference]: Without dead ends: 1618 [2018-11-23 14:18:30,377 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:30,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-11-23 14:18:30,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-11-23 14:18:30,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-11-23 14:18:30,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2081 transitions. [2018-11-23 14:18:30,465 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2081 transitions. Word has length 141 [2018-11-23 14:18:30,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:30,465 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2081 transitions. [2018-11-23 14:18:30,465 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:30,466 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2081 transitions. [2018-11-23 14:18:30,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:30,467 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:30,467 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:30,468 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:30,468 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:30,468 INFO L82 PathProgramCache]: Analyzing trace with hash -230628026, now seen corresponding path program 1 times [2018-11-23 14:18:30,468 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:30,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:30,469 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:30,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:30,469 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:30,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:30,523 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:30,523 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:30,523 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:30,523 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:30,524 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:30,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:30,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:30,524 INFO L87 Difference]: Start difference. First operand 1618 states and 2081 transitions. Second operand 5 states. [2018-11-23 14:18:30,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:30,871 INFO L93 Difference]: Finished difference Result 3212 states and 4146 transitions. [2018-11-23 14:18:30,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:18:30,872 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-11-23 14:18:30,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:30,876 INFO L225 Difference]: With dead ends: 3212 [2018-11-23 14:18:30,877 INFO L226 Difference]: Without dead ends: 1618 [2018-11-23 14:18:30,880 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:18:30,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-11-23 14:18:30,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-11-23 14:18:30,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-11-23 14:18:30,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2065 transitions. [2018-11-23 14:18:30,971 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2065 transitions. Word has length 141 [2018-11-23 14:18:30,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:30,971 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2065 transitions. [2018-11-23 14:18:30,971 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:30,971 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2065 transitions. [2018-11-23 14:18:30,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:30,974 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:30,974 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:30,974 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:30,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:30,974 INFO L82 PathProgramCache]: Analyzing trace with hash 213272648, now seen corresponding path program 1 times [2018-11-23 14:18:30,974 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:30,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:30,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:30,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:30,975 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:30,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:31,035 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:31,035 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:31,035 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:31,035 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:31,035 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:31,036 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:31,036 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:31,036 INFO L87 Difference]: Start difference. First operand 1618 states and 2065 transitions. Second operand 5 states. [2018-11-23 14:18:31,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:31,574 INFO L93 Difference]: Finished difference Result 4062 states and 5227 transitions. [2018-11-23 14:18:31,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:31,575 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-11-23 14:18:31,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:31,588 INFO L225 Difference]: With dead ends: 4062 [2018-11-23 14:18:31,588 INFO L226 Difference]: Without dead ends: 2468 [2018-11-23 14:18:31,594 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:31,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2468 states. [2018-11-23 14:18:31,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2468 to 2324. [2018-11-23 14:18:31,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2018-11-23 14:18:31,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2887 transitions. [2018-11-23 14:18:31,797 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2887 transitions. Word has length 141 [2018-11-23 14:18:31,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:31,798 INFO L480 AbstractCegarLoop]: Abstraction has 2324 states and 2887 transitions. [2018-11-23 14:18:31,798 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:31,798 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2887 transitions. [2018-11-23 14:18:31,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:31,800 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:31,800 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:31,800 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:31,801 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:31,801 INFO L82 PathProgramCache]: Analyzing trace with hash 1751612678, now seen corresponding path program 1 times [2018-11-23 14:18:31,801 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:31,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:31,802 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:31,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:31,802 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:31,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:31,874 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:31,874 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:31,874 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:31,875 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:31,875 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:31,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:31,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:31,875 INFO L87 Difference]: Start difference. First operand 2324 states and 2887 transitions. Second operand 5 states. [2018-11-23 14:18:32,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:32,655 INFO L93 Difference]: Finished difference Result 5495 states and 7170 transitions. [2018-11-23 14:18:32,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:32,656 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-11-23 14:18:32,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:32,666 INFO L225 Difference]: With dead ends: 5495 [2018-11-23 14:18:32,666 INFO L226 Difference]: Without dead ends: 3197 [2018-11-23 14:18:32,671 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:32,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3197 states. [2018-11-23 14:18:32,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3197 to 2836. [2018-11-23 14:18:32,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2836 states. [2018-11-23 14:18:32,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2836 states to 2836 states and 3435 transitions. [2018-11-23 14:18:32,869 INFO L78 Accepts]: Start accepts. Automaton has 2836 states and 3435 transitions. Word has length 141 [2018-11-23 14:18:32,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:32,869 INFO L480 AbstractCegarLoop]: Abstraction has 2836 states and 3435 transitions. [2018-11-23 14:18:32,869 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:32,869 INFO L276 IsEmpty]: Start isEmpty. Operand 2836 states and 3435 transitions. [2018-11-23 14:18:32,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:32,872 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:32,872 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:32,872 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:32,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:32,872 INFO L82 PathProgramCache]: Analyzing trace with hash -276973432, now seen corresponding path program 1 times [2018-11-23 14:18:32,873 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:32,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:32,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:32,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:32,874 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:32,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:32,979 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:32,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:32,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:32,979 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:32,980 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:32,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:32,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:32,980 INFO L87 Difference]: Start difference. First operand 2836 states and 3435 transitions. Second operand 5 states. [2018-11-23 14:18:33,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:33,602 INFO L93 Difference]: Finished difference Result 6035 states and 7539 transitions. [2018-11-23 14:18:33,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:33,604 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-11-23 14:18:33,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:33,612 INFO L225 Difference]: With dead ends: 6035 [2018-11-23 14:18:33,612 INFO L226 Difference]: Without dead ends: 3225 [2018-11-23 14:18:33,617 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:33,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3225 states. [2018-11-23 14:18:33,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3225 to 3060. [2018-11-23 14:18:33,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3060 states. [2018-11-23 14:18:33,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3060 states to 3060 states and 3641 transitions. [2018-11-23 14:18:33,773 INFO L78 Accepts]: Start accepts. Automaton has 3060 states and 3641 transitions. Word has length 141 [2018-11-23 14:18:33,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:33,773 INFO L480 AbstractCegarLoop]: Abstraction has 3060 states and 3641 transitions. [2018-11-23 14:18:33,773 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:33,773 INFO L276 IsEmpty]: Start isEmpty. Operand 3060 states and 3641 transitions. [2018-11-23 14:18:33,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:33,775 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:33,776 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:33,776 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:33,776 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:33,776 INFO L82 PathProgramCache]: Analyzing trace with hash -758053690, now seen corresponding path program 1 times [2018-11-23 14:18:33,776 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:33,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:33,777 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:33,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:33,777 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:33,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:33,834 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-23 14:18:33,835 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:18:33,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 14:18:33,835 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:33,835 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:18:33,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:18:33,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:18:33,836 INFO L87 Difference]: Start difference. First operand 3060 states and 3641 transitions. Second operand 5 states. [2018-11-23 14:18:34,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:34,379 INFO L93 Difference]: Finished difference Result 6473 states and 8022 transitions. [2018-11-23 14:18:34,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:18:34,380 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-11-23 14:18:34,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:34,389 INFO L225 Difference]: With dead ends: 6473 [2018-11-23 14:18:34,389 INFO L226 Difference]: Without dead ends: 3437 [2018-11-23 14:18:34,396 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:18:34,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states. [2018-11-23 14:18:34,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3206. [2018-11-23 14:18:34,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3206 states. [2018-11-23 14:18:34,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3206 states to 3206 states and 3739 transitions. [2018-11-23 14:18:34,613 INFO L78 Accepts]: Start accepts. Automaton has 3206 states and 3739 transitions. Word has length 141 [2018-11-23 14:18:34,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:34,614 INFO L480 AbstractCegarLoop]: Abstraction has 3206 states and 3739 transitions. [2018-11-23 14:18:34,614 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:18:34,614 INFO L276 IsEmpty]: Start isEmpty. Operand 3206 states and 3739 transitions. [2018-11-23 14:18:34,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-23 14:18:34,616 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:34,616 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:34,616 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:34,616 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:34,617 INFO L82 PathProgramCache]: Analyzing trace with hash -773572408, now seen corresponding path program 1 times [2018-11-23 14:18:34,617 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:34,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:34,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:34,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:34,618 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:34,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:34,657 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-23 14:18:34,658 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:18:34,658 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:18:34,659 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 142 with the following transitions: [2018-11-23 14:18:34,660 INFO L202 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [330], [332], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [542], [555], [568], [581], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [696], [697], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:18:34,689 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:18:34,689 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:18:34,927 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:18:34,929 INFO L272 AbstractInterpreter]: Visited 110 different actions 110 times. Never merged. Never widened. Performed 971 root evaluator evaluations with a maximum evaluation depth of 3. Performed 971 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 58 variables. [2018-11-23 14:18:34,947 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:34,947 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:18:35,210 INFO L227 lantSequenceWeakener]: Weakened 118 states. On average, predicates are now at 69.56% of their original sizes. [2018-11-23 14:18:35,210 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:18:36,128 INFO L415 sIntCurrentIteration]: We unified 140 AI predicates to 140 [2018-11-23 14:18:36,128 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:18:36,129 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:18:36,129 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [46] imperfect sequences [3] total 47 [2018-11-23 14:18:36,129 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:36,129 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-11-23 14:18:36,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-11-23 14:18:36,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=414, Invalid=1656, Unknown=0, NotChecked=0, Total=2070 [2018-11-23 14:18:36,130 INFO L87 Difference]: Start difference. First operand 3206 states and 3739 transitions. Second operand 46 states. [2018-11-23 14:18:44,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:18:44,463 INFO L93 Difference]: Finished difference Result 6513 states and 7626 transitions. [2018-11-23 14:18:44,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-23 14:18:44,463 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 141 [2018-11-23 14:18:44,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:18:44,474 INFO L225 Difference]: With dead ends: 6513 [2018-11-23 14:18:44,474 INFO L226 Difference]: Without dead ends: 3322 [2018-11-23 14:18:44,481 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 170 GetRequests, 96 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1530 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1227, Invalid=4473, Unknown=0, NotChecked=0, Total=5700 [2018-11-23 14:18:44,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states. [2018-11-23 14:18:44,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 3309. [2018-11-23 14:18:44,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3309 states. [2018-11-23 14:18:44,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3309 states to 3309 states and 3847 transitions. [2018-11-23 14:18:44,666 INFO L78 Accepts]: Start accepts. Automaton has 3309 states and 3847 transitions. Word has length 141 [2018-11-23 14:18:44,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:18:44,667 INFO L480 AbstractCegarLoop]: Abstraction has 3309 states and 3847 transitions. [2018-11-23 14:18:44,667 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-11-23 14:18:44,667 INFO L276 IsEmpty]: Start isEmpty. Operand 3309 states and 3847 transitions. [2018-11-23 14:18:44,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-11-23 14:18:44,670 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:18:44,670 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:18:44,670 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:18:44,670 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:44,671 INFO L82 PathProgramCache]: Analyzing trace with hash -1812010618, now seen corresponding path program 1 times [2018-11-23 14:18:44,671 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:18:44,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:44,671 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:18:44,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:18:44,672 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:18:44,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:18:44,711 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 9 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 14:18:44,711 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:18:44,711 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:18:44,711 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 146 with the following transitions: [2018-11-23 14:18:44,712 INFO L202 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [330], [332], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [565], [568], [572], [578], [581], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [696], [697], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:18:44,716 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:18:44,716 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:18:44,801 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:18:44,801 INFO L272 AbstractInterpreter]: Visited 130 different actions 152 times. Merged at 13 different actions 13 times. Never widened. Performed 1404 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1404 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-11-23 14:18:44,808 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:18:44,809 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:18:44,953 INFO L227 lantSequenceWeakener]: Weakened 140 states. On average, predicates are now at 72.97% of their original sizes. [2018-11-23 14:18:44,953 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:18:45,708 INFO L415 sIntCurrentIteration]: We unified 144 AI predicates to 144 [2018-11-23 14:18:45,708 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:18:45,708 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:18:45,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [55] imperfect sequences [3] total 56 [2018-11-23 14:18:45,709 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:18:45,709 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-11-23 14:18:45,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-11-23 14:18:45,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=751, Invalid=2219, Unknown=0, NotChecked=0, Total=2970 [2018-11-23 14:18:45,710 INFO L87 Difference]: Start difference. First operand 3309 states and 3847 transitions. Second operand 55 states. [2018-11-23 14:19:06,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:19:06,508 INFO L93 Difference]: Finished difference Result 24421 states and 30695 transitions. [2018-11-23 14:19:06,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-11-23 14:19:06,508 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 145 [2018-11-23 14:19:06,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:19:06,569 INFO L225 Difference]: With dead ends: 24421 [2018-11-23 14:19:06,569 INFO L226 Difference]: Without dead ends: 16699 [2018-11-23 14:19:06,610 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 195 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3582 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2359, Invalid=8771, Unknown=0, NotChecked=0, Total=11130 [2018-11-23 14:19:06,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16699 states. [2018-11-23 14:19:08,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16699 to 16217. [2018-11-23 14:19:08,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16217 states. [2018-11-23 14:19:08,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16217 states to 16217 states and 19636 transitions. [2018-11-23 14:19:08,562 INFO L78 Accepts]: Start accepts. Automaton has 16217 states and 19636 transitions. Word has length 145 [2018-11-23 14:19:08,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:19:08,563 INFO L480 AbstractCegarLoop]: Abstraction has 16217 states and 19636 transitions. [2018-11-23 14:19:08,563 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-11-23 14:19:08,563 INFO L276 IsEmpty]: Start isEmpty. Operand 16217 states and 19636 transitions. [2018-11-23 14:19:08,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2018-11-23 14:19:08,590 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:19:08,590 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:19:08,590 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:19:08,590 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:08,591 INFO L82 PathProgramCache]: Analyzing trace with hash -708564301, now seen corresponding path program 1 times [2018-11-23 14:19:08,591 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:19:08,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:08,591 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:19:08,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:08,592 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:19:08,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:19:08,698 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-23 14:19:08,698 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:19:08,698 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 14:19:08,698 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:19:08,699 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:19:08,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:19:08,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:19:08,699 INFO L87 Difference]: Start difference. First operand 16217 states and 19636 transitions. Second operand 4 states. [2018-11-23 14:19:09,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:19:09,881 INFO L93 Difference]: Finished difference Result 31187 states and 38714 transitions. [2018-11-23 14:19:09,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:19:09,882 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 207 [2018-11-23 14:19:09,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:19:10,044 INFO L225 Difference]: With dead ends: 31187 [2018-11-23 14:19:10,044 INFO L226 Difference]: Without dead ends: 15097 [2018-11-23 14:19:10,069 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:19:10,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15097 states. [2018-11-23 14:19:11,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15097 to 15012. [2018-11-23 14:19:11,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15012 states. [2018-11-23 14:19:11,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15012 states to 15012 states and 17698 transitions. [2018-11-23 14:19:11,040 INFO L78 Accepts]: Start accepts. Automaton has 15012 states and 17698 transitions. Word has length 207 [2018-11-23 14:19:11,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:19:11,040 INFO L480 AbstractCegarLoop]: Abstraction has 15012 states and 17698 transitions. [2018-11-23 14:19:11,040 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:19:11,041 INFO L276 IsEmpty]: Start isEmpty. Operand 15012 states and 17698 transitions. [2018-11-23 14:19:11,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2018-11-23 14:19:11,063 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:19:11,064 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:19:11,064 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:19:11,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:11,065 INFO L82 PathProgramCache]: Analyzing trace with hash -913434924, now seen corresponding path program 1 times [2018-11-23 14:19:11,065 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:19:11,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:11,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:19:11,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:11,066 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:19:11,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:19:11,159 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-11-23 14:19:11,159 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:19:11,160 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:19:11,160 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 211 with the following transitions: [2018-11-23 14:19:11,160 INFO L202 CegarAbsIntRunner]: [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [552], [559], [565], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:19:11,165 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:19:11,165 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:19:11,258 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:19:11,259 INFO L272 AbstractInterpreter]: Visited 131 different actions 152 times. Merged at 14 different actions 14 times. Never widened. Performed 1651 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1651 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-11-23 14:19:11,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:11,261 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:19:11,431 INFO L227 lantSequenceWeakener]: Weakened 146 states. On average, predicates are now at 69.13% of their original sizes. [2018-11-23 14:19:11,431 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:19:12,356 INFO L415 sIntCurrentIteration]: We unified 209 AI predicates to 209 [2018-11-23 14:19:12,356 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:19:12,356 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:19:12,356 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [57] imperfect sequences [6] total 61 [2018-11-23 14:19:12,357 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:19:12,357 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-23 14:19:12,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-23 14:19:12,358 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=791, Invalid=2401, Unknown=0, NotChecked=0, Total=3192 [2018-11-23 14:19:12,358 INFO L87 Difference]: Start difference. First operand 15012 states and 17698 transitions. Second operand 57 states. [2018-11-23 14:19:27,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:19:27,031 INFO L93 Difference]: Finished difference Result 30059 states and 35455 transitions. [2018-11-23 14:19:27,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-11-23 14:19:27,031 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 210 [2018-11-23 14:19:27,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:19:27,059 INFO L225 Difference]: With dead ends: 30059 [2018-11-23 14:19:27,059 INFO L226 Difference]: Without dead ends: 15174 [2018-11-23 14:19:27,080 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 252 GetRequests, 154 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3161 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2346, Invalid=7554, Unknown=0, NotChecked=0, Total=9900 [2018-11-23 14:19:27,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15174 states. [2018-11-23 14:19:27,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15174 to 15153. [2018-11-23 14:19:27,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15153 states. [2018-11-23 14:19:28,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15153 states to 15153 states and 17847 transitions. [2018-11-23 14:19:28,006 INFO L78 Accepts]: Start accepts. Automaton has 15153 states and 17847 transitions. Word has length 210 [2018-11-23 14:19:28,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:19:28,007 INFO L480 AbstractCegarLoop]: Abstraction has 15153 states and 17847 transitions. [2018-11-23 14:19:28,007 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-23 14:19:28,007 INFO L276 IsEmpty]: Start isEmpty. Operand 15153 states and 17847 transitions. [2018-11-23 14:19:28,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 214 [2018-11-23 14:19:28,025 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:19:28,025 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:19:28,025 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:19:28,026 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:28,026 INFO L82 PathProgramCache]: Analyzing trace with hash -1170762779, now seen corresponding path program 1 times [2018-11-23 14:19:28,026 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:19:28,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:28,027 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:19:28,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:28,027 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:19:28,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:19:28,116 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:19:28,116 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:19:28,117 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:19:28,117 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 214 with the following transitions: [2018-11-23 14:19:28,117 INFO L202 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [565], [568], [572], [575], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:19:28,122 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:19:28,127 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:19:28,205 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:19:28,205 INFO L272 AbstractInterpreter]: Visited 138 different actions 157 times. Merged at 11 different actions 11 times. Never widened. Performed 1442 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1442 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-11-23 14:19:28,217 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:28,217 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:19:28,473 INFO L227 lantSequenceWeakener]: Weakened 153 states. On average, predicates are now at 70% of their original sizes. [2018-11-23 14:19:28,473 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:19:29,362 INFO L415 sIntCurrentIteration]: We unified 212 AI predicates to 212 [2018-11-23 14:19:29,362 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:19:29,362 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:19:29,363 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-11-23 14:19:29,363 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:19:29,363 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-11-23 14:19:29,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-11-23 14:19:29,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=774, Invalid=2766, Unknown=0, NotChecked=0, Total=3540 [2018-11-23 14:19:29,364 INFO L87 Difference]: Start difference. First operand 15153 states and 17847 transitions. Second operand 60 states. [2018-11-23 14:19:38,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:19:38,870 INFO L93 Difference]: Finished difference Result 30357 states and 35873 transitions. [2018-11-23 14:19:38,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-11-23 14:19:38,870 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 213 [2018-11-23 14:19:38,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:19:38,915 INFO L225 Difference]: With dead ends: 30357 [2018-11-23 14:19:38,915 INFO L226 Difference]: Without dead ends: 15463 [2018-11-23 14:19:38,948 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 252 GetRequests, 154 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2901 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2027, Invalid=7873, Unknown=0, NotChecked=0, Total=9900 [2018-11-23 14:19:38,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15463 states. [2018-11-23 14:19:40,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15463 to 15443. [2018-11-23 14:19:40,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15443 states. [2018-11-23 14:19:40,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15443 states to 15443 states and 18195 transitions. [2018-11-23 14:19:40,179 INFO L78 Accepts]: Start accepts. Automaton has 15443 states and 18195 transitions. Word has length 213 [2018-11-23 14:19:40,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:19:40,179 INFO L480 AbstractCegarLoop]: Abstraction has 15443 states and 18195 transitions. [2018-11-23 14:19:40,180 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-11-23 14:19:40,180 INFO L276 IsEmpty]: Start isEmpty. Operand 15443 states and 18195 transitions. [2018-11-23 14:19:40,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-11-23 14:19:40,191 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:19:40,191 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:19:40,192 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:19:40,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:40,192 INFO L82 PathProgramCache]: Analyzing trace with hash -105925495, now seen corresponding path program 1 times [2018-11-23 14:19:40,192 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:19:40,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:40,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:19:40,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:40,193 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:19:40,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:19:40,252 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:19:40,252 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:19:40,253 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:19:40,253 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 215 with the following transitions: [2018-11-23 14:19:40,253 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [549], [555], [559], [565], [568], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:19:40,255 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:19:40,255 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:19:40,313 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:19:40,313 INFO L272 AbstractInterpreter]: Visited 141 different actions 164 times. Merged at 13 different actions 13 times. Never widened. Performed 1709 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1709 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-23 14:19:40,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:40,321 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:19:40,436 INFO L227 lantSequenceWeakener]: Weakened 149 states. On average, predicates are now at 68.55% of their original sizes. [2018-11-23 14:19:40,437 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:19:41,464 INFO L415 sIntCurrentIteration]: We unified 213 AI predicates to 213 [2018-11-23 14:19:41,464 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:19:41,464 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:19:41,464 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-11-23 14:19:41,464 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:19:41,464 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-11-23 14:19:41,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-11-23 14:19:41,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=635, Invalid=2905, Unknown=0, NotChecked=0, Total=3540 [2018-11-23 14:19:41,465 INFO L87 Difference]: Start difference. First operand 15443 states and 18195 transitions. Second operand 60 states. [2018-11-23 14:19:52,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:19:52,581 INFO L93 Difference]: Finished difference Result 23771 states and 27984 transitions. [2018-11-23 14:19:52,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-11-23 14:19:52,582 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 214 [2018-11-23 14:19:52,582 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:19:52,608 INFO L225 Difference]: With dead ends: 23771 [2018-11-23 14:19:52,608 INFO L226 Difference]: Without dead ends: 15742 [2018-11-23 14:19:52,619 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 258 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3201 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1794, Invalid=9126, Unknown=0, NotChecked=0, Total=10920 [2018-11-23 14:19:52,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15742 states. [2018-11-23 14:19:53,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15742 to 15717. [2018-11-23 14:19:53,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15717 states. [2018-11-23 14:19:53,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15717 states to 15717 states and 18521 transitions. [2018-11-23 14:19:53,711 INFO L78 Accepts]: Start accepts. Automaton has 15717 states and 18521 transitions. Word has length 214 [2018-11-23 14:19:53,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:19:53,712 INFO L480 AbstractCegarLoop]: Abstraction has 15717 states and 18521 transitions. [2018-11-23 14:19:53,712 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-11-23 14:19:53,712 INFO L276 IsEmpty]: Start isEmpty. Operand 15717 states and 18521 transitions. [2018-11-23 14:19:53,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-11-23 14:19:53,725 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:19:53,725 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:19:53,725 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:19:53,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:53,725 INFO L82 PathProgramCache]: Analyzing trace with hash 1361264291, now seen corresponding path program 1 times [2018-11-23 14:19:53,726 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:19:53,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:53,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:19:53,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:19:53,726 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:19:53,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:19:53,793 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:19:53,793 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:19:53,793 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:19:53,793 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 215 with the following transitions: [2018-11-23 14:19:53,794 INFO L202 CegarAbsIntRunner]: [33], [36], [47], [49], [51], [53], [57], [60], [76], [78], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [562], [568], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:19:53,795 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:19:53,795 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:19:53,846 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:19:53,847 INFO L272 AbstractInterpreter]: Visited 141 different actions 164 times. Merged at 13 different actions 13 times. Never widened. Performed 1711 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1711 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-23 14:19:53,852 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:19:53,853 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:19:53,962 INFO L227 lantSequenceWeakener]: Weakened 149 states. On average, predicates are now at 68.56% of their original sizes. [2018-11-23 14:19:53,962 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:19:55,075 INFO L415 sIntCurrentIteration]: We unified 213 AI predicates to 213 [2018-11-23 14:19:55,075 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:19:55,076 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:19:55,076 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-11-23 14:19:55,076 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:19:55,076 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-11-23 14:19:55,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-11-23 14:19:55,077 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=671, Invalid=2869, Unknown=0, NotChecked=0, Total=3540 [2018-11-23 14:19:55,078 INFO L87 Difference]: Start difference. First operand 15717 states and 18521 transitions. Second operand 60 states. [2018-11-23 14:20:09,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:20:09,862 INFO L93 Difference]: Finished difference Result 23998 states and 28234 transitions. [2018-11-23 14:20:09,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-11-23 14:20:09,862 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 214 [2018-11-23 14:20:09,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:20:09,891 INFO L225 Difference]: With dead ends: 23998 [2018-11-23 14:20:09,891 INFO L226 Difference]: Without dead ends: 16168 [2018-11-23 14:20:09,904 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 258 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3264 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1907, Invalid=9013, Unknown=0, NotChecked=0, Total=10920 [2018-11-23 14:20:09,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16168 states. [2018-11-23 14:20:11,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16168 to 16141. [2018-11-23 14:20:11,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16141 states. [2018-11-23 14:20:11,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16141 states to 16141 states and 18992 transitions. [2018-11-23 14:20:11,051 INFO L78 Accepts]: Start accepts. Automaton has 16141 states and 18992 transitions. Word has length 214 [2018-11-23 14:20:11,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:20:11,051 INFO L480 AbstractCegarLoop]: Abstraction has 16141 states and 18992 transitions. [2018-11-23 14:20:11,051 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-11-23 14:20:11,052 INFO L276 IsEmpty]: Start isEmpty. Operand 16141 states and 18992 transitions. [2018-11-23 14:20:11,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2018-11-23 14:20:11,062 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:20:11,063 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:20:11,063 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:20:11,063 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:11,063 INFO L82 PathProgramCache]: Analyzing trace with hash -1427190956, now seen corresponding path program 1 times [2018-11-23 14:20:11,063 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:20:11,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:11,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:20:11,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:11,064 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:20:11,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:20:11,146 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-11-23 14:20:11,146 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:20:11,146 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:20:11,146 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 218 with the following transitions: [2018-11-23 14:20:11,147 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:20:11,148 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:20:11,148 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:20:11,252 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:20:11,252 INFO L272 AbstractInterpreter]: Visited 142 different actions 249 times. Merged at 18 different actions 50 times. Never widened. Performed 3315 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3315 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-23 14:20:11,253 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:11,254 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:20:11,254 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:20:11,255 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:20:11,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:20:11,263 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:20:11,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:20:11,379 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:20:11,429 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 51 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-23 14:20:11,429 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:20:11,615 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-11-23 14:20:11,634 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:20:11,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 7 [2018-11-23 14:20:11,635 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:20:11,635 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:20:11,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:20:11,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:20:11,636 INFO L87 Difference]: Start difference. First operand 16141 states and 18992 transitions. Second operand 3 states. [2018-11-23 14:20:13,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:20:13,618 INFO L93 Difference]: Finished difference Result 41019 states and 51056 transitions. [2018-11-23 14:20:13,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:20:13,619 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 217 [2018-11-23 14:20:13,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:20:13,669 INFO L225 Difference]: With dead ends: 41019 [2018-11-23 14:20:13,669 INFO L226 Difference]: Without dead ends: 26134 [2018-11-23 14:20:13,704 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 440 GetRequests, 431 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:20:13,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26134 states. [2018-11-23 14:20:15,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26134 to 26118. [2018-11-23 14:20:15,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26118 states. [2018-11-23 14:20:15,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26118 states to 26118 states and 31415 transitions. [2018-11-23 14:20:15,350 INFO L78 Accepts]: Start accepts. Automaton has 26118 states and 31415 transitions. Word has length 217 [2018-11-23 14:20:15,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:20:15,350 INFO L480 AbstractCegarLoop]: Abstraction has 26118 states and 31415 transitions. [2018-11-23 14:20:15,350 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:20:15,350 INFO L276 IsEmpty]: Start isEmpty. Operand 26118 states and 31415 transitions. [2018-11-23 14:20:15,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-11-23 14:20:15,367 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:20:15,367 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:20:15,368 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:20:15,368 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:15,368 INFO L82 PathProgramCache]: Analyzing trace with hash -375898583, now seen corresponding path program 1 times [2018-11-23 14:20:15,368 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:20:15,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:15,369 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:20:15,369 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:15,369 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:20:15,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:20:15,443 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-11-23 14:20:15,443 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:20:15,443 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:20:15,443 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 219 with the following transitions: [2018-11-23 14:20:15,444 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [572], [575], [578], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:20:15,447 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:20:15,447 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:20:15,586 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:20:15,586 INFO L272 AbstractInterpreter]: Visited 143 different actions 253 times. Merged at 18 different actions 50 times. Never widened. Performed 3994 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3994 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-23 14:20:15,593 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:15,593 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:20:15,593 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:20:15,593 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:20:15,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:20:15,601 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:20:15,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:20:15,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:20:15,805 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 47 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-23 14:20:15,806 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:20:16,042 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2018-11-23 14:20:16,073 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:20:16,074 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [6, 5] total 10 [2018-11-23 14:20:16,074 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:20:16,074 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:20:16,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:20:16,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-23 14:20:16,075 INFO L87 Difference]: Start difference. First operand 26118 states and 31415 transitions. Second operand 5 states. [2018-11-23 14:20:18,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:20:18,787 INFO L93 Difference]: Finished difference Result 42632 states and 52441 transitions. [2018-11-23 14:20:18,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:20:18,787 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 218 [2018-11-23 14:20:18,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:20:18,849 INFO L225 Difference]: With dead ends: 42632 [2018-11-23 14:20:18,849 INFO L226 Difference]: Without dead ends: 27807 [2018-11-23 14:20:18,893 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 442 GetRequests, 429 SyntacticMatches, 5 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-23 14:20:18,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27807 states. [2018-11-23 14:20:20,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27807 to 27726. [2018-11-23 14:20:20,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27726 states. [2018-11-23 14:20:21,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27726 states to 27726 states and 33745 transitions. [2018-11-23 14:20:21,065 INFO L78 Accepts]: Start accepts. Automaton has 27726 states and 33745 transitions. Word has length 218 [2018-11-23 14:20:21,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:20:21,066 INFO L480 AbstractCegarLoop]: Abstraction has 27726 states and 33745 transitions. [2018-11-23 14:20:21,066 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:20:21,066 INFO L276 IsEmpty]: Start isEmpty. Operand 27726 states and 33745 transitions. [2018-11-23 14:20:21,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-11-23 14:20:21,092 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:20:21,092 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:20:21,092 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:20:21,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:21,093 INFO L82 PathProgramCache]: Analyzing trace with hash 438612538, now seen corresponding path program 1 times [2018-11-23 14:20:21,093 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:20:21,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:21,094 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:20:21,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:21,094 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:20:21,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:20:21,202 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:20:21,203 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:20:21,203 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:20:21,204 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 222 with the following transitions: [2018-11-23 14:20:21,204 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [549], [555], [559], [565], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:20:21,205 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:20:21,206 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:20:21,282 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:20:21,282 INFO L272 AbstractInterpreter]: Visited 146 different actions 164 times. Merged at 10 different actions 10 times. Never widened. Performed 1492 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1492 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-23 14:20:21,285 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:21,285 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:20:21,581 INFO L227 lantSequenceWeakener]: Weakened 159 states. On average, predicates are now at 68.9% of their original sizes. [2018-11-23 14:20:21,581 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:20:22,682 INFO L415 sIntCurrentIteration]: We unified 220 AI predicates to 220 [2018-11-23 14:20:22,682 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:20:22,682 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:20:22,683 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [62] imperfect sequences [4] total 64 [2018-11-23 14:20:22,683 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:20:22,683 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-23 14:20:22,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-23 14:20:22,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=603, Invalid=3179, Unknown=0, NotChecked=0, Total=3782 [2018-11-23 14:20:22,684 INFO L87 Difference]: Start difference. First operand 27726 states and 33745 transitions. Second operand 62 states. [2018-11-23 14:20:38,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:20:38,295 INFO L93 Difference]: Finished difference Result 36754 states and 44718 transitions. [2018-11-23 14:20:38,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-11-23 14:20:38,296 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 221 [2018-11-23 14:20:38,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:20:38,350 INFO L225 Difference]: With dead ends: 36754 [2018-11-23 14:20:38,350 INFO L226 Difference]: Without dead ends: 28003 [2018-11-23 14:20:38,371 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 262 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3060 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1621, Invalid=9091, Unknown=0, NotChecked=0, Total=10712 [2018-11-23 14:20:38,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28003 states. [2018-11-23 14:20:40,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28003 to 27986. [2018-11-23 14:20:40,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27986 states. [2018-11-23 14:20:40,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27986 states to 27986 states and 34065 transitions. [2018-11-23 14:20:40,585 INFO L78 Accepts]: Start accepts. Automaton has 27986 states and 34065 transitions. Word has length 221 [2018-11-23 14:20:40,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:20:40,585 INFO L480 AbstractCegarLoop]: Abstraction has 27986 states and 34065 transitions. [2018-11-23 14:20:40,585 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-23 14:20:40,585 INFO L276 IsEmpty]: Start isEmpty. Operand 27986 states and 34065 transitions. [2018-11-23 14:20:40,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-11-23 14:20:40,601 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:20:40,601 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:20:40,601 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:20:40,602 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:40,602 INFO L82 PathProgramCache]: Analyzing trace with hash 1279761248, now seen corresponding path program 1 times [2018-11-23 14:20:40,602 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:20:40,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:40,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:20:40,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:20:40,603 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:20:40,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:20:40,676 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:20:40,677 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:20:40,677 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:20:40,677 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 222 with the following transitions: [2018-11-23 14:20:40,677 INFO L202 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [60], [76], [78], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [562], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:20:40,678 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:20:40,679 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:20:40,752 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:20:40,752 INFO L272 AbstractInterpreter]: Visited 146 different actions 164 times. Merged at 10 different actions 10 times. Never widened. Performed 1494 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1494 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-23 14:20:40,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:20:40,761 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:20:40,918 INFO L227 lantSequenceWeakener]: Weakened 159 states. On average, predicates are now at 68.91% of their original sizes. [2018-11-23 14:20:40,918 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:20:41,950 INFO L415 sIntCurrentIteration]: We unified 220 AI predicates to 220 [2018-11-23 14:20:41,950 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:20:41,950 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:20:41,950 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [62] imperfect sequences [4] total 64 [2018-11-23 14:20:41,950 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:20:41,951 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-23 14:20:41,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-23 14:20:41,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=640, Invalid=3142, Unknown=0, NotChecked=0, Total=3782 [2018-11-23 14:20:41,952 INFO L87 Difference]: Start difference. First operand 27986 states and 34065 transitions. Second operand 62 states. [2018-11-23 14:21:00,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:21:00,871 INFO L93 Difference]: Finished difference Result 36849 states and 44839 transitions. [2018-11-23 14:21:00,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-11-23 14:21:00,871 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 221 [2018-11-23 14:21:00,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:21:00,926 INFO L225 Difference]: With dead ends: 36849 [2018-11-23 14:21:00,926 INFO L226 Difference]: Without dead ends: 28325 [2018-11-23 14:21:00,943 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 263 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3205 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1750, Invalid=9170, Unknown=0, NotChecked=0, Total=10920 [2018-11-23 14:21:00,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28325 states. [2018-11-23 14:21:03,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28325 to 28303. [2018-11-23 14:21:03,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28303 states. [2018-11-23 14:21:03,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28303 states to 28303 states and 34442 transitions. [2018-11-23 14:21:03,235 INFO L78 Accepts]: Start accepts. Automaton has 28303 states and 34442 transitions. Word has length 221 [2018-11-23 14:21:03,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:21:03,236 INFO L480 AbstractCegarLoop]: Abstraction has 28303 states and 34442 transitions. [2018-11-23 14:21:03,236 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-23 14:21:03,236 INFO L276 IsEmpty]: Start isEmpty. Operand 28303 states and 34442 transitions. [2018-11-23 14:21:03,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2018-11-23 14:21:03,253 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:21:03,253 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:21:03,254 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:21:03,254 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:03,254 INFO L82 PathProgramCache]: Analyzing trace with hash -287017233, now seen corresponding path program 1 times [2018-11-23 14:21:03,254 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:21:03,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:03,255 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:03,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:03,255 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:21:03,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:03,319 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 16 proven. 5 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:21:03,319 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:03,319 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:21:03,319 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 224 with the following transitions: [2018-11-23 14:21:03,320 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:21:03,321 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:21:03,321 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:21:03,419 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:21:03,420 INFO L272 AbstractInterpreter]: Visited 159 different actions 314 times. Merged at 31 different actions 55 times. Never widened. Performed 3315 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3315 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 8 fixpoints after 5 different actions. Largest state had 60 variables. [2018-11-23 14:21:03,421 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:03,421 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:21:03,421 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:03,421 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:21:03,428 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:03,428 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:21:03,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:03,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:21:03,543 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 73 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:21:03,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:21:03,643 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-11-23 14:21:03,660 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:21:03,660 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-11-23 14:21:03,660 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:21:03,660 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:21:03,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:21:03,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:21:03,660 INFO L87 Difference]: Start difference. First operand 28303 states and 34442 transitions. Second operand 4 states. [2018-11-23 14:21:05,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:21:05,877 INFO L93 Difference]: Finished difference Result 40618 states and 50723 transitions. [2018-11-23 14:21:05,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:21:05,878 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 223 [2018-11-23 14:21:05,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:21:05,925 INFO L225 Difference]: With dead ends: 40618 [2018-11-23 14:21:05,926 INFO L226 Difference]: Without dead ends: 24248 [2018-11-23 14:21:05,962 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 454 GetRequests, 445 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:21:05,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24248 states. [2018-11-23 14:21:07,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24248 to 23992. [2018-11-23 14:21:07,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23992 states. [2018-11-23 14:21:07,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23992 states to 23992 states and 28992 transitions. [2018-11-23 14:21:07,904 INFO L78 Accepts]: Start accepts. Automaton has 23992 states and 28992 transitions. Word has length 223 [2018-11-23 14:21:07,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:21:07,905 INFO L480 AbstractCegarLoop]: Abstraction has 23992 states and 28992 transitions. [2018-11-23 14:21:07,905 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:21:07,905 INFO L276 IsEmpty]: Start isEmpty. Operand 23992 states and 28992 transitions. [2018-11-23 14:21:07,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 446 [2018-11-23 14:21:07,926 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:21:07,926 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:21:07,926 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:21:07,926 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:07,926 INFO L82 PathProgramCache]: Analyzing trace with hash 1061386636, now seen corresponding path program 1 times [2018-11-23 14:21:07,926 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:21:07,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:07,927 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:07,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:07,927 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:21:07,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:08,044 INFO L134 CoverageAnalysis]: Checked inductivity of 525 backedges. 64 proven. 31 refuted. 0 times theorem prover too weak. 430 trivial. 0 not checked. [2018-11-23 14:21:08,044 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:08,044 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:21:08,045 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 446 with the following transitions: [2018-11-23 14:21:08,045 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [542], [546], [549], [552], [555], [559], [562], [565], [572], [575], [578], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-11-23 14:21:08,046 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:21:08,046 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:21:08,414 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:21:08,414 INFO L272 AbstractInterpreter]: Visited 181 different actions 1067 times. Merged at 47 different actions 184 times. Widened at 1 different actions 1 times. Performed 11056 root evaluator evaluations with a maximum evaluation depth of 3. Performed 11056 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 61 fixpoints after 18 different actions. Largest state had 60 variables. [2018-11-23 14:21:08,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:08,417 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:21:08,417 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:08,417 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:21:08,426 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:08,426 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:21:08,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:08,551 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:21:08,625 INFO L134 CoverageAnalysis]: Checked inductivity of 525 backedges. 291 proven. 0 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-11-23 14:21:08,625 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:21:08,828 INFO L134 CoverageAnalysis]: Checked inductivity of 525 backedges. 69 proven. 3 refuted. 0 times theorem prover too weak. 453 trivial. 0 not checked. [2018-11-23 14:21:08,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:21:08,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8, 3] total 9 [2018-11-23 14:21:08,846 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:21:08,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:21:08,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:21:08,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:21:08,847 INFO L87 Difference]: Start difference. First operand 23992 states and 28992 transitions. Second operand 3 states. [2018-11-23 14:21:11,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:21:11,753 INFO L93 Difference]: Finished difference Result 60836 states and 78061 transitions. [2018-11-23 14:21:11,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:21:11,754 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 445 [2018-11-23 14:21:11,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:21:11,826 INFO L225 Difference]: With dead ends: 60836 [2018-11-23 14:21:11,826 INFO L226 Difference]: Without dead ends: 39190 [2018-11-23 14:21:11,873 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 900 GetRequests, 891 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:21:11,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39190 states. [2018-11-23 14:21:14,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39190 to 37230. [2018-11-23 14:21:14,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37230 states. [2018-11-23 14:21:14,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37230 states to 37230 states and 47177 transitions. [2018-11-23 14:21:14,737 INFO L78 Accepts]: Start accepts. Automaton has 37230 states and 47177 transitions. Word has length 445 [2018-11-23 14:21:14,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:21:14,738 INFO L480 AbstractCegarLoop]: Abstraction has 37230 states and 47177 transitions. [2018-11-23 14:21:14,738 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:21:14,738 INFO L276 IsEmpty]: Start isEmpty. Operand 37230 states and 47177 transitions. [2018-11-23 14:21:14,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2018-11-23 14:21:14,779 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:21:14,779 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:21:14,779 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:21:14,779 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:14,779 INFO L82 PathProgramCache]: Analyzing trace with hash 342535070, now seen corresponding path program 1 times [2018-11-23 14:21:14,779 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:21:14,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:14,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:14,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:14,780 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:21:14,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:14,980 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 38 proven. 26 refuted. 0 times theorem prover too weak. 584 trivial. 0 not checked. [2018-11-23 14:21:14,981 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:14,981 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:21:14,981 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 491 with the following transitions: [2018-11-23 14:21:14,981 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [207], [210], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [296], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [542], [546], [549], [555], [559], [562], [565], [572], [575], [578], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-11-23 14:21:14,983 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:21:14,983 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:21:15,748 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:21:15,749 INFO L272 AbstractInterpreter]: Visited 198 different actions 2043 times. Merged at 65 different actions 323 times. Widened at 2 different actions 2 times. Performed 22983 root evaluator evaluations with a maximum evaluation depth of 3. Performed 22983 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 104 fixpoints after 20 different actions. Largest state had 60 variables. [2018-11-23 14:21:15,750 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:15,750 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:21:15,750 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:15,750 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:21:15,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:15,758 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:21:15,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:15,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:21:16,141 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 469 proven. 0 refuted. 0 times theorem prover too weak. 179 trivial. 0 not checked. [2018-11-23 14:21:16,141 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:21:16,418 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 135 proven. 0 refuted. 0 times theorem prover too weak. 513 trivial. 0 not checked. [2018-11-23 14:21:16,435 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:21:16,436 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [8] total 10 [2018-11-23 14:21:16,436 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:21:16,436 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:21:16,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:21:16,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-11-23 14:21:16,436 INFO L87 Difference]: Start difference. First operand 37230 states and 47177 transitions. Second operand 3 states. [2018-11-23 14:21:19,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:21:19,642 INFO L93 Difference]: Finished difference Result 77150 states and 102795 transitions. [2018-11-23 14:21:19,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:21:19,643 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 490 [2018-11-23 14:21:19,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:21:19,740 INFO L225 Difference]: With dead ends: 77150 [2018-11-23 14:21:19,740 INFO L226 Difference]: Without dead ends: 40231 [2018-11-23 14:21:19,845 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 990 GetRequests, 980 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-11-23 14:21:19,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40231 states. [2018-11-23 14:21:22,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40231 to 40225. [2018-11-23 14:21:22,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40225 states. [2018-11-23 14:21:23,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40225 states to 40225 states and 49186 transitions. [2018-11-23 14:21:23,041 INFO L78 Accepts]: Start accepts. Automaton has 40225 states and 49186 transitions. Word has length 490 [2018-11-23 14:21:23,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:21:23,042 INFO L480 AbstractCegarLoop]: Abstraction has 40225 states and 49186 transitions. [2018-11-23 14:21:23,042 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:21:23,042 INFO L276 IsEmpty]: Start isEmpty. Operand 40225 states and 49186 transitions. [2018-11-23 14:21:23,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-11-23 14:21:23,080 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:21:23,081 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:21:23,081 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:21:23,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:23,081 INFO L82 PathProgramCache]: Analyzing trace with hash -1185449005, now seen corresponding path program 1 times [2018-11-23 14:21:23,081 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:21:23,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:23,082 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:23,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:23,082 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:21:23,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:23,179 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 17 proven. 7 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-11-23 14:21:23,179 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:23,180 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:21:23,180 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 295 with the following transitions: [2018-11-23 14:21:23,180 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [555], [559], [562], [572], [575], [585], [588], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:21:23,182 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:21:23,182 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:21:23,235 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 14:21:23,235 INFO L272 AbstractInterpreter]: Visited 153 different actions 167 times. Merged at 8 different actions 8 times. Never widened. Performed 1525 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1525 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-23 14:21:23,237 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:23,237 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 14:21:23,368 INFO L227 lantSequenceWeakener]: Weakened 173 states. On average, predicates are now at 69.32% of their original sizes. [2018-11-23 14:21:23,369 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 14:21:24,529 INFO L415 sIntCurrentIteration]: We unified 293 AI predicates to 293 [2018-11-23 14:21:24,529 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 14:21:24,529 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:21:24,530 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [66] imperfect sequences [4] total 68 [2018-11-23 14:21:24,530 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:21:24,530 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-11-23 14:21:24,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-11-23 14:21:24,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=590, Invalid=3700, Unknown=0, NotChecked=0, Total=4290 [2018-11-23 14:21:24,532 INFO L87 Difference]: Start difference. First operand 40225 states and 49186 transitions. Second operand 66 states. [2018-11-23 14:21:52,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:21:52,492 INFO L93 Difference]: Finished difference Result 55893 states and 67940 transitions. [2018-11-23 14:21:52,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-23 14:21:52,492 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 294 [2018-11-23 14:21:52,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:21:52,575 INFO L225 Difference]: With dead ends: 55893 [2018-11-23 14:21:52,575 INFO L226 Difference]: Without dead ends: 40810 [2018-11-23 14:21:52,756 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 340 GetRequests, 229 SyntacticMatches, 0 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3803 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1612, Invalid=11044, Unknown=0, NotChecked=0, Total=12656 [2018-11-23 14:21:52,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40810 states. [2018-11-23 14:21:55,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40810 to 40791. [2018-11-23 14:21:55,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40791 states. [2018-11-23 14:21:55,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40791 states to 40791 states and 49845 transitions. [2018-11-23 14:21:55,862 INFO L78 Accepts]: Start accepts. Automaton has 40791 states and 49845 transitions. Word has length 294 [2018-11-23 14:21:55,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:21:55,863 INFO L480 AbstractCegarLoop]: Abstraction has 40791 states and 49845 transitions. [2018-11-23 14:21:55,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-11-23 14:21:55,863 INFO L276 IsEmpty]: Start isEmpty. Operand 40791 states and 49845 transitions. [2018-11-23 14:21:55,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 296 [2018-11-23 14:21:55,902 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:21:55,902 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:21:55,902 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:21:55,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:55,902 INFO L82 PathProgramCache]: Analyzing trace with hash 734138646, now seen corresponding path program 1 times [2018-11-23 14:21:55,903 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:21:55,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:55,904 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:55,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:21:55,904 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:21:55,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:55,997 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-11-23 14:21:55,998 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:55,998 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:21:55,998 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 296 with the following transitions: [2018-11-23 14:21:55,998 INFO L202 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [562], [572], [575], [585], [588], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:21:55,999 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:21:55,999 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:21:56,295 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:21:56,295 INFO L272 AbstractInterpreter]: Visited 175 different actions 851 times. Merged at 44 different actions 159 times. Never widened. Performed 7911 root evaluator evaluations with a maximum evaluation depth of 3. Performed 7911 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 32 fixpoints after 11 different actions. Largest state had 60 variables. [2018-11-23 14:21:56,297 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:21:56,297 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:21:56,297 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:21:56,297 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:21:56,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:21:56,306 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:21:56,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:21:56,395 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:21:56,439 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 127 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-11-23 14:21:56,439 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:21:56,574 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-11-23 14:21:56,591 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:21:56,591 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-11-23 14:21:56,591 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:21:56,591 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:21:56,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:21:56,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:21:56,592 INFO L87 Difference]: Start difference. First operand 40791 states and 49845 transitions. Second operand 4 states. [2018-11-23 14:22:00,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:22:00,089 INFO L93 Difference]: Finished difference Result 67612 states and 86240 transitions. [2018-11-23 14:22:00,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:22:00,089 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 295 [2018-11-23 14:22:00,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:22:00,181 INFO L225 Difference]: With dead ends: 67612 [2018-11-23 14:22:00,181 INFO L226 Difference]: Without dead ends: 39195 [2018-11-23 14:22:00,249 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 598 GetRequests, 591 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:22:00,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39195 states. [2018-11-23 14:22:03,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39195 to 39055. [2018-11-23 14:22:03,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39055 states. [2018-11-23 14:22:03,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39055 states to 39055 states and 48395 transitions. [2018-11-23 14:22:03,161 INFO L78 Accepts]: Start accepts. Automaton has 39055 states and 48395 transitions. Word has length 295 [2018-11-23 14:22:03,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:22:03,162 INFO L480 AbstractCegarLoop]: Abstraction has 39055 states and 48395 transitions. [2018-11-23 14:22:03,162 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:22:03,162 INFO L276 IsEmpty]: Start isEmpty. Operand 39055 states and 48395 transitions. [2018-11-23 14:22:03,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 557 [2018-11-23 14:22:03,212 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:22:03,212 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:22:03,213 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:22:03,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:03,213 INFO L82 PathProgramCache]: Analyzing trace with hash -1972365443, now seen corresponding path program 1 times [2018-11-23 14:22:03,213 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:22:03,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:03,213 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:03,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:03,213 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:22:03,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:03,337 INFO L134 CoverageAnalysis]: Checked inductivity of 914 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 856 trivial. 0 not checked. [2018-11-23 14:22:03,337 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:03,337 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:22:03,337 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 557 with the following transitions: [2018-11-23 14:22:03,337 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [546], [549], [555], [559], [562], [565], [572], [575], [578], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-11-23 14:22:03,338 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:22:03,338 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:22:04,355 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:22:04,356 INFO L272 AbstractInterpreter]: Visited 201 different actions 2822 times. Merged at 73 different actions 489 times. Widened at 1 different actions 2 times. Performed 30429 root evaluator evaluations with a maximum evaluation depth of 3. Performed 30429 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 143 fixpoints after 25 different actions. Largest state had 60 variables. [2018-11-23 14:22:04,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:04,365 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:22:04,365 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:04,365 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:22:04,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:04,373 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:22:04,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:04,524 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:22:04,661 INFO L134 CoverageAnalysis]: Checked inductivity of 914 backedges. 518 proven. 0 refuted. 0 times theorem prover too weak. 396 trivial. 0 not checked. [2018-11-23 14:22:04,661 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:22:05,163 INFO L134 CoverageAnalysis]: Checked inductivity of 914 backedges. 85 proven. 60 refuted. 0 times theorem prover too weak. 769 trivial. 0 not checked. [2018-11-23 14:22:05,193 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:22:05,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2018-11-23 14:22:05,194 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:22:05,195 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:22:05,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:22:05,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:22:05,195 INFO L87 Difference]: Start difference. First operand 39055 states and 48395 transitions. Second operand 3 states. [2018-11-23 14:22:10,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:22:10,001 INFO L93 Difference]: Finished difference Result 89759 states and 118565 transitions. [2018-11-23 14:22:10,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:22:10,001 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 556 [2018-11-23 14:22:10,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:22:10,132 INFO L225 Difference]: With dead ends: 89759 [2018-11-23 14:22:10,132 INFO L226 Difference]: Without dead ends: 53494 [2018-11-23 14:22:10,235 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1115 GetRequests, 1111 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:22:10,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53494 states. [2018-11-23 14:22:14,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53494 to 50935. [2018-11-23 14:22:14,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50935 states. [2018-11-23 14:22:14,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50935 states to 50935 states and 63827 transitions. [2018-11-23 14:22:14,757 INFO L78 Accepts]: Start accepts. Automaton has 50935 states and 63827 transitions. Word has length 556 [2018-11-23 14:22:14,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:22:14,757 INFO L480 AbstractCegarLoop]: Abstraction has 50935 states and 63827 transitions. [2018-11-23 14:22:14,757 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:22:14,758 INFO L276 IsEmpty]: Start isEmpty. Operand 50935 states and 63827 transitions. [2018-11-23 14:22:14,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 495 [2018-11-23 14:22:14,826 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:22:14,826 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:22:14,826 INFO L423 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:22:14,826 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:14,826 INFO L82 PathProgramCache]: Analyzing trace with hash 971550640, now seen corresponding path program 1 times [2018-11-23 14:22:14,826 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:22:14,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:14,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:14,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:14,827 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:22:14,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:14,969 INFO L134 CoverageAnalysis]: Checked inductivity of 668 backedges. 41 proven. 26 refuted. 0 times theorem prover too weak. 601 trivial. 0 not checked. [2018-11-23 14:22:14,969 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:14,969 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:22:14,969 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 495 with the following transitions: [2018-11-23 14:22:14,970 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [546], [549], [555], [559], [562], [565], [572], [575], [581], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-11-23 14:22:14,971 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:22:14,971 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:22:15,502 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:22:15,502 INFO L272 AbstractInterpreter]: Visited 187 different actions 1382 times. Merged at 62 different actions 250 times. Never widened. Performed 13253 root evaluator evaluations with a maximum evaluation depth of 3. Performed 13253 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 70 fixpoints after 16 different actions. Largest state had 60 variables. [2018-11-23 14:22:15,512 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:15,513 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:22:15,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:15,513 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:22:15,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:15,521 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:22:15,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:15,654 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:22:15,749 INFO L134 CoverageAnalysis]: Checked inductivity of 668 backedges. 308 proven. 0 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2018-11-23 14:22:15,750 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:22:15,992 INFO L134 CoverageAnalysis]: Checked inductivity of 668 backedges. 46 proven. 12 refuted. 0 times theorem prover too weak. 610 trivial. 0 not checked. [2018-11-23 14:22:16,007 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:22:16,008 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8, 6] total 12 [2018-11-23 14:22:16,008 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:22:16,008 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:22:16,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:22:16,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-11-23 14:22:16,008 INFO L87 Difference]: Start difference. First operand 50935 states and 63827 transitions. Second operand 6 states. [2018-11-23 14:22:18,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:22:18,404 INFO L93 Difference]: Finished difference Result 79240 states and 99191 transitions. [2018-11-23 14:22:18,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:22:18,404 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 494 [2018-11-23 14:22:18,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:22:18,470 INFO L225 Difference]: With dead ends: 79240 [2018-11-23 14:22:18,471 INFO L226 Difference]: Without dead ends: 28772 [2018-11-23 14:22:18,542 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1000 GetRequests, 982 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2018-11-23 14:22:18,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28772 states. [2018-11-23 14:22:20,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28772 to 26280. [2018-11-23 14:22:20,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26280 states. [2018-11-23 14:22:20,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26280 states to 26280 states and 30402 transitions. [2018-11-23 14:22:20,778 INFO L78 Accepts]: Start accepts. Automaton has 26280 states and 30402 transitions. Word has length 494 [2018-11-23 14:22:20,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:22:20,778 INFO L480 AbstractCegarLoop]: Abstraction has 26280 states and 30402 transitions. [2018-11-23 14:22:20,779 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:22:20,779 INFO L276 IsEmpty]: Start isEmpty. Operand 26280 states and 30402 transitions. [2018-11-23 14:22:20,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 375 [2018-11-23 14:22:20,804 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:22:20,804 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:22:20,804 INFO L423 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:22:20,804 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:20,804 INFO L82 PathProgramCache]: Analyzing trace with hash -762444735, now seen corresponding path program 1 times [2018-11-23 14:22:20,804 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:22:20,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:20,805 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:20,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:20,805 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:22:20,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:20,931 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 36 proven. 7 refuted. 0 times theorem prover too weak. 326 trivial. 0 not checked. [2018-11-23 14:22:20,931 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:20,931 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:22:20,931 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 375 with the following transitions: [2018-11-23 14:22:20,932 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [555], [559], [562], [568], [572], [575], [578], [585], [588], [594], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:22:20,935 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:22:20,935 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:22:21,072 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:22:21,072 INFO L272 AbstractInterpreter]: Visited 176 different actions 421 times. Merged at 31 different actions 66 times. Never widened. Performed 4086 root evaluator evaluations with a maximum evaluation depth of 3. Performed 4086 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 16 fixpoints after 6 different actions. Largest state had 60 variables. [2018-11-23 14:22:21,077 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:21,077 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:22:21,078 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:21,078 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:22:21,088 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:21,088 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:22:21,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:21,203 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:22:21,251 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 265 proven. 0 refuted. 0 times theorem prover too weak. 104 trivial. 0 not checked. [2018-11-23 14:22:21,251 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:22:21,613 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 40 proven. 20 refuted. 0 times theorem prover too weak. 309 trivial. 0 not checked. [2018-11-23 14:22:21,632 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:22:21,632 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 3] total 5 [2018-11-23 14:22:21,632 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:22:21,633 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:22:21,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:22:21,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:22:21,633 INFO L87 Difference]: Start difference. First operand 26280 states and 30402 transitions. Second operand 3 states. [2018-11-23 14:22:23,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:22:23,581 INFO L93 Difference]: Finished difference Result 45113 states and 52079 transitions. [2018-11-23 14:22:23,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:22:23,581 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 374 [2018-11-23 14:22:23,582 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:22:23,625 INFO L225 Difference]: With dead ends: 45113 [2018-11-23 14:22:23,625 INFO L226 Difference]: Without dead ends: 22311 [2018-11-23 14:22:23,663 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 752 GetRequests, 749 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:22:23,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22311 states. [2018-11-23 14:22:25,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22311 to 21688. [2018-11-23 14:22:25,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21688 states. [2018-11-23 14:22:25,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21688 states to 21688 states and 24571 transitions. [2018-11-23 14:22:25,497 INFO L78 Accepts]: Start accepts. Automaton has 21688 states and 24571 transitions. Word has length 374 [2018-11-23 14:22:25,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:22:25,497 INFO L480 AbstractCegarLoop]: Abstraction has 21688 states and 24571 transitions. [2018-11-23 14:22:25,498 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:22:25,498 INFO L276 IsEmpty]: Start isEmpty. Operand 21688 states and 24571 transitions. [2018-11-23 14:22:25,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 376 [2018-11-23 14:22:25,515 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:22:25,515 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:22:25,515 INFO L423 AbstractCegarLoop]: === Iteration 43 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:22:25,515 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:25,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1085876353, now seen corresponding path program 1 times [2018-11-23 14:22:25,516 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:22:25,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:25,516 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:25,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:25,517 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:22:25,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:25,645 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 37 proven. 7 refuted. 0 times theorem prover too weak. 327 trivial. 0 not checked. [2018-11-23 14:22:25,645 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:25,645 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:22:25,645 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 376 with the following transitions: [2018-11-23 14:22:25,646 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [555], [559], [562], [565], [572], [575], [578], [585], [588], [594], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-11-23 14:22:25,647 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:22:25,647 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:22:26,252 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:22:26,252 INFO L272 AbstractInterpreter]: Visited 186 different actions 1251 times. Merged at 66 different actions 248 times. Widened at 1 different actions 1 times. Performed 12127 root evaluator evaluations with a maximum evaluation depth of 3. Performed 12127 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 65 fixpoints after 20 different actions. Largest state had 60 variables. [2018-11-23 14:22:26,260 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:26,261 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:22:26,261 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:26,261 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:22:26,277 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:26,277 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:22:26,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:26,431 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:22:26,549 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 203 proven. 0 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-11-23 14:22:26,550 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:22:26,837 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 37 proven. 7 refuted. 0 times theorem prover too weak. 327 trivial. 0 not checked. [2018-11-23 14:22:26,856 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:22:26,856 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-11-23 14:22:26,856 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:22:26,857 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:22:26,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:22:26,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:22:26,857 INFO L87 Difference]: Start difference. First operand 21688 states and 24571 transitions. Second operand 4 states. [2018-11-23 14:22:28,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:22:28,441 INFO L93 Difference]: Finished difference Result 30855 states and 34920 transitions. [2018-11-23 14:22:28,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 14:22:28,442 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 375 [2018-11-23 14:22:28,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:22:28,461 INFO L225 Difference]: With dead ends: 30855 [2018-11-23 14:22:28,461 INFO L226 Difference]: Without dead ends: 6047 [2018-11-23 14:22:28,493 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 756 GetRequests, 749 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:22:28,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6047 states. [2018-11-23 14:22:29,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6047 to 5946. [2018-11-23 14:22:29,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5946 states. [2018-11-23 14:22:29,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5946 states to 5946 states and 6564 transitions. [2018-11-23 14:22:29,016 INFO L78 Accepts]: Start accepts. Automaton has 5946 states and 6564 transitions. Word has length 375 [2018-11-23 14:22:29,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:22:29,017 INFO L480 AbstractCegarLoop]: Abstraction has 5946 states and 6564 transitions. [2018-11-23 14:22:29,017 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:22:29,017 INFO L276 IsEmpty]: Start isEmpty. Operand 5946 states and 6564 transitions. [2018-11-23 14:22:29,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 584 [2018-11-23 14:22:29,024 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:22:29,024 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:22:29,024 INFO L423 AbstractCegarLoop]: === Iteration 44 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:22:29,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:29,025 INFO L82 PathProgramCache]: Analyzing trace with hash 1800881173, now seen corresponding path program 1 times [2018-11-23 14:22:29,025 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:22:29,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:29,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:29,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:29,025 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:22:29,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:29,145 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 67 proven. 50 refuted. 0 times theorem prover too weak. 881 trivial. 0 not checked. [2018-11-23 14:22:29,145 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:29,145 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 14:22:29,146 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 584 with the following transitions: [2018-11-23 14:22:29,146 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [207], [212], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [304], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [345], [348], [350], [355], [360], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [542], [546], [549], [555], [559], [562], [565], [568], [572], [575], [578], [581], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-11-23 14:22:29,148 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 14:22:29,148 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 14:22:30,641 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 14:22:30,642 INFO L272 AbstractInterpreter]: Visited 240 different actions 4829 times. Merged at 91 different actions 1047 times. Widened at 1 different actions 2 times. Performed 47332 root evaluator evaluations with a maximum evaluation depth of 3. Performed 47332 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 308 fixpoints after 32 different actions. Largest state had 60 variables. [2018-11-23 14:22:30,654 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:30,654 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 14:22:30,654 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:22:30,654 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:22:30,662 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:30,662 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 14:22:30,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:22:30,781 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:22:30,865 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 564 proven. 0 refuted. 0 times theorem prover too weak. 434 trivial. 0 not checked. [2018-11-23 14:22:30,865 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 14:22:31,134 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 67 proven. 50 refuted. 0 times theorem prover too weak. 881 trivial. 0 not checked. [2018-11-23 14:22:31,150 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:22:31,150 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 3 [2018-11-23 14:22:31,150 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 14:22:31,150 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:22:31,150 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:22:31,150 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:22:31,151 INFO L87 Difference]: Start difference. First operand 5946 states and 6564 transitions. Second operand 3 states. [2018-11-23 14:22:31,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:22:31,566 INFO L93 Difference]: Finished difference Result 9553 states and 10528 transitions. [2018-11-23 14:22:31,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:22:31,567 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 583 [2018-11-23 14:22:31,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:22:31,575 INFO L225 Difference]: With dead ends: 9553 [2018-11-23 14:22:31,576 INFO L226 Difference]: Without dead ends: 4778 [2018-11-23 14:22:31,581 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1168 GetRequests, 1165 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:22:31,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4778 states. [2018-11-23 14:22:32,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4778 to 4769. [2018-11-23 14:22:32,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4769 states. [2018-11-23 14:22:32,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4769 states to 4769 states and 5178 transitions. [2018-11-23 14:22:32,219 INFO L78 Accepts]: Start accepts. Automaton has 4769 states and 5178 transitions. Word has length 583 [2018-11-23 14:22:32,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:22:32,220 INFO L480 AbstractCegarLoop]: Abstraction has 4769 states and 5178 transitions. [2018-11-23 14:22:32,220 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:22:32,220 INFO L276 IsEmpty]: Start isEmpty. Operand 4769 states and 5178 transitions. [2018-11-23 14:22:32,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 443 [2018-11-23 14:22:32,225 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:22:32,225 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:22:32,226 INFO L423 AbstractCegarLoop]: === Iteration 45 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 14:22:32,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:22:32,226 INFO L82 PathProgramCache]: Analyzing trace with hash 613832725, now seen corresponding path program 1 times [2018-11-23 14:22:32,226 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 14:22:32,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:32,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:22:32,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:22:32,227 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 14:22:32,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:22:32,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 14:22:32,454 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); VAL [|old(~E_1~0)|=21, |old(~E_2~0)|=5, |old(~E_3~0)|=25, |old(~E_4~0)|=11, |old(~M_E~0)|=17, |old(~m_i~0)|=7, |old(~m_pc~0)|=15, |old(~m_st~0)|=16, |old(~T1_E~0)|=3, |old(~t1_i~0)|=19, |old(~t1_pc~0)|=9, |old(~t1_st~0)|=4, |old(~T2_E~0)|=18, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=10, |old(~t2_st~0)|=13, |old(~T3_E~0)|=23, |old(~t3_i~0)|=24, |old(~t3_pc~0)|=8, |old(~t3_st~0)|=14, |old(~T4_E~0)|=26, |old(~t4_i~0)|=20, |old(~t4_pc~0)|=22, |old(~t4_st~0)|=12, ~E_1~0=21, ~E_2~0=5, ~E_3~0=25, ~E_4~0=11, ~M_E~0=17, ~m_i~0=7, ~m_pc~0=15, ~m_st~0=16, ~T1_E~0=3, ~t1_i~0=19, ~t1_pc~0=9, ~t1_st~0=4, ~T2_E~0=18, ~t2_i~0=6, ~t2_pc~0=10, ~t2_st~0=13, ~T3_E~0=23, ~t3_i~0=24, ~t3_pc~0=8, ~t3_st~0=14, ~T4_E~0=26, ~t4_i~0=20, ~t4_pc~0=22, ~t4_st~0=12] [?] ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; VAL [|old(~E_1~0)|=21, |old(~E_2~0)|=5, |old(~E_3~0)|=25, |old(~E_4~0)|=11, |old(~M_E~0)|=17, |old(~m_i~0)|=7, |old(~m_pc~0)|=15, |old(~m_st~0)|=16, |old(~T1_E~0)|=3, |old(~t1_i~0)|=19, |old(~t1_pc~0)|=9, |old(~t1_st~0)|=4, |old(~T2_E~0)|=18, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=10, |old(~t2_st~0)|=13, |old(~T3_E~0)|=23, |old(~t3_i~0)|=24, |old(~t3_pc~0)|=8, |old(~t3_st~0)|=14, |old(~T4_E~0)|=26, |old(~t4_i~0)|=20, |old(~t4_pc~0)|=22, |old(~t4_st~0)|=12, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=21, |old(~E_2~0)|=5, |old(~E_3~0)|=25, |old(~E_4~0)|=11, |old(~M_E~0)|=17, |old(~m_i~0)|=7, |old(~m_pc~0)|=15, |old(~m_st~0)|=16, |old(~T1_E~0)|=3, |old(~t1_i~0)|=19, |old(~t1_pc~0)|=9, |old(~t1_st~0)|=4, |old(~T2_E~0)|=18, |old(~t2_i~0)|=6, |old(~t2_pc~0)|=10, |old(~t2_st~0)|=13, |old(~T3_E~0)|=23, |old(~t3_i~0)|=24, |old(~t3_pc~0)|=8, |old(~t3_st~0)|=14, |old(~T4_E~0)|=26, |old(~t4_i~0)|=20, |old(~t4_pc~0)|=22, |old(~t4_st~0)|=12, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #739#return; VAL [~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret14 := main(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~__retres1~6; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call init_model(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] ~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #677#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call start_simulation(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~kernel_st~0;havoc ~tmp~3;havoc ~tmp___0~1;~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call update_channels(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #709#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call init_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 1 == ~m_i~0;~m_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 1 == ~t1_i~0;~t1_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 1 == ~t2_i~0;~t2_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 1 == ~t3_i~0;~t3_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 1 == ~t4_i~0;~t4_st~0 := 0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #711#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call fire_delta_events(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~T1_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~T2_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~T3_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~T4_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #713#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret6 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~m_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #683#return; VAL [|activate_threads_#t~ret6|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647;~tmp~1 := #t~ret6;havoc #t~ret6; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret7 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~t1_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #685#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp___0~0 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret8 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~t2_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #687#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___1~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret9 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~t3_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #689#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___2~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret10 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~t4_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #691#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___3~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #715#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call reset_delta_events(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~T1_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~T2_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~T3_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~T4_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #717#return; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !false; VAL [start_simulation_~kernel_st~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~kernel_st~0 := 1; VAL [start_simulation_~kernel_st~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call eval(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~tmp~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret0 := exists_runnable_thread(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~m_st~0;~__retres1~5 := 1; VAL [exists_runnable_thread_~__retres1~5=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] #res := ~__retres1~5; VAL [exists_runnable_thread_~__retres1~5=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [exists_runnable_thread_~__retres1~5=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #697#return; VAL [|eval_#t~ret0|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647;~tmp~0 := #t~ret0;havoc #t~ret0; VAL [eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 != ~tmp~0; VAL [eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~m_st~0;havoc ~tmp_ndt_1~0;assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647;~tmp_ndt_1~0 := #t~nondet1;havoc #t~nondet1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 != ~tmp_ndt_1~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~t1_st~0;havoc ~tmp_ndt_2~0;assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647;~tmp_ndt_2~0 := #t~nondet2;havoc #t~nondet2; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 != ~tmp_ndt_2~0;~t1_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call transmit1(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~t1_pc~0 := 1;~t1_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #701#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~t2_st~0;havoc ~tmp_ndt_3~0;assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647;~tmp_ndt_3~0 := #t~nondet3;havoc #t~nondet3; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 != ~tmp_ndt_3~0;~t2_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call transmit2(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] ~t2_pc~0 := 1;~t2_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] RET #703#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~t3_st~0;havoc ~tmp_ndt_4~0;assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647;~tmp_ndt_4~0 := #t~nondet4;havoc #t~nondet4; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume !(0 != ~tmp_ndt_4~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 == ~t4_st~0;havoc ~tmp_ndt_5~0;assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647;~tmp_ndt_5~0 := #t~nondet5;havoc #t~nondet5; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [?] assume 0 != ~tmp_ndt_5~0;~t4_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [?] CALL call transmit4(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [?] assume 0 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [?] ~t4_pc~0 := 1;~t4_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #707#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !false; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret0 := exists_runnable_thread(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~m_st~0;~__retres1~5 := 1; VAL [exists_runnable_thread_~__retres1~5=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~5; VAL [exists_runnable_thread_~__retres1~5=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [exists_runnable_thread_~__retres1~5=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #697#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |eval_#t~ret0|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647;~tmp~0 := #t~ret0;havoc #t~ret0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp~0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~m_st~0;havoc ~tmp_ndt_1~0;assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647;~tmp_ndt_1~0 := #t~nondet1;havoc #t~nondet1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp_ndt_1~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 == ~t1_st~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 == ~t2_st~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=0, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~t3_st~0;havoc ~tmp_ndt_4~0;assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647;~tmp_ndt_4~0 := #t~nondet4;havoc #t~nondet4; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp_ndt_4~0;~t3_st~0 := 1; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call transmit3(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~t3_pc~0 := 1;~t3_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #705#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 == ~t4_st~0); VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !false; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret0 := exists_runnable_thread(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~5; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~m_st~0;~__retres1~5 := 1; VAL [exists_runnable_thread_~__retres1~5=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~5; VAL [exists_runnable_thread_~__retres1~5=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [exists_runnable_thread_~__retres1~5=1, |exists_runnable_thread_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #697#return; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |eval_#t~ret0|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647;~tmp~0 := #t~ret0;havoc #t~ret0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp~0; VAL [eval_~tmp_ndt_1~0=0, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~m_st~0;havoc ~tmp_ndt_1~0;assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647;~tmp_ndt_1~0 := #t~nondet1;havoc #t~nondet1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp_ndt_1~0;~m_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call master(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~E_1~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret6 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~m_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #683#return; VAL [|activate_threads_#t~ret6|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647;~tmp~1 := #t~ret6;havoc #t~ret6; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret7 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~E_1~0;~__retres1~1 := 1; VAL [is_transmit1_triggered_~__retres1~1=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=1, |is_transmit1_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=1, |is_transmit1_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #685#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret7|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp___0~0 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp___0~0;~t1_st~0 := 0; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret8 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #687#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___1~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret9 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #689#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___2~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret10 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #691#return; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___3~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=1, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #693#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #695#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~E_1~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~m_pc~0 := 1;~m_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=1, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #699#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~t1_st~0;havoc ~tmp_ndt_2~0;assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647;~tmp_ndt_2~0 := #t~nondet2;havoc #t~nondet2; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp_ndt_2~0;~t1_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call transmit1(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 == ~t1_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~E_2~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret6 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #683#return; VAL [|activate_threads_#t~ret6|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647;~tmp~1 := #t~ret6;havoc #t~ret6; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret7 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #685#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp___0~0 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret8 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~E_2~0;~__retres1~2 := 1; VAL [is_transmit2_triggered_~__retres1~2=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=1, |is_transmit2_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=1, |is_transmit2_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #687#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___1~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp___1~0;~t2_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret9 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #689#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___2~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret10 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #691#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___3~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=1, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #693#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #669#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~E_2~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~t1_pc~0 := 1;~t1_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=1, |old(~t1_st~0)|=1, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #701#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~t2_st~0;havoc ~tmp_ndt_3~0;assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647;~tmp_ndt_3~0 := #t~nondet3;havoc #t~nondet3; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp_ndt_3~0;~t2_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call transmit2(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 == ~t2_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~E_3~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret6 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #683#return; VAL [|activate_threads_#t~ret6|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647;~tmp~1 := #t~ret6;havoc #t~ret6; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret7 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #685#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp___0~0 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret8 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #687#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___1~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret9 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~E_3~0;~__retres1~3 := 1; VAL [is_transmit3_triggered_~__retres1~3=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=1, |is_transmit3_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=1, |is_transmit3_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #689#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___2~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp___2~0;~t3_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret10 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_4~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~4 := 0; VAL [is_transmit4_triggered_~__retres1~4=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=0, |is_transmit4_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #691#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___3~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___3~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=1, activate_threads_~tmp___3~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #693#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #673#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~E_3~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~t2_pc~0 := 1;~t2_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=1, |old(~t2_st~0)|=1, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=2, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #703#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 == ~t3_st~0;havoc ~tmp_ndt_4~0;assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647;~tmp_ndt_4~0 := #t~nondet4;havoc #t~nondet4; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp_ndt_4~0;~t3_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call transmit3(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 == ~t3_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~E_4~0 := 1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call immediate_notify(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call activate_threads(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~0;havoc ~tmp___1~0;havoc ~tmp___2~0;havoc ~tmp___3~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret6 := is_master_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~m_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~M_E~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~0 := 0; VAL [is_master_triggered_~__retres1~0=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~0; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_master_triggered_~__retres1~0=0, |is_master_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #683#return; VAL [|activate_threads_#t~ret6|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647;~tmp~1 := #t~ret6;havoc #t~ret6; VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp~1); VAL [activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret7 := is_transmit1_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~1; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t1_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_1~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~1 := 0; VAL [is_transmit1_triggered_~__retres1~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~1; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit1_triggered_~__retres1~1=0, |is_transmit1_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #685#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret7|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647;~tmp___0~0 := #t~ret7;havoc #t~ret7; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___0~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret8 := is_transmit2_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t2_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_2~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~2 := 0; VAL [is_transmit2_triggered_~__retres1~2=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~2; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit2_triggered_~__retres1~2=0, |is_transmit2_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #687#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret8|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647;~tmp___1~0 := #t~ret8;havoc #t~ret8; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___1~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret9 := is_transmit3_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~3; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t3_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(1 == ~E_3~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] ~__retres1~3 := 0; VAL [is_transmit3_triggered_~__retres1~3=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~3; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit3_triggered_~__retres1~3=0, |is_transmit3_triggered_#res|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #689#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret9|=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647;~tmp___2~0 := #t~ret9;havoc #t~ret9; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume !(0 != ~tmp___2~0); VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] CALL call #t~ret10 := is_transmit4_triggered(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] havoc ~__retres1~4; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 1 == ~E_4~0;~__retres1~4 := 1; VAL [is_transmit4_triggered_~__retres1~4=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] #res := ~__retres1~4; VAL [is_transmit4_triggered_~__retres1~4=1, |is_transmit4_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume true; VAL [is_transmit4_triggered_~__retres1~4=1, |is_transmit4_triggered_#res|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] RET #691#return; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp~1=0, |activate_threads_#t~ret10|=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647;~tmp___3~0 := #t~ret10;havoc #t~ret10; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [?] assume 0 != ~tmp___3~0;~t4_st~0 := 0; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] assume true; VAL [activate_threads_~tmp___0~0=0, activate_threads_~tmp___1~0=0, activate_threads_~tmp___2~0=0, activate_threads_~tmp___3~0=1, activate_threads_~tmp~1=0, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] RET #693#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] RET #671#return; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] ~E_4~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] ~t3_pc~0 := 1;~t3_st~0 := 2; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] assume true; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=2, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=2, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=2, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=1, |old(~t3_st~0)|=1, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] RET #705#return; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] assume 0 == ~t4_st~0;havoc ~tmp_ndt_5~0;assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647;~tmp_ndt_5~0 := #t~nondet5;havoc #t~nondet5; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [?] assume 0 != ~tmp_ndt_5~0;~t4_st~0 := 1; VAL [eval_~tmp_ndt_1~0=1, eval_~tmp_ndt_2~0=1, eval_~tmp_ndt_3~0=1, eval_~tmp_ndt_4~0=1, eval_~tmp_ndt_5~0=1, eval_~tmp~0=1, |old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=0, |old(~t4_st~0)|=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [?] CALL call transmit4(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [?] assume !(0 == ~t4_pc~0); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [?] assume 1 == ~t4_pc~0; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [?] CALL call error(); VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [?] assume !false; VAL [|old(~E_1~0)|=2, |old(~E_2~0)|=2, |old(~E_3~0)|=2, |old(~E_4~0)|=2, |old(~M_E~0)|=2, |old(~m_i~0)|=0, |old(~m_pc~0)|=0, |old(~m_st~0)|=0, |old(~T1_E~0)|=2, |old(~t1_i~0)|=0, |old(~t1_pc~0)|=0, |old(~t1_st~0)|=0, |old(~T2_E~0)|=2, |old(~t2_i~0)|=0, |old(~t2_pc~0)|=0, |old(~t2_st~0)|=0, |old(~T3_E~0)|=2, |old(~t3_i~0)|=0, |old(~t3_pc~0)|=0, |old(~t3_st~0)|=0, |old(~T4_E~0)|=2, |old(~t4_i~0)|=0, |old(~t4_pc~0)|=1, |old(~t4_st~0)|=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [?] CALL call ULTIMATE.init(); VAL [old(~E_1~0)=21, old(~E_2~0)=5, old(~E_3~0)=25, old(~E_4~0)=11, old(~M_E~0)=17, old(~m_i~0)=7, old(~m_pc~0)=15, old(~m_st~0)=16, old(~T1_E~0)=3, old(~t1_i~0)=19, old(~t1_pc~0)=9, old(~t1_st~0)=4, old(~T2_E~0)=18, old(~t2_i~0)=6, old(~t2_pc~0)=10, old(~t2_st~0)=13, old(~T3_E~0)=23, old(~t3_i~0)=24, old(~t3_pc~0)=8, old(~t3_st~0)=14, old(~T4_E~0)=26, old(~t4_i~0)=20, old(~t4_pc~0)=22, old(~t4_st~0)=12, ~E_1~0=21, ~E_2~0=5, ~E_3~0=25, ~E_4~0=11, ~M_E~0=17, ~m_i~0=7, ~m_pc~0=15, ~m_st~0=16, ~T1_E~0=3, ~t1_i~0=19, ~t1_pc~0=9, ~t1_st~0=4, ~T2_E~0=18, ~t2_i~0=6, ~t2_pc~0=10, ~t2_st~0=13, ~T3_E~0=23, ~t3_i~0=24, ~t3_pc~0=8, ~t3_st~0=14, ~T4_E~0=26, ~t4_i~0=20, ~t4_pc~0=22, ~t4_st~0=12] [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; VAL [old(~E_1~0)=21, old(~E_2~0)=5, old(~E_3~0)=25, old(~E_4~0)=11, old(~M_E~0)=17, old(~m_i~0)=7, old(~m_pc~0)=15, old(~m_st~0)=16, old(~T1_E~0)=3, old(~t1_i~0)=19, old(~t1_pc~0)=9, old(~t1_st~0)=4, old(~T2_E~0)=18, old(~t2_i~0)=6, old(~t2_pc~0)=10, old(~t2_st~0)=13, old(~T3_E~0)=23, old(~t3_i~0)=24, old(~t3_pc~0)=8, old(~t3_st~0)=14, old(~T4_E~0)=26, old(~t4_i~0)=20, old(~t4_pc~0)=22, old(~t4_st~0)=12, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] ensures true; VAL [old(~E_1~0)=21, old(~E_2~0)=5, old(~E_3~0)=25, old(~E_4~0)=11, old(~M_E~0)=17, old(~m_i~0)=7, old(~m_pc~0)=15, old(~m_st~0)=16, old(~T1_E~0)=3, old(~t1_i~0)=19, old(~t1_pc~0)=9, old(~t1_st~0)=4, old(~T2_E~0)=18, old(~t2_i~0)=6, old(~t2_pc~0)=10, old(~t2_st~0)=13, old(~T3_E~0)=23, old(~t3_i~0)=24, old(~t3_pc~0)=8, old(~t3_st~0)=14, old(~T4_E~0)=26, old(~t4_i~0)=20, old(~t4_pc~0)=22, old(~t4_st~0)=12, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] RET call ULTIMATE.init(); VAL [~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret14 := main(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [L811] havoc ~__retres1~6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [L815] CALL call init_model(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L719-L731] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L815] RET call init_model(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L816] CALL call start_simulation(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L759] CALL call update_channels(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L319-L326] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L759] RET call update_channels(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L760] CALL call init_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L331-L335] assume 1 == ~m_i~0; [L332] ~m_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L336-L340] assume 1 == ~t1_i~0; [L337] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L341-L345] assume 1 == ~t2_i~0; [L342] ~t2_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L346-L350] assume 1 == ~t3_i~0; [L347] ~t3_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L351-L355] assume 1 == ~t4_i~0; [L352] ~t4_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L327-L359] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L760] RET call init_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L761] CALL call fire_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L492-L496] assume !(0 == ~M_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L497-L501] assume !(0 == ~T1_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L502-L506] assume !(0 == ~T2_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L507-L511] assume !(0 == ~T3_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L512-L516] assume !(0 == ~T4_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L517-L521] assume !(0 == ~E_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L522-L526] assume !(0 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L527-L531] assume !(0 == ~E_3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L532-L536] assume !(0 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L488-L540] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L761] RET call fire_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L762] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L228-L237] assume !(1 == ~m_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L39] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~1=0] [L605-L609] assume !(0 != ~tmp~1); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L247-L256] assume !(1 == ~t1_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L40] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] assume !(0 != ~tmp___0~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L266-L275] assume !(1 == ~t2_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L41] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] assume !(0 != ~tmp___1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L285-L294] assume !(1 == ~t3_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L42] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] assume !(0 != ~tmp___2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L304-L313] assume !(1 == ~t4_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L43] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] assume !(0 != ~tmp___3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L594-L645] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L762] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L763] CALL call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L545-L549] assume !(1 == ~M_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L550-L554] assume !(1 == ~T1_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L555-L559] assume !(1 == ~T2_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L560-L564] assume !(1 == ~T3_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L565-L569] assume !(1 == ~T4_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L570-L574] assume !(1 == ~E_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L575-L579] assume !(1 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L580-L584] assume !(1 == ~E_3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L585-L589] assume !(1 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L541-L593] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L763] RET call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L766-L803] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L769] ~kernel_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L770] CALL call eval(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L397] havoc ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L401-L481] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L364-L389] assume 0 == ~m_st~0; [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L360-L394] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~0=1] [L406-L410] assume 0 != ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~0=1] [L411-L424] assume 0 == ~m_st~0; [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L414-L421] assume !(0 != ~tmp_ndt_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L425-L438] assume 0 == ~t1_st~0; [L426] havoc ~tmp_ndt_2~0; [L427] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L428-L435] assume 0 != ~tmp_ndt_2~0; [L430] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L431] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L90-L98] assume 0 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L101-L113] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L103] ~t1_pc~0 := 1; [L104] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L86-L120] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L431] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L439-L452] assume 0 == ~t2_st~0; [L440] havoc ~tmp_ndt_3~0; [L441] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L442-L449] assume 0 != ~tmp_ndt_3~0; [L444] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L445] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L125-L133] assume 0 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L136-L148] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L138] ~t2_pc~0 := 1; [L139] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L121-L155] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L445] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L453-L466] assume 0 == ~t3_st~0; [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp~0=1] [L456-L463] assume !(0 != ~tmp_ndt_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp~0=1] [L467-L480] assume 0 == ~t4_st~0; [L468] havoc ~tmp_ndt_5~0; [L469] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L470-L477] assume 0 != ~tmp_ndt_5~0; [L472] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L473] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L195-L203] assume 0 == ~t4_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L206-L216] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L208] ~t4_pc~0 := 1; [L209] ~t4_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L191-L223] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L473] RET call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L401-L481] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L364-L389] assume 0 == ~m_st~0; [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L360-L394] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L406-L410] assume 0 != ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L411-L424] assume 0 == ~m_st~0; [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L414-L421] assume !(0 != ~tmp_ndt_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L425-L438] assume !(0 == ~t1_st~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L439-L452] assume !(0 == ~t2_st~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L453-L466] assume 0 == ~t3_st~0; [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L456-L463] assume 0 != ~tmp_ndt_4~0; [L458] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L459] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L160-L168] assume 0 == ~t3_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L171-L183] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L173] ~t3_pc~0 := 1; [L174] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L156-L190] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L459] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L467-L480] assume !(0 == ~t4_st~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L401-L481] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L364-L389] assume 0 == ~m_st~0; [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L360-L394] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L406-L410] assume 0 != ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L411-L424] assume 0 == ~m_st~0; [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L414-L421] assume 0 != ~tmp_ndt_1~0; [L416] ~m_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L417] CALL call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L49-L57] assume 0 == ~m_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L60-L78] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L63] ~E_1~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L64] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228-L237] assume !(1 == ~m_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L39] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] assume !(0 != ~tmp~1); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247-L256] assume 1 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248-L253] assume 1 == ~E_1~0; [L249] ~__retres1~1 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L40] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L613-L617] assume 0 != ~tmp___0~0; [L614] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266-L275] assume 1 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267-L272] assume !(1 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L41] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] assume !(0 != ~tmp___1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285-L294] assume 1 == ~t3_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286-L291] assume !(1 == ~E_3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L42] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] assume !(0 != ~tmp___2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304-L313] assume 1 == ~t4_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305-L310] assume !(1 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L43] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] assume !(0 != ~tmp___3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L594-L645] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L44] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L64] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L65] ~E_1~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L68-L75] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L70] ~m_pc~0 := 1; [L71] ~m_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L45-L85] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L417] RET call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L425-L438] assume 0 == ~t1_st~0; [L426] havoc ~tmp_ndt_2~0; [L427] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L428-L435] assume 0 != ~tmp_ndt_2~0; [L430] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L431] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L90-L98] assume !(0 == ~t1_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L93-L97] assume 1 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L109] ~E_2~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L110] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228-L237] assume 1 == ~m_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229-L234] assume !(1 == ~M_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L39] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] assume !(0 != ~tmp~1); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247-L256] assume 1 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248-L253] assume !(1 == ~E_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L40] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] assume !(0 != ~tmp___0~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266-L275] assume 1 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267-L272] assume 1 == ~E_2~0; [L268] ~__retres1~2 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L41] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L621-L625] assume 0 != ~tmp___1~0; [L622] ~t2_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285-L294] assume 1 == ~t3_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286-L291] assume !(1 == ~E_3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L42] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] assume !(0 != ~tmp___2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304-L313] assume 1 == ~t4_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305-L310] assume !(1 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L43] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] assume !(0 != ~tmp___3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L594-L645] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L44] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L110] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L111] ~E_2~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L101-L113] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L103] ~t1_pc~0 := 1; [L104] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L86-L120] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L431] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L439-L452] assume 0 == ~t2_st~0; [L440] havoc ~tmp_ndt_3~0; [L441] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L442-L449] assume 0 != ~tmp_ndt_3~0; [L444] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L445] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L125-L133] assume !(0 == ~t2_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L128-L132] assume 1 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L144] ~E_3~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L145] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228-L237] assume 1 == ~m_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229-L234] assume !(1 == ~M_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L39] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] assume !(0 != ~tmp~1); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247-L256] assume 1 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248-L253] assume !(1 == ~E_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L40] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] assume !(0 != ~tmp___0~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266-L275] assume 1 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267-L272] assume !(1 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L41] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] assume !(0 != ~tmp___1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285-L294] assume 1 == ~t3_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286-L291] assume 1 == ~E_3~0; [L287] ~__retres1~3 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L42] ensures true; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L629-L633] assume 0 != ~tmp___2~0; [L630] ~t3_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304-L313] assume 1 == ~t4_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305-L310] assume !(1 == ~E_4~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L43] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] assume !(0 != ~tmp___3~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L594-L645] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L44] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L145] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L146] ~E_3~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L136-L148] assume !false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L138] ~t2_pc~0 := 1; [L139] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L121-L155] ensures true; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L445] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L453-L466] assume 0 == ~t3_st~0; [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L456-L463] assume 0 != ~tmp_ndt_4~0; [L458] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L459] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L160-L168] assume !(0 == ~t3_pc~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L163-L167] assume 1 == ~t3_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L179] ~E_4~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L180] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228-L237] assume 1 == ~m_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229-L234] assume !(1 == ~M_E~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L39] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] assume !(0 != ~tmp~1); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247-L256] assume 1 == ~t1_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248-L253] assume !(1 == ~E_1~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L40] ensures true; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] assume !(0 != ~tmp___0~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266-L275] assume 1 == ~t2_pc~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267-L272] assume !(1 == ~E_2~0); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L266] COND FALSE !(1 == ~t2_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L285] COND FALSE !(1 == ~t3_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L304] COND FALSE !(1 == ~t4_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L762] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L763] CALL call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L545] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L550] COND FALSE !(1 == ~T1_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L555] COND FALSE !(1 == ~T2_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L560] COND FALSE !(1 == ~T3_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L565] COND FALSE !(1 == ~T4_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L570] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L575] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L580] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L585] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L763] RET call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L766-L803] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L769] ~kernel_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L770] CALL call eval(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L397] havoc ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L401-L481] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~0=1] [L406-L410] COND TRUE 0 != ~tmp~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~0=1] [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L428-L435] COND TRUE 0 != ~tmp_ndt_2~0 [L430] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L431] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L90] COND TRUE 0 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L101-L113] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L103] ~t1_pc~0 := 1; [L104] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L431] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L442-L449] COND TRUE 0 != ~tmp_ndt_3~0 [L444] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L445] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L125] COND TRUE 0 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L136-L148] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L138] ~t2_pc~0 := 1; [L139] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L445] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp~0=1] [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp~0=1] [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L470-L477] COND TRUE 0 != ~tmp_ndt_5~0 [L472] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L473] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L195] COND TRUE 0 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L206-L216] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L208] ~t4_pc~0 := 1; [L209] ~t4_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L473] RET call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L401-L481] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L406-L410] COND TRUE 0 != ~tmp~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L425] COND FALSE !(0 == ~t1_st~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L439] COND FALSE !(0 == ~t2_st~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L456-L463] COND TRUE 0 != ~tmp_ndt_4~0 [L458] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L459] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L160] COND TRUE 0 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L171-L183] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L173] ~t3_pc~0 := 1; [L174] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L459] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L467] COND FALSE !(0 == ~t4_st~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L401-L481] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L406-L410] COND TRUE 0 != ~tmp~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L414-L421] COND TRUE 0 != ~tmp_ndt_1~0 [L416] ~m_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L417] CALL call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L49] COND TRUE 0 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L60-L78] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L63] ~E_1~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L64] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND FALSE !(1 == ~m_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND TRUE 1 == ~E_1~0 [L249] ~__retres1~1 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L613-L617] COND TRUE 0 != ~tmp___0~0 [L614] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L64] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L65] ~E_1~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L68-L75] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L70] ~m_pc~0 := 1; [L71] ~m_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L417] RET call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L428-L435] COND TRUE 0 != ~tmp_ndt_2~0 [L430] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L431] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L90] COND FALSE !(0 == ~t1_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L93] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L109] ~E_2~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L110] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND TRUE 1 == ~E_2~0 [L268] ~__retres1~2 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L621-L625] COND TRUE 0 != ~tmp___1~0 [L622] ~t2_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L110] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L111] ~E_2~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L101-L113] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L103] ~t1_pc~0 := 1; [L104] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L431] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L442-L449] COND TRUE 0 != ~tmp_ndt_3~0 [L444] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L445] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L125] COND FALSE !(0 == ~t2_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L128] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L144] ~E_3~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L145] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND TRUE 1 == ~E_3~0 [L287] ~__retres1~3 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L629-L633] COND TRUE 0 != ~tmp___2~0 [L630] ~t3_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L145] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L146] ~E_3~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L136-L148] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L138] ~t2_pc~0 := 1; [L139] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L445] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L456-L463] COND TRUE 0 != ~tmp_ndt_4~0 [L458] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L459] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L160] COND FALSE !(0 == ~t3_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L163] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L179] ~E_4~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L180] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND TRUE 1 == ~E_4~0 [L306] ~__retres1~4 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp~1=0] [L637-L641] COND TRUE 0 != ~tmp___3~0 [L638] ~t4_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L180] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L181] ~E_4~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L171-L183] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L173] ~t3_pc~0 := 1; [L174] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L459] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L470-L477] COND TRUE 0 != ~tmp_ndt_5~0 [L472] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L473] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L195] COND FALSE !(0 == ~t4_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L198] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L214] CALL call error(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L11] assert false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); VAL [old(~E_1~0)=21, old(~E_2~0)=5, old(~E_3~0)=25, old(~E_4~0)=11, old(~M_E~0)=17, old(~m_i~0)=7, old(~m_pc~0)=15, old(~m_st~0)=16, old(~T1_E~0)=3, old(~t1_i~0)=19, old(~t1_pc~0)=9, old(~t1_st~0)=4, old(~T2_E~0)=18, old(~t2_i~0)=6, old(~t2_pc~0)=10, old(~t2_st~0)=13, old(~T3_E~0)=23, old(~t3_i~0)=24, old(~t3_pc~0)=8, old(~t3_st~0)=14, old(~T4_E~0)=26, old(~t4_i~0)=20, old(~t4_pc~0)=22, old(~t4_st~0)=12, ~E_1~0=21, ~E_2~0=5, ~E_3~0=25, ~E_4~0=11, ~M_E~0=17, ~m_i~0=7, ~m_pc~0=15, ~m_st~0=16, ~T1_E~0=3, ~t1_i~0=19, ~t1_pc~0=9, ~t1_st~0=4, ~T2_E~0=18, ~t2_i~0=6, ~t2_pc~0=10, ~t2_st~0=13, ~T3_E~0=23, ~t3_i~0=24, ~t3_pc~0=8, ~t3_st~0=14, ~T4_E~0=26, ~t4_i~0=20, ~t4_pc~0=22, ~t4_st~0=12] [L15] ~m_pc~0 := 0; [L16] ~t1_pc~0 := 0; [L17] ~t2_pc~0 := 0; [L18] ~t3_pc~0 := 0; [L19] ~t4_pc~0 := 0; [L20] ~m_st~0 := 0; [L21] ~t1_st~0 := 0; [L22] ~t2_st~0 := 0; [L23] ~t3_st~0 := 0; [L24] ~t4_st~0 := 0; [L25] ~m_i~0 := 0; [L26] ~t1_i~0 := 0; [L27] ~t2_i~0 := 0; [L28] ~t3_i~0 := 0; [L29] ~t4_i~0 := 0; [L30] ~M_E~0 := 2; [L31] ~T1_E~0 := 2; [L32] ~T2_E~0 := 2; [L33] ~T3_E~0 := 2; [L34] ~T4_E~0 := 2; [L35] ~E_1~0 := 2; [L36] ~E_2~0 := 2; [L37] ~E_3~0 := 2; [L38] ~E_4~0 := 2; VAL [old(~E_1~0)=21, old(~E_2~0)=5, old(~E_3~0)=25, old(~E_4~0)=11, old(~M_E~0)=17, old(~m_i~0)=7, old(~m_pc~0)=15, old(~m_st~0)=16, old(~T1_E~0)=3, old(~t1_i~0)=19, old(~t1_pc~0)=9, old(~t1_st~0)=4, old(~T2_E~0)=18, old(~t2_i~0)=6, old(~t2_pc~0)=10, old(~t2_st~0)=13, old(~T3_E~0)=23, old(~t3_i~0)=24, old(~t3_pc~0)=8, old(~t3_st~0)=14, old(~T4_E~0)=26, old(~t4_i~0)=20, old(~t4_pc~0)=22, old(~t4_st~0)=12, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] RET call ULTIMATE.init(); VAL [~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [?] CALL call #t~ret14 := main(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [L811] havoc ~__retres1~6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [L815] CALL call init_model(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=0, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=0, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=0, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=0, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=0, ~t4_pc~0=0, ~t4_st~0=0] [L723] ~m_i~0 := 1; [L724] ~t1_i~0 := 1; [L725] ~t2_i~0 := 1; [L726] ~t3_i~0 := 1; [L727] ~t4_i~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L815] RET call init_model(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L816] CALL call start_simulation(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L752] havoc ~kernel_st~0; [L753] havoc ~tmp~3; [L754] havoc ~tmp___0~1; [L758] ~kernel_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L759] CALL call update_channels(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L759] RET call update_channels(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L760] CALL call init_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L331] COND TRUE 1 == ~m_i~0 [L332] ~m_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L336] COND TRUE 1 == ~t1_i~0 [L337] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L341] COND TRUE 1 == ~t2_i~0 [L342] ~t2_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L346] COND TRUE 1 == ~t3_i~0 [L347] ~t3_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L351] COND TRUE 1 == ~t4_i~0 [L352] ~t4_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L760] RET call init_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L761] CALL call fire_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L492] COND FALSE !(0 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L497] COND FALSE !(0 == ~T1_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L502] COND FALSE !(0 == ~T2_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L507] COND FALSE !(0 == ~T3_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L512] COND FALSE !(0 == ~T4_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L517] COND FALSE !(0 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L522] COND FALSE !(0 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L527] COND FALSE !(0 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L532] COND FALSE !(0 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L761] RET call fire_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L762] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L228] COND FALSE !(1 == ~m_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L247] COND FALSE !(1 == ~t1_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L266] COND FALSE !(1 == ~t2_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L285] COND FALSE !(1 == ~t3_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L304] COND FALSE !(1 == ~t4_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L762] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L763] CALL call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L545] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L550] COND FALSE !(1 == ~T1_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L555] COND FALSE !(1 == ~T2_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L560] COND FALSE !(1 == ~T3_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L565] COND FALSE !(1 == ~T4_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L570] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L575] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L580] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L585] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L763] RET call reset_delta_events(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L766-L803] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=0, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L769] ~kernel_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~kernel_st~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L770] CALL call eval(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L397] havoc ~tmp~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L401-L481] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~0=1] [L406-L410] COND TRUE 0 != ~tmp~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp~0=1] [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp~0=1] [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L428-L435] COND TRUE 0 != ~tmp_ndt_2~0 [L430] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L431] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L90] COND TRUE 0 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L101-L113] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=0, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L103] ~t1_pc~0 := 1; [L104] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L431] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp~0=1] [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L442-L449] COND TRUE 0 != ~tmp_ndt_3~0 [L444] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L445] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L125] COND TRUE 0 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L136-L148] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=0, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L138] ~t2_pc~0 := 1; [L139] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0] [L445] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp~0=1] [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp~0=1] [L456-L463] COND FALSE !(0 != ~tmp_ndt_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp~0=1] [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=0, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L470-L477] COND TRUE 0 != ~tmp_ndt_5~0 [L472] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L473] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L195] COND TRUE 0 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L206-L216] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=0, ~t4_st~0=1] [L208] ~t4_pc~0 := 1; [L209] ~t4_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L473] RET call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L401-L481] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L406-L410] COND TRUE 0 != ~tmp~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L414-L421] COND FALSE !(0 != ~tmp_ndt_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L425] COND FALSE !(0 == ~t1_st~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L439] COND FALSE !(0 == ~t2_st~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=0, ~tmp_ndt_5~0=1, ~tmp~0=1] [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L456-L463] COND TRUE 0 != ~tmp_ndt_4~0 [L458] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L459] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L160] COND TRUE 0 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L171-L183] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=0, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L173] ~t3_pc~0 := 1; [L174] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L459] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L467] COND FALSE !(0 == ~t4_st~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L401-L481] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] CALL call #t~ret0 := exists_runnable_thread(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L361] havoc ~__retres1~5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L364] COND TRUE 0 == ~m_st~0 [L365] ~__retres1~5 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L392] #res := ~__retres1~5; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~__retres1~5=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L404] RET call #t~ret0 := exists_runnable_thread(); VAL [#t~ret0=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L404] assume -2147483648 <= #t~ret0 && #t~ret0 <= 2147483647; [L404] ~tmp~0 := #t~ret0; [L404] havoc #t~ret0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L406-L410] COND TRUE 0 != ~tmp~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=0, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L411] COND TRUE 0 == ~m_st~0 [L412] havoc ~tmp_ndt_1~0; [L413] assume -2147483648 <= #t~nondet1 && #t~nondet1 <= 2147483647; [L413] ~tmp_ndt_1~0 := #t~nondet1; [L413] havoc #t~nondet1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=0, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L414-L421] COND TRUE 0 != ~tmp_ndt_1~0 [L416] ~m_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L417] CALL call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L49] COND TRUE 0 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L60-L78] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L63] ~E_1~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L64] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND FALSE !(1 == ~m_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND TRUE 1 == ~E_1~0 [L249] ~__retres1~1 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=1, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L613-L617] COND TRUE 0 != ~tmp___0~0 [L614] ~t1_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=1, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L64] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=1, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L65] ~E_1~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L68-L75] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=0, ~m_st~0=1, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L70] ~m_pc~0 := 1; [L71] ~m_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=1, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L417] RET call master(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L425] COND TRUE 0 == ~t1_st~0 [L426] havoc ~tmp_ndt_2~0; [L427] assume -2147483648 <= #t~nondet2 && #t~nondet2 <= 2147483647; [L427] ~tmp_ndt_2~0 := #t~nondet2; [L427] havoc #t~nondet2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=0, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L428-L435] COND TRUE 0 != ~tmp_ndt_2~0 [L430] ~t1_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L431] CALL call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L90] COND FALSE !(0 == ~t1_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L93] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L109] ~E_2~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L110] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND TRUE 1 == ~E_2~0 [L268] ~__retres1~2 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=1, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L621-L625] COND TRUE 0 != ~tmp___1~0 [L622] ~t2_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=1, ~tmp___2~0=0, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L110] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=1, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L111] ~E_2~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L101-L113] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=1, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L103] ~t1_pc~0 := 1; [L104] ~t1_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=1, old(~t1_st~0)=1, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L431] RET call transmit1(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L439] COND TRUE 0 == ~t2_st~0 [L440] havoc ~tmp_ndt_3~0; [L441] assume -2147483648 <= #t~nondet3 && #t~nondet3 <= 2147483647; [L441] ~tmp_ndt_3~0 := #t~nondet3; [L441] havoc #t~nondet3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=0, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L442-L449] COND TRUE 0 != ~tmp_ndt_3~0 [L444] ~t2_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L445] CALL call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L125] COND FALSE !(0 == ~t2_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L128] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L144] ~E_3~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L145] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND TRUE 1 == ~E_3~0 [L287] ~__retres1~3 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L629-L633] COND TRUE 0 != ~tmp___2~0 [L630] ~t3_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND FALSE !(1 == ~E_4~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L314] ~__retres1~4 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L637-L641] COND FALSE !(0 != ~tmp___3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=1, ~tmp___3~0=0, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L145] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=1, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L146] ~E_3~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L136-L148] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=1, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L138] ~t2_pc~0 := 1; [L139] ~t2_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=1, old(~t2_st~0)=1, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=2, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L445] RET call transmit2(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L453] COND TRUE 0 == ~t3_st~0 [L454] havoc ~tmp_ndt_4~0; [L455] assume -2147483648 <= #t~nondet4 && #t~nondet4 <= 2147483647; [L455] ~tmp_ndt_4~0 := #t~nondet4; [L455] havoc #t~nondet4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=0, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L456-L463] COND TRUE 0 != ~tmp_ndt_4~0 [L458] ~t3_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L459] CALL call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L160] COND FALSE !(0 == ~t3_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L163] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L179] ~E_4~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L180] CALL call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L651] CALL call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L595] havoc ~tmp~1; [L596] havoc ~tmp___0~0; [L597] havoc ~tmp___1~0; [L598] havoc ~tmp___2~0; [L599] havoc ~tmp___3~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] CALL call #t~ret6 := is_master_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L225] havoc ~__retres1~0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L228] COND TRUE 1 == ~m_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L229] COND FALSE !(1 == ~M_E~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L238] ~__retres1~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L240] #res := ~__retres1~0; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~0=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] RET call #t~ret6 := is_master_triggered(); VAL [#t~ret6=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L603] assume -2147483648 <= #t~ret6 && #t~ret6 <= 2147483647; [L603] ~tmp~1 := #t~ret6; [L603] havoc #t~ret6; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L605-L609] COND FALSE !(0 != ~tmp~1) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] CALL call #t~ret7 := is_transmit1_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L244] havoc ~__retres1~1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L247] COND TRUE 1 == ~t1_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L248] COND FALSE !(1 == ~E_1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L257] ~__retres1~1 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L259] #res := ~__retres1~1; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~1=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L611] RET call #t~ret7 := is_transmit1_triggered(); VAL [#t~ret7=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp~1=0] [L611] assume -2147483648 <= #t~ret7 && #t~ret7 <= 2147483647; [L611] ~tmp___0~0 := #t~ret7; [L611] havoc #t~ret7; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L613-L617] COND FALSE !(0 != ~tmp___0~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] CALL call #t~ret8 := is_transmit2_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L263] havoc ~__retres1~2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L266] COND TRUE 1 == ~t2_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L267] COND FALSE !(1 == ~E_2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L276] ~__retres1~2 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L278] #res := ~__retres1~2; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~2=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L619] RET call #t~ret8 := is_transmit2_triggered(); VAL [#t~ret8=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp~1=0] [L619] assume -2147483648 <= #t~ret8 && #t~ret8 <= 2147483647; [L619] ~tmp___1~0 := #t~ret8; [L619] havoc #t~ret8; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L621-L625] COND FALSE !(0 != ~tmp___1~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] CALL call #t~ret9 := is_transmit3_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L282] havoc ~__retres1~3; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L285] COND TRUE 1 == ~t3_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L286] COND FALSE !(1 == ~E_3~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L295] ~__retres1~3 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L297] #res := ~__retres1~3; VAL [#res=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~3=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L627] RET call #t~ret9 := is_transmit3_triggered(); VAL [#t~ret9=0, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp~1=0] [L627] assume -2147483648 <= #t~ret9 && #t~ret9 <= 2147483647; [L627] ~tmp___2~0 := #t~ret9; [L627] havoc #t~ret9; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L629-L633] COND FALSE !(0 != ~tmp___2~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] CALL call #t~ret10 := is_transmit4_triggered(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L301] havoc ~__retres1~4; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L304] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L305] COND TRUE 1 == ~E_4~0 [L306] ~__retres1~4 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L316] #res := ~__retres1~4; VAL [#res=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~__retres1~4=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2] [L635] RET call #t~ret10 := is_transmit4_triggered(); VAL [#t~ret10=1, old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp~1=0] [L635] assume -2147483648 <= #t~ret10 && #t~ret10 <= 2147483647; [L635] ~tmp___3~0 := #t~ret10; [L635] havoc #t~ret10; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=2, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp~1=0] [L637-L641] COND TRUE 0 != ~tmp___3~0 [L638] ~t4_st~0 := 0; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~tmp___0~0=0, ~tmp___1~0=0, ~tmp___2~0=0, ~tmp___3~0=1, ~tmp~1=0] [L651] RET call activate_threads(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L180] RET call immediate_notify(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=1, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L181] ~E_4~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L171-L183] COND FALSE !(false) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=1, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L173] ~t3_pc~0 := 1; [L174] ~t3_st~0 := 2; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=2, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=2, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=2, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=1, old(~t3_st~0)=1, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=2, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0] [L459] RET call transmit3(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L467] COND TRUE 0 == ~t4_st~0 [L468] havoc ~tmp_ndt_5~0; [L469] assume -2147483648 <= #t~nondet5 && #t~nondet5 <= 2147483647; [L469] ~tmp_ndt_5~0 := #t~nondet5; [L469] havoc #t~nondet5; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=0, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L470-L477] COND TRUE 0 != ~tmp_ndt_5~0 [L472] ~t4_st~0 := 1; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=0, old(~t4_st~0)=0, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1, ~tmp_ndt_1~0=1, ~tmp_ndt_2~0=1, ~tmp_ndt_3~0=1, ~tmp_ndt_4~0=1, ~tmp_ndt_5~0=1, ~tmp~0=1] [L473] CALL call transmit4(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L195] COND FALSE !(0 == ~t4_pc~0) VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L198] COND TRUE 1 == ~t4_pc~0 VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L214] CALL call error(); VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L11] assert false; VAL [old(~E_1~0)=2, old(~E_2~0)=2, old(~E_3~0)=2, old(~E_4~0)=2, old(~M_E~0)=2, old(~m_i~0)=0, old(~m_pc~0)=0, old(~m_st~0)=0, old(~T1_E~0)=2, old(~t1_i~0)=0, old(~t1_pc~0)=0, old(~t1_st~0)=0, old(~T2_E~0)=2, old(~t2_i~0)=0, old(~t2_pc~0)=0, old(~t2_st~0)=0, old(~T3_E~0)=2, old(~t3_i~0)=0, old(~t3_pc~0)=0, old(~t3_st~0)=0, old(~T4_E~0)=2, old(~t4_i~0)=0, old(~t4_pc~0)=1, old(~t4_st~0)=1, ~E_1~0=2, ~E_2~0=2, ~E_3~0=2, ~E_4~0=2, ~M_E~0=2, ~m_i~0=1, ~m_pc~0=1, ~m_st~0=2, ~T1_E~0=2, ~t1_i~0=1, ~t1_pc~0=1, ~t1_st~0=2, ~T2_E~0=2, ~t2_i~0=1, ~t2_pc~0=1, ~t2_st~0=2, ~T3_E~0=2, ~t3_i~0=1, ~t3_pc~0=1, ~t3_st~0=2, ~T4_E~0=2, ~t4_i~0=1, ~t4_pc~0=1, ~t4_st~0=1] [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [\old(E_1)=21, \old(E_2)=5, \old(E_3)=25, \old(E_4)=11, \old(M_E)=17, \old(m_i)=7, \old(m_pc)=15, \old(m_st)=16, \old(T1_E)=3, \old(t1_i)=19, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=18, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=13, \old(T3_E)=23, \old(t3_i)=24, \old(t3_pc)=8, \old(t3_st)=14, \old(T4_E)=26, \old(t4_i)=20, \old(t4_pc)=22, \old(t4_st)=12, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L815] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L815] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L816] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L759] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L762] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L762] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L397] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L473] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L425] COND FALSE !(t1_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L439] COND FALSE !(t2_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND FALSE !(t4_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L417] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L417] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L180] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L180] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L214] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] ----- [2018-11-23 14:23:30,817 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_ebf49585-64e1-4def-9e53-0b91af529595/bin-2019/utaipan/witness.graphml [2018-11-23 14:23:30,818 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 14:23:30,818 INFO L168 Benchmark]: Toolchain (without parser) took 308972.35 ms. Allocated memory was 1.0 GB in the beginning and 4.5 GB in the end (delta: 3.5 GB). Free memory was 961.1 MB in the beginning and 738.2 MB in the end (delta: 222.9 MB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2018-11-23 14:23:30,819 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 14:23:30,819 INFO L168 Benchmark]: CACSL2BoogieTranslator took 260.03 ms. Allocated memory is still 1.0 GB. Free memory was 961.1 MB in the beginning and 941.0 MB in the end (delta: 20.1 MB). Peak memory consumption was 20.1 MB. Max. memory is 11.5 GB. [2018-11-23 14:23:30,820 INFO L168 Benchmark]: Boogie Procedure Inliner took 55.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 158.9 MB). Free memory was 941.0 MB in the beginning and 1.2 GB in the end (delta: -215.8 MB). Peak memory consumption was 14.9 MB. Max. memory is 11.5 GB. [2018-11-23 14:23:30,820 INFO L168 Benchmark]: Boogie Preprocessor took 36.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-23 14:23:30,820 INFO L168 Benchmark]: RCFGBuilder took 594.48 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 59.5 MB). Peak memory consumption was 59.5 MB. Max. memory is 11.5 GB. [2018-11-23 14:23:30,820 INFO L168 Benchmark]: TraceAbstraction took 265939.30 ms. Allocated memory was 1.2 GB in the beginning and 4.5 GB in the end (delta: 3.3 GB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -81.8 MB). Peak memory consumption was 3.2 GB. Max. memory is 11.5 GB. [2018-11-23 14:23:30,832 INFO L168 Benchmark]: Witness Printer took 42083.35 ms. Allocated memory is still 4.5 GB. Free memory was 1.2 GB in the beginning and 738.2 MB in the end (delta: 437.5 MB). Peak memory consumption was 437.5 MB. Max. memory is 11.5 GB. [2018-11-23 14:23:30,834 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 260.03 ms. Allocated memory is still 1.0 GB. Free memory was 961.1 MB in the beginning and 941.0 MB in the end (delta: 20.1 MB). Peak memory consumption was 20.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 55.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 158.9 MB). Free memory was 941.0 MB in the beginning and 1.2 GB in the end (delta: -215.8 MB). Peak memory consumption was 14.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 36.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 594.48 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 59.5 MB). Peak memory consumption was 59.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 265939.30 ms. Allocated memory was 1.2 GB in the beginning and 4.5 GB in the end (delta: 3.3 GB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -81.8 MB). Peak memory consumption was 3.2 GB. Max. memory is 11.5 GB. * Witness Printer took 42083.35 ms. Allocated memory is still 4.5 GB. Free memory was 1.2 GB in the beginning and 738.2 MB in the end (delta: 437.5 MB). Peak memory consumption was 437.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [\old(E_1)=21, \old(E_2)=5, \old(E_3)=25, \old(E_4)=11, \old(M_E)=17, \old(m_i)=7, \old(m_pc)=15, \old(m_st)=16, \old(T1_E)=3, \old(t1_i)=19, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=18, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=13, \old(T3_E)=23, \old(t3_i)=24, \old(t3_pc)=8, \old(t3_st)=14, \old(T4_E)=26, \old(t4_i)=20, \old(t4_pc)=22, \old(t4_st)=12, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L815] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L815] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L816] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L759] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L762] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L762] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L397] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L473] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L425] COND FALSE !(t1_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L439] COND FALSE !(t2_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND FALSE !(t4_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L417] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L417] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L180] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L180] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L214] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 27 procedures, 229 locations, 1 error locations. UNSAFE Result, 265.8s OverallTime, 45 OverallIterations, 7 TraceHistogramMax, 180.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 16533 SDtfs, 28780 SDslu, 67121 SDs, 0 SdLazy, 42508 SolverSat, 8132 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 34.0s Time, PredicateUnifierStatistics: 18 DeclaredPredicates, 11079 GetRequests, 9951 SyntacticMatches, 66 SemanticMatches, 1062 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27807 ImplicationChecksByTransitivity, 18.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=50935occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 6.5s AbstIntTime, 20 AbstIntIterations, 9 AbstIntStrong, 0.9929530765288962 AbsIntWeakeningRatio, 0.6094420600858369 AbsIntAvgWeakeningVarsNumRemoved, 19.221030042918454 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 41.2s AutomataMinimizationTime, 44 MinimizatonAttempts, 10303 StatesRemovedByMinimization, 41 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 1.3s SatisfiabilityAnalysisTime, 6.2s InterpolantComputationTime, 13990 NumberOfCodeBlocks, 13990 NumberOfCodeBlocksAsserted, 56 NumberOfCheckSat, 17752 ConstructedInterpolants, 0 QuantifiedInterpolants, 7748287 SizeOfPredicates, 10 NumberOfNonLiveVariables, 17532 ConjunctsInSsa, 47 ConjunctsInUnsatCore, 66 InterpolantComputations, 37 PerfectInterpolantSequences, 15014/15471 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...