./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/config/TaipanMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c -s /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9af739900018493f70ca6be86d814e194413d937 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 05:11:50,238 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 05:11:50,239 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 05:11:50,245 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 05:11:50,245 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 05:11:50,246 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 05:11:50,246 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 05:11:50,247 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 05:11:50,248 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 05:11:50,248 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 05:11:50,249 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 05:11:50,249 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 05:11:50,249 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 05:11:50,250 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 05:11:50,251 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 05:11:50,251 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 05:11:50,251 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 05:11:50,252 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 05:11:50,253 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 05:11:50,254 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 05:11:50,255 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 05:11:50,255 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 05:11:50,256 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 05:11:50,256 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 05:11:50,257 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 05:11:50,257 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 05:11:50,258 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 05:11:50,258 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 05:11:50,258 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 05:11:50,259 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 05:11:50,259 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 05:11:50,259 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 05:11:50,259 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 05:11:50,260 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 05:11:50,260 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 05:11:50,260 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 05:11:50,261 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf [2018-12-02 05:11:50,268 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 05:11:50,268 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 05:11:50,269 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-02 05:11:50,269 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-02 05:11:50,269 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-02 05:11:50,270 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-02 05:11:50,270 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-02 05:11:50,270 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-02 05:11:50,270 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 05:11:50,270 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-02 05:11:50,270 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-12-02 05:11:50,270 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 05:11:50,270 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-02 05:11:50,270 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-02 05:11:50,271 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 05:11:50,271 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 05:11:50,271 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 05:11:50,272 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 05:11:50,272 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-02 05:11:50,272 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 05:11:50,272 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 05:11:50,272 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9af739900018493f70ca6be86d814e194413d937 [2018-12-02 05:11:50,290 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 05:11:50,298 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 05:11:50,301 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 05:11:50,302 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 05:11:50,302 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 05:11:50,303 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-12-02 05:11:50,341 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/data/c296b9339/90dbbf91bc004666a4bcb79038f6ba2e/FLAGebcb6abb5 [2018-12-02 05:11:50,710 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 05:11:50,710 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-12-02 05:11:50,713 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/data/c296b9339/90dbbf91bc004666a4bcb79038f6ba2e/FLAGebcb6abb5 [2018-12-02 05:11:51,081 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/data/c296b9339/90dbbf91bc004666a4bcb79038f6ba2e [2018-12-02 05:11:51,083 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 05:11:51,083 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 05:11:51,084 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 05:11:51,084 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 05:11:51,086 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 05:11:51,086 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,088 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@46c28d91 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51, skipping insertion in model container [2018-12-02 05:11:51,088 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,093 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 05:11:51,102 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 05:11:51,191 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 05:11:51,196 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 05:11:51,207 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 05:11:51,215 INFO L195 MainTranslator]: Completed translation [2018-12-02 05:11:51,215 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51 WrapperNode [2018-12-02 05:11:51,215 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 05:11:51,216 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 05:11:51,216 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 05:11:51,216 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 05:11:51,220 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,225 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,228 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 05:11:51,229 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 05:11:51,229 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 05:11:51,229 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 05:11:51,234 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,234 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,235 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,235 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,239 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,270 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,271 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... [2018-12-02 05:11:51,273 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 05:11:51,273 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 05:11:51,273 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 05:11:51,273 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 05:11:51,274 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 05:11:51,303 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-02 05:11:51,304 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 05:11:51,304 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 05:11:51,304 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-02 05:11:51,304 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-12-02 05:11:51,304 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-12-02 05:11:51,304 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 05:11:51,304 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 05:11:51,304 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-02 05:11:51,304 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 05:11:51,304 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 05:11:51,304 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-02 05:11:51,427 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 05:11:51,427 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-12-02 05:11:51,427 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 05:11:51 BoogieIcfgContainer [2018-12-02 05:11:51,428 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 05:11:51,428 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 05:11:51,428 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 05:11:51,430 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 05:11:51,430 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 05:11:51" (1/3) ... [2018-12-02 05:11:51,431 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5f1e01ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 05:11:51, skipping insertion in model container [2018-12-02 05:11:51,431 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 05:11:51" (2/3) ... [2018-12-02 05:11:51,431 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5f1e01ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 05:11:51, skipping insertion in model container [2018-12-02 05:11:51,431 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 05:11:51" (3/3) ... [2018-12-02 05:11:51,432 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-12-02 05:11:51,438 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 05:11:51,443 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-12-02 05:11:51,452 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-12-02 05:11:51,467 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 05:11:51,467 INFO L383 AbstractCegarLoop]: Hoare is false [2018-12-02 05:11:51,467 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 05:11:51,467 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 05:11:51,467 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 05:11:51,468 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 05:11:51,468 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 05:11:51,468 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 05:11:51,477 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2018-12-02 05:11:51,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-12-02 05:11:51,482 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:51,483 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:51,484 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:51,487 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:51,488 INFO L82 PathProgramCache]: Analyzing trace with hash 1909189377, now seen corresponding path program 1 times [2018-12-02 05:11:51,489 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:51,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,516 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:51,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,516 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:51,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:51,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:51,572 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 05:11:51,572 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 05:11:51,572 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 05:11:51,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 05:11:51,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 05:11:51,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 05:11:51,585 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 3 states. [2018-12-02 05:11:51,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:51,624 INFO L93 Difference]: Finished difference Result 58 states and 63 transitions. [2018-12-02 05:11:51,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 05:11:51,626 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 10 [2018-12-02 05:11:51,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:51,631 INFO L225 Difference]: With dead ends: 58 [2018-12-02 05:11:51,631 INFO L226 Difference]: Without dead ends: 54 [2018-12-02 05:11:51,632 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 05:11:51,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-12-02 05:11:51,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 39. [2018-12-02 05:11:51,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-02 05:11:51,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 42 transitions. [2018-12-02 05:11:51,656 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 42 transitions. Word has length 10 [2018-12-02 05:11:51,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:51,657 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 42 transitions. [2018-12-02 05:11:51,657 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 05:11:51,657 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 42 transitions. [2018-12-02 05:11:51,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-12-02 05:11:51,657 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:51,657 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:51,657 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:51,658 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:51,658 INFO L82 PathProgramCache]: Analyzing trace with hash -941983064, now seen corresponding path program 1 times [2018-12-02 05:11:51,658 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:51,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,659 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:51,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,659 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:51,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:51,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:51,711 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 05:11:51,711 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 05:11:51,711 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 05:11:51,712 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 05:11:51,712 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 05:11:51,712 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-02 05:11:51,713 INFO L87 Difference]: Start difference. First operand 39 states and 42 transitions. Second operand 6 states. [2018-12-02 05:11:51,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:51,799 INFO L93 Difference]: Finished difference Result 83 states and 88 transitions. [2018-12-02 05:11:51,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 05:11:51,800 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 11 [2018-12-02 05:11:51,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:51,802 INFO L225 Difference]: With dead ends: 83 [2018-12-02 05:11:51,802 INFO L226 Difference]: Without dead ends: 83 [2018-12-02 05:11:51,802 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 05:11:51,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-12-02 05:11:51,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 53. [2018-12-02 05:11:51,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-12-02 05:11:51,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 61 transitions. [2018-12-02 05:11:51,806 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 61 transitions. Word has length 11 [2018-12-02 05:11:51,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:51,807 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 61 transitions. [2018-12-02 05:11:51,807 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 05:11:51,807 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 61 transitions. [2018-12-02 05:11:51,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-02 05:11:51,807 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:51,807 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:51,807 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:51,807 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:51,807 INFO L82 PathProgramCache]: Analyzing trace with hash 863296133, now seen corresponding path program 1 times [2018-12-02 05:11:51,808 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:51,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,808 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:51,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,808 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:51,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:51,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:51,838 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 05:11:51,839 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 05:11:51,839 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 05:11:51,839 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 05:11:51,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 05:11:51,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 05:11:51,839 INFO L87 Difference]: Start difference. First operand 53 states and 61 transitions. Second operand 5 states. [2018-12-02 05:11:51,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:51,882 INFO L93 Difference]: Finished difference Result 52 states and 59 transitions. [2018-12-02 05:11:51,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 05:11:51,882 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 12 [2018-12-02 05:11:51,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:51,883 INFO L225 Difference]: With dead ends: 52 [2018-12-02 05:11:51,883 INFO L226 Difference]: Without dead ends: 52 [2018-12-02 05:11:51,883 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 05:11:51,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-12-02 05:11:51,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2018-12-02 05:11:51,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-12-02 05:11:51,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 59 transitions. [2018-12-02 05:11:51,887 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 59 transitions. Word has length 12 [2018-12-02 05:11:51,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:51,887 INFO L480 AbstractCegarLoop]: Abstraction has 52 states and 59 transitions. [2018-12-02 05:11:51,887 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 05:11:51,887 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 59 transitions. [2018-12-02 05:11:51,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-02 05:11:51,888 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:51,888 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:51,888 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:51,888 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:51,888 INFO L82 PathProgramCache]: Analyzing trace with hash 863296134, now seen corresponding path program 1 times [2018-12-02 05:11:51,888 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:51,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:51,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:51,889 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:51,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:51,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:51,966 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 05:11:51,966 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 05:11:51,966 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 05:11:51,966 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-02 05:11:51,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-02 05:11:51,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-12-02 05:11:51,967 INFO L87 Difference]: Start difference. First operand 52 states and 59 transitions. Second operand 7 states. [2018-12-02 05:11:52,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:52,049 INFO L93 Difference]: Finished difference Result 59 states and 64 transitions. [2018-12-02 05:11:52,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 05:11:52,049 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 12 [2018-12-02 05:11:52,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:52,050 INFO L225 Difference]: With dead ends: 59 [2018-12-02 05:11:52,050 INFO L226 Difference]: Without dead ends: 59 [2018-12-02 05:11:52,050 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-02 05:11:52,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-12-02 05:11:52,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 52. [2018-12-02 05:11:52,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-12-02 05:11:52,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 58 transitions. [2018-12-02 05:11:52,053 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 58 transitions. Word has length 12 [2018-12-02 05:11:52,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:52,053 INFO L480 AbstractCegarLoop]: Abstraction has 52 states and 58 transitions. [2018-12-02 05:11:52,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-02 05:11:52,053 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 58 transitions. [2018-12-02 05:11:52,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-12-02 05:11:52,053 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:52,053 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:52,053 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:52,053 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:52,054 INFO L82 PathProgramCache]: Analyzing trace with hash 1623425863, now seen corresponding path program 1 times [2018-12-02 05:11:52,054 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:52,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,054 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:52,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,054 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:52,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:52,119 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:52,119 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:52,119 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:52,120 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 17 with the following transitions: [2018-12-02 05:11:52,121 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [10], [11], [12], [13], [16], [18], [27], [35], [73], [74], [75], [77] [2018-12-02 05:11:52,142 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 05:11:52,142 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 05:11:52,244 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 05:11:52,245 INFO L272 AbstractInterpreter]: Visited 15 different actions 27 times. Merged at 5 different actions 10 times. Never widened. Performed 153 root evaluator evaluations with a maximum evaluation depth of 3. Performed 153 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 20 variables. [2018-12-02 05:11:52,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:52,251 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 05:11:52,251 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:52,251 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:52,257 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:52,257 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:52,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:52,272 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:52,311 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:52,311 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:52,340 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:52,354 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:52,355 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 3, 3] total 11 [2018-12-02 05:11:52,355 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:52,355 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-02 05:11:52,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-02 05:11:52,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-12-02 05:11:52,355 INFO L87 Difference]: Start difference. First operand 52 states and 58 transitions. Second operand 10 states. [2018-12-02 05:11:52,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:52,503 INFO L93 Difference]: Finished difference Result 88 states and 97 transitions. [2018-12-02 05:11:52,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-02 05:11:52,503 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 16 [2018-12-02 05:11:52,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:52,504 INFO L225 Difference]: With dead ends: 88 [2018-12-02 05:11:52,504 INFO L226 Difference]: Without dead ends: 88 [2018-12-02 05:11:52,504 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=70, Invalid=170, Unknown=0, NotChecked=0, Total=240 [2018-12-02 05:11:52,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-12-02 05:11:52,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 61. [2018-12-02 05:11:52,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-12-02 05:11:52,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 68 transitions. [2018-12-02 05:11:52,508 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 68 transitions. Word has length 16 [2018-12-02 05:11:52,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:52,508 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 68 transitions. [2018-12-02 05:11:52,508 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-02 05:11:52,508 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 68 transitions. [2018-12-02 05:11:52,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-12-02 05:11:52,508 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:52,508 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:52,509 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:52,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:52,509 INFO L82 PathProgramCache]: Analyzing trace with hash 2121234189, now seen corresponding path program 1 times [2018-12-02 05:11:52,509 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:52,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,510 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:52,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,510 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:52,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:52,571 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:52,571 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:52,571 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:52,571 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 21 with the following transitions: [2018-12-02 05:11:52,571 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [35], [37], [39], [73], [74], [75], [77], [78] [2018-12-02 05:11:52,572 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 05:11:52,572 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 05:11:52,612 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 05:11:52,612 INFO L272 AbstractInterpreter]: Visited 20 different actions 38 times. Merged at 5 different actions 15 times. Never widened. Performed 196 root evaluator evaluations with a maximum evaluation depth of 3. Performed 196 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 21 variables. [2018-12-02 05:11:52,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:52,614 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 05:11:52,614 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:52,614 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:52,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:52,625 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:52,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:52,634 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:52,672 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:52,673 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:52,739 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 05:11:52,753 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:52,753 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2018-12-02 05:11:52,753 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:52,754 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-02 05:11:52,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-02 05:11:52,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-12-02 05:11:52,754 INFO L87 Difference]: Start difference. First operand 61 states and 68 transitions. Second operand 10 states. [2018-12-02 05:11:52,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:52,903 INFO L93 Difference]: Finished difference Result 93 states and 98 transitions. [2018-12-02 05:11:52,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-02 05:11:52,903 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 20 [2018-12-02 05:11:52,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:52,904 INFO L225 Difference]: With dead ends: 93 [2018-12-02 05:11:52,904 INFO L226 Difference]: Without dead ends: 84 [2018-12-02 05:11:52,904 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 32 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=171, Unknown=0, NotChecked=0, Total=240 [2018-12-02 05:11:52,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-12-02 05:11:52,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 66. [2018-12-02 05:11:52,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-12-02 05:11:52,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 71 transitions. [2018-12-02 05:11:52,907 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 71 transitions. Word has length 20 [2018-12-02 05:11:52,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:52,907 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 71 transitions. [2018-12-02 05:11:52,908 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-02 05:11:52,908 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 71 transitions. [2018-12-02 05:11:52,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-02 05:11:52,908 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:52,908 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:52,908 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:52,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:52,908 INFO L82 PathProgramCache]: Analyzing trace with hash -523456178, now seen corresponding path program 2 times [2018-12-02 05:11:52,908 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:52,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,909 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:52,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,909 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:52,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:52,936 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:52,936 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 05:11:52,936 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 05:11:52,936 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 05:11:52,937 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 05:11:52,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 05:11:52,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 05:11:52,937 INFO L87 Difference]: Start difference. First operand 66 states and 71 transitions. Second operand 3 states. [2018-12-02 05:11:52,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:52,946 INFO L93 Difference]: Finished difference Result 64 states and 69 transitions. [2018-12-02 05:11:52,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 05:11:52,946 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-02 05:11:52,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:52,947 INFO L225 Difference]: With dead ends: 64 [2018-12-02 05:11:52,947 INFO L226 Difference]: Without dead ends: 64 [2018-12-02 05:11:52,947 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 05:11:52,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-12-02 05:11:52,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2018-12-02 05:11:52,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-12-02 05:11:52,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 69 transitions. [2018-12-02 05:11:52,950 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 69 transitions. Word has length 25 [2018-12-02 05:11:52,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:52,950 INFO L480 AbstractCegarLoop]: Abstraction has 64 states and 69 transitions. [2018-12-02 05:11:52,950 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 05:11:52,950 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 69 transitions. [2018-12-02 05:11:52,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-02 05:11:52,950 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:52,951 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:52,951 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:52,951 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:52,951 INFO L82 PathProgramCache]: Analyzing trace with hash -523456177, now seen corresponding path program 1 times [2018-12-02 05:11:52,951 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:52,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,951 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:11:52,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:52,952 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:52,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:52,975 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:52,975 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 05:11:52,975 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 05:11:52,975 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 05:11:52,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 05:11:52,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 05:11:52,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 05:11:52,976 INFO L87 Difference]: Start difference. First operand 64 states and 69 transitions. Second operand 3 states. [2018-12-02 05:11:52,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:52,998 INFO L93 Difference]: Finished difference Result 68 states and 73 transitions. [2018-12-02 05:11:52,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 05:11:52,998 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-02 05:11:52,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:52,998 INFO L225 Difference]: With dead ends: 68 [2018-12-02 05:11:52,998 INFO L226 Difference]: Without dead ends: 68 [2018-12-02 05:11:52,999 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 05:11:52,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-12-02 05:11:53,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 66. [2018-12-02 05:11:53,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-12-02 05:11:53,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 71 transitions. [2018-12-02 05:11:53,001 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 71 transitions. Word has length 25 [2018-12-02 05:11:53,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:53,001 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 71 transitions. [2018-12-02 05:11:53,001 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 05:11:53,001 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 71 transitions. [2018-12-02 05:11:53,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-12-02 05:11:53,002 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:53,002 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:53,002 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:53,002 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:53,002 INFO L82 PathProgramCache]: Analyzing trace with hash 2020089664, now seen corresponding path program 1 times [2018-12-02 05:11:53,002 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:53,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:53,003 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:53,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:53,003 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:53,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:53,032 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:53,032 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:53,033 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:53,033 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 32 with the following transitions: [2018-12-02 05:11:53,033 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [33], [35], [37], [38], [41], [43], [47], [55], [58], [73], [74], [75], [77], [78] [2018-12-02 05:11:53,034 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 05:11:53,034 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 05:11:53,132 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 05:11:53,132 INFO L272 AbstractInterpreter]: Visited 26 different actions 124 times. Merged at 14 different actions 58 times. Never widened. Performed 640 root evaluator evaluations with a maximum evaluation depth of 4. Performed 640 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 10 fixpoints after 4 different actions. Largest state had 21 variables. [2018-12-02 05:11:53,133 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:53,133 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 05:11:53,133 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:53,133 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:53,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:53,140 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:53,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:53,150 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:53,156 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:53,156 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:53,168 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:53,182 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:53,183 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2018-12-02 05:11:53,183 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:53,183 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 05:11:53,183 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 05:11:53,183 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-12-02 05:11:53,183 INFO L87 Difference]: Start difference. First operand 66 states and 71 transitions. Second operand 5 states. [2018-12-02 05:11:53,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:53,218 INFO L93 Difference]: Finished difference Result 90 states and 96 transitions. [2018-12-02 05:11:53,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 05:11:53,218 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2018-12-02 05:11:53,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:53,219 INFO L225 Difference]: With dead ends: 90 [2018-12-02 05:11:53,219 INFO L226 Difference]: Without dead ends: 90 [2018-12-02 05:11:53,219 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 60 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-12-02 05:11:53,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-12-02 05:11:53,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 73. [2018-12-02 05:11:53,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-12-02 05:11:53,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 80 transitions. [2018-12-02 05:11:53,222 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 80 transitions. Word has length 31 [2018-12-02 05:11:53,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:53,222 INFO L480 AbstractCegarLoop]: Abstraction has 73 states and 80 transitions. [2018-12-02 05:11:53,222 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 05:11:53,222 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 80 transitions. [2018-12-02 05:11:53,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-02 05:11:53,222 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:53,222 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:53,223 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:53,223 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:53,223 INFO L82 PathProgramCache]: Analyzing trace with hash -1860847279, now seen corresponding path program 1 times [2018-12-02 05:11:53,223 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:53,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:53,223 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:53,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:53,223 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:53,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:53,267 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 30 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 05:11:53,267 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:53,267 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:53,267 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 47 with the following transitions: [2018-12-02 05:11:53,267 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [35], [37], [38], [40], [41], [43], [73], [74], [75], [77], [78] [2018-12-02 05:11:53,268 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 05:11:53,268 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 05:11:53,363 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 05:11:53,364 INFO L272 AbstractInterpreter]: Visited 23 different actions 146 times. Merged at 15 different actions 75 times. Never widened. Performed 808 root evaluator evaluations with a maximum evaluation depth of 4. Performed 808 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 11 fixpoints after 3 different actions. Largest state had 21 variables. [2018-12-02 05:11:53,365 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:53,365 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 05:11:53,365 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:53,365 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:53,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:53,371 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:53,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:53,386 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:53,447 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 05:11:53,447 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:53,528 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 05:11:53,542 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:53,542 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 15 [2018-12-02 05:11:53,542 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:53,542 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-02 05:11:53,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-02 05:11:53,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=149, Unknown=0, NotChecked=0, Total=210 [2018-12-02 05:11:53,543 INFO L87 Difference]: Start difference. First operand 73 states and 80 transitions. Second operand 12 states. [2018-12-02 05:11:53,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:53,718 INFO L93 Difference]: Finished difference Result 94 states and 99 transitions. [2018-12-02 05:11:53,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-02 05:11:53,719 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 46 [2018-12-02 05:11:53,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:53,719 INFO L225 Difference]: With dead ends: 94 [2018-12-02 05:11:53,719 INFO L226 Difference]: Without dead ends: 91 [2018-12-02 05:11:53,719 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 82 SyntacticMatches, 4 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=129, Invalid=291, Unknown=0, NotChecked=0, Total=420 [2018-12-02 05:11:53,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-12-02 05:11:53,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 73. [2018-12-02 05:11:53,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-12-02 05:11:53,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 79 transitions. [2018-12-02 05:11:53,722 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 79 transitions. Word has length 46 [2018-12-02 05:11:53,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:53,722 INFO L480 AbstractCegarLoop]: Abstraction has 73 states and 79 transitions. [2018-12-02 05:11:53,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-02 05:11:53,722 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 79 transitions. [2018-12-02 05:11:53,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-12-02 05:11:53,723 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:53,723 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:53,723 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:53,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:53,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1288534185, now seen corresponding path program 1 times [2018-12-02 05:11:53,723 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:53,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:53,724 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:53,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:53,724 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:53,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:53,792 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 60 proven. 7 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:53,792 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:53,792 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:53,792 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 49 with the following transitions: [2018-12-02 05:11:53,792 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [15], [16], [18], [22], [23], [27], [35], [37], [38], [41], [43], [73], [74], [75], [77], [78] [2018-12-02 05:11:53,793 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 05:11:53,793 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 05:11:53,836 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 05:11:53,836 INFO L272 AbstractInterpreter]: Visited 23 different actions 105 times. Merged at 15 different actions 54 times. Never widened. Performed 540 root evaluator evaluations with a maximum evaluation depth of 4. Performed 540 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 7 fixpoints after 4 different actions. Largest state had 21 variables. [2018-12-02 05:11:53,837 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:53,838 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 05:11:53,838 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:53,838 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:53,844 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:53,844 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:53,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:53,858 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:53,924 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 65 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:53,924 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:53,956 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 65 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 05:11:53,971 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:53,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 15 [2018-12-02 05:11:53,971 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:53,972 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-02 05:11:53,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-02 05:11:53,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-12-02 05:11:53,972 INFO L87 Difference]: Start difference. First operand 73 states and 79 transitions. Second operand 15 states. [2018-12-02 05:11:54,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:54,083 INFO L93 Difference]: Finished difference Result 118 states and 122 transitions. [2018-12-02 05:11:54,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-02 05:11:54,083 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 48 [2018-12-02 05:11:54,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:54,084 INFO L225 Difference]: With dead ends: 118 [2018-12-02 05:11:54,084 INFO L226 Difference]: Without dead ends: 118 [2018-12-02 05:11:54,085 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 85 SyntacticMatches, 7 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=113, Invalid=267, Unknown=0, NotChecked=0, Total=380 [2018-12-02 05:11:54,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-12-02 05:11:54,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 99. [2018-12-02 05:11:54,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-12-02 05:11:54,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 105 transitions. [2018-12-02 05:11:54,088 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 105 transitions. Word has length 48 [2018-12-02 05:11:54,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:54,088 INFO L480 AbstractCegarLoop]: Abstraction has 99 states and 105 transitions. [2018-12-02 05:11:54,089 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-02 05:11:54,089 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 105 transitions. [2018-12-02 05:11:54,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-12-02 05:11:54,090 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:54,090 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:54,090 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:54,090 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:54,090 INFO L82 PathProgramCache]: Analyzing trace with hash -1743494932, now seen corresponding path program 2 times [2018-12-02 05:11:54,090 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:54,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:54,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:54,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:54,091 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:54,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:54,151 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 05:11:54,152 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:54,152 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:54,152 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:54,152 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:54,152 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:54,152 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:54,161 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:11:54,161 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:11:54,174 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-02 05:11:54,174 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:11:54,177 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:54,203 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:11:54,206 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:11:54,207 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-02 05:11:54,207 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 05:11:54,226 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 05:11:54,233 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-02 05:11:54,234 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-02 05:11:54,238 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-02 05:11:54,238 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-12-02 05:11:54,334 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 05:11:54,334 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:54,369 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 05:11:54,384 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:54,384 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 3] total 9 [2018-12-02 05:11:54,384 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:54,385 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-02 05:11:54,385 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-02 05:11:54,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2018-12-02 05:11:54,385 INFO L87 Difference]: Start difference. First operand 99 states and 105 transitions. Second operand 8 states. [2018-12-02 05:11:54,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:54,494 INFO L93 Difference]: Finished difference Result 103 states and 109 transitions. [2018-12-02 05:11:54,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 05:11:54,494 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-12-02 05:11:54,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:54,495 INFO L225 Difference]: With dead ends: 103 [2018-12-02 05:11:54,495 INFO L226 Difference]: Without dead ends: 103 [2018-12-02 05:11:54,495 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 94 SyntacticMatches, 4 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-12-02 05:11:54,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-12-02 05:11:54,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 101. [2018-12-02 05:11:54,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-12-02 05:11:54,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 107 transitions. [2018-12-02 05:11:54,498 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 107 transitions. Word has length 51 [2018-12-02 05:11:54,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:54,498 INFO L480 AbstractCegarLoop]: Abstraction has 101 states and 107 transitions. [2018-12-02 05:11:54,498 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-02 05:11:54,498 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 107 transitions. [2018-12-02 05:11:54,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-12-02 05:11:54,499 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:54,499 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:54,499 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:54,499 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:54,499 INFO L82 PathProgramCache]: Analyzing trace with hash 841147677, now seen corresponding path program 2 times [2018-12-02 05:11:54,499 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:54,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:54,500 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:11:54,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:54,500 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:54,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:54,619 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 39 proven. 19 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 05:11:54,619 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:54,619 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:54,619 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:54,619 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:54,620 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:54,620 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:54,625 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:11:54,625 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:11:54,637 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2018-12-02 05:11:54,638 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:11:54,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:54,649 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-02 05:11:54,649 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-02 05:11:54,654 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:11:54,655 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:11:54,656 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-02 05:11:54,656 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-02 05:11:54,660 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 05:11:54,663 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-02 05:11:54,664 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2018-12-02 05:11:54,766 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-12-02 05:11:54,766 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:54,843 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-12-02 05:11:54,866 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-02 05:11:54,866 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5, 4] imperfect sequences [10] total 17 [2018-12-02 05:11:54,867 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 05:11:54,867 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 05:11:54,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 05:11:54,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-12-02 05:11:54,867 INFO L87 Difference]: Start difference. First operand 101 states and 107 transitions. Second operand 6 states. [2018-12-02 05:11:54,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:54,906 INFO L93 Difference]: Finished difference Result 99 states and 104 transitions. [2018-12-02 05:11:54,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 05:11:54,907 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 57 [2018-12-02 05:11:54,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:54,907 INFO L225 Difference]: With dead ends: 99 [2018-12-02 05:11:54,907 INFO L226 Difference]: Without dead ends: 99 [2018-12-02 05:11:54,908 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 105 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-12-02 05:11:54,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-12-02 05:11:54,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 97. [2018-12-02 05:11:54,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-12-02 05:11:54,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 102 transitions. [2018-12-02 05:11:54,910 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 102 transitions. Word has length 57 [2018-12-02 05:11:54,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:54,910 INFO L480 AbstractCegarLoop]: Abstraction has 97 states and 102 transitions. [2018-12-02 05:11:54,910 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 05:11:54,910 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 102 transitions. [2018-12-02 05:11:54,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-12-02 05:11:54,911 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:54,911 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:54,911 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:54,911 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:54,912 INFO L82 PathProgramCache]: Analyzing trace with hash 1791241707, now seen corresponding path program 1 times [2018-12-02 05:11:54,912 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:54,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:54,912 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:11:54,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:54,913 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:54,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:55,034 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 39 proven. 19 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 05:11:55,035 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:55,035 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:55,035 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 61 with the following transitions: [2018-12-02 05:11:55,035 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [33], [35], [37], [38], [41], [43], [47], [55], [56], [61], [63], [72], [73], [74], [75], [77], [78] [2018-12-02 05:11:55,036 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 05:11:55,036 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 05:11:55,116 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 05:11:55,116 INFO L272 AbstractInterpreter]: Visited 29 different actions 137 times. Merged at 15 different actions 67 times. Widened at 1 different actions 1 times. Performed 701 root evaluator evaluations with a maximum evaluation depth of 4. Performed 701 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 11 fixpoints after 4 different actions. Largest state had 21 variables. [2018-12-02 05:11:55,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:55,122 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 05:11:55,122 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:55,122 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:55,130 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:55,131 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:55,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:55,150 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:55,191 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 05:11:55,191 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:55,213 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 05:11:55,228 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:55,228 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5, 5] total 14 [2018-12-02 05:11:55,228 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:55,228 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-12-02 05:11:55,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-12-02 05:11:55,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2018-12-02 05:11:55,228 INFO L87 Difference]: Start difference. First operand 97 states and 102 transitions. Second operand 13 states. [2018-12-02 05:11:55,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:55,387 INFO L93 Difference]: Finished difference Result 115 states and 120 transitions. [2018-12-02 05:11:55,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-12-02 05:11:55,388 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 60 [2018-12-02 05:11:55,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:55,388 INFO L225 Difference]: With dead ends: 115 [2018-12-02 05:11:55,389 INFO L226 Difference]: Without dead ends: 115 [2018-12-02 05:11:55,389 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 117 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=114, Invalid=392, Unknown=0, NotChecked=0, Total=506 [2018-12-02 05:11:55,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-12-02 05:11:55,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 83. [2018-12-02 05:11:55,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-12-02 05:11:55,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 85 transitions. [2018-12-02 05:11:55,391 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 85 transitions. Word has length 60 [2018-12-02 05:11:55,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:55,392 INFO L480 AbstractCegarLoop]: Abstraction has 83 states and 85 transitions. [2018-12-02 05:11:55,392 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-12-02 05:11:55,392 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 85 transitions. [2018-12-02 05:11:55,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-12-02 05:11:55,392 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:55,393 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:55,393 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:55,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:55,393 INFO L82 PathProgramCache]: Analyzing trace with hash -213546900, now seen corresponding path program 2 times [2018-12-02 05:11:55,393 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:55,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:55,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:55,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:55,394 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:55,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:55,476 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 100 proven. 24 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-12-02 05:11:55,477 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:55,477 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:55,477 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:55,477 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:55,477 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:55,477 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:55,483 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:11:55,483 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:11:55,497 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-12-02 05:11:55,497 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:11:55,499 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:55,503 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:11:55,505 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:11:55,512 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:11:55,513 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:11:55,538 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:11:55,545 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:11:55,545 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-02 05:11:55,625 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 100 proven. 16 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2018-12-02 05:11:55,626 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:55,730 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 100 proven. 16 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2018-12-02 05:11:55,745 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:55,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9, 8] total 21 [2018-12-02 05:11:55,745 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:55,746 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-02 05:11:55,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-02 05:11:55,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=372, Unknown=0, NotChecked=0, Total=462 [2018-12-02 05:11:55,746 INFO L87 Difference]: Start difference. First operand 83 states and 85 transitions. Second operand 15 states. [2018-12-02 05:11:56,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:56,031 INFO L93 Difference]: Finished difference Result 135 states and 140 transitions. [2018-12-02 05:11:56,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-02 05:11:56,031 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 74 [2018-12-02 05:11:56,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:56,032 INFO L225 Difference]: With dead ends: 135 [2018-12-02 05:11:56,032 INFO L226 Difference]: Without dead ends: 135 [2018-12-02 05:11:56,032 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 131 SyntacticMatches, 4 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 282 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=246, Invalid=810, Unknown=0, NotChecked=0, Total=1056 [2018-12-02 05:11:56,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-12-02 05:11:56,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 114. [2018-12-02 05:11:56,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-12-02 05:11:56,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 118 transitions. [2018-12-02 05:11:56,035 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 118 transitions. Word has length 74 [2018-12-02 05:11:56,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:56,035 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 118 transitions. [2018-12-02 05:11:56,035 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-02 05:11:56,035 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 118 transitions. [2018-12-02 05:11:56,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 05:11:56,036 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:56,036 INFO L402 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:56,036 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:56,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:56,037 INFO L82 PathProgramCache]: Analyzing trace with hash 868331390, now seen corresponding path program 3 times [2018-12-02 05:11:56,037 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:56,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:56,037 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:11:56,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:56,037 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:56,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:56,157 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 306 proven. 87 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-12-02 05:11:56,157 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:56,157 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:56,158 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:56,158 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:56,158 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:56,158 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:56,176 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:11:56,176 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:11:56,198 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:11:56,198 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:11:56,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:56,301 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 282 proven. 102 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-12-02 05:11:56,301 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:56,439 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 288 proven. 96 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-12-02 05:11:56,453 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:56,453 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 28 [2018-12-02 05:11:56,453 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:56,454 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-12-02 05:11:56,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-12-02 05:11:56,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=622, Unknown=0, NotChecked=0, Total=756 [2018-12-02 05:11:56,454 INFO L87 Difference]: Start difference. First operand 114 states and 118 transitions. Second operand 22 states. [2018-12-02 05:11:56,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:56,701 INFO L93 Difference]: Finished difference Result 140 states and 143 transitions. [2018-12-02 05:11:56,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-02 05:11:56,701 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 105 [2018-12-02 05:11:56,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:56,702 INFO L225 Difference]: With dead ends: 140 [2018-12-02 05:11:56,702 INFO L226 Difference]: Without dead ends: 120 [2018-12-02 05:11:56,702 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 234 GetRequests, 191 SyntacticMatches, 7 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 369 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=324, Invalid=1082, Unknown=0, NotChecked=0, Total=1406 [2018-12-02 05:11:56,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-12-02 05:11:56,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 114. [2018-12-02 05:11:56,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-12-02 05:11:56,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 116 transitions. [2018-12-02 05:11:56,704 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 116 transitions. Word has length 105 [2018-12-02 05:11:56,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:56,705 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 116 transitions. [2018-12-02 05:11:56,705 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-12-02 05:11:56,705 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 116 transitions. [2018-12-02 05:11:56,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-12-02 05:11:56,706 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:56,706 INFO L402 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:56,706 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:56,706 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:56,706 INFO L82 PathProgramCache]: Analyzing trace with hash -1118070359, now seen corresponding path program 4 times [2018-12-02 05:11:56,706 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:56,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:56,707 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:11:56,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:56,707 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:56,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:56,817 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 225 proven. 42 refuted. 0 times theorem prover too weak. 246 trivial. 0 not checked. [2018-12-02 05:11:56,817 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:56,817 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:56,817 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:56,817 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:56,817 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:56,817 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:56,824 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:56,824 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:56,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:56,851 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:56,853 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:11:56,857 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:11:56,860 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:11:56,861 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:11:56,866 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:11:56,872 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:11:56,872 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:11:56,955 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 225 proven. 42 refuted. 0 times theorem prover too weak. 246 trivial. 0 not checked. [2018-12-02 05:11:56,955 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:57,041 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 225 proven. 42 refuted. 0 times theorem prover too weak. 246 trivial. 0 not checked. [2018-12-02 05:11:57,057 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:57,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 21 [2018-12-02 05:11:57,057 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:57,057 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-02 05:11:57,057 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-02 05:11:57,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=351, Unknown=0, NotChecked=0, Total=462 [2018-12-02 05:11:57,057 INFO L87 Difference]: Start difference. First operand 114 states and 116 transitions. Second operand 15 states. [2018-12-02 05:11:57,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:57,213 INFO L93 Difference]: Finished difference Result 136 states and 140 transitions. [2018-12-02 05:11:57,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-02 05:11:57,214 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 110 [2018-12-02 05:11:57,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:57,214 INFO L225 Difference]: With dead ends: 136 [2018-12-02 05:11:57,214 INFO L226 Difference]: Without dead ends: 136 [2018-12-02 05:11:57,215 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 200 SyntacticMatches, 8 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 175 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=185, Invalid=517, Unknown=0, NotChecked=0, Total=702 [2018-12-02 05:11:57,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-12-02 05:11:57,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 119. [2018-12-02 05:11:57,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-12-02 05:11:57,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 122 transitions. [2018-12-02 05:11:57,216 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 122 transitions. Word has length 110 [2018-12-02 05:11:57,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:57,217 INFO L480 AbstractCegarLoop]: Abstraction has 119 states and 122 transitions. [2018-12-02 05:11:57,217 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-02 05:11:57,217 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 122 transitions. [2018-12-02 05:11:57,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-02 05:11:57,217 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:57,217 INFO L402 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:57,217 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:57,218 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:57,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1763761020, now seen corresponding path program 5 times [2018-12-02 05:11:57,218 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:57,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:57,218 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:57,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:57,218 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:57,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:57,296 INFO L134 CoverageAnalysis]: Checked inductivity of 584 backedges. 329 proven. 33 refuted. 0 times theorem prover too weak. 222 trivial. 0 not checked. [2018-12-02 05:11:57,296 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:57,296 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:57,297 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:57,297 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:57,297 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:57,297 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:57,302 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:11:57,302 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:11:57,321 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-12-02 05:11:57,321 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:11:57,323 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:57,325 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:11:57,327 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:11:57,332 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:11:57,332 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:11:57,337 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:11:57,350 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:11:57,350 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-02 05:11:57,503 INFO L134 CoverageAnalysis]: Checked inductivity of 584 backedges. 273 proven. 34 refuted. 0 times theorem prover too weak. 277 trivial. 0 not checked. [2018-12-02 05:11:57,503 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:57,661 INFO L134 CoverageAnalysis]: Checked inductivity of 584 backedges. 273 proven. 34 refuted. 0 times theorem prover too weak. 277 trivial. 0 not checked. [2018-12-02 05:11:57,676 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:57,676 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 10, 9] total 31 [2018-12-02 05:11:57,676 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:57,677 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-12-02 05:11:57,677 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-12-02 05:11:57,677 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=796, Unknown=0, NotChecked=0, Total=930 [2018-12-02 05:11:57,677 INFO L87 Difference]: Start difference. First operand 119 states and 122 transitions. Second operand 23 states. [2018-12-02 05:11:58,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:58,083 INFO L93 Difference]: Finished difference Result 164 states and 168 transitions. [2018-12-02 05:11:58,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-12-02 05:11:58,083 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 115 [2018-12-02 05:11:58,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:58,084 INFO L225 Difference]: With dead ends: 164 [2018-12-02 05:11:58,084 INFO L226 Difference]: Without dead ends: 164 [2018-12-02 05:11:58,084 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 209 SyntacticMatches, 5 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 575 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=418, Invalid=1744, Unknown=0, NotChecked=0, Total=2162 [2018-12-02 05:11:58,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-12-02 05:11:58,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 160. [2018-12-02 05:11:58,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 05:11:58,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 164 transitions. [2018-12-02 05:11:58,086 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 164 transitions. Word has length 115 [2018-12-02 05:11:58,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:58,086 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 164 transitions. [2018-12-02 05:11:58,087 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-12-02 05:11:58,087 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 164 transitions. [2018-12-02 05:11:58,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-12-02 05:11:58,087 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:58,087 INFO L402 BasicCegarLoop]: trace histogram [19, 19, 18, 18, 18, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:58,088 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:58,088 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:58,088 INFO L82 PathProgramCache]: Analyzing trace with hash 1016423052, now seen corresponding path program 6 times [2018-12-02 05:11:58,088 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:58,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:58,089 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:11:58,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:58,089 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:58,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:58,201 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 681 proven. 147 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-12-02 05:11:58,201 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:58,201 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:58,201 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:58,201 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:58,201 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:58,201 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:58,207 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:11:58,207 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:11:58,230 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:11:58,231 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:11:58,233 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:58,344 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 600 proven. 179 refuted. 0 times theorem prover too weak. 194 trivial. 0 not checked. [2018-12-02 05:11:58,344 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:58,522 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 606 proven. 173 refuted. 0 times theorem prover too weak. 194 trivial. 0 not checked. [2018-12-02 05:11:58,545 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:58,545 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15] total 33 [2018-12-02 05:11:58,545 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:58,545 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-02 05:11:58,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-02 05:11:58,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=875, Unknown=0, NotChecked=0, Total=1056 [2018-12-02 05:11:58,546 INFO L87 Difference]: Start difference. First operand 160 states and 164 transitions. Second operand 26 states. [2018-12-02 05:11:58,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:58,914 INFO L93 Difference]: Finished difference Result 171 states and 173 transitions. [2018-12-02 05:11:58,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-12-02 05:11:58,914 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 146 [2018-12-02 05:11:58,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:58,915 INFO L225 Difference]: With dead ends: 171 [2018-12-02 05:11:58,915 INFO L226 Difference]: Without dead ends: 165 [2018-12-02 05:11:58,916 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 321 GetRequests, 269 SyntacticMatches, 8 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 621 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=457, Invalid=1613, Unknown=0, NotChecked=0, Total=2070 [2018-12-02 05:11:58,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-12-02 05:11:58,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 160. [2018-12-02 05:11:58,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 05:11:58,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 162 transitions. [2018-12-02 05:11:58,923 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 162 transitions. Word has length 146 [2018-12-02 05:11:58,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:58,924 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 162 transitions. [2018-12-02 05:11:58,924 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-02 05:11:58,924 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 162 transitions. [2018-12-02 05:11:58,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-12-02 05:11:58,924 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:58,924 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 19, 19, 19, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:58,924 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:58,925 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:58,925 INFO L82 PathProgramCache]: Analyzing trace with hash 422435815, now seen corresponding path program 7 times [2018-12-02 05:11:58,925 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:58,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:58,925 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:11:58,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:58,925 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:58,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:59,045 INFO L134 CoverageAnalysis]: Checked inductivity of 1070 backedges. 420 proven. 65 refuted. 0 times theorem prover too weak. 585 trivial. 0 not checked. [2018-12-02 05:11:59,046 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:59,046 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:59,046 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:59,046 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:59,046 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:59,046 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:59,051 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:59,051 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:11:59,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:59,081 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:59,083 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:11:59,085 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:11:59,089 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:11:59,089 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:11:59,096 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:11:59,106 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:11:59,106 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:11:59,216 INFO L134 CoverageAnalysis]: Checked inductivity of 1070 backedges. 420 proven. 65 refuted. 0 times theorem prover too weak. 585 trivial. 0 not checked. [2018-12-02 05:11:59,216 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:11:59,328 INFO L134 CoverageAnalysis]: Checked inductivity of 1070 backedges. 420 proven. 65 refuted. 0 times theorem prover too weak. 585 trivial. 0 not checked. [2018-12-02 05:11:59,343 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:11:59,343 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 24 [2018-12-02 05:11:59,343 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:11:59,343 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-12-02 05:11:59,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-12-02 05:11:59,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=458, Unknown=0, NotChecked=0, Total=600 [2018-12-02 05:11:59,344 INFO L87 Difference]: Start difference. First operand 160 states and 162 transitions. Second operand 17 states. [2018-12-02 05:11:59,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:11:59,570 INFO L93 Difference]: Finished difference Result 173 states and 176 transitions. [2018-12-02 05:11:59,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-02 05:11:59,570 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 151 [2018-12-02 05:11:59,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:11:59,572 INFO L225 Difference]: With dead ends: 173 [2018-12-02 05:11:59,572 INFO L226 Difference]: Without dead ends: 173 [2018-12-02 05:11:59,572 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 317 GetRequests, 278 SyntacticMatches, 10 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 246 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=240, Invalid=690, Unknown=0, NotChecked=0, Total=930 [2018-12-02 05:11:59,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-12-02 05:11:59,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 165. [2018-12-02 05:11:59,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-12-02 05:11:59,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 168 transitions. [2018-12-02 05:11:59,578 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 168 transitions. Word has length 151 [2018-12-02 05:11:59,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:11:59,579 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 168 transitions. [2018-12-02 05:11:59,579 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-12-02 05:11:59,579 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 168 transitions. [2018-12-02 05:11:59,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-12-02 05:11:59,580 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:11:59,580 INFO L402 BasicCegarLoop]: trace histogram [21, 21, 20, 20, 20, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:11:59,581 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:11:59,581 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:11:59,581 INFO L82 PathProgramCache]: Analyzing trace with hash -671966970, now seen corresponding path program 8 times [2018-12-02 05:11:59,581 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:11:59,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:59,582 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:11:59,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:11:59,582 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:11:59,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:11:59,711 INFO L134 CoverageAnalysis]: Checked inductivity of 1172 backedges. 576 proven. 55 refuted. 0 times theorem prover too weak. 541 trivial. 0 not checked. [2018-12-02 05:11:59,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:59,712 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:11:59,712 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:11:59,712 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:11:59,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:11:59,712 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:11:59,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:11:59,721 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:11:59,766 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-12-02 05:11:59,766 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:11:59,769 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:11:59,928 INFO L134 CoverageAnalysis]: Checked inductivity of 1172 backedges. 706 proven. 217 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-02 05:11:59,928 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:00,117 INFO L134 CoverageAnalysis]: Checked inductivity of 1172 backedges. 706 proven. 217 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-02 05:12:00,132 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:00,132 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 19] total 36 [2018-12-02 05:12:00,132 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:00,132 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-02 05:12:00,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-02 05:12:00,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=1046, Unknown=0, NotChecked=0, Total=1260 [2018-12-02 05:12:00,132 INFO L87 Difference]: Start difference. First operand 165 states and 168 transitions. Second operand 30 states. [2018-12-02 05:12:00,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:00,545 INFO L93 Difference]: Finished difference Result 221 states and 225 transitions. [2018-12-02 05:12:00,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-12-02 05:12:00,546 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 156 [2018-12-02 05:12:00,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:00,546 INFO L225 Difference]: With dead ends: 221 [2018-12-02 05:12:00,546 INFO L226 Difference]: Without dead ends: 221 [2018-12-02 05:12:00,547 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 281 SyntacticMatches, 12 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 714 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=585, Invalid=2171, Unknown=0, NotChecked=0, Total=2756 [2018-12-02 05:12:00,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states. [2018-12-02 05:12:00,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 212. [2018-12-02 05:12:00,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-12-02 05:12:00,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 216 transitions. [2018-12-02 05:12:00,549 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 216 transitions. Word has length 156 [2018-12-02 05:12:00,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:00,550 INFO L480 AbstractCegarLoop]: Abstraction has 212 states and 216 transitions. [2018-12-02 05:12:00,550 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-02 05:12:00,550 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 216 transitions. [2018-12-02 05:12:00,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-12-02 05:12:00,550 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:00,550 INFO L402 BasicCegarLoop]: trace histogram [27, 27, 26, 26, 26, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:00,550 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:00,551 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:00,551 INFO L82 PathProgramCache]: Analyzing trace with hash 1169596100, now seen corresponding path program 9 times [2018-12-02 05:12:00,551 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:00,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:00,551 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:00,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:00,551 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:00,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:00,699 INFO L134 CoverageAnalysis]: Checked inductivity of 1963 backedges. 700 proven. 93 refuted. 0 times theorem prover too weak. 1170 trivial. 0 not checked. [2018-12-02 05:12:00,700 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:00,700 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:00,700 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:00,700 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:00,700 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:00,700 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:00,706 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:00,707 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:00,746 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:00,746 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:00,748 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:00,750 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:00,752 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:00,758 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:00,758 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:00,768 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:00,776 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:00,776 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:12:00,914 INFO L134 CoverageAnalysis]: Checked inductivity of 1963 backedges. 700 proven. 93 refuted. 0 times theorem prover too weak. 1170 trivial. 0 not checked. [2018-12-02 05:12:00,915 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:01,057 INFO L134 CoverageAnalysis]: Checked inductivity of 1963 backedges. 700 proven. 93 refuted. 0 times theorem prover too weak. 1170 trivial. 0 not checked. [2018-12-02 05:12:01,072 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:01,072 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 10] total 27 [2018-12-02 05:12:01,072 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:01,072 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-12-02 05:12:01,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-12-02 05:12:01,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=177, Invalid=579, Unknown=0, NotChecked=0, Total=756 [2018-12-02 05:12:01,073 INFO L87 Difference]: Start difference. First operand 212 states and 216 transitions. Second operand 19 states. [2018-12-02 05:12:01,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:01,309 INFO L93 Difference]: Finished difference Result 225 states and 230 transitions. [2018-12-02 05:12:01,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-02 05:12:01,309 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 197 [2018-12-02 05:12:01,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:01,310 INFO L225 Difference]: With dead ends: 225 [2018-12-02 05:12:01,310 INFO L226 Difference]: Without dead ends: 225 [2018-12-02 05:12:01,310 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 411 GetRequests, 366 SyntacticMatches, 12 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 329 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=302, Invalid=888, Unknown=0, NotChecked=0, Total=1190 [2018-12-02 05:12:01,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-12-02 05:12:01,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 217. [2018-12-02 05:12:01,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-12-02 05:12:01,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 222 transitions. [2018-12-02 05:12:01,314 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 222 transitions. Word has length 197 [2018-12-02 05:12:01,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:01,314 INFO L480 AbstractCegarLoop]: Abstraction has 217 states and 222 transitions. [2018-12-02 05:12:01,314 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-12-02 05:12:01,314 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 222 transitions. [2018-12-02 05:12:01,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-12-02 05:12:01,314 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:01,314 INFO L402 BasicCegarLoop]: trace histogram [28, 28, 27, 27, 27, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:01,315 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:01,315 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:01,315 INFO L82 PathProgramCache]: Analyzing trace with hash -978184119, now seen corresponding path program 10 times [2018-12-02 05:12:01,315 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:01,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:01,315 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:01,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:01,315 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:01,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:01,459 INFO L134 CoverageAnalysis]: Checked inductivity of 2101 backedges. 918 proven. 83 refuted. 0 times theorem prover too weak. 1100 trivial. 0 not checked. [2018-12-02 05:12:01,460 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:01,460 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:01,460 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:01,460 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:01,460 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:01,460 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:01,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:01,466 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:01,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:01,505 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:01,618 INFO L134 CoverageAnalysis]: Checked inductivity of 2101 backedges. 931 proven. 70 refuted. 0 times theorem prover too weak. 1100 trivial. 0 not checked. [2018-12-02 05:12:01,618 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:01,711 INFO L134 CoverageAnalysis]: Checked inductivity of 2101 backedges. 931 proven. 70 refuted. 0 times theorem prover too weak. 1100 trivial. 0 not checked. [2018-12-02 05:12:01,725 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:01,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 27 [2018-12-02 05:12:01,726 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:01,726 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-02 05:12:01,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-02 05:12:01,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=172, Invalid=530, Unknown=0, NotChecked=0, Total=702 [2018-12-02 05:12:01,727 INFO L87 Difference]: Start difference. First operand 217 states and 222 transitions. Second operand 27 states. [2018-12-02 05:12:01,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:01,991 INFO L93 Difference]: Finished difference Result 330 states and 340 transitions. [2018-12-02 05:12:01,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-12-02 05:12:01,992 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 202 [2018-12-02 05:12:01,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:01,993 INFO L225 Difference]: With dead ends: 330 [2018-12-02 05:12:01,993 INFO L226 Difference]: Without dead ends: 330 [2018-12-02 05:12:01,993 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 434 GetRequests, 381 SyntacticMatches, 15 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 457 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=429, Invalid=1131, Unknown=0, NotChecked=0, Total=1560 [2018-12-02 05:12:01,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-12-02 05:12:01,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 316. [2018-12-02 05:12:01,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 316 states. [2018-12-02 05:12:02,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 326 transitions. [2018-12-02 05:12:02,001 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 326 transitions. Word has length 202 [2018-12-02 05:12:02,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:02,001 INFO L480 AbstractCegarLoop]: Abstraction has 316 states and 326 transitions. [2018-12-02 05:12:02,001 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-02 05:12:02,001 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 326 transitions. [2018-12-02 05:12:02,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-12-02 05:12:02,003 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:02,003 INFO L402 BasicCegarLoop]: trace histogram [33, 33, 32, 32, 32, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:02,003 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:02,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:02,004 INFO L82 PathProgramCache]: Analyzing trace with hash 574052742, now seen corresponding path program 11 times [2018-12-02 05:12:02,004 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:02,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:02,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:02,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:02,005 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:02,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:02,204 INFO L134 CoverageAnalysis]: Checked inductivity of 2957 backedges. 1004 proven. 126 refuted. 0 times theorem prover too weak. 1827 trivial. 0 not checked. [2018-12-02 05:12:02,204 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:02,204 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:02,204 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:02,204 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:02,204 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:02,204 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:02,210 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:02,211 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:02,261 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-12-02 05:12:02,261 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:02,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:02,477 INFO L134 CoverageAnalysis]: Checked inductivity of 2957 backedges. 1577 proven. 305 refuted. 0 times theorem prover too weak. 1075 trivial. 0 not checked. [2018-12-02 05:12:02,477 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:02,848 INFO L134 CoverageAnalysis]: Checked inductivity of 2957 backedges. 1577 proven. 305 refuted. 0 times theorem prover too weak. 1075 trivial. 0 not checked. [2018-12-02 05:12:02,863 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:02,863 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 21, 21] total 47 [2018-12-02 05:12:02,863 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:02,864 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-02 05:12:02,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-02 05:12:02,865 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=292, Invalid=1870, Unknown=0, NotChecked=0, Total=2162 [2018-12-02 05:12:02,865 INFO L87 Difference]: Start difference. First operand 316 states and 326 transitions. Second operand 32 states. [2018-12-02 05:12:03,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:03,956 INFO L93 Difference]: Finished difference Result 391 states and 404 transitions. [2018-12-02 05:12:03,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-12-02 05:12:03,956 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 238 [2018-12-02 05:12:03,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:03,957 INFO L225 Difference]: With dead ends: 391 [2018-12-02 05:12:03,957 INFO L226 Difference]: Without dead ends: 391 [2018-12-02 05:12:03,958 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 517 GetRequests, 437 SyntacticMatches, 5 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1411 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1071, Invalid=4781, Unknown=0, NotChecked=0, Total=5852 [2018-12-02 05:12:03,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states. [2018-12-02 05:12:03,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 277. [2018-12-02 05:12:03,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-12-02 05:12:03,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 285 transitions. [2018-12-02 05:12:03,963 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 285 transitions. Word has length 238 [2018-12-02 05:12:03,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:03,964 INFO L480 AbstractCegarLoop]: Abstraction has 277 states and 285 transitions. [2018-12-02 05:12:03,964 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-02 05:12:03,964 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 285 transitions. [2018-12-02 05:12:03,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 254 [2018-12-02 05:12:03,965 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:03,965 INFO L402 BasicCegarLoop]: trace histogram [36, 36, 35, 35, 35, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:03,965 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:03,965 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:03,965 INFO L82 PathProgramCache]: Analyzing trace with hash -65711679, now seen corresponding path program 12 times [2018-12-02 05:12:03,966 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:03,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:03,966 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:03,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:03,966 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:03,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:04,176 INFO L134 CoverageAnalysis]: Checked inductivity of 3479 backedges. 1221 proven. 164 refuted. 0 times theorem prover too weak. 2094 trivial. 0 not checked. [2018-12-02 05:12:04,177 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:04,177 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:04,177 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:04,177 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:04,177 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:04,177 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:04,183 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:04,183 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:04,227 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:04,227 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:04,232 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:04,506 INFO L134 CoverageAnalysis]: Checked inductivity of 3479 backedges. 1306 proven. 493 refuted. 0 times theorem prover too weak. 1680 trivial. 0 not checked. [2018-12-02 05:12:04,506 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:04,795 INFO L134 CoverageAnalysis]: Checked inductivity of 3479 backedges. 1306 proven. 493 refuted. 0 times theorem prover too weak. 1680 trivial. 0 not checked. [2018-12-02 05:12:04,810 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:04,810 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 23, 23] total 47 [2018-12-02 05:12:04,810 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:04,810 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-02 05:12:04,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-02 05:12:04,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=1879, Unknown=0, NotChecked=0, Total=2162 [2018-12-02 05:12:04,811 INFO L87 Difference]: Start difference. First operand 277 states and 285 transitions. Second operand 35 states. [2018-12-02 05:12:05,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:05,958 INFO L93 Difference]: Finished difference Result 479 states and 501 transitions. [2018-12-02 05:12:05,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-12-02 05:12:05,958 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 253 [2018-12-02 05:12:05,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:05,960 INFO L225 Difference]: With dead ends: 479 [2018-12-02 05:12:05,960 INFO L226 Difference]: Without dead ends: 479 [2018-12-02 05:12:05,961 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 559 GetRequests, 470 SyntacticMatches, 10 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1678 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=935, Invalid=5545, Unknown=0, NotChecked=0, Total=6480 [2018-12-02 05:12:05,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states. [2018-12-02 05:12:05,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 453. [2018-12-02 05:12:05,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 453 states. [2018-12-02 05:12:05,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453 states to 453 states and 475 transitions. [2018-12-02 05:12:05,971 INFO L78 Accepts]: Start accepts. Automaton has 453 states and 475 transitions. Word has length 253 [2018-12-02 05:12:05,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:05,972 INFO L480 AbstractCegarLoop]: Abstraction has 453 states and 475 transitions. [2018-12-02 05:12:05,972 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-02 05:12:05,972 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 475 transitions. [2018-12-02 05:12:05,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-12-02 05:12:05,974 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:05,974 INFO L402 BasicCegarLoop]: trace histogram [42, 42, 41, 41, 41, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:05,974 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:05,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:05,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1551966633, now seen corresponding path program 13 times [2018-12-02 05:12:05,974 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:05,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:05,975 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:05,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:05,975 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:05,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:06,134 INFO L134 CoverageAnalysis]: Checked inductivity of 4769 backedges. 2089 proven. 892 refuted. 0 times theorem prover too weak. 1788 trivial. 0 not checked. [2018-12-02 05:12:06,135 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:06,135 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:06,135 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:06,135 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:06,135 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:06,135 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:06,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:06,145 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:06,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:06,205 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:06,329 INFO L134 CoverageAnalysis]: Checked inductivity of 4769 backedges. 2877 proven. 55 refuted. 0 times theorem prover too weak. 1837 trivial. 0 not checked. [2018-12-02 05:12:06,329 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:06,527 INFO L134 CoverageAnalysis]: Checked inductivity of 4769 backedges. 2135 proven. 411 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-12-02 05:12:06,543 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:06,544 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14, 14] total 31 [2018-12-02 05:12:06,544 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:06,544 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-12-02 05:12:06,544 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-12-02 05:12:06,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=191, Invalid=739, Unknown=0, NotChecked=0, Total=930 [2018-12-02 05:12:06,545 INFO L87 Difference]: Start difference. First operand 453 states and 475 transitions. Second operand 25 states. [2018-12-02 05:12:06,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:06,873 INFO L93 Difference]: Finished difference Result 400 states and 411 transitions. [2018-12-02 05:12:06,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-12-02 05:12:06,873 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 294 [2018-12-02 05:12:06,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:06,874 INFO L225 Difference]: With dead ends: 400 [2018-12-02 05:12:06,874 INFO L226 Difference]: Without dead ends: 385 [2018-12-02 05:12:06,874 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 620 GetRequests, 570 SyntacticMatches, 7 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 539 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=461, Invalid=1519, Unknown=0, NotChecked=0, Total=1980 [2018-12-02 05:12:06,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385 states. [2018-12-02 05:12:06,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385 to 382. [2018-12-02 05:12:06,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-12-02 05:12:06,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 393 transitions. [2018-12-02 05:12:06,880 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 393 transitions. Word has length 294 [2018-12-02 05:12:06,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:06,880 INFO L480 AbstractCegarLoop]: Abstraction has 382 states and 393 transitions. [2018-12-02 05:12:06,880 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-12-02 05:12:06,880 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 393 transitions. [2018-12-02 05:12:06,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 300 [2018-12-02 05:12:06,881 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:06,881 INFO L402 BasicCegarLoop]: trace histogram [43, 43, 42, 42, 42, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:06,881 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:06,881 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:06,881 INFO L82 PathProgramCache]: Analyzing trace with hash -1453092182, now seen corresponding path program 14 times [2018-12-02 05:12:06,881 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:06,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:06,881 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:06,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:06,882 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:06,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:07,045 INFO L134 CoverageAnalysis]: Checked inductivity of 4984 backedges. 2403 proven. 805 refuted. 0 times theorem prover too weak. 1776 trivial. 0 not checked. [2018-12-02 05:12:07,045 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:07,045 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:07,046 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:07,046 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:07,046 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:07,046 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:07,053 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:07,053 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:07,135 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-12-02 05:12:07,135 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:07,140 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:07,143 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:07,145 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:07,152 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:07,153 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:07,159 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:07,178 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:07,178 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:12:07,703 INFO L134 CoverageAnalysis]: Checked inductivity of 4984 backedges. 2097 proven. 630 refuted. 0 times theorem prover too weak. 2257 trivial. 0 not checked. [2018-12-02 05:12:07,703 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:08,172 INFO L134 CoverageAnalysis]: Checked inductivity of 4984 backedges. 2033 proven. 694 refuted. 0 times theorem prover too weak. 2257 trivial. 0 not checked. [2018-12-02 05:12:08,187 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:08,188 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 18, 17] total 53 [2018-12-02 05:12:08,188 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:08,188 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-02 05:12:08,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-02 05:12:08,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=331, Invalid=2425, Unknown=0, NotChecked=0, Total=2756 [2018-12-02 05:12:08,189 INFO L87 Difference]: Start difference. First operand 382 states and 393 transitions. Second operand 37 states. [2018-12-02 05:12:10,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:10,434 INFO L93 Difference]: Finished difference Result 337 states and 342 transitions. [2018-12-02 05:12:10,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-02 05:12:10,435 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 299 [2018-12-02 05:12:10,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:10,435 INFO L225 Difference]: With dead ends: 337 [2018-12-02 05:12:10,435 INFO L226 Difference]: Without dead ends: 328 [2018-12-02 05:12:10,437 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 659 GetRequests, 554 SyntacticMatches, 13 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2805 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1376, Invalid=7366, Unknown=0, NotChecked=0, Total=8742 [2018-12-02 05:12:10,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states. [2018-12-02 05:12:10,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 318. [2018-12-02 05:12:10,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 318 states. [2018-12-02 05:12:10,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 323 transitions. [2018-12-02 05:12:10,441 INFO L78 Accepts]: Start accepts. Automaton has 318 states and 323 transitions. Word has length 299 [2018-12-02 05:12:10,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:10,441 INFO L480 AbstractCegarLoop]: Abstraction has 318 states and 323 transitions. [2018-12-02 05:12:10,441 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-02 05:12:10,441 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 323 transitions. [2018-12-02 05:12:10,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 305 [2018-12-02 05:12:10,443 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:10,443 INFO L402 BasicCegarLoop]: trace histogram [44, 44, 43, 43, 43, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:10,443 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:10,443 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:10,443 INFO L82 PathProgramCache]: Analyzing trace with hash 1810634863, now seen corresponding path program 15 times [2018-12-02 05:12:10,443 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:10,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:10,444 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:10,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:10,444 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:10,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:10,659 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2809 proven. 625 refuted. 0 times theorem prover too weak. 1770 trivial. 0 not checked. [2018-12-02 05:12:10,659 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:10,659 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:10,659 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:10,659 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:10,659 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:10,659 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:10,666 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:10,666 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:10,715 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:10,715 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:10,719 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:10,914 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2805 proven. 506 refuted. 0 times theorem prover too weak. 1893 trivial. 0 not checked. [2018-12-02 05:12:10,914 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:11,199 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2811 proven. 500 refuted. 0 times theorem prover too weak. 1893 trivial. 0 not checked. [2018-12-02 05:12:11,214 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:11,214 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 44 [2018-12-02 05:12:11,214 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:11,215 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-12-02 05:12:11,215 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-12-02 05:12:11,215 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=1556, Unknown=0, NotChecked=0, Total=1892 [2018-12-02 05:12:11,215 INFO L87 Difference]: Start difference. First operand 318 states and 323 transitions. Second operand 34 states. [2018-12-02 05:12:11,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:11,693 INFO L93 Difference]: Finished difference Result 327 states and 330 transitions. [2018-12-02 05:12:11,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-02 05:12:11,693 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 304 [2018-12-02 05:12:11,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:11,694 INFO L225 Difference]: With dead ends: 327 [2018-12-02 05:12:11,694 INFO L226 Difference]: Without dead ends: 321 [2018-12-02 05:12:11,695 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 648 GetRequests, 577 SyntacticMatches, 11 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1219 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=862, Invalid=2920, Unknown=0, NotChecked=0, Total=3782 [2018-12-02 05:12:11,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-12-02 05:12:11,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 318. [2018-12-02 05:12:11,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 318 states. [2018-12-02 05:12:11,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 321 transitions. [2018-12-02 05:12:11,699 INFO L78 Accepts]: Start accepts. Automaton has 318 states and 321 transitions. Word has length 304 [2018-12-02 05:12:11,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:11,699 INFO L480 AbstractCegarLoop]: Abstraction has 318 states and 321 transitions. [2018-12-02 05:12:11,699 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-12-02 05:12:11,699 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 321 transitions. [2018-12-02 05:12:11,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 310 [2018-12-02 05:12:11,700 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:11,701 INFO L402 BasicCegarLoop]: trace histogram [45, 45, 44, 44, 44, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:11,701 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:11,701 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:11,701 INFO L82 PathProgramCache]: Analyzing trace with hash 221588708, now seen corresponding path program 16 times [2018-12-02 05:12:11,701 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:11,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:11,702 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:11,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:11,702 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:11,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:11,923 INFO L134 CoverageAnalysis]: Checked inductivity of 5429 backedges. 1947 proven. 157 refuted. 0 times theorem prover too weak. 3325 trivial. 0 not checked. [2018-12-02 05:12:11,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:11,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:11,923 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:11,923 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:11,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:11,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:11,929 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:11,929 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:11,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:11,985 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:12,142 INFO L134 CoverageAnalysis]: Checked inductivity of 5429 backedges. 1964 proven. 140 refuted. 0 times theorem prover too weak. 3325 trivial. 0 not checked. [2018-12-02 05:12:12,142 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:12,284 INFO L134 CoverageAnalysis]: Checked inductivity of 5429 backedges. 1964 proven. 140 refuted. 0 times theorem prover too weak. 3325 trivial. 0 not checked. [2018-12-02 05:12:12,298 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:12,298 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 33 [2018-12-02 05:12:12,299 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:12,299 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-02 05:12:12,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-02 05:12:12,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=802, Unknown=0, NotChecked=0, Total=1056 [2018-12-02 05:12:12,299 INFO L87 Difference]: Start difference. First operand 318 states and 321 transitions. Second operand 33 states. [2018-12-02 05:12:12,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:12,569 INFO L93 Difference]: Finished difference Result 384 states and 388 transitions. [2018-12-02 05:12:12,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-02 05:12:12,569 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 309 [2018-12-02 05:12:12,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:12,570 INFO L225 Difference]: With dead ends: 384 [2018-12-02 05:12:12,570 INFO L226 Difference]: Without dead ends: 384 [2018-12-02 05:12:12,571 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 589 SyntacticMatches, 19 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 735 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=659, Invalid=1791, Unknown=0, NotChecked=0, Total=2450 [2018-12-02 05:12:12,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states. [2018-12-02 05:12:12,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 374. [2018-12-02 05:12:12,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-12-02 05:12:12,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 378 transitions. [2018-12-02 05:12:12,574 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 378 transitions. Word has length 309 [2018-12-02 05:12:12,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:12,575 INFO L480 AbstractCegarLoop]: Abstraction has 374 states and 378 transitions. [2018-12-02 05:12:12,575 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-02 05:12:12,575 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 378 transitions. [2018-12-02 05:12:12,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-12-02 05:12:12,576 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:12,576 INFO L402 BasicCegarLoop]: trace histogram [53, 53, 52, 52, 52, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:12,576 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:12,576 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:12,576 INFO L82 PathProgramCache]: Analyzing trace with hash -48662420, now seen corresponding path program 17 times [2018-12-02 05:12:12,576 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:12,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:12,577 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:12,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:12,577 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:12,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:12,795 INFO L134 CoverageAnalysis]: Checked inductivity of 7542 backedges. 4691 proven. 537 refuted. 0 times theorem prover too weak. 2314 trivial. 0 not checked. [2018-12-02 05:12:12,795 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:12,795 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:12,795 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:12,795 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:12,795 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:12,796 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:12,801 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:12,801 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:12,881 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-12-02 05:12:12,881 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:12,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:13,209 INFO L134 CoverageAnalysis]: Checked inductivity of 7542 backedges. 3544 proven. 526 refuted. 0 times theorem prover too weak. 3472 trivial. 0 not checked. [2018-12-02 05:12:13,210 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:13,691 INFO L134 CoverageAnalysis]: Checked inductivity of 7542 backedges. 3544 proven. 526 refuted. 0 times theorem prover too weak. 3472 trivial. 0 not checked. [2018-12-02 05:12:13,705 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:13,705 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 25] total 65 [2018-12-02 05:12:13,705 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:13,706 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-12-02 05:12:13,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-12-02 05:12:13,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=563, Invalid=3597, Unknown=0, NotChecked=0, Total=4160 [2018-12-02 05:12:13,707 INFO L87 Difference]: Start difference. First operand 374 states and 378 transitions. Second operand 46 states. [2018-12-02 05:12:14,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:14,767 INFO L93 Difference]: Finished difference Result 389 states and 391 transitions. [2018-12-02 05:12:14,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-02 05:12:14,768 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 360 [2018-12-02 05:12:14,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:14,770 INFO L225 Difference]: With dead ends: 389 [2018-12-02 05:12:14,770 INFO L226 Difference]: Without dead ends: 383 [2018-12-02 05:12:14,771 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 784 GetRequests, 676 SyntacticMatches, 5 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3305 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1829, Invalid=9091, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 05:12:14,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383 states. [2018-12-02 05:12:14,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383 to 374. [2018-12-02 05:12:14,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-12-02 05:12:14,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 376 transitions. [2018-12-02 05:12:14,776 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 376 transitions. Word has length 360 [2018-12-02 05:12:14,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:14,777 INFO L480 AbstractCegarLoop]: Abstraction has 374 states and 376 transitions. [2018-12-02 05:12:14,777 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-12-02 05:12:14,777 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 376 transitions. [2018-12-02 05:12:14,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 366 [2018-12-02 05:12:14,780 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:14,780 INFO L402 BasicCegarLoop]: trace histogram [54, 54, 53, 53, 53, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:14,780 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:14,781 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:14,781 INFO L82 PathProgramCache]: Analyzing trace with hash -62569721, now seen corresponding path program 18 times [2018-12-02 05:12:14,781 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:14,781 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:14,782 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:14,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:14,782 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:14,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:15,057 INFO L134 CoverageAnalysis]: Checked inductivity of 7813 backedges. 2200 proven. 207 refuted. 0 times theorem prover too weak. 5406 trivial. 0 not checked. [2018-12-02 05:12:15,058 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:15,058 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:15,058 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:15,058 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:15,058 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:15,058 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:15,064 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:15,064 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:15,137 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:15,137 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:15,142 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:15,144 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:15,146 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:15,150 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:15,150 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:15,159 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:15,169 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:15,169 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:12:15,468 INFO L134 CoverageAnalysis]: Checked inductivity of 7813 backedges. 2200 proven. 207 refuted. 0 times theorem prover too weak. 5406 trivial. 0 not checked. [2018-12-02 05:12:15,468 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:15,744 INFO L134 CoverageAnalysis]: Checked inductivity of 7813 backedges. 2200 proven. 207 refuted. 0 times theorem prover too weak. 5406 trivial. 0 not checked. [2018-12-02 05:12:15,759 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:15,760 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 13] total 36 [2018-12-02 05:12:15,760 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:15,760 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-12-02 05:12:15,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-12-02 05:12:15,760 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=1026, Unknown=0, NotChecked=0, Total=1332 [2018-12-02 05:12:15,760 INFO L87 Difference]: Start difference. First operand 374 states and 376 transitions. Second operand 25 states. [2018-12-02 05:12:16,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:16,206 INFO L93 Difference]: Finished difference Result 387 states and 390 transitions. [2018-12-02 05:12:16,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-02 05:12:16,207 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 365 [2018-12-02 05:12:16,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:16,208 INFO L225 Difference]: With dead ends: 387 [2018-12-02 05:12:16,208 INFO L226 Difference]: Without dead ends: 387 [2018-12-02 05:12:16,208 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 753 GetRequests, 690 SyntacticMatches, 18 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 650 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=530, Invalid=1632, Unknown=0, NotChecked=0, Total=2162 [2018-12-02 05:12:16,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387 states. [2018-12-02 05:12:16,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387 to 379. [2018-12-02 05:12:16,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 379 states. [2018-12-02 05:12:16,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 379 states to 379 states and 382 transitions. [2018-12-02 05:12:16,211 INFO L78 Accepts]: Start accepts. Automaton has 379 states and 382 transitions. Word has length 365 [2018-12-02 05:12:16,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:16,212 INFO L480 AbstractCegarLoop]: Abstraction has 379 states and 382 transitions. [2018-12-02 05:12:16,212 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-12-02 05:12:16,212 INFO L276 IsEmpty]: Start isEmpty. Operand 379 states and 382 transitions. [2018-12-02 05:12:16,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 371 [2018-12-02 05:12:16,213 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:16,213 INFO L402 BasicCegarLoop]: trace histogram [55, 55, 54, 54, 54, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:16,213 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:16,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:16,213 INFO L82 PathProgramCache]: Analyzing trace with hash 1157539302, now seen corresponding path program 19 times [2018-12-02 05:12:16,214 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:16,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:16,214 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:16,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:16,214 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:16,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:16,407 INFO L134 CoverageAnalysis]: Checked inductivity of 8089 backedges. 2664 proven. 203 refuted. 0 times theorem prover too weak. 5222 trivial. 0 not checked. [2018-12-02 05:12:16,407 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:16,407 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:16,407 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:16,407 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:16,407 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:16,407 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:16,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:16,415 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:16,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:16,477 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:16,688 INFO L134 CoverageAnalysis]: Checked inductivity of 8089 backedges. 2683 proven. 184 refuted. 0 times theorem prover too weak. 5222 trivial. 0 not checked. [2018-12-02 05:12:16,688 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:16,876 INFO L134 CoverageAnalysis]: Checked inductivity of 8089 backedges. 2683 proven. 184 refuted. 0 times theorem prover too weak. 5222 trivial. 0 not checked. [2018-12-02 05:12:16,891 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:16,891 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23, 23] total 36 [2018-12-02 05:12:16,892 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:16,892 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-12-02 05:12:16,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-12-02 05:12:16,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=959, Unknown=0, NotChecked=0, Total=1260 [2018-12-02 05:12:16,892 INFO L87 Difference]: Start difference. First operand 379 states and 382 transitions. Second operand 36 states. [2018-12-02 05:12:17,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:17,368 INFO L93 Difference]: Finished difference Result 450 states and 454 transitions. [2018-12-02 05:12:17,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-02 05:12:17,368 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 370 [2018-12-02 05:12:17,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:17,369 INFO L225 Difference]: With dead ends: 450 [2018-12-02 05:12:17,369 INFO L226 Difference]: Without dead ends: 450 [2018-12-02 05:12:17,369 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 782 GetRequests, 708 SyntacticMatches, 21 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 898 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=792, Invalid=2178, Unknown=0, NotChecked=0, Total=2970 [2018-12-02 05:12:17,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-12-02 05:12:17,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 440. [2018-12-02 05:12:17,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 440 states. [2018-12-02 05:12:17,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 444 transitions. [2018-12-02 05:12:17,373 INFO L78 Accepts]: Start accepts. Automaton has 440 states and 444 transitions. Word has length 370 [2018-12-02 05:12:17,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:17,373 INFO L480 AbstractCegarLoop]: Abstraction has 440 states and 444 transitions. [2018-12-02 05:12:17,373 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-12-02 05:12:17,373 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 444 transitions. [2018-12-02 05:12:17,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 427 [2018-12-02 05:12:17,374 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:17,375 INFO L402 BasicCegarLoop]: trace histogram [64, 64, 63, 63, 63, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:17,375 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:17,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:17,375 INFO L82 PathProgramCache]: Analyzing trace with hash 1376752291, now seen corresponding path program 20 times [2018-12-02 05:12:17,375 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:17,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:17,375 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:17,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:17,375 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:17,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:17,605 INFO L134 CoverageAnalysis]: Checked inductivity of 10953 backedges. 5169 proven. 1020 refuted. 0 times theorem prover too weak. 4764 trivial. 0 not checked. [2018-12-02 05:12:17,605 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:17,605 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:17,605 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:17,605 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:17,605 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:17,605 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:17,613 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:17,613 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:17,695 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-12-02 05:12:17,695 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:17,699 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:18,051 INFO L134 CoverageAnalysis]: Checked inductivity of 10953 backedges. 4880 proven. 659 refuted. 0 times theorem prover too weak. 5414 trivial. 0 not checked. [2018-12-02 05:12:18,051 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:18,579 INFO L134 CoverageAnalysis]: Checked inductivity of 10953 backedges. 4880 proven. 659 refuted. 0 times theorem prover too weak. 5414 trivial. 0 not checked. [2018-12-02 05:12:18,593 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:18,594 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27, 27] total 71 [2018-12-02 05:12:18,594 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:18,594 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-02 05:12:18,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-02 05:12:18,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=667, Invalid=4303, Unknown=0, NotChecked=0, Total=4970 [2018-12-02 05:12:18,595 INFO L87 Difference]: Start difference. First operand 440 states and 444 transitions. Second operand 50 states. [2018-12-02 05:12:20,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:20,016 INFO L93 Difference]: Finished difference Result 455 states and 457 transitions. [2018-12-02 05:12:20,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-12-02 05:12:20,016 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 426 [2018-12-02 05:12:20,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:20,017 INFO L225 Difference]: With dead ends: 455 [2018-12-02 05:12:20,017 INFO L226 Difference]: Without dead ends: 449 [2018-12-02 05:12:20,018 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 929 GetRequests, 804 SyntacticMatches, 5 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4752 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2181, Invalid=12581, Unknown=0, NotChecked=0, Total=14762 [2018-12-02 05:12:20,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states. [2018-12-02 05:12:20,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 440. [2018-12-02 05:12:20,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 440 states. [2018-12-02 05:12:20,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 442 transitions. [2018-12-02 05:12:20,022 INFO L78 Accepts]: Start accepts. Automaton has 440 states and 442 transitions. Word has length 426 [2018-12-02 05:12:20,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:20,022 INFO L480 AbstractCegarLoop]: Abstraction has 440 states and 442 transitions. [2018-12-02 05:12:20,022 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-02 05:12:20,022 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 442 transitions. [2018-12-02 05:12:20,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 432 [2018-12-02 05:12:20,023 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:20,023 INFO L402 BasicCegarLoop]: trace histogram [65, 65, 64, 64, 64, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:20,023 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:20,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:20,024 INFO L82 PathProgramCache]: Analyzing trace with hash -1122718684, now seen corresponding path program 21 times [2018-12-02 05:12:20,024 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:20,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:20,024 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:20,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:20,024 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:20,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:20,301 INFO L134 CoverageAnalysis]: Checked inductivity of 11280 backedges. 2970 proven. 255 refuted. 0 times theorem prover too weak. 8055 trivial. 0 not checked. [2018-12-02 05:12:20,301 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:20,301 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:20,301 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:20,301 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:20,301 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:20,301 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:20,307 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:20,307 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:20,397 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:20,397 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:20,402 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:20,404 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:20,407 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:20,411 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:20,412 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:20,427 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:20,446 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:20,446 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:12:20,870 INFO L134 CoverageAnalysis]: Checked inductivity of 11280 backedges. 2970 proven. 255 refuted. 0 times theorem prover too weak. 8055 trivial. 0 not checked. [2018-12-02 05:12:20,871 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:21,183 INFO L134 CoverageAnalysis]: Checked inductivity of 11280 backedges. 2970 proven. 255 refuted. 0 times theorem prover too weak. 8055 trivial. 0 not checked. [2018-12-02 05:12:21,197 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:21,198 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 14] total 39 [2018-12-02 05:12:21,198 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:21,198 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-02 05:12:21,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-02 05:12:21,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=1203, Unknown=0, NotChecked=0, Total=1560 [2018-12-02 05:12:21,198 INFO L87 Difference]: Start difference. First operand 440 states and 442 transitions. Second operand 27 states. [2018-12-02 05:12:21,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:21,655 INFO L93 Difference]: Finished difference Result 453 states and 456 transitions. [2018-12-02 05:12:21,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-02 05:12:21,656 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 431 [2018-12-02 05:12:21,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:21,657 INFO L225 Difference]: With dead ends: 453 [2018-12-02 05:12:21,657 INFO L226 Difference]: Without dead ends: 453 [2018-12-02 05:12:21,658 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 887 GetRequests, 818 SyntacticMatches, 20 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 781 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=620, Invalid=1930, Unknown=0, NotChecked=0, Total=2550 [2018-12-02 05:12:21,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 453 states. [2018-12-02 05:12:21,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 453 to 445. [2018-12-02 05:12:21,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 445 states. [2018-12-02 05:12:21,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 448 transitions. [2018-12-02 05:12:21,663 INFO L78 Accepts]: Start accepts. Automaton has 445 states and 448 transitions. Word has length 431 [2018-12-02 05:12:21,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:21,663 INFO L480 AbstractCegarLoop]: Abstraction has 445 states and 448 transitions. [2018-12-02 05:12:21,663 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-02 05:12:21,664 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 448 transitions. [2018-12-02 05:12:21,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 437 [2018-12-02 05:12:21,666 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:21,666 INFO L402 BasicCegarLoop]: trace histogram [66, 66, 65, 65, 65, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:21,666 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:21,666 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:21,666 INFO L82 PathProgramCache]: Analyzing trace with hash 199583465, now seen corresponding path program 22 times [2018-12-02 05:12:21,666 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:21,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:21,667 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:21,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:21,667 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:21,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:21,923 INFO L134 CoverageAnalysis]: Checked inductivity of 11612 backedges. 3536 proven. 255 refuted. 0 times theorem prover too weak. 7821 trivial. 0 not checked. [2018-12-02 05:12:21,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:21,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:21,923 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:21,923 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:21,924 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:21,924 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:21,929 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:21,929 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:21,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:21,994 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:22,243 INFO L134 CoverageAnalysis]: Checked inductivity of 11612 backedges. 3557 proven. 234 refuted. 0 times theorem prover too weak. 7821 trivial. 0 not checked. [2018-12-02 05:12:22,243 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:22,450 INFO L134 CoverageAnalysis]: Checked inductivity of 11612 backedges. 3557 proven. 234 refuted. 0 times theorem prover too weak. 7821 trivial. 0 not checked. [2018-12-02 05:12:22,464 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:22,465 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 39 [2018-12-02 05:12:22,465 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:22,465 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-12-02 05:12:22,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-12-02 05:12:22,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=352, Invalid=1130, Unknown=0, NotChecked=0, Total=1482 [2018-12-02 05:12:22,466 INFO L87 Difference]: Start difference. First operand 445 states and 448 transitions. Second operand 39 states. [2018-12-02 05:12:22,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:22,989 INFO L93 Difference]: Finished difference Result 521 states and 525 transitions. [2018-12-02 05:12:22,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-02 05:12:22,989 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 436 [2018-12-02 05:12:22,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:22,990 INFO L225 Difference]: With dead ends: 521 [2018-12-02 05:12:22,990 INFO L226 Difference]: Without dead ends: 521 [2018-12-02 05:12:22,991 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 918 GetRequests, 837 SyntacticMatches, 23 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1077 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=937, Invalid=2603, Unknown=0, NotChecked=0, Total=3540 [2018-12-02 05:12:22,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2018-12-02 05:12:22,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 511. [2018-12-02 05:12:22,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 511 states. [2018-12-02 05:12:22,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 511 states to 511 states and 515 transitions. [2018-12-02 05:12:22,994 INFO L78 Accepts]: Start accepts. Automaton has 511 states and 515 transitions. Word has length 436 [2018-12-02 05:12:22,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:22,994 INFO L480 AbstractCegarLoop]: Abstraction has 511 states and 515 transitions. [2018-12-02 05:12:22,994 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-12-02 05:12:22,995 INFO L276 IsEmpty]: Start isEmpty. Operand 511 states and 515 transitions. [2018-12-02 05:12:22,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 498 [2018-12-02 05:12:22,996 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:22,996 INFO L402 BasicCegarLoop]: trace histogram [76, 76, 75, 75, 75, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:22,996 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:22,996 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:22,996 INFO L82 PathProgramCache]: Analyzing trace with hash -398596697, now seen corresponding path program 23 times [2018-12-02 05:12:22,997 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:22,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:22,997 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:22,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:22,997 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:23,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:23,346 INFO L134 CoverageAnalysis]: Checked inductivity of 15385 backedges. 3842 proven. 308 refuted. 0 times theorem prover too weak. 11235 trivial. 0 not checked. [2018-12-02 05:12:23,346 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:23,346 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:23,346 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:23,346 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:23,347 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:23,347 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:23,353 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:23,353 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:23,457 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-12-02 05:12:23,457 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:23,460 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:23,887 INFO L134 CoverageAnalysis]: Checked inductivity of 15385 backedges. 6514 proven. 807 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-02 05:12:23,887 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:24,571 INFO L134 CoverageAnalysis]: Checked inductivity of 15385 backedges. 6514 proven. 807 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-02 05:12:24,585 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:24,586 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 29, 29] total 67 [2018-12-02 05:12:24,586 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:24,586 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-12-02 05:12:24,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-12-02 05:12:24,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=598, Invalid=3824, Unknown=0, NotChecked=0, Total=4422 [2018-12-02 05:12:24,586 INFO L87 Difference]: Start difference. First operand 511 states and 515 transitions. Second operand 44 states. [2018-12-02 05:12:26,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:26,163 INFO L93 Difference]: Finished difference Result 603 states and 609 transitions. [2018-12-02 05:12:26,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-12-02 05:12:26,163 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 497 [2018-12-02 05:12:26,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:26,164 INFO L225 Difference]: With dead ends: 603 [2018-12-02 05:12:26,164 INFO L226 Difference]: Without dead ends: 603 [2018-12-02 05:12:26,165 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1050 GetRequests, 939 SyntacticMatches, 5 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2950 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2110, Invalid=9446, Unknown=0, NotChecked=0, Total=11556 [2018-12-02 05:12:26,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 603 states. [2018-12-02 05:12:26,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 603 to 522. [2018-12-02 05:12:26,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 522 states. [2018-12-02 05:12:26,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 522 states to 522 states and 527 transitions. [2018-12-02 05:12:26,169 INFO L78 Accepts]: Start accepts. Automaton has 522 states and 527 transitions. Word has length 497 [2018-12-02 05:12:26,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:26,170 INFO L480 AbstractCegarLoop]: Abstraction has 522 states and 527 transitions. [2018-12-02 05:12:26,170 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-12-02 05:12:26,170 INFO L276 IsEmpty]: Start isEmpty. Operand 522 states and 527 transitions. [2018-12-02 05:12:26,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 508 [2018-12-02 05:12:26,173 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:26,173 INFO L402 BasicCegarLoop]: trace histogram [78, 78, 77, 77, 77, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:26,173 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:26,173 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:26,174 INFO L82 PathProgramCache]: Analyzing trace with hash 138009825, now seen corresponding path program 24 times [2018-12-02 05:12:26,174 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:26,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:26,174 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:26,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:26,174 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:26,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:26,582 INFO L134 CoverageAnalysis]: Checked inductivity of 16166 backedges. 4235 proven. 366 refuted. 0 times theorem prover too weak. 11565 trivial. 0 not checked. [2018-12-02 05:12:26,582 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:26,583 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:26,583 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:26,583 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:26,583 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:26,583 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:26,588 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:26,588 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:26,653 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:26,653 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:26,657 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:27,081 INFO L134 CoverageAnalysis]: Checked inductivity of 16166 backedges. 4486 proven. 1159 refuted. 0 times theorem prover too weak. 10521 trivial. 0 not checked. [2018-12-02 05:12:27,081 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:27,617 INFO L134 CoverageAnalysis]: Checked inductivity of 16166 backedges. 4486 proven. 1159 refuted. 0 times theorem prover too weak. 10521 trivial. 0 not checked. [2018-12-02 05:12:27,631 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:27,632 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 31, 31] total 63 [2018-12-02 05:12:27,632 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:27,632 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-12-02 05:12:27,632 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-12-02 05:12:27,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=521, Invalid=3385, Unknown=0, NotChecked=0, Total=3906 [2018-12-02 05:12:27,632 INFO L87 Difference]: Start difference. First operand 522 states and 527 transitions. Second operand 47 states. [2018-12-02 05:12:30,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:30,486 INFO L93 Difference]: Finished difference Result 698 states and 709 transitions. [2018-12-02 05:12:30,486 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-12-02 05:12:30,486 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 507 [2018-12-02 05:12:30,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:30,487 INFO L225 Difference]: With dead ends: 698 [2018-12-02 05:12:30,487 INFO L226 Difference]: Without dead ends: 698 [2018-12-02 05:12:30,488 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1086 GetRequests, 966 SyntacticMatches, 14 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3146 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=1579, Invalid=9977, Unknown=0, NotChecked=0, Total=11556 [2018-12-02 05:12:30,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 698 states. [2018-12-02 05:12:30,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 698 to 676. [2018-12-02 05:12:30,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 676 states. [2018-12-02 05:12:30,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 676 states to 676 states and 687 transitions. [2018-12-02 05:12:30,493 INFO L78 Accepts]: Start accepts. Automaton has 676 states and 687 transitions. Word has length 507 [2018-12-02 05:12:30,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:30,493 INFO L480 AbstractCegarLoop]: Abstraction has 676 states and 687 transitions. [2018-12-02 05:12:30,493 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-12-02 05:12:30,493 INFO L276 IsEmpty]: Start isEmpty. Operand 676 states and 687 transitions. [2018-12-02 05:12:30,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 574 [2018-12-02 05:12:30,495 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:30,495 INFO L402 BasicCegarLoop]: trace histogram [89, 89, 88, 88, 88, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:30,495 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:30,495 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:30,495 INFO L82 PathProgramCache]: Analyzing trace with hash -1361082870, now seen corresponding path program 25 times [2018-12-02 05:12:30,495 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:30,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:30,496 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:30,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:30,496 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:30,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:30,803 INFO L134 CoverageAnalysis]: Checked inductivity of 21021 backedges. 8365 proven. 2007 refuted. 0 times theorem prover too weak. 10649 trivial. 0 not checked. [2018-12-02 05:12:30,803 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:30,803 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:30,803 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:30,803 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:30,803 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:30,803 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:30,812 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:30,812 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:30,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:30,897 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:31,150 INFO L134 CoverageAnalysis]: Checked inductivity of 21021 backedges. 11472 proven. 235 refuted. 0 times theorem prover too weak. 9314 trivial. 0 not checked. [2018-12-02 05:12:31,150 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:31,544 INFO L134 CoverageAnalysis]: Checked inductivity of 21021 backedges. 8491 proven. 810 refuted. 0 times theorem prover too weak. 11720 trivial. 0 not checked. [2018-12-02 05:12:31,558 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:31,559 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 24, 24] total 51 [2018-12-02 05:12:31,559 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:31,559 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-12-02 05:12:31,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-12-02 05:12:31,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=531, Invalid=2019, Unknown=0, NotChecked=0, Total=2550 [2018-12-02 05:12:31,560 INFO L87 Difference]: Start difference. First operand 676 states and 687 transitions. Second operand 40 states. [2018-12-02 05:12:32,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:32,174 INFO L93 Difference]: Finished difference Result 604 states and 609 transitions. [2018-12-02 05:12:32,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-12-02 05:12:32,174 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 573 [2018-12-02 05:12:32,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:32,175 INFO L225 Difference]: With dead ends: 604 [2018-12-02 05:12:32,175 INFO L226 Difference]: Without dead ends: 595 [2018-12-02 05:12:32,176 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1198 GetRequests, 1113 SyntacticMatches, 12 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1804 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1296, Invalid=4254, Unknown=0, NotChecked=0, Total=5550 [2018-12-02 05:12:32,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 595 states. [2018-12-02 05:12:32,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 595 to 592. [2018-12-02 05:12:32,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 592 states. [2018-12-02 05:12:32,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 592 states and 597 transitions. [2018-12-02 05:12:32,179 INFO L78 Accepts]: Start accepts. Automaton has 592 states and 597 transitions. Word has length 573 [2018-12-02 05:12:32,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:32,179 INFO L480 AbstractCegarLoop]: Abstraction has 592 states and 597 transitions. [2018-12-02 05:12:32,179 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-12-02 05:12:32,179 INFO L276 IsEmpty]: Start isEmpty. Operand 592 states and 597 transitions. [2018-12-02 05:12:32,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 579 [2018-12-02 05:12:32,181 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:32,181 INFO L402 BasicCegarLoop]: trace histogram [90, 90, 89, 89, 89, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:32,181 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:32,181 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:32,182 INFO L82 PathProgramCache]: Analyzing trace with hash -1751763953, now seen corresponding path program 26 times [2018-12-02 05:12:32,182 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:32,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:32,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:32,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:32,182 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:32,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:32,525 INFO L134 CoverageAnalysis]: Checked inductivity of 21475 backedges. 9333 proven. 1499 refuted. 0 times theorem prover too weak. 10643 trivial. 0 not checked. [2018-12-02 05:12:32,525 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:32,525 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:32,525 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:32,525 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:32,525 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:32,525 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:32,531 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:32,531 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:32,642 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-12-02 05:12:32,642 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:32,647 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:32,649 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:32,651 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:32,654 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:32,655 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:32,661 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:32,669 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:32,669 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:12:33,656 INFO L134 CoverageAnalysis]: Checked inductivity of 21475 backedges. 8423 proven. 1074 refuted. 0 times theorem prover too weak. 11978 trivial. 0 not checked. [2018-12-02 05:12:33,656 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:34,695 INFO L134 CoverageAnalysis]: Checked inductivity of 21475 backedges. 8361 proven. 1136 refuted. 0 times theorem prover too weak. 11978 trivial. 0 not checked. [2018-12-02 05:12:34,710 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:34,710 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 22, 21] total 71 [2018-12-02 05:12:34,710 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:34,711 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-12-02 05:12:34,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-12-02 05:12:34,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=695, Invalid=4275, Unknown=0, NotChecked=0, Total=4970 [2018-12-02 05:12:34,711 INFO L87 Difference]: Start difference. First operand 592 states and 597 transitions. Second operand 51 states. [2018-12-02 05:12:37,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:37,874 INFO L93 Difference]: Finished difference Result 605 states and 608 transitions. [2018-12-02 05:12:37,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-12-02 05:12:37,875 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 578 [2018-12-02 05:12:37,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:37,876 INFO L225 Difference]: With dead ends: 605 [2018-12-02 05:12:37,876 INFO L226 Difference]: Without dead ends: 599 [2018-12-02 05:12:37,876 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1250 GetRequests, 1096 SyntacticMatches, 21 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6192 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=2969, Invalid=15121, Unknown=0, NotChecked=0, Total=18090 [2018-12-02 05:12:37,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 599 states. [2018-12-02 05:12:37,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 599 to 592. [2018-12-02 05:12:37,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 592 states. [2018-12-02 05:12:37,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 592 states and 595 transitions. [2018-12-02 05:12:37,879 INFO L78 Accepts]: Start accepts. Automaton has 592 states and 595 transitions. Word has length 578 [2018-12-02 05:12:37,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:37,880 INFO L480 AbstractCegarLoop]: Abstraction has 592 states and 595 transitions. [2018-12-02 05:12:37,880 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-12-02 05:12:37,880 INFO L276 IsEmpty]: Start isEmpty. Operand 592 states and 595 transitions. [2018-12-02 05:12:37,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 584 [2018-12-02 05:12:37,882 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:37,882 INFO L402 BasicCegarLoop]: trace histogram [91, 91, 90, 90, 90, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:37,882 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:37,882 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:37,882 INFO L82 PathProgramCache]: Analyzing trace with hash -1053710780, now seen corresponding path program 27 times [2018-12-02 05:12:37,882 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:37,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:37,882 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:37,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:37,883 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:37,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:38,206 INFO L134 CoverageAnalysis]: Checked inductivity of 21934 backedges. 5805 proven. 377 refuted. 0 times theorem prover too weak. 15752 trivial. 0 not checked. [2018-12-02 05:12:38,206 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:38,206 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:38,206 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:38,206 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:38,206 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:38,206 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:38,212 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:38,212 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:38,291 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:38,291 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:38,296 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:38,703 INFO L134 CoverageAnalysis]: Checked inductivity of 21934 backedges. 5706 proven. 1368 refuted. 0 times theorem prover too weak. 14860 trivial. 0 not checked. [2018-12-02 05:12:38,703 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:39,061 INFO L134 CoverageAnalysis]: Checked inductivity of 21934 backedges. 5706 proven. 1368 refuted. 0 times theorem prover too weak. 14860 trivial. 0 not checked. [2018-12-02 05:12:39,075 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:39,076 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 33, 33] total 52 [2018-12-02 05:12:39,076 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:39,076 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-02 05:12:39,076 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-02 05:12:39,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=2156, Unknown=0, NotChecked=0, Total=2652 [2018-12-02 05:12:39,076 INFO L87 Difference]: Start difference. First operand 592 states and 595 transitions. Second operand 49 states. [2018-12-02 05:12:39,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:39,799 INFO L93 Difference]: Finished difference Result 678 states and 682 transitions. [2018-12-02 05:12:39,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-12-02 05:12:39,799 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 583 [2018-12-02 05:12:39,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:39,800 INFO L225 Difference]: With dead ends: 678 [2018-12-02 05:12:39,800 INFO L226 Difference]: Without dead ends: 678 [2018-12-02 05:12:39,801 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1222 GetRequests, 1116 SyntacticMatches, 29 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2013 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1282, Invalid=4880, Unknown=0, NotChecked=0, Total=6162 [2018-12-02 05:12:39,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2018-12-02 05:12:39,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 668. [2018-12-02 05:12:39,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 668 states. [2018-12-02 05:12:39,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 668 states and 672 transitions. [2018-12-02 05:12:39,805 INFO L78 Accepts]: Start accepts. Automaton has 668 states and 672 transitions. Word has length 583 [2018-12-02 05:12:39,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:39,805 INFO L480 AbstractCegarLoop]: Abstraction has 668 states and 672 transitions. [2018-12-02 05:12:39,805 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-02 05:12:39,805 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 672 transitions. [2018-12-02 05:12:39,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 655 [2018-12-02 05:12:39,808 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:39,808 INFO L402 BasicCegarLoop]: trace histogram [103, 103, 102, 102, 102, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:39,808 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:39,808 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:39,808 INFO L82 PathProgramCache]: Analyzing trace with hash 1839611212, now seen corresponding path program 28 times [2018-12-02 05:12:39,808 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:39,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:39,809 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:39,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:39,809 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:39,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:40,220 INFO L134 CoverageAnalysis]: Checked inductivity of 28059 backedges. 14877 proven. 1167 refuted. 0 times theorem prover too weak. 12015 trivial. 0 not checked. [2018-12-02 05:12:40,220 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:40,220 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:40,220 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:40,221 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:40,221 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:40,221 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:40,226 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:40,226 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:40,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:40,325 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:40,729 INFO L134 CoverageAnalysis]: Checked inductivity of 28059 backedges. 11525 proven. 342 refuted. 0 times theorem prover too weak. 16192 trivial. 0 not checked. [2018-12-02 05:12:40,730 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:41,297 INFO L134 CoverageAnalysis]: Checked inductivity of 28059 backedges. 11525 proven. 342 refuted. 0 times theorem prover too weak. 16192 trivial. 0 not checked. [2018-12-02 05:12:41,312 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:41,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 28, 28] total 68 [2018-12-02 05:12:41,312 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:41,312 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-12-02 05:12:41,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-12-02 05:12:41,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=797, Invalid=3759, Unknown=0, NotChecked=0, Total=4556 [2018-12-02 05:12:41,313 INFO L87 Difference]: Start difference. First operand 668 states and 672 transitions. Second operand 55 states. [2018-12-02 05:12:42,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:42,456 INFO L93 Difference]: Finished difference Result 679 states and 681 transitions. [2018-12-02 05:12:42,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-02 05:12:42,456 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 654 [2018-12-02 05:12:42,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:42,457 INFO L225 Difference]: With dead ends: 679 [2018-12-02 05:12:42,458 INFO L226 Difference]: Without dead ends: 673 [2018-12-02 05:12:42,458 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1377 GetRequests, 1260 SyntacticMatches, 14 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4358 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2046, Invalid=8874, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 05:12:42,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 673 states. [2018-12-02 05:12:42,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 673 to 668. [2018-12-02 05:12:42,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 668 states. [2018-12-02 05:12:42,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 668 states and 670 transitions. [2018-12-02 05:12:42,462 INFO L78 Accepts]: Start accepts. Automaton has 668 states and 670 transitions. Word has length 654 [2018-12-02 05:12:42,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:42,462 INFO L480 AbstractCegarLoop]: Abstraction has 668 states and 670 transitions. [2018-12-02 05:12:42,462 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-12-02 05:12:42,462 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 670 transitions. [2018-12-02 05:12:42,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 660 [2018-12-02 05:12:42,464 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:42,464 INFO L402 BasicCegarLoop]: trace histogram [104, 104, 103, 103, 103, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:42,464 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:42,464 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:42,465 INFO L82 PathProgramCache]: Analyzing trace with hash -120136921, now seen corresponding path program 29 times [2018-12-02 05:12:42,465 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:42,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:42,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:42,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:42,465 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:42,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:42,911 INFO L134 CoverageAnalysis]: Checked inductivity of 28584 backedges. 6300 proven. 429 refuted. 0 times theorem prover too weak. 21855 trivial. 0 not checked. [2018-12-02 05:12:42,911 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:42,911 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:42,911 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:42,912 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:42,912 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:42,912 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:42,917 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:42,917 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:43,035 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-12-02 05:12:43,036 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:43,040 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:43,042 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:43,044 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:43,058 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:43,059 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:43,064 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:43,070 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:43,070 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:12:43,697 INFO L134 CoverageAnalysis]: Checked inductivity of 28584 backedges. 6300 proven. 429 refuted. 0 times theorem prover too weak. 21855 trivial. 0 not checked. [2018-12-02 05:12:43,697 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:44,354 INFO L134 CoverageAnalysis]: Checked inductivity of 28584 backedges. 6300 proven. 429 refuted. 0 times theorem prover too weak. 21855 trivial. 0 not checked. [2018-12-02 05:12:44,368 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:44,369 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 18] total 37 [2018-12-02 05:12:44,369 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:44,369 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-12-02 05:12:44,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-12-02 05:12:44,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=518, Invalid=888, Unknown=0, NotChecked=0, Total=1406 [2018-12-02 05:12:44,369 INFO L87 Difference]: Start difference. First operand 668 states and 670 transitions. Second operand 21 states. [2018-12-02 05:12:44,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:44,673 INFO L93 Difference]: Finished difference Result 681 states and 684 transitions. [2018-12-02 05:12:44,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-12-02 05:12:44,674 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 659 [2018-12-02 05:12:44,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:44,675 INFO L225 Difference]: With dead ends: 681 [2018-12-02 05:12:44,675 INFO L226 Difference]: Without dead ends: 681 [2018-12-02 05:12:44,675 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1349 GetRequests, 1273 SyntacticMatches, 26 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 385 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1009, Invalid=1643, Unknown=0, NotChecked=0, Total=2652 [2018-12-02 05:12:44,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states. [2018-12-02 05:12:44,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 673. [2018-12-02 05:12:44,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2018-12-02 05:12:44,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 676 transitions. [2018-12-02 05:12:44,679 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 676 transitions. Word has length 659 [2018-12-02 05:12:44,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:44,679 INFO L480 AbstractCegarLoop]: Abstraction has 673 states and 676 transitions. [2018-12-02 05:12:44,679 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-12-02 05:12:44,679 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 676 transitions. [2018-12-02 05:12:44,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 665 [2018-12-02 05:12:44,681 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:44,682 INFO L402 BasicCegarLoop]: trace histogram [105, 105, 104, 104, 104, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:44,682 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:44,682 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:44,682 INFO L82 PathProgramCache]: Analyzing trace with hash 306651590, now seen corresponding path program 30 times [2018-12-02 05:12:44,682 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:44,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:44,683 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:44,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:44,683 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:44,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:45,040 INFO L134 CoverageAnalysis]: Checked inductivity of 29114 backedges. 7232 proven. 447 refuted. 0 times theorem prover too weak. 21435 trivial. 0 not checked. [2018-12-02 05:12:45,040 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:45,040 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:45,040 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:45,040 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:45,040 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:45,041 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:45,046 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:45,046 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:45,129 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:45,130 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:45,135 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:45,604 INFO L134 CoverageAnalysis]: Checked inductivity of 29114 backedges. 7126 proven. 1594 refuted. 0 times theorem prover too weak. 20394 trivial. 0 not checked. [2018-12-02 05:12:45,605 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:46,043 INFO L134 CoverageAnalysis]: Checked inductivity of 29114 backedges. 7126 proven. 1594 refuted. 0 times theorem prover too weak. 20394 trivial. 0 not checked. [2018-12-02 05:12:46,057 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:46,058 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 35, 35] total 55 [2018-12-02 05:12:46,058 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:46,058 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-12-02 05:12:46,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-12-02 05:12:46,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=559, Invalid=2411, Unknown=0, NotChecked=0, Total=2970 [2018-12-02 05:12:46,058 INFO L87 Difference]: Start difference. First operand 673 states and 676 transitions. Second operand 52 states. [2018-12-02 05:12:46,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:46,891 INFO L93 Difference]: Finished difference Result 764 states and 768 transitions. [2018-12-02 05:12:46,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-12-02 05:12:46,891 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 664 [2018-12-02 05:12:46,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:46,893 INFO L225 Difference]: With dead ends: 764 [2018-12-02 05:12:46,893 INFO L226 Difference]: Without dead ends: 764 [2018-12-02 05:12:46,893 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1388 GetRequests, 1275 SyntacticMatches, 31 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2281 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1458, Invalid=5514, Unknown=0, NotChecked=0, Total=6972 [2018-12-02 05:12:46,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 764 states. [2018-12-02 05:12:46,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 764 to 754. [2018-12-02 05:12:46,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 754 states. [2018-12-02 05:12:46,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 758 transitions. [2018-12-02 05:12:46,899 INFO L78 Accepts]: Start accepts. Automaton has 754 states and 758 transitions. Word has length 664 [2018-12-02 05:12:46,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:46,899 INFO L480 AbstractCegarLoop]: Abstraction has 754 states and 758 transitions. [2018-12-02 05:12:46,899 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-12-02 05:12:46,899 INFO L276 IsEmpty]: Start isEmpty. Operand 754 states and 758 transitions. [2018-12-02 05:12:46,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 741 [2018-12-02 05:12:46,902 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:46,903 INFO L402 BasicCegarLoop]: trace histogram [118, 118, 117, 117, 117, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:46,903 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:46,903 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:46,903 INFO L82 PathProgramCache]: Analyzing trace with hash -1843296445, now seen corresponding path program 31 times [2018-12-02 05:12:46,903 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:46,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:46,904 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:46,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:46,904 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:46,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:47,385 INFO L134 CoverageAnalysis]: Checked inductivity of 36712 backedges. 14191 proven. 2062 refuted. 0 times theorem prover too weak. 20459 trivial. 0 not checked. [2018-12-02 05:12:47,385 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:47,385 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:47,385 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:47,385 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:47,385 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:47,386 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:47,393 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:47,393 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:47,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:47,502 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:47,902 INFO L134 CoverageAnalysis]: Checked inductivity of 36712 backedges. 14365 proven. 403 refuted. 0 times theorem prover too weak. 21944 trivial. 0 not checked. [2018-12-02 05:12:47,902 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:48,487 INFO L134 CoverageAnalysis]: Checked inductivity of 36712 backedges. 14365 proven. 403 refuted. 0 times theorem prover too weak. 21944 trivial. 0 not checked. [2018-12-02 05:12:48,501 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:48,502 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 30, 30] total 63 [2018-12-02 05:12:48,502 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:48,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-02 05:12:48,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-02 05:12:48,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=819, Invalid=3087, Unknown=0, NotChecked=0, Total=3906 [2018-12-02 05:12:48,503 INFO L87 Difference]: Start difference. First operand 754 states and 758 transitions. Second operand 49 states. [2018-12-02 05:12:49,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:49,274 INFO L93 Difference]: Finished difference Result 765 states and 767 transitions. [2018-12-02 05:12:49,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-02 05:12:49,274 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 740 [2018-12-02 05:12:49,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:49,275 INFO L225 Difference]: With dead ends: 765 [2018-12-02 05:12:49,275 INFO L226 Difference]: Without dead ends: 759 [2018-12-02 05:12:49,275 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1544 GetRequests, 1438 SyntacticMatches, 15 SemanticMatches, 91 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2911 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2001, Invalid=6555, Unknown=0, NotChecked=0, Total=8556 [2018-12-02 05:12:49,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 759 states. [2018-12-02 05:12:49,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 759 to 754. [2018-12-02 05:12:49,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 754 states. [2018-12-02 05:12:49,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 756 transitions. [2018-12-02 05:12:49,279 INFO L78 Accepts]: Start accepts. Automaton has 754 states and 756 transitions. Word has length 740 [2018-12-02 05:12:49,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:49,280 INFO L480 AbstractCegarLoop]: Abstraction has 754 states and 756 transitions. [2018-12-02 05:12:49,280 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-02 05:12:49,280 INFO L276 IsEmpty]: Start isEmpty. Operand 754 states and 756 transitions. [2018-12-02 05:12:49,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 746 [2018-12-02 05:12:49,282 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:49,282 INFO L402 BasicCegarLoop]: trace histogram [119, 119, 118, 118, 118, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:49,283 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:49,283 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:49,283 INFO L82 PathProgramCache]: Analyzing trace with hash -1981355388, now seen corresponding path program 32 times [2018-12-02 05:12:49,283 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:49,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:49,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:49,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:49,283 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:49,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:49,785 INFO L134 CoverageAnalysis]: Checked inductivity of 37313 backedges. 7800 proven. 497 refuted. 0 times theorem prover too weak. 29016 trivial. 0 not checked. [2018-12-02 05:12:49,785 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:49,786 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:49,786 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:49,786 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:49,786 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:49,786 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:49,793 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:49,793 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:49,953 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-12-02 05:12:49,953 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:49,959 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:49,961 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:49,963 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:49,967 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:49,967 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:49,972 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:49,978 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:49,979 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:12:50,750 INFO L134 CoverageAnalysis]: Checked inductivity of 37313 backedges. 7800 proven. 497 refuted. 0 times theorem prover too weak. 29016 trivial. 0 not checked. [2018-12-02 05:12:50,750 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:51,480 INFO L134 CoverageAnalysis]: Checked inductivity of 37313 backedges. 7800 proven. 497 refuted. 0 times theorem prover too weak. 29016 trivial. 0 not checked. [2018-12-02 05:12:51,495 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:51,496 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 19] total 39 [2018-12-02 05:12:51,496 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:51,496 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-12-02 05:12:51,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-12-02 05:12:51,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=583, Invalid=977, Unknown=0, NotChecked=0, Total=1560 [2018-12-02 05:12:51,497 INFO L87 Difference]: Start difference. First operand 754 states and 756 transitions. Second operand 22 states. [2018-12-02 05:12:51,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:51,849 INFO L93 Difference]: Finished difference Result 767 states and 770 transitions. [2018-12-02 05:12:51,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-02 05:12:51,850 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 745 [2018-12-02 05:12:51,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:51,851 INFO L225 Difference]: With dead ends: 767 [2018-12-02 05:12:51,851 INFO L226 Difference]: Without dead ends: 767 [2018-12-02 05:12:51,851 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1523 GetRequests, 1442 SyntacticMatches, 28 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 420 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1139, Invalid=1831, Unknown=0, NotChecked=0, Total=2970 [2018-12-02 05:12:51,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 767 states. [2018-12-02 05:12:51,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 767 to 759. [2018-12-02 05:12:51,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 759 states. [2018-12-02 05:12:51,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 759 states to 759 states and 762 transitions. [2018-12-02 05:12:51,856 INFO L78 Accepts]: Start accepts. Automaton has 759 states and 762 transitions. Word has length 745 [2018-12-02 05:12:51,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:51,856 INFO L480 AbstractCegarLoop]: Abstraction has 759 states and 762 transitions. [2018-12-02 05:12:51,856 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-12-02 05:12:51,856 INFO L276 IsEmpty]: Start isEmpty. Operand 759 states and 762 transitions. [2018-12-02 05:12:51,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 751 [2018-12-02 05:12:51,859 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:51,859 INFO L402 BasicCegarLoop]: trace histogram [120, 120, 119, 119, 119, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:51,859 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:51,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:51,859 INFO L82 PathProgramCache]: Analyzing trace with hash -493149047, now seen corresponding path program 33 times [2018-12-02 05:12:51,859 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:51,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:51,860 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:51,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:51,860 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:51,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:52,326 INFO L134 CoverageAnalysis]: Checked inductivity of 37919 backedges. 8874 proven. 523 refuted. 0 times theorem prover too weak. 28522 trivial. 0 not checked. [2018-12-02 05:12:52,326 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:52,327 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:52,327 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:52,327 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:52,327 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:52,327 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:52,333 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:12:52,333 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:12:52,427 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:12:52,427 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:52,433 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:52,991 INFO L134 CoverageAnalysis]: Checked inductivity of 37919 backedges. 8761 proven. 1837 refuted. 0 times theorem prover too weak. 27321 trivial. 0 not checked. [2018-12-02 05:12:52,991 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:53,480 INFO L134 CoverageAnalysis]: Checked inductivity of 37919 backedges. 8761 proven. 1837 refuted. 0 times theorem prover too weak. 27321 trivial. 0 not checked. [2018-12-02 05:12:53,503 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:53,504 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 37, 37] total 58 [2018-12-02 05:12:53,504 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:53,504 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-12-02 05:12:53,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-12-02 05:12:53,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=626, Invalid=2680, Unknown=0, NotChecked=0, Total=3306 [2018-12-02 05:12:53,504 INFO L87 Difference]: Start difference. First operand 759 states and 762 transitions. Second operand 55 states. [2018-12-02 05:12:54,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:54,335 INFO L93 Difference]: Finished difference Result 855 states and 859 transitions. [2018-12-02 05:12:54,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-12-02 05:12:54,335 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 750 [2018-12-02 05:12:54,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:54,337 INFO L225 Difference]: With dead ends: 855 [2018-12-02 05:12:54,337 INFO L226 Difference]: Without dead ends: 855 [2018-12-02 05:12:54,337 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1564 GetRequests, 1444 SyntacticMatches, 33 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2565 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1646, Invalid=6186, Unknown=0, NotChecked=0, Total=7832 [2018-12-02 05:12:54,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 855 states. [2018-12-02 05:12:54,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 855 to 845. [2018-12-02 05:12:54,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-12-02 05:12:54,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 849 transitions. [2018-12-02 05:12:54,342 INFO L78 Accepts]: Start accepts. Automaton has 845 states and 849 transitions. Word has length 750 [2018-12-02 05:12:54,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:54,342 INFO L480 AbstractCegarLoop]: Abstraction has 845 states and 849 transitions. [2018-12-02 05:12:54,342 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-12-02 05:12:54,342 INFO L276 IsEmpty]: Start isEmpty. Operand 845 states and 849 transitions. [2018-12-02 05:12:54,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 832 [2018-12-02 05:12:54,345 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:54,345 INFO L402 BasicCegarLoop]: trace histogram [134, 134, 133, 133, 133, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:54,345 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:54,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:54,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1588837063, now seen corresponding path program 34 times [2018-12-02 05:12:54,346 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:54,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:54,346 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:12:54,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:54,346 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:54,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:54,922 INFO L134 CoverageAnalysis]: Checked inductivity of 47208 backedges. 23186 proven. 1572 refuted. 0 times theorem prover too weak. 22450 trivial. 0 not checked. [2018-12-02 05:12:54,922 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:54,922 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:54,922 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:54,922 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:54,922 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:54,922 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:54,928 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:54,928 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:12:55,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:55,051 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:55,611 INFO L134 CoverageAnalysis]: Checked inductivity of 47208 backedges. 17634 proven. 469 refuted. 0 times theorem prover too weak. 29105 trivial. 0 not checked. [2018-12-02 05:12:55,611 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:12:56,374 INFO L134 CoverageAnalysis]: Checked inductivity of 47208 backedges. 17634 proven. 469 refuted. 0 times theorem prover too weak. 29105 trivial. 0 not checked. [2018-12-02 05:12:56,388 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:12:56,389 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 32, 32] total 78 [2018-12-02 05:12:56,389 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:12:56,389 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-12-02 05:12:56,389 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-12-02 05:12:56,389 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1039, Invalid=4967, Unknown=0, NotChecked=0, Total=6006 [2018-12-02 05:12:56,390 INFO L87 Difference]: Start difference. First operand 845 states and 849 transitions. Second operand 63 states. [2018-12-02 05:12:58,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:12:58,595 INFO L93 Difference]: Finished difference Result 856 states and 858 transitions. [2018-12-02 05:12:58,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-12-02 05:12:58,595 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 831 [2018-12-02 05:12:58,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:12:58,597 INFO L225 Difference]: With dead ends: 856 [2018-12-02 05:12:58,597 INFO L226 Difference]: Without dead ends: 850 [2018-12-02 05:12:58,598 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1741 GetRequests, 1606 SyntacticMatches, 16 SemanticMatches, 119 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5956 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2677, Invalid=11843, Unknown=0, NotChecked=0, Total=14520 [2018-12-02 05:12:58,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states. [2018-12-02 05:12:58,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 845. [2018-12-02 05:12:58,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-12-02 05:12:58,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 847 transitions. [2018-12-02 05:12:58,604 INFO L78 Accepts]: Start accepts. Automaton has 845 states and 847 transitions. Word has length 831 [2018-12-02 05:12:58,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:12:58,604 INFO L480 AbstractCegarLoop]: Abstraction has 845 states and 847 transitions. [2018-12-02 05:12:58,604 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-12-02 05:12:58,604 INFO L276 IsEmpty]: Start isEmpty. Operand 845 states and 847 transitions. [2018-12-02 05:12:58,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 837 [2018-12-02 05:12:58,608 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:12:58,609 INFO L402 BasicCegarLoop]: trace histogram [135, 135, 134, 134, 134, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:12:58,609 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:12:58,609 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:12:58,609 INFO L82 PathProgramCache]: Analyzing trace with hash -1695298804, now seen corresponding path program 35 times [2018-12-02 05:12:58,609 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:12:58,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:58,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:12:58,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:12:58,610 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:12:58,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:12:59,237 INFO L134 CoverageAnalysis]: Checked inductivity of 47890 backedges. 9520 proven. 570 refuted. 0 times theorem prover too weak. 37800 trivial. 0 not checked. [2018-12-02 05:12:59,237 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:59,237 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:12:59,238 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:12:59,238 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:12:59,238 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:12:59,238 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:12:59,245 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:12:59,245 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:12:59,416 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-12-02 05:12:59,416 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:12:59,422 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:12:59,425 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:12:59,427 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:12:59,432 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:12:59,432 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:12:59,438 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:12:59,444 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:12:59,444 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:13:00,337 INFO L134 CoverageAnalysis]: Checked inductivity of 47890 backedges. 9520 proven. 570 refuted. 0 times theorem prover too weak. 37800 trivial. 0 not checked. [2018-12-02 05:13:00,337 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:01,171 INFO L134 CoverageAnalysis]: Checked inductivity of 47890 backedges. 9520 proven. 570 refuted. 0 times theorem prover too weak. 37800 trivial. 0 not checked. [2018-12-02 05:13:01,186 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:01,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 21, 20] total 41 [2018-12-02 05:13:01,186 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:01,187 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-12-02 05:13:01,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-12-02 05:13:01,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=652, Invalid=1070, Unknown=0, NotChecked=0, Total=1722 [2018-12-02 05:13:01,187 INFO L87 Difference]: Start difference. First operand 845 states and 847 transitions. Second operand 23 states. [2018-12-02 05:13:01,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:01,543 INFO L93 Difference]: Finished difference Result 858 states and 861 transitions. [2018-12-02 05:13:01,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-12-02 05:13:01,543 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 836 [2018-12-02 05:13:01,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:01,544 INFO L225 Difference]: With dead ends: 858 [2018-12-02 05:13:01,544 INFO L226 Difference]: Without dead ends: 858 [2018-12-02 05:13:01,545 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1707 GetRequests, 1621 SyntacticMatches, 30 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 456 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1277, Invalid=2029, Unknown=0, NotChecked=0, Total=3306 [2018-12-02 05:13:01,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 858 states. [2018-12-02 05:13:01,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 858 to 850. [2018-12-02 05:13:01,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 850 states. [2018-12-02 05:13:01,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 853 transitions. [2018-12-02 05:13:01,549 INFO L78 Accepts]: Start accepts. Automaton has 850 states and 853 transitions. Word has length 836 [2018-12-02 05:13:01,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:01,549 INFO L480 AbstractCegarLoop]: Abstraction has 850 states and 853 transitions. [2018-12-02 05:13:01,549 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-12-02 05:13:01,549 INFO L276 IsEmpty]: Start isEmpty. Operand 850 states and 853 transitions. [2018-12-02 05:13:01,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 842 [2018-12-02 05:13:01,552 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:01,553 INFO L402 BasicCegarLoop]: trace histogram [136, 136, 135, 135, 135, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:01,553 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:01,553 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:01,553 INFO L82 PathProgramCache]: Analyzing trace with hash -1095935743, now seen corresponding path program 36 times [2018-12-02 05:13:01,553 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:01,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:01,553 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:01,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:01,553 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:01,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:02,091 INFO L134 CoverageAnalysis]: Checked inductivity of 48577 backedges. 10746 proven. 605 refuted. 0 times theorem prover too weak. 37226 trivial. 0 not checked. [2018-12-02 05:13:02,091 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:02,092 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:02,092 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:02,092 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:02,092 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:02,092 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:02,097 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:13:02,097 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:13:02,203 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:13:02,203 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:02,209 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:02,795 INFO L134 CoverageAnalysis]: Checked inductivity of 48577 backedges. 10626 proven. 2097 refuted. 0 times theorem prover too weak. 35854 trivial. 0 not checked. [2018-12-02 05:13:02,795 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:03,375 INFO L134 CoverageAnalysis]: Checked inductivity of 48577 backedges. 10626 proven. 2097 refuted. 0 times theorem prover too weak. 35854 trivial. 0 not checked. [2018-12-02 05:13:03,390 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:03,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 39, 39] total 61 [2018-12-02 05:13:03,391 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:03,391 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-12-02 05:13:03,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-12-02 05:13:03,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=697, Invalid=2963, Unknown=0, NotChecked=0, Total=3660 [2018-12-02 05:13:03,392 INFO L87 Difference]: Start difference. First operand 850 states and 853 transitions. Second operand 58 states. [2018-12-02 05:13:04,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:04,397 INFO L93 Difference]: Finished difference Result 951 states and 955 transitions. [2018-12-02 05:13:04,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-12-02 05:13:04,398 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 841 [2018-12-02 05:13:04,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:04,399 INFO L225 Difference]: With dead ends: 951 [2018-12-02 05:13:04,399 INFO L226 Difference]: Without dead ends: 951 [2018-12-02 05:13:04,400 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1750 GetRequests, 1623 SyntacticMatches, 35 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2865 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1846, Invalid=6896, Unknown=0, NotChecked=0, Total=8742 [2018-12-02 05:13:04,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 951 states. [2018-12-02 05:13:04,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 951 to 941. [2018-12-02 05:13:04,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 941 states. [2018-12-02 05:13:04,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 941 states to 941 states and 945 transitions. [2018-12-02 05:13:04,406 INFO L78 Accepts]: Start accepts. Automaton has 941 states and 945 transitions. Word has length 841 [2018-12-02 05:13:04,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:04,406 INFO L480 AbstractCegarLoop]: Abstraction has 941 states and 945 transitions. [2018-12-02 05:13:04,406 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-12-02 05:13:04,406 INFO L276 IsEmpty]: Start isEmpty. Operand 941 states and 945 transitions. [2018-12-02 05:13:04,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 928 [2018-12-02 05:13:04,410 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:04,410 INFO L402 BasicCegarLoop]: trace histogram [151, 151, 150, 150, 150, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:04,410 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:04,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:04,410 INFO L82 PathProgramCache]: Analyzing trace with hash -519548770, now seen corresponding path program 37 times [2018-12-02 05:13:04,410 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:04,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:04,411 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:04,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:04,411 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:04,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:05,028 INFO L134 CoverageAnalysis]: Checked inductivity of 59790 backedges. 21156 proven. 2709 refuted. 0 times theorem prover too weak. 35925 trivial. 0 not checked. [2018-12-02 05:13:05,028 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:05,028 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:05,028 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:05,028 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:05,028 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:05,029 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:05,034 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:05,034 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:13:05,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:05,175 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:05,664 INFO L134 CoverageAnalysis]: Checked inductivity of 59790 backedges. 21362 proven. 540 refuted. 0 times theorem prover too weak. 37888 trivial. 0 not checked. [2018-12-02 05:13:05,664 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:06,438 INFO L134 CoverageAnalysis]: Checked inductivity of 59790 backedges. 21362 proven. 540 refuted. 0 times theorem prover too weak. 37888 trivial. 0 not checked. [2018-12-02 05:13:06,453 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:06,454 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 34, 34] total 71 [2018-12-02 05:13:06,454 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:06,454 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-12-02 05:13:06,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-12-02 05:13:06,455 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1046, Invalid=3924, Unknown=0, NotChecked=0, Total=4970 [2018-12-02 05:13:06,455 INFO L87 Difference]: Start difference. First operand 941 states and 945 transitions. Second operand 55 states. [2018-12-02 05:13:07,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:07,416 INFO L93 Difference]: Finished difference Result 952 states and 954 transitions. [2018-12-02 05:13:07,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-02 05:13:07,417 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 927 [2018-12-02 05:13:07,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:07,418 INFO L225 Difference]: With dead ends: 952 [2018-12-02 05:13:07,418 INFO L226 Difference]: Without dead ends: 946 [2018-12-02 05:13:07,419 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1926 GetRequests, 1806 SyntacticMatches, 17 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3794 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2556, Invalid=8364, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 05:13:07,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 946 states. [2018-12-02 05:13:07,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 946 to 941. [2018-12-02 05:13:07,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 941 states. [2018-12-02 05:13:07,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 941 states to 941 states and 943 transitions. [2018-12-02 05:13:07,424 INFO L78 Accepts]: Start accepts. Automaton has 941 states and 943 transitions. Word has length 927 [2018-12-02 05:13:07,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:07,424 INFO L480 AbstractCegarLoop]: Abstraction has 941 states and 943 transitions. [2018-12-02 05:13:07,424 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-12-02 05:13:07,424 INFO L276 IsEmpty]: Start isEmpty. Operand 941 states and 943 transitions. [2018-12-02 05:13:07,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 933 [2018-12-02 05:13:07,428 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:07,428 INFO L402 BasicCegarLoop]: trace histogram [152, 152, 151, 151, 151, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:07,428 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:07,428 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:07,429 INFO L82 PathProgramCache]: Analyzing trace with hash -426911351, now seen corresponding path program 38 times [2018-12-02 05:13:07,429 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:07,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:07,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:07,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:07,429 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:07,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:08,118 INFO L134 CoverageAnalysis]: Checked inductivity of 60558 backedges. 11475 proven. 648 refuted. 0 times theorem prover too weak. 48435 trivial. 0 not checked. [2018-12-02 05:13:08,118 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:08,118 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:08,118 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:08,118 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:08,118 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:08,118 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:08,124 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:13:08,125 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:13:08,355 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-12-02 05:13:08,355 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:08,362 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:08,364 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:13:08,370 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:13:08,378 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:13:08,379 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:13:08,384 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:13:08,390 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:13:08,390 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:13:09,458 INFO L134 CoverageAnalysis]: Checked inductivity of 60558 backedges. 11475 proven. 648 refuted. 0 times theorem prover too weak. 48435 trivial. 0 not checked. [2018-12-02 05:13:09,459 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:10,374 INFO L134 CoverageAnalysis]: Checked inductivity of 60558 backedges. 11475 proven. 648 refuted. 0 times theorem prover too weak. 48435 trivial. 0 not checked. [2018-12-02 05:13:10,389 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:10,389 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 21] total 43 [2018-12-02 05:13:10,389 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:10,390 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-12-02 05:13:10,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-12-02 05:13:10,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=723, Invalid=1169, Unknown=0, NotChecked=0, Total=1892 [2018-12-02 05:13:10,390 INFO L87 Difference]: Start difference. First operand 941 states and 943 transitions. Second operand 24 states. [2018-12-02 05:13:10,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:10,768 INFO L93 Difference]: Finished difference Result 954 states and 957 transitions. [2018-12-02 05:13:10,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-12-02 05:13:10,769 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 932 [2018-12-02 05:13:10,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:10,770 INFO L225 Difference]: With dead ends: 954 [2018-12-02 05:13:10,770 INFO L226 Difference]: Without dead ends: 954 [2018-12-02 05:13:10,771 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1901 GetRequests, 1810 SyntacticMatches, 32 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 508 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1420, Invalid=2240, Unknown=0, NotChecked=0, Total=3660 [2018-12-02 05:13:10,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 954 states. [2018-12-02 05:13:10,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 954 to 946. [2018-12-02 05:13:10,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 946 states. [2018-12-02 05:13:10,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 946 states to 946 states and 949 transitions. [2018-12-02 05:13:10,775 INFO L78 Accepts]: Start accepts. Automaton has 946 states and 949 transitions. Word has length 932 [2018-12-02 05:13:10,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:10,775 INFO L480 AbstractCegarLoop]: Abstraction has 946 states and 949 transitions. [2018-12-02 05:13:10,776 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-12-02 05:13:10,776 INFO L276 IsEmpty]: Start isEmpty. Operand 946 states and 949 transitions. [2018-12-02 05:13:10,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 938 [2018-12-02 05:13:10,779 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:10,779 INFO L402 BasicCegarLoop]: trace histogram [153, 153, 152, 152, 152, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:10,779 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:10,780 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:10,780 INFO L82 PathProgramCache]: Analyzing trace with hash 1551487140, now seen corresponding path program 39 times [2018-12-02 05:13:10,780 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:10,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:10,780 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:10,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:10,780 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:10,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:11,360 INFO L134 CoverageAnalysis]: Checked inductivity of 61331 backedges. 12863 proven. 693 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2018-12-02 05:13:11,361 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:11,361 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:11,361 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:11,361 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:11,361 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:11,361 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:11,370 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:13:11,370 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:13:11,500 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:13:11,500 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:11,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:12,215 INFO L134 CoverageAnalysis]: Checked inductivity of 61331 backedges. 12736 proven. 2374 refuted. 0 times theorem prover too weak. 46221 trivial. 0 not checked. [2018-12-02 05:13:12,215 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:12,855 INFO L134 CoverageAnalysis]: Checked inductivity of 61331 backedges. 12736 proven. 2374 refuted. 0 times theorem prover too weak. 46221 trivial. 0 not checked. [2018-12-02 05:13:12,870 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:12,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 41, 41] total 64 [2018-12-02 05:13:12,871 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:12,871 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-12-02 05:13:12,871 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-12-02 05:13:12,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=772, Invalid=3260, Unknown=0, NotChecked=0, Total=4032 [2018-12-02 05:13:12,871 INFO L87 Difference]: Start difference. First operand 946 states and 949 transitions. Second operand 61 states. [2018-12-02 05:13:14,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:14,990 INFO L93 Difference]: Finished difference Result 1052 states and 1056 transitions. [2018-12-02 05:13:14,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-12-02 05:13:14,990 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 937 [2018-12-02 05:13:14,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:14,994 INFO L225 Difference]: With dead ends: 1052 [2018-12-02 05:13:14,994 INFO L226 Difference]: Without dead ends: 1052 [2018-12-02 05:13:14,994 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1946 GetRequests, 1812 SyntacticMatches, 37 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3181 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2058, Invalid=7644, Unknown=0, NotChecked=0, Total=9702 [2018-12-02 05:13:14,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1052 states. [2018-12-02 05:13:15,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1052 to 1042. [2018-12-02 05:13:15,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1042 states. [2018-12-02 05:13:15,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1042 states to 1042 states and 1046 transitions. [2018-12-02 05:13:15,004 INFO L78 Accepts]: Start accepts. Automaton has 1042 states and 1046 transitions. Word has length 937 [2018-12-02 05:13:15,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:15,005 INFO L480 AbstractCegarLoop]: Abstraction has 1042 states and 1046 transitions. [2018-12-02 05:13:15,005 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-12-02 05:13:15,005 INFO L276 IsEmpty]: Start isEmpty. Operand 1042 states and 1046 transitions. [2018-12-02 05:13:15,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1029 [2018-12-02 05:13:15,013 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:15,013 INFO L402 BasicCegarLoop]: trace histogram [169, 169, 168, 168, 168, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:15,014 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:15,014 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:15,014 INFO L82 PathProgramCache]: Analyzing trace with hash -139595476, now seen corresponding path program 40 times [2018-12-02 05:13:15,014 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:15,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:15,015 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:15,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:15,015 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:15,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:15,835 INFO L134 CoverageAnalysis]: Checked inductivity of 74716 backedges. 13592 proven. 731 refuted. 0 times theorem prover too weak. 60393 trivial. 0 not checked. [2018-12-02 05:13:15,835 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:15,835 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:15,835 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:15,835 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:15,835 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:15,835 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:15,843 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:15,843 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:13:15,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:15,994 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:16,780 INFO L134 CoverageAnalysis]: Checked inductivity of 74716 backedges. 25579 proven. 616 refuted. 0 times theorem prover too weak. 48521 trivial. 0 not checked. [2018-12-02 05:13:16,780 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:17,776 INFO L134 CoverageAnalysis]: Checked inductivity of 74716 backedges. 25579 proven. 616 refuted. 0 times theorem prover too weak. 48521 trivial. 0 not checked. [2018-12-02 05:13:17,792 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:17,792 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 36, 36] total 74 [2018-12-02 05:13:17,792 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:17,792 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-12-02 05:13:17,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-12-02 05:13:17,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=862, Invalid=4540, Unknown=0, NotChecked=0, Total=5402 [2018-12-02 05:13:17,793 INFO L87 Difference]: Start difference. First operand 1042 states and 1046 transitions. Second operand 57 states. [2018-12-02 05:13:19,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:19,659 INFO L93 Difference]: Finished difference Result 1061 states and 1064 transitions. [2018-12-02 05:13:19,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-02 05:13:19,660 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 1028 [2018-12-02 05:13:19,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:19,663 INFO L225 Difference]: With dead ends: 1061 [2018-12-02 05:13:19,663 INFO L226 Difference]: Without dead ends: 1055 [2018-12-02 05:13:19,664 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2126 GetRequests, 1987 SyntacticMatches, 18 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4425 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2693, Invalid=12313, Unknown=0, NotChecked=0, Total=15006 [2018-12-02 05:13:19,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1055 states. [2018-12-02 05:13:19,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1055 to 1047. [2018-12-02 05:13:19,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1047 states. [2018-12-02 05:13:19,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1047 states to 1047 states and 1050 transitions. [2018-12-02 05:13:19,674 INFO L78 Accepts]: Start accepts. Automaton has 1047 states and 1050 transitions. Word has length 1028 [2018-12-02 05:13:19,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:19,674 INFO L480 AbstractCegarLoop]: Abstraction has 1047 states and 1050 transitions. [2018-12-02 05:13:19,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-12-02 05:13:19,674 INFO L276 IsEmpty]: Start isEmpty. Operand 1047 states and 1050 transitions. [2018-12-02 05:13:19,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1039 [2018-12-02 05:13:19,683 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:19,683 INFO L402 BasicCegarLoop]: trace histogram [171, 171, 170, 170, 170, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:19,683 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:19,683 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:19,683 INFO L82 PathProgramCache]: Analyzing trace with hash -1792127834, now seen corresponding path program 41 times [2018-12-02 05:13:19,684 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:19,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:19,684 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:19,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:19,684 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:19,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:20,512 INFO L134 CoverageAnalysis]: Checked inductivity of 76439 backedges. 14456 proven. 819 refuted. 0 times theorem prover too weak. 61164 trivial. 0 not checked. [2018-12-02 05:13:20,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:20,513 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:20,513 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:20,513 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:20,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:20,513 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:20,519 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:13:20,519 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:13:20,775 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-12-02 05:13:20,775 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:20,782 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:21,783 INFO L134 CoverageAnalysis]: Checked inductivity of 76439 backedges. 23891 proven. 3494 refuted. 0 times theorem prover too weak. 49054 trivial. 0 not checked. [2018-12-02 05:13:21,784 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:23,265 INFO L134 CoverageAnalysis]: Checked inductivity of 76439 backedges. 23891 proven. 3494 refuted. 0 times theorem prover too weak. 49054 trivial. 0 not checked. [2018-12-02 05:13:23,280 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:23,280 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 43, 43] total 101 [2018-12-02 05:13:23,281 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:23,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-02 05:13:23,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-02 05:13:23,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1350, Invalid=8750, Unknown=0, NotChecked=0, Total=10100 [2018-12-02 05:13:23,282 INFO L87 Difference]: Start difference. First operand 1047 states and 1050 transitions. Second operand 65 states. [2018-12-02 05:13:27,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:27,746 INFO L93 Difference]: Finished difference Result 1171 states and 1176 transitions. [2018-12-02 05:13:27,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-12-02 05:13:27,746 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1038 [2018-12-02 05:13:27,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:27,748 INFO L225 Difference]: With dead ends: 1171 [2018-12-02 05:13:27,748 INFO L226 Difference]: Without dead ends: 1171 [2018-12-02 05:13:27,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2160 GetRequests, 1993 SyntacticMatches, 6 SemanticMatches, 161 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7163 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=4683, Invalid=21723, Unknown=0, NotChecked=0, Total=26406 [2018-12-02 05:13:27,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1171 states. [2018-12-02 05:13:27,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1171 to 1153. [2018-12-02 05:13:27,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1153 states. [2018-12-02 05:13:27,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1153 states to 1153 states and 1158 transitions. [2018-12-02 05:13:27,755 INFO L78 Accepts]: Start accepts. Automaton has 1153 states and 1158 transitions. Word has length 1038 [2018-12-02 05:13:27,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:27,755 INFO L480 AbstractCegarLoop]: Abstraction has 1153 states and 1158 transitions. [2018-12-02 05:13:27,755 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-02 05:13:27,755 INFO L276 IsEmpty]: Start isEmpty. Operand 1153 states and 1158 transitions. [2018-12-02 05:13:27,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1140 [2018-12-02 05:13:27,761 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:27,761 INFO L402 BasicCegarLoop]: trace histogram [189, 189, 188, 188, 188, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:27,761 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:27,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:27,761 INFO L82 PathProgramCache]: Analyzing trace with hash -1047165046, now seen corresponding path program 42 times [2018-12-02 05:13:27,761 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:27,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:27,762 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:27,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:27,762 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:27,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:28,597 INFO L134 CoverageAnalysis]: Checked inductivity of 93214 backedges. 30939 proven. 3440 refuted. 0 times theorem prover too weak. 58835 trivial. 0 not checked. [2018-12-02 05:13:28,597 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:28,597 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:28,597 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:28,598 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:28,598 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:28,598 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:28,605 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:13:28,605 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:13:28,770 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:13:28,770 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:28,779 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:29,524 INFO L134 CoverageAnalysis]: Checked inductivity of 93214 backedges. 30985 proven. 2636 refuted. 0 times theorem prover too weak. 59593 trivial. 0 not checked. [2018-12-02 05:13:29,524 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:30,586 INFO L134 CoverageAnalysis]: Checked inductivity of 93214 backedges. 30991 proven. 2630 refuted. 0 times theorem prover too weak. 59593 trivial. 0 not checked. [2018-12-02 05:13:30,602 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:30,602 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 41, 41] total 84 [2018-12-02 05:13:30,602 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:30,603 INFO L459 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-12-02 05:13:30,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-12-02 05:13:30,603 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1331, Invalid=5641, Unknown=0, NotChecked=0, Total=6972 [2018-12-02 05:13:30,603 INFO L87 Difference]: Start difference. First operand 1153 states and 1158 transitions. Second operand 64 states. [2018-12-02 05:13:31,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:31,958 INFO L93 Difference]: Finished difference Result 1162 states and 1165 transitions. [2018-12-02 05:13:31,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-12-02 05:13:31,958 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1139 [2018-12-02 05:13:31,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:31,960 INFO L225 Difference]: With dead ends: 1162 [2018-12-02 05:13:31,960 INFO L226 Difference]: Without dead ends: 1156 [2018-12-02 05:13:31,961 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2358 GetRequests, 2217 SyntacticMatches, 21 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5374 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3397, Invalid=11365, Unknown=0, NotChecked=0, Total=14762 [2018-12-02 05:13:31,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1156 states. [2018-12-02 05:13:31,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1156 to 1153. [2018-12-02 05:13:31,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1153 states. [2018-12-02 05:13:31,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1153 states to 1153 states and 1156 transitions. [2018-12-02 05:13:31,966 INFO L78 Accepts]: Start accepts. Automaton has 1153 states and 1156 transitions. Word has length 1139 [2018-12-02 05:13:31,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:31,967 INFO L480 AbstractCegarLoop]: Abstraction has 1153 states and 1156 transitions. [2018-12-02 05:13:31,967 INFO L481 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-12-02 05:13:31,967 INFO L276 IsEmpty]: Start isEmpty. Operand 1153 states and 1156 transitions. [2018-12-02 05:13:31,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1145 [2018-12-02 05:13:31,972 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:31,973 INFO L402 BasicCegarLoop]: trace histogram [190, 190, 189, 189, 189, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:31,973 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:31,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:31,973 INFO L82 PathProgramCache]: Analyzing trace with hash 7672105, now seen corresponding path program 43 times [2018-12-02 05:13:31,973 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:31,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:31,974 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:31,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:31,974 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:32,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:32,771 INFO L134 CoverageAnalysis]: Checked inductivity of 94174 backedges. 17892 proven. 887 refuted. 0 times theorem prover too weak. 75395 trivial. 0 not checked. [2018-12-02 05:13:32,771 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:32,771 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:32,771 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:32,771 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:32,772 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:32,772 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:32,779 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:32,779 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:13:32,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:32,950 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:33,747 INFO L134 CoverageAnalysis]: Checked inductivity of 94174 backedges. 17929 proven. 850 refuted. 0 times theorem prover too weak. 75395 trivial. 0 not checked. [2018-12-02 05:13:33,747 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:34,439 INFO L134 CoverageAnalysis]: Checked inductivity of 94174 backedges. 17929 proven. 850 refuted. 0 times theorem prover too weak. 75395 trivial. 0 not checked. [2018-12-02 05:13:34,455 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:34,455 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 41, 41] total 63 [2018-12-02 05:13:34,455 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:34,456 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-12-02 05:13:34,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-12-02 05:13:34,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=904, Invalid=3002, Unknown=0, NotChecked=0, Total=3906 [2018-12-02 05:13:34,456 INFO L87 Difference]: Start difference. First operand 1153 states and 1156 transitions. Second operand 63 states. [2018-12-02 05:13:35,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:35,453 INFO L93 Difference]: Finished difference Result 1269 states and 1273 transitions. [2018-12-02 05:13:35,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-12-02 05:13:35,453 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1144 [2018-12-02 05:13:35,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:35,455 INFO L225 Difference]: With dead ends: 1269 [2018-12-02 05:13:35,455 INFO L226 Difference]: Without dead ends: 1269 [2018-12-02 05:13:35,456 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2366 GetRequests, 2229 SyntacticMatches, 39 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3085 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=2529, Invalid=7371, Unknown=0, NotChecked=0, Total=9900 [2018-12-02 05:13:35,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1269 states. [2018-12-02 05:13:35,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1269 to 1259. [2018-12-02 05:13:35,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1259 states. [2018-12-02 05:13:35,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1259 states to 1259 states and 1263 transitions. [2018-12-02 05:13:35,461 INFO L78 Accepts]: Start accepts. Automaton has 1259 states and 1263 transitions. Word has length 1144 [2018-12-02 05:13:35,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:35,462 INFO L480 AbstractCegarLoop]: Abstraction has 1259 states and 1263 transitions. [2018-12-02 05:13:35,462 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-12-02 05:13:35,462 INFO L276 IsEmpty]: Start isEmpty. Operand 1259 states and 1263 transitions. [2018-12-02 05:13:35,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1246 [2018-12-02 05:13:35,468 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:35,468 INFO L402 BasicCegarLoop]: trace histogram [208, 208, 207, 207, 207, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:35,468 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:35,468 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:35,468 INFO L82 PathProgramCache]: Analyzing trace with hash -700055321, now seen corresponding path program 44 times [2018-12-02 05:13:35,469 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:35,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:35,469 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:35,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:35,469 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:35,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:36,463 INFO L134 CoverageAnalysis]: Checked inductivity of 112707 backedges. 48036 proven. 2562 refuted. 0 times theorem prover too weak. 62109 trivial. 0 not checked. [2018-12-02 05:13:36,463 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:36,463 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:36,463 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:36,463 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:36,463 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:36,463 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:36,469 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:13:36,469 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:13:36,762 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-12-02 05:13:36,762 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:36,771 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:38,020 INFO L134 CoverageAnalysis]: Checked inductivity of 112707 backedges. 33914 proven. 2531 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-02 05:13:38,021 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:39,859 INFO L134 CoverageAnalysis]: Checked inductivity of 112707 backedges. 33914 proven. 2531 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-02 05:13:39,874 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:39,875 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 45, 45] total 125 [2018-12-02 05:13:39,875 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:39,875 INFO L459 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-12-02 05:13:39,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-12-02 05:13:39,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2113, Invalid=13387, Unknown=0, NotChecked=0, Total=15500 [2018-12-02 05:13:39,876 INFO L87 Difference]: Start difference. First operand 1259 states and 1263 transitions. Second operand 86 states. [2018-12-02 05:13:42,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:42,698 INFO L93 Difference]: Finished difference Result 1274 states and 1276 transitions. [2018-12-02 05:13:42,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-12-02 05:13:42,699 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 1245 [2018-12-02 05:13:42,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:42,701 INFO L225 Difference]: With dead ends: 1274 [2018-12-02 05:13:42,701 INFO L226 Difference]: Without dead ends: 1268 [2018-12-02 05:13:42,703 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2614 GetRequests, 2406 SyntacticMatches, 5 SemanticMatches, 203 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13720 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=6944, Invalid=34876, Unknown=0, NotChecked=0, Total=41820 [2018-12-02 05:13:42,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1268 states. [2018-12-02 05:13:42,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1268 to 1259. [2018-12-02 05:13:42,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1259 states. [2018-12-02 05:13:42,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1259 states to 1259 states and 1261 transitions. [2018-12-02 05:13:42,710 INFO L78 Accepts]: Start accepts. Automaton has 1259 states and 1261 transitions. Word has length 1245 [2018-12-02 05:13:42,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:42,710 INFO L480 AbstractCegarLoop]: Abstraction has 1259 states and 1261 transitions. [2018-12-02 05:13:42,710 INFO L481 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-12-02 05:13:42,710 INFO L276 IsEmpty]: Start isEmpty. Operand 1259 states and 1261 transitions. [2018-12-02 05:13:42,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1251 [2018-12-02 05:13:42,718 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:42,718 INFO L402 BasicCegarLoop]: trace histogram [209, 209, 208, 208, 208, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:42,718 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:42,718 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:42,719 INFO L82 PathProgramCache]: Analyzing trace with hash 1926949356, now seen corresponding path program 45 times [2018-12-02 05:13:42,719 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:42,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:42,719 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:42,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:42,719 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:42,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:43,752 INFO L134 CoverageAnalysis]: Checked inductivity of 113763 backedges. 18900 proven. 912 refuted. 0 times theorem prover too weak. 93951 trivial. 0 not checked. [2018-12-02 05:13:43,753 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:43,753 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:43,753 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:43,753 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:43,753 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:43,753 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:43,760 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:13:43,760 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:13:44,083 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:13:44,083 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:44,096 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:44,098 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:13:44,104 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:13:44,118 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:13:44,118 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:13:44,124 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:13:44,134 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:13:44,134 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:13:46,122 INFO L134 CoverageAnalysis]: Checked inductivity of 113763 backedges. 18900 proven. 912 refuted. 0 times theorem prover too weak. 93951 trivial. 0 not checked. [2018-12-02 05:13:46,122 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:47,276 INFO L134 CoverageAnalysis]: Checked inductivity of 113763 backedges. 18900 proven. 912 refuted. 0 times theorem prover too weak. 93951 trivial. 0 not checked. [2018-12-02 05:13:47,295 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:47,295 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 23] total 66 [2018-12-02 05:13:47,295 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:47,295 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-12-02 05:13:47,296 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-12-02 05:13:47,296 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=961, Invalid=3461, Unknown=0, NotChecked=0, Total=4422 [2018-12-02 05:13:47,296 INFO L87 Difference]: Start difference. First operand 1259 states and 1261 transitions. Second operand 45 states. [2018-12-02 05:13:48,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:48,363 INFO L93 Difference]: Finished difference Result 1272 states and 1275 transitions. [2018-12-02 05:13:48,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-12-02 05:13:48,364 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 1250 [2018-12-02 05:13:48,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:48,366 INFO L225 Difference]: With dead ends: 1272 [2018-12-02 05:13:48,366 INFO L226 Difference]: Without dead ends: 1272 [2018-12-02 05:13:48,366 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2543 GetRequests, 2420 SyntacticMatches, 38 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2479 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1682, Invalid=5800, Unknown=0, NotChecked=0, Total=7482 [2018-12-02 05:13:48,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1272 states. [2018-12-02 05:13:48,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1272 to 1264. [2018-12-02 05:13:48,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1264 states. [2018-12-02 05:13:48,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1264 states to 1264 states and 1267 transitions. [2018-12-02 05:13:48,372 INFO L78 Accepts]: Start accepts. Automaton has 1264 states and 1267 transitions. Word has length 1250 [2018-12-02 05:13:48,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:48,373 INFO L480 AbstractCegarLoop]: Abstraction has 1264 states and 1267 transitions. [2018-12-02 05:13:48,373 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-12-02 05:13:48,373 INFO L276 IsEmpty]: Start isEmpty. Operand 1264 states and 1267 transitions. [2018-12-02 05:13:48,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1256 [2018-12-02 05:13:48,380 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:48,380 INFO L402 BasicCegarLoop]: trace histogram [210, 210, 209, 209, 209, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:48,380 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:48,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:48,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1858504225, now seen corresponding path program 46 times [2018-12-02 05:13:48,380 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:48,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:48,381 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:13:48,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:48,381 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:48,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:49,314 INFO L134 CoverageAnalysis]: Checked inductivity of 114824 backedges. 20834 proven. 993 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-02 05:13:49,314 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:49,314 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:49,314 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:49,314 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:49,314 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:49,314 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:49,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:49,321 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:13:49,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:49,515 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:50,433 INFO L134 CoverageAnalysis]: Checked inductivity of 114824 backedges. 20873 proven. 954 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-02 05:13:50,433 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:51,255 INFO L134 CoverageAnalysis]: Checked inductivity of 114824 backedges. 20873 proven. 954 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-02 05:13:51,271 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:51,271 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 43, 43] total 66 [2018-12-02 05:13:51,271 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:51,272 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-12-02 05:13:51,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-12-02 05:13:51,272 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=991, Invalid=3299, Unknown=0, NotChecked=0, Total=4290 [2018-12-02 05:13:51,272 INFO L87 Difference]: Start difference. First operand 1264 states and 1267 transitions. Second operand 66 states. [2018-12-02 05:13:52,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:13:52,498 INFO L93 Difference]: Finished difference Result 1385 states and 1389 transitions. [2018-12-02 05:13:52,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-12-02 05:13:52,499 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 1255 [2018-12-02 05:13:52,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:13:52,503 INFO L225 Difference]: With dead ends: 1385 [2018-12-02 05:13:52,503 INFO L226 Difference]: Without dead ends: 1385 [2018-12-02 05:13:52,504 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2592 GetRequests, 2448 SyntacticMatches, 41 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3408 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2782, Invalid=8138, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 05:13:52,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1385 states. [2018-12-02 05:13:52,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1385 to 1375. [2018-12-02 05:13:52,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1375 states. [2018-12-02 05:13:52,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1375 states to 1375 states and 1379 transitions. [2018-12-02 05:13:52,517 INFO L78 Accepts]: Start accepts. Automaton has 1375 states and 1379 transitions. Word has length 1255 [2018-12-02 05:13:52,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:13:52,517 INFO L480 AbstractCegarLoop]: Abstraction has 1375 states and 1379 transitions. [2018-12-02 05:13:52,517 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-12-02 05:13:52,517 INFO L276 IsEmpty]: Start isEmpty. Operand 1375 states and 1379 transitions. [2018-12-02 05:13:52,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1362 [2018-12-02 05:13:52,528 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:13:52,528 INFO L402 BasicCegarLoop]: trace histogram [229, 229, 228, 228, 228, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:13:52,528 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:13:52,528 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:13:52,528 INFO L82 PathProgramCache]: Analyzing trace with hash 945394430, now seen corresponding path program 47 times [2018-12-02 05:13:52,528 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:13:52,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:52,529 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:13:52,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:13:52,529 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:13:52,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:13:53,600 INFO L134 CoverageAnalysis]: Checked inductivity of 136363 backedges. 41194 proven. 4255 refuted. 0 times theorem prover too weak. 90914 trivial. 0 not checked. [2018-12-02 05:13:53,600 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:53,600 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:13:53,600 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:13:53,600 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:13:53,600 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:13:53,600 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:13:53,608 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:13:53,608 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:13:54,026 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-12-02 05:13:54,026 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:13:54,035 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:13:55,445 INFO L134 CoverageAnalysis]: Checked inductivity of 136363 backedges. 39580 proven. 2814 refuted. 0 times theorem prover too weak. 93969 trivial. 0 not checked. [2018-12-02 05:13:55,446 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:13:57,387 INFO L134 CoverageAnalysis]: Checked inductivity of 136363 backedges. 39580 proven. 2814 refuted. 0 times theorem prover too weak. 93969 trivial. 0 not checked. [2018-12-02 05:13:57,402 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:13:57,403 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 47, 47] total 131 [2018-12-02 05:13:57,403 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:13:57,403 INFO L459 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-12-02 05:13:57,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-12-02 05:13:57,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2307, Invalid=14723, Unknown=0, NotChecked=0, Total=17030 [2018-12-02 05:13:57,404 INFO L87 Difference]: Start difference. First operand 1375 states and 1379 transitions. Second operand 90 states. [2018-12-02 05:14:00,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:00,791 INFO L93 Difference]: Finished difference Result 1390 states and 1392 transitions. [2018-12-02 05:14:00,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2018-12-02 05:14:00,791 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 1361 [2018-12-02 05:14:00,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:00,793 INFO L225 Difference]: With dead ends: 1390 [2018-12-02 05:14:00,794 INFO L226 Difference]: Without dead ends: 1384 [2018-12-02 05:14:00,796 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2869 GetRequests, 2634 SyntacticMatches, 5 SemanticMatches, 230 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18647 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=7481, Invalid=46111, Unknown=0, NotChecked=0, Total=53592 [2018-12-02 05:14:00,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1384 states. [2018-12-02 05:14:00,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1384 to 1375. [2018-12-02 05:14:00,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1375 states. [2018-12-02 05:14:00,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1375 states to 1375 states and 1377 transitions. [2018-12-02 05:14:00,803 INFO L78 Accepts]: Start accepts. Automaton has 1375 states and 1377 transitions. Word has length 1361 [2018-12-02 05:14:00,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:00,803 INFO L480 AbstractCegarLoop]: Abstraction has 1375 states and 1377 transitions. [2018-12-02 05:14:00,803 INFO L481 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-12-02 05:14:00,804 INFO L276 IsEmpty]: Start isEmpty. Operand 1375 states and 1377 transitions. [2018-12-02 05:14:00,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1367 [2018-12-02 05:14:00,811 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:00,811 INFO L402 BasicCegarLoop]: trace histogram [230, 230, 229, 229, 229, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:00,811 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:00,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:00,812 INFO L82 PathProgramCache]: Analyzing trace with hash -1625873879, now seen corresponding path program 48 times [2018-12-02 05:14:00,812 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:00,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:00,812 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:14:00,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:00,812 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:00,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:01,996 INFO L134 CoverageAnalysis]: Checked inductivity of 137525 backedges. 21945 proven. 1010 refuted. 0 times theorem prover too weak. 114570 trivial. 0 not checked. [2018-12-02 05:14:01,997 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:01,997 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:01,997 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:01,997 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:01,997 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:01,997 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:02,004 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:14:02,004 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:14:02,364 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:14:02,364 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:14:02,379 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:14:02,381 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:14:02,386 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:14:02,390 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:14:02,390 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:14:02,396 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:14:02,405 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:14:02,405 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:14:04,862 INFO L134 CoverageAnalysis]: Checked inductivity of 137525 backedges. 21945 proven. 1010 refuted. 0 times theorem prover too weak. 114570 trivial. 0 not checked. [2018-12-02 05:14:04,862 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:14:06,195 INFO L134 CoverageAnalysis]: Checked inductivity of 137525 backedges. 21945 proven. 1010 refuted. 0 times theorem prover too weak. 114570 trivial. 0 not checked. [2018-12-02 05:14:06,213 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:14:06,213 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 24] total 69 [2018-12-02 05:14:06,214 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:14:06,214 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-12-02 05:14:06,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-12-02 05:14:06,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1033, Invalid=3797, Unknown=0, NotChecked=0, Total=4830 [2018-12-02 05:14:06,215 INFO L87 Difference]: Start difference. First operand 1375 states and 1377 transitions. Second operand 47 states. [2018-12-02 05:14:07,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:07,307 INFO L93 Difference]: Finished difference Result 1388 states and 1391 transitions. [2018-12-02 05:14:07,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-12-02 05:14:07,307 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 1366 [2018-12-02 05:14:07,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:07,309 INFO L225 Difference]: With dead ends: 1388 [2018-12-02 05:14:07,310 INFO L226 Difference]: Without dead ends: 1388 [2018-12-02 05:14:07,310 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2777 GetRequests, 2648 SyntacticMatches, 40 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2715 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1806, Invalid=6384, Unknown=0, NotChecked=0, Total=8190 [2018-12-02 05:14:07,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1388 states. [2018-12-02 05:14:07,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1388 to 1380. [2018-12-02 05:14:07,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1380 states. [2018-12-02 05:14:07,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1380 states to 1380 states and 1383 transitions. [2018-12-02 05:14:07,320 INFO L78 Accepts]: Start accepts. Automaton has 1380 states and 1383 transitions. Word has length 1366 [2018-12-02 05:14:07,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:07,321 INFO L480 AbstractCegarLoop]: Abstraction has 1380 states and 1383 transitions. [2018-12-02 05:14:07,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-12-02 05:14:07,321 INFO L276 IsEmpty]: Start isEmpty. Operand 1380 states and 1383 transitions. [2018-12-02 05:14:07,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1372 [2018-12-02 05:14:07,334 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:07,334 INFO L402 BasicCegarLoop]: trace histogram [231, 231, 230, 230, 230, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:07,334 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:07,334 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:07,334 INFO L82 PathProgramCache]: Analyzing trace with hash 2139417604, now seen corresponding path program 49 times [2018-12-02 05:14:07,335 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:07,335 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:07,335 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:14:07,335 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:07,335 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:07,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:08,384 INFO L134 CoverageAnalysis]: Checked inductivity of 138692 backedges. 24081 proven. 1105 refuted. 0 times theorem prover too weak. 113506 trivial. 0 not checked. [2018-12-02 05:14:08,384 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:08,384 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:08,385 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:08,385 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:08,385 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:08,385 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:08,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:14:08,394 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:14:08,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:08,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:14:09,639 INFO L134 CoverageAnalysis]: Checked inductivity of 138692 backedges. 24122 proven. 1064 refuted. 0 times theorem prover too weak. 113506 trivial. 0 not checked. [2018-12-02 05:14:09,639 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:14:10,635 INFO L134 CoverageAnalysis]: Checked inductivity of 138692 backedges. 24122 proven. 1064 refuted. 0 times theorem prover too weak. 113506 trivial. 0 not checked. [2018-12-02 05:14:10,651 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:14:10,652 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 45, 45] total 69 [2018-12-02 05:14:10,652 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:14:10,653 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-02 05:14:10,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-02 05:14:10,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1082, Invalid=3610, Unknown=0, NotChecked=0, Total=4692 [2018-12-02 05:14:10,653 INFO L87 Difference]: Start difference. First operand 1380 states and 1383 transitions. Second operand 69 states. [2018-12-02 05:14:11,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:11,711 INFO L93 Difference]: Finished difference Result 1506 states and 1510 transitions. [2018-12-02 05:14:11,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-12-02 05:14:11,711 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1371 [2018-12-02 05:14:11,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:11,714 INFO L225 Difference]: With dead ends: 1506 [2018-12-02 05:14:11,714 INFO L226 Difference]: Without dead ends: 1506 [2018-12-02 05:14:11,715 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2828 GetRequests, 2677 SyntacticMatches, 43 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3747 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3047, Invalid=8943, Unknown=0, NotChecked=0, Total=11990 [2018-12-02 05:14:11,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1506 states. [2018-12-02 05:14:11,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1506 to 1496. [2018-12-02 05:14:11,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1496 states. [2018-12-02 05:14:11,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1496 states to 1496 states and 1500 transitions. [2018-12-02 05:14:11,723 INFO L78 Accepts]: Start accepts. Automaton has 1496 states and 1500 transitions. Word has length 1371 [2018-12-02 05:14:11,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:11,724 INFO L480 AbstractCegarLoop]: Abstraction has 1496 states and 1500 transitions. [2018-12-02 05:14:11,724 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-02 05:14:11,724 INFO L276 IsEmpty]: Start isEmpty. Operand 1496 states and 1500 transitions. [2018-12-02 05:14:11,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1483 [2018-12-02 05:14:11,733 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:11,733 INFO L402 BasicCegarLoop]: trace histogram [251, 251, 250, 250, 250, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:11,734 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:11,734 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:11,734 INFO L82 PathProgramCache]: Analyzing trace with hash 781243404, now seen corresponding path program 50 times [2018-12-02 05:14:11,734 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:11,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:11,735 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:14:11,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:11,735 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:11,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:13,014 INFO L134 CoverageAnalysis]: Checked inductivity of 163545 backedges. 65297 proven. 3147 refuted. 0 times theorem prover too weak. 95101 trivial. 0 not checked. [2018-12-02 05:14:13,014 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:13,015 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:13,015 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:13,015 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:13,015 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:13,015 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:13,021 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:14:13,021 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:14:13,514 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-12-02 05:14:13,514 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:14:13,524 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:14:15,072 INFO L134 CoverageAnalysis]: Checked inductivity of 163545 backedges. 45844 proven. 3112 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-02 05:14:15,072 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:14:17,177 INFO L134 CoverageAnalysis]: Checked inductivity of 163545 backedges. 45844 proven. 3112 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-02 05:14:17,193 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:14:17,193 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 49, 49] total 137 [2018-12-02 05:14:17,193 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:14:17,194 INFO L459 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-12-02 05:14:17,194 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-12-02 05:14:17,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2543, Invalid=16089, Unknown=0, NotChecked=0, Total=18632 [2018-12-02 05:14:17,195 INFO L87 Difference]: Start difference. First operand 1496 states and 1500 transitions. Second operand 94 states. [2018-12-02 05:14:22,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:22,716 INFO L93 Difference]: Finished difference Result 1511 states and 1513 transitions. [2018-12-02 05:14:22,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-12-02 05:14:22,716 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 1482 [2018-12-02 05:14:22,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:22,718 INFO L225 Difference]: With dead ends: 1511 [2018-12-02 05:14:22,718 INFO L226 Difference]: Without dead ends: 1505 [2018-12-02 05:14:22,720 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3100 GetRequests, 2872 SyntacticMatches, 5 SemanticMatches, 223 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16655 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=8363, Invalid=42037, Unknown=0, NotChecked=0, Total=50400 [2018-12-02 05:14:22,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1505 states. [2018-12-02 05:14:22,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1505 to 1496. [2018-12-02 05:14:22,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1496 states. [2018-12-02 05:14:22,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1496 states to 1496 states and 1498 transitions. [2018-12-02 05:14:22,727 INFO L78 Accepts]: Start accepts. Automaton has 1496 states and 1498 transitions. Word has length 1482 [2018-12-02 05:14:22,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:22,727 INFO L480 AbstractCegarLoop]: Abstraction has 1496 states and 1498 transitions. [2018-12-02 05:14:22,727 INFO L481 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-12-02 05:14:22,727 INFO L276 IsEmpty]: Start isEmpty. Operand 1496 states and 1498 transitions. [2018-12-02 05:14:22,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1488 [2018-12-02 05:14:22,736 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:22,736 INFO L402 BasicCegarLoop]: trace histogram [252, 252, 251, 251, 251, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:22,736 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:22,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:22,736 INFO L82 PathProgramCache]: Analyzing trace with hash 303144551, now seen corresponding path program 51 times [2018-12-02 05:14:22,736 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:22,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:22,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:14:22,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:22,737 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:22,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:24,091 INFO L134 CoverageAnalysis]: Checked inductivity of 164818 backedges. 25300 proven. 1113 refuted. 0 times theorem prover too weak. 138405 trivial. 0 not checked. [2018-12-02 05:14:24,091 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:24,091 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:24,091 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:24,091 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:24,091 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:24,091 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:24,098 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:14:24,098 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:14:24,518 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:14:24,518 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:14:24,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:14:24,536 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:14:24,538 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:14:24,543 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:14:24,543 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:14:24,556 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:14:24,562 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:14:24,562 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:14:27,377 INFO L134 CoverageAnalysis]: Checked inductivity of 164818 backedges. 25300 proven. 1113 refuted. 0 times theorem prover too weak. 138405 trivial. 0 not checked. [2018-12-02 05:14:27,378 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:14:28,876 INFO L134 CoverageAnalysis]: Checked inductivity of 164818 backedges. 25300 proven. 1113 refuted. 0 times theorem prover too weak. 138405 trivial. 0 not checked. [2018-12-02 05:14:28,895 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:14:28,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 25] total 72 [2018-12-02 05:14:28,896 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:14:28,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-02 05:14:28,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-02 05:14:28,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1105, Invalid=4151, Unknown=0, NotChecked=0, Total=5256 [2018-12-02 05:14:28,897 INFO L87 Difference]: Start difference. First operand 1496 states and 1498 transitions. Second operand 49 states. [2018-12-02 05:14:30,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:30,875 INFO L93 Difference]: Finished difference Result 1509 states and 1512 transitions. [2018-12-02 05:14:30,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-02 05:14:30,875 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 1487 [2018-12-02 05:14:30,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:30,877 INFO L225 Difference]: With dead ends: 1509 [2018-12-02 05:14:30,877 INFO L226 Difference]: Without dead ends: 1509 [2018-12-02 05:14:30,877 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3021 GetRequests, 2886 SyntacticMatches, 42 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2959 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1929, Invalid=7001, Unknown=0, NotChecked=0, Total=8930 [2018-12-02 05:14:30,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1509 states. [2018-12-02 05:14:30,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1509 to 1501. [2018-12-02 05:14:30,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1501 states. [2018-12-02 05:14:30,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1501 states to 1501 states and 1504 transitions. [2018-12-02 05:14:30,884 INFO L78 Accepts]: Start accepts. Automaton has 1501 states and 1504 transitions. Word has length 1487 [2018-12-02 05:14:30,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:30,885 INFO L480 AbstractCegarLoop]: Abstraction has 1501 states and 1504 transitions. [2018-12-02 05:14:30,885 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-02 05:14:30,885 INFO L276 IsEmpty]: Start isEmpty. Operand 1501 states and 1504 transitions. [2018-12-02 05:14:30,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1493 [2018-12-02 05:14:30,893 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:30,893 INFO L402 BasicCegarLoop]: trace histogram [253, 253, 252, 252, 252, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:30,893 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:30,893 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:30,893 INFO L82 PathProgramCache]: Analyzing trace with hash -612079994, now seen corresponding path program 52 times [2018-12-02 05:14:30,894 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:30,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:30,894 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:14:30,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:30,894 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:30,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:32,064 INFO L134 CoverageAnalysis]: Checked inductivity of 166096 backedges. 27648 proven. 1223 refuted. 0 times theorem prover too weak. 137225 trivial. 0 not checked. [2018-12-02 05:14:32,064 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:32,064 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:32,065 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:32,065 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:32,065 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:32,065 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:32,070 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:14:32,070 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:14:32,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:32,293 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:14:33,460 INFO L134 CoverageAnalysis]: Checked inductivity of 166096 backedges. 27691 proven. 1180 refuted. 0 times theorem prover too weak. 137225 trivial. 0 not checked. [2018-12-02 05:14:33,460 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:14:34,479 INFO L134 CoverageAnalysis]: Checked inductivity of 166096 backedges. 27691 proven. 1180 refuted. 0 times theorem prover too weak. 137225 trivial. 0 not checked. [2018-12-02 05:14:34,495 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:14:34,495 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 47, 47] total 72 [2018-12-02 05:14:34,495 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:14:34,496 INFO L459 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-12-02 05:14:34,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-12-02 05:14:34,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=3935, Unknown=0, NotChecked=0, Total=5112 [2018-12-02 05:14:34,496 INFO L87 Difference]: Start difference. First operand 1501 states and 1504 transitions. Second operand 72 states. [2018-12-02 05:14:35,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:35,891 INFO L93 Difference]: Finished difference Result 1632 states and 1636 transitions. [2018-12-02 05:14:35,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-02 05:14:35,892 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1492 [2018-12-02 05:14:35,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:35,894 INFO L225 Difference]: With dead ends: 1632 [2018-12-02 05:14:35,894 INFO L226 Difference]: Without dead ends: 1632 [2018-12-02 05:14:35,895 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3074 GetRequests, 2916 SyntacticMatches, 45 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4102 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3324, Invalid=9786, Unknown=0, NotChecked=0, Total=13110 [2018-12-02 05:14:35,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1632 states. [2018-12-02 05:14:35,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1632 to 1622. [2018-12-02 05:14:35,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1622 states. [2018-12-02 05:14:35,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1622 states to 1622 states and 1626 transitions. [2018-12-02 05:14:35,902 INFO L78 Accepts]: Start accepts. Automaton has 1622 states and 1626 transitions. Word has length 1492 [2018-12-02 05:14:35,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:35,903 INFO L480 AbstractCegarLoop]: Abstraction has 1622 states and 1626 transitions. [2018-12-02 05:14:35,903 INFO L481 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-12-02 05:14:35,903 INFO L276 IsEmpty]: Start isEmpty. Operand 1622 states and 1626 transitions. [2018-12-02 05:14:35,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1609 [2018-12-02 05:14:35,913 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:35,913 INFO L402 BasicCegarLoop]: trace histogram [274, 274, 273, 273, 273, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:35,913 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:35,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:35,913 INFO L82 PathProgramCache]: Analyzing trace with hash 1669692803, now seen corresponding path program 53 times [2018-12-02 05:14:35,914 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:35,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:35,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:14:35,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:35,914 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:35,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:37,312 INFO L134 CoverageAnalysis]: Checked inductivity of 194586 backedges. 54747 proven. 5154 refuted. 0 times theorem prover too weak. 134685 trivial. 0 not checked. [2018-12-02 05:14:37,312 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:37,312 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:37,313 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:37,313 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:37,313 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:37,313 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:37,320 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:14:37,320 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:14:37,946 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-12-02 05:14:37,947 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:14:37,957 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:14:39,653 INFO L134 CoverageAnalysis]: Checked inductivity of 194586 backedges. 52736 proven. 3425 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-02 05:14:39,654 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:14:42,020 INFO L134 CoverageAnalysis]: Checked inductivity of 194586 backedges. 52736 proven. 3425 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-02 05:14:42,036 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:14:42,037 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 51, 51] total 143 [2018-12-02 05:14:42,037 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:14:42,037 INFO L459 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-12-02 05:14:42,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-12-02 05:14:42,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2755, Invalid=17551, Unknown=0, NotChecked=0, Total=20306 [2018-12-02 05:14:42,038 INFO L87 Difference]: Start difference. First operand 1622 states and 1626 transitions. Second operand 98 states. [2018-12-02 05:14:50,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:50,198 INFO L93 Difference]: Finished difference Result 1637 states and 1639 transitions. [2018-12-02 05:14:50,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 119 states. [2018-12-02 05:14:50,198 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 1608 [2018-12-02 05:14:50,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:50,202 INFO L225 Difference]: With dead ends: 1637 [2018-12-02 05:14:50,202 INFO L226 Difference]: Without dead ends: 1631 [2018-12-02 05:14:50,204 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3377 GetRequests, 3120 SyntacticMatches, 5 SemanticMatches, 252 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22518 ImplicationChecksByTransitivity, 7.2s TimeCoverageRelationStatistics Valid=8925, Invalid=55337, Unknown=0, NotChecked=0, Total=64262 [2018-12-02 05:14:50,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1631 states. [2018-12-02 05:14:50,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1631 to 1622. [2018-12-02 05:14:50,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1622 states. [2018-12-02 05:14:50,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1622 states to 1622 states and 1624 transitions. [2018-12-02 05:14:50,213 INFO L78 Accepts]: Start accepts. Automaton has 1622 states and 1624 transitions. Word has length 1608 [2018-12-02 05:14:50,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:50,214 INFO L480 AbstractCegarLoop]: Abstraction has 1622 states and 1624 transitions. [2018-12-02 05:14:50,214 INFO L481 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-12-02 05:14:50,214 INFO L276 IsEmpty]: Start isEmpty. Operand 1622 states and 1624 transitions. [2018-12-02 05:14:50,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1614 [2018-12-02 05:14:50,225 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:50,226 INFO L402 BasicCegarLoop]: trace histogram [275, 275, 274, 274, 274, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:50,226 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:50,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:50,226 INFO L82 PathProgramCache]: Analyzing trace with hash 1280506436, now seen corresponding path program 54 times [2018-12-02 05:14:50,226 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:50,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:50,227 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:14:50,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:50,227 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:50,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:51,767 INFO L134 CoverageAnalysis]: Checked inductivity of 195975 backedges. 28980 proven. 1221 refuted. 0 times theorem prover too weak. 165774 trivial. 0 not checked. [2018-12-02 05:14:51,767 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:51,767 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:51,767 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:51,767 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:51,767 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:51,768 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:51,775 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:14:51,775 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:14:52,279 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:14:52,279 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:14:52,297 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:14:52,299 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:14:52,301 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:14:52,307 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:14:52,307 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:14:52,312 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:14:52,318 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:14:52,319 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:14:55,551 INFO L134 CoverageAnalysis]: Checked inductivity of 195975 backedges. 28980 proven. 1221 refuted. 0 times theorem prover too weak. 165774 trivial. 0 not checked. [2018-12-02 05:14:55,552 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:14:57,228 INFO L134 CoverageAnalysis]: Checked inductivity of 195975 backedges. 28980 proven. 1221 refuted. 0 times theorem prover too weak. 165774 trivial. 0 not checked. [2018-12-02 05:14:57,248 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:14:57,248 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 26] total 75 [2018-12-02 05:14:57,248 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:14:57,248 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-12-02 05:14:57,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-12-02 05:14:57,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=4523, Unknown=0, NotChecked=0, Total=5700 [2018-12-02 05:14:57,249 INFO L87 Difference]: Start difference. First operand 1622 states and 1624 transitions. Second operand 51 states. [2018-12-02 05:14:58,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:14:58,615 INFO L93 Difference]: Finished difference Result 1635 states and 1638 transitions. [2018-12-02 05:14:58,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-12-02 05:14:58,616 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 1613 [2018-12-02 05:14:58,616 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:14:58,618 INFO L225 Difference]: With dead ends: 1635 [2018-12-02 05:14:58,618 INFO L226 Difference]: Without dead ends: 1635 [2018-12-02 05:14:58,618 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3275 GetRequests, 3134 SyntacticMatches, 44 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3211 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2051, Invalid=7651, Unknown=0, NotChecked=0, Total=9702 [2018-12-02 05:14:58,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1635 states. [2018-12-02 05:14:58,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1635 to 1627. [2018-12-02 05:14:58,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1627 states. [2018-12-02 05:14:58,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1627 states to 1627 states and 1630 transitions. [2018-12-02 05:14:58,626 INFO L78 Accepts]: Start accepts. Automaton has 1627 states and 1630 transitions. Word has length 1613 [2018-12-02 05:14:58,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:14:58,627 INFO L480 AbstractCegarLoop]: Abstraction has 1627 states and 1630 transitions. [2018-12-02 05:14:58,627 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-12-02 05:14:58,627 INFO L276 IsEmpty]: Start isEmpty. Operand 1627 states and 1630 transitions. [2018-12-02 05:14:58,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1619 [2018-12-02 05:14:58,636 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:14:58,637 INFO L402 BasicCegarLoop]: trace histogram [276, 276, 275, 275, 275, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:14:58,637 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:14:58,637 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:14:58,637 INFO L82 PathProgramCache]: Analyzing trace with hash -1543312183, now seen corresponding path program 55 times [2018-12-02 05:14:58,637 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:14:58,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:58,638 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:14:58,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:14:58,638 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:14:58,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:14:59,960 INFO L134 CoverageAnalysis]: Checked inductivity of 197369 backedges. 31550 proven. 1347 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-02 05:14:59,961 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:59,961 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:14:59,961 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:14:59,961 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:14:59,961 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:14:59,961 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:14:59,968 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:14:59,969 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:15:00,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:15:00,207 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:15:01,527 INFO L134 CoverageAnalysis]: Checked inductivity of 197369 backedges. 31595 proven. 1302 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-02 05:15:01,527 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:15:02,713 INFO L134 CoverageAnalysis]: Checked inductivity of 197369 backedges. 31595 proven. 1302 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-02 05:15:02,729 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:15:02,730 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49, 49] total 75 [2018-12-02 05:15:02,730 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:15:02,730 INFO L459 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-12-02 05:15:02,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-12-02 05:15:02,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=4274, Unknown=0, NotChecked=0, Total=5550 [2018-12-02 05:15:02,731 INFO L87 Difference]: Start difference. First operand 1627 states and 1630 transitions. Second operand 75 states. [2018-12-02 05:15:04,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:15:04,226 INFO L93 Difference]: Finished difference Result 1763 states and 1767 transitions. [2018-12-02 05:15:04,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-12-02 05:15:04,227 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 1618 [2018-12-02 05:15:04,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:15:04,228 INFO L225 Difference]: With dead ends: 1763 [2018-12-02 05:15:04,229 INFO L226 Difference]: Without dead ends: 1763 [2018-12-02 05:15:04,229 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3330 GetRequests, 3165 SyntacticMatches, 47 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4473 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3613, Invalid=10667, Unknown=0, NotChecked=0, Total=14280 [2018-12-02 05:15:04,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1763 states. [2018-12-02 05:15:04,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1763 to 1753. [2018-12-02 05:15:04,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1753 states. [2018-12-02 05:15:04,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1753 states to 1753 states and 1757 transitions. [2018-12-02 05:15:04,237 INFO L78 Accepts]: Start accepts. Automaton has 1753 states and 1757 transitions. Word has length 1618 [2018-12-02 05:15:04,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:15:04,238 INFO L480 AbstractCegarLoop]: Abstraction has 1753 states and 1757 transitions. [2018-12-02 05:15:04,238 INFO L481 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-12-02 05:15:04,238 INFO L276 IsEmpty]: Start isEmpty. Operand 1753 states and 1757 transitions. [2018-12-02 05:15:04,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1740 [2018-12-02 05:15:04,250 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:15:04,250 INFO L402 BasicCegarLoop]: trace histogram [298, 298, 297, 297, 297, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:15:04,250 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:15:04,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:15:04,250 INFO L82 PathProgramCache]: Analyzing trace with hash -389187577, now seen corresponding path program 56 times [2018-12-02 05:15:04,250 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:15:04,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:04,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:15:04,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:04,251 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:15:04,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:15:05,910 INFO L134 CoverageAnalysis]: Checked inductivity of 229834 backedges. 86262 proven. 3792 refuted. 0 times theorem prover too weak. 139780 trivial. 0 not checked. [2018-12-02 05:15:05,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:05,910 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:15:05,910 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:15:05,910 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:15:05,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:05,910 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:15:05,916 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:15:05,917 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:15:06,763 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-12-02 05:15:06,763 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:15:06,776 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:15:08,726 INFO L134 CoverageAnalysis]: Checked inductivity of 229834 backedges. 60286 proven. 3753 refuted. 0 times theorem prover too weak. 165795 trivial. 0 not checked. [2018-12-02 05:15:08,726 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:15:11,338 INFO L134 CoverageAnalysis]: Checked inductivity of 229834 backedges. 60286 proven. 3753 refuted. 0 times theorem prover too weak. 165795 trivial. 0 not checked. [2018-12-02 05:15:11,354 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:15:11,355 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 53, 53] total 149 [2018-12-02 05:15:11,355 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:15:11,355 INFO L459 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-12-02 05:15:11,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-12-02 05:15:11,356 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3013, Invalid=19039, Unknown=0, NotChecked=0, Total=22052 [2018-12-02 05:15:11,356 INFO L87 Difference]: Start difference. First operand 1753 states and 1757 transitions. Second operand 102 states. [2018-12-02 05:15:17,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:15:17,184 INFO L93 Difference]: Finished difference Result 1768 states and 1770 transitions. [2018-12-02 05:15:17,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2018-12-02 05:15:17,185 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 1739 [2018-12-02 05:15:17,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:15:17,188 INFO L225 Difference]: With dead ends: 1768 [2018-12-02 05:15:17,188 INFO L226 Difference]: Without dead ends: 1762 [2018-12-02 05:15:17,192 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3626 GetRequests, 3378 SyntacticMatches, 5 SemanticMatches, 243 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19874 ImplicationChecksByTransitivity, 6.2s TimeCoverageRelationStatistics Valid=9914, Invalid=49866, Unknown=0, NotChecked=0, Total=59780 [2018-12-02 05:15:17,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1762 states. [2018-12-02 05:15:17,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1762 to 1753. [2018-12-02 05:15:17,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1753 states. [2018-12-02 05:15:17,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1753 states to 1753 states and 1755 transitions. [2018-12-02 05:15:17,206 INFO L78 Accepts]: Start accepts. Automaton has 1753 states and 1755 transitions. Word has length 1739 [2018-12-02 05:15:17,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:15:17,207 INFO L480 AbstractCegarLoop]: Abstraction has 1753 states and 1755 transitions. [2018-12-02 05:15:17,207 INFO L481 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-12-02 05:15:17,207 INFO L276 IsEmpty]: Start isEmpty. Operand 1753 states and 1755 transitions. [2018-12-02 05:15:17,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1745 [2018-12-02 05:15:17,222 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:15:17,222 INFO L402 BasicCegarLoop]: trace histogram [299, 299, 298, 298, 298, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:15:17,222 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:15:17,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:15:17,222 INFO L82 PathProgramCache]: Analyzing trace with hash 2087778252, now seen corresponding path program 57 times [2018-12-02 05:15:17,222 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:15:17,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:17,223 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:15:17,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:17,223 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:15:17,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:15:18,910 INFO L134 CoverageAnalysis]: Checked inductivity of 231344 backedges. 33000 proven. 1334 refuted. 0 times theorem prover too weak. 197010 trivial. 0 not checked. [2018-12-02 05:15:18,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:18,910 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:15:18,911 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:15:18,911 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:15:18,911 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:18,911 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:15:18,919 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:15:18,919 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:15:19,457 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:15:19,457 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:15:19,477 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:15:19,479 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:15:19,481 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:15:19,485 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:15:19,485 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:15:19,490 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:15:19,496 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:15:19,496 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:15:23,243 INFO L134 CoverageAnalysis]: Checked inductivity of 231344 backedges. 33000 proven. 1334 refuted. 0 times theorem prover too weak. 197010 trivial. 0 not checked. [2018-12-02 05:15:23,244 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:15:25,160 INFO L134 CoverageAnalysis]: Checked inductivity of 231344 backedges. 33000 proven. 1334 refuted. 0 times theorem prover too weak. 197010 trivial. 0 not checked. [2018-12-02 05:15:25,180 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:15:25,181 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 27] total 78 [2018-12-02 05:15:25,181 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:15:25,181 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-12-02 05:15:25,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-12-02 05:15:25,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1249, Invalid=4913, Unknown=0, NotChecked=0, Total=6162 [2018-12-02 05:15:25,182 INFO L87 Difference]: Start difference. First operand 1753 states and 1755 transitions. Second operand 53 states. [2018-12-02 05:15:27,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:15:27,939 INFO L93 Difference]: Finished difference Result 1766 states and 1769 transitions. [2018-12-02 05:15:27,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-02 05:15:27,940 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 1744 [2018-12-02 05:15:27,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:15:27,944 INFO L225 Difference]: With dead ends: 1766 [2018-12-02 05:15:27,944 INFO L226 Difference]: Without dead ends: 1766 [2018-12-02 05:15:27,945 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3539 GetRequests, 3392 SyntacticMatches, 46 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3471 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2172, Invalid=8334, Unknown=0, NotChecked=0, Total=10506 [2018-12-02 05:15:27,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1766 states. [2018-12-02 05:15:27,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1766 to 1758. [2018-12-02 05:15:27,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1758 states. [2018-12-02 05:15:27,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1758 states to 1758 states and 1761 transitions. [2018-12-02 05:15:27,959 INFO L78 Accepts]: Start accepts. Automaton has 1758 states and 1761 transitions. Word has length 1744 [2018-12-02 05:15:27,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:15:27,960 INFO L480 AbstractCegarLoop]: Abstraction has 1758 states and 1761 transitions. [2018-12-02 05:15:27,961 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-12-02 05:15:27,961 INFO L276 IsEmpty]: Start isEmpty. Operand 1758 states and 1761 transitions. [2018-12-02 05:15:27,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1750 [2018-12-02 05:15:27,975 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:15:27,976 INFO L402 BasicCegarLoop]: trace histogram [300, 300, 299, 299, 299, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:15:27,976 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:15:27,976 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:15:27,976 INFO L82 PathProgramCache]: Analyzing trace with hash -1607588799, now seen corresponding path program 58 times [2018-12-02 05:15:27,976 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:15:27,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:27,977 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:15:27,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:27,977 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:15:28,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:15:29,480 INFO L134 CoverageAnalysis]: Checked inductivity of 232859 backedges. 35802 proven. 1477 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-02 05:15:29,480 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:29,480 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:15:29,480 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:15:29,480 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:15:29,480 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:29,480 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:15:29,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:15:29,487 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:15:29,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:15:29,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:15:31,235 INFO L134 CoverageAnalysis]: Checked inductivity of 232859 backedges. 35849 proven. 1430 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-02 05:15:31,235 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:15:32,541 INFO L134 CoverageAnalysis]: Checked inductivity of 232859 backedges. 35849 proven. 1430 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-02 05:15:32,557 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:15:32,557 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 51, 51] total 78 [2018-12-02 05:15:32,557 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:15:32,558 INFO L459 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-12-02 05:15:32,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-12-02 05:15:32,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1379, Invalid=4627, Unknown=0, NotChecked=0, Total=6006 [2018-12-02 05:15:32,558 INFO L87 Difference]: Start difference. First operand 1758 states and 1761 transitions. Second operand 78 states. [2018-12-02 05:15:33,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:15:33,910 INFO L93 Difference]: Finished difference Result 1899 states and 1903 transitions. [2018-12-02 05:15:33,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-12-02 05:15:33,910 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1749 [2018-12-02 05:15:33,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:15:33,913 INFO L225 Difference]: With dead ends: 1899 [2018-12-02 05:15:33,913 INFO L226 Difference]: Without dead ends: 1899 [2018-12-02 05:15:33,914 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3596 GetRequests, 3424 SyntacticMatches, 49 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4860 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=3914, Invalid=11586, Unknown=0, NotChecked=0, Total=15500 [2018-12-02 05:15:33,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1899 states. [2018-12-02 05:15:33,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1899 to 1889. [2018-12-02 05:15:33,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1889 states. [2018-12-02 05:15:33,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1889 states to 1889 states and 1893 transitions. [2018-12-02 05:15:33,922 INFO L78 Accepts]: Start accepts. Automaton has 1889 states and 1893 transitions. Word has length 1749 [2018-12-02 05:15:33,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:15:33,923 INFO L480 AbstractCegarLoop]: Abstraction has 1889 states and 1893 transitions. [2018-12-02 05:15:33,923 INFO L481 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-12-02 05:15:33,923 INFO L276 IsEmpty]: Start isEmpty. Operand 1889 states and 1893 transitions. [2018-12-02 05:15:33,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1876 [2018-12-02 05:15:33,936 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:15:33,936 INFO L402 BasicCegarLoop]: trace histogram [323, 323, 322, 322, 322, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:15:33,936 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:15:33,936 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:15:33,936 INFO L82 PathProgramCache]: Analyzing trace with hash 1904395870, now seen corresponding path program 59 times [2018-12-02 05:15:33,936 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:15:33,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:33,937 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:15:33,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:33,937 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:15:34,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:15:35,703 INFO L134 CoverageAnalysis]: Checked inductivity of 269652 backedges. 70976 proven. 6137 refuted. 0 times theorem prover too weak. 192539 trivial. 0 not checked. [2018-12-02 05:15:35,704 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:35,704 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:15:35,704 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:15:35,704 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:15:35,704 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:35,704 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:15:35,712 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:15:35,712 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:15:36,920 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-12-02 05:15:36,920 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:15:36,933 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:15:39,080 INFO L134 CoverageAnalysis]: Checked inductivity of 269652 backedges. 68524 proven. 4096 refuted. 0 times theorem prover too weak. 197032 trivial. 0 not checked. [2018-12-02 05:15:39,080 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:15:41,969 INFO L134 CoverageAnalysis]: Checked inductivity of 269652 backedges. 68524 proven. 4096 refuted. 0 times theorem prover too weak. 197032 trivial. 0 not checked. [2018-12-02 05:15:41,986 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:15:41,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 55, 55] total 155 [2018-12-02 05:15:41,987 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:15:41,987 INFO L459 AbstractCegarLoop]: Interpolant automaton has 106 states [2018-12-02 05:15:41,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 106 interpolants. [2018-12-02 05:15:41,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3243, Invalid=20627, Unknown=0, NotChecked=0, Total=23870 [2018-12-02 05:15:41,988 INFO L87 Difference]: Start difference. First operand 1889 states and 1893 transitions. Second operand 106 states. [2018-12-02 05:15:48,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:15:48,927 INFO L93 Difference]: Finished difference Result 1904 states and 1906 transitions. [2018-12-02 05:15:48,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 129 states. [2018-12-02 05:15:48,928 INFO L78 Accepts]: Start accepts. Automaton has 106 states. Word has length 1875 [2018-12-02 05:15:48,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:15:48,933 INFO L225 Difference]: With dead ends: 1904 [2018-12-02 05:15:48,933 INFO L226 Difference]: Without dead ends: 1898 [2018-12-02 05:15:48,938 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3925 GetRequests, 3646 SyntacticMatches, 5 SemanticMatches, 274 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26753 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=10497, Invalid=65403, Unknown=0, NotChecked=0, Total=75900 [2018-12-02 05:15:48,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1898 states. [2018-12-02 05:15:48,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1898 to 1889. [2018-12-02 05:15:48,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1889 states. [2018-12-02 05:15:48,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1889 states to 1889 states and 1891 transitions. [2018-12-02 05:15:48,958 INFO L78 Accepts]: Start accepts. Automaton has 1889 states and 1891 transitions. Word has length 1875 [2018-12-02 05:15:48,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:15:48,959 INFO L480 AbstractCegarLoop]: Abstraction has 1889 states and 1891 transitions. [2018-12-02 05:15:48,959 INFO L481 AbstractCegarLoop]: Interpolant automaton has 106 states. [2018-12-02 05:15:48,959 INFO L276 IsEmpty]: Start isEmpty. Operand 1889 states and 1891 transitions. [2018-12-02 05:15:48,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1881 [2018-12-02 05:15:48,974 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:15:48,974 INFO L402 BasicCegarLoop]: trace histogram [324, 324, 323, 323, 323, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:15:48,974 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:15:48,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:15:48,974 INFO L82 PathProgramCache]: Analyzing trace with hash -763782711, now seen corresponding path program 60 times [2018-12-02 05:15:48,974 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:15:48,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:48,975 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:15:48,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:48,975 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:15:49,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:15:50,877 INFO L134 CoverageAnalysis]: Checked inductivity of 271288 backedges. 37375 proven. 1452 refuted. 0 times theorem prover too weak. 232461 trivial. 0 not checked. [2018-12-02 05:15:50,877 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:50,877 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:15:50,877 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:15:50,877 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:15:50,878 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:15:50,878 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:15:50,883 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:15:50,883 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:15:51,536 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:15:51,536 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:15:51,563 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:15:51,565 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:15:51,567 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:15:51,572 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:15:51,572 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:15:51,578 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:15:51,585 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:15:51,585 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:15:55,936 INFO L134 CoverageAnalysis]: Checked inductivity of 271288 backedges. 37375 proven. 1452 refuted. 0 times theorem prover too weak. 232461 trivial. 0 not checked. [2018-12-02 05:15:55,936 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:15:58,360 INFO L134 CoverageAnalysis]: Checked inductivity of 271288 backedges. 37375 proven. 1452 refuted. 0 times theorem prover too weak. 232461 trivial. 0 not checked. [2018-12-02 05:15:58,381 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:15:58,381 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 28] total 81 [2018-12-02 05:15:58,381 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:15:58,382 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-12-02 05:15:58,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-12-02 05:15:58,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1321, Invalid=5321, Unknown=0, NotChecked=0, Total=6642 [2018-12-02 05:15:58,382 INFO L87 Difference]: Start difference. First operand 1889 states and 1891 transitions. Second operand 55 states. [2018-12-02 05:15:59,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:15:59,899 INFO L93 Difference]: Finished difference Result 1902 states and 1905 transitions. [2018-12-02 05:15:59,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-02 05:15:59,899 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 1880 [2018-12-02 05:15:59,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:15:59,903 INFO L225 Difference]: With dead ends: 1902 [2018-12-02 05:15:59,903 INFO L226 Difference]: Without dead ends: 1902 [2018-12-02 05:15:59,904 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3813 GetRequests, 3660 SyntacticMatches, 48 SemanticMatches, 105 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3739 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2292, Invalid=9050, Unknown=0, NotChecked=0, Total=11342 [2018-12-02 05:15:59,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1902 states. [2018-12-02 05:15:59,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1902 to 1894. [2018-12-02 05:15:59,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1894 states. [2018-12-02 05:15:59,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1894 states to 1894 states and 1897 transitions. [2018-12-02 05:15:59,918 INFO L78 Accepts]: Start accepts. Automaton has 1894 states and 1897 transitions. Word has length 1880 [2018-12-02 05:15:59,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:15:59,919 INFO L480 AbstractCegarLoop]: Abstraction has 1894 states and 1897 transitions. [2018-12-02 05:15:59,919 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-12-02 05:15:59,919 INFO L276 IsEmpty]: Start isEmpty. Operand 1894 states and 1897 transitions. [2018-12-02 05:15:59,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1886 [2018-12-02 05:15:59,932 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:15:59,932 INFO L402 BasicCegarLoop]: trace histogram [325, 325, 324, 324, 324, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:15:59,932 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:15:59,932 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:15:59,932 INFO L82 PathProgramCache]: Analyzing trace with hash 991705188, now seen corresponding path program 61 times [2018-12-02 05:15:59,932 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:15:59,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:59,933 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:15:59,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:15:59,933 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:16:00,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:16:01,666 INFO L134 CoverageAnalysis]: Checked inductivity of 272929 backedges. 40419 proven. 1613 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-02 05:16:01,667 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:01,667 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:16:01,667 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:16:01,667 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:16:01,667 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:01,667 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:16:01,674 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:16:01,674 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:16:01,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:16:01,968 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:16:03,600 INFO L134 CoverageAnalysis]: Checked inductivity of 272929 backedges. 40468 proven. 1564 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-02 05:16:03,600 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:16:05,067 INFO L134 CoverageAnalysis]: Checked inductivity of 272929 backedges. 40468 proven. 1564 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-02 05:16:05,083 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:16:05,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53, 53] total 81 [2018-12-02 05:16:05,084 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:16:05,085 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-12-02 05:16:05,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-12-02 05:16:05,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1486, Invalid=4994, Unknown=0, NotChecked=0, Total=6480 [2018-12-02 05:16:05,085 INFO L87 Difference]: Start difference. First operand 1894 states and 1897 transitions. Second operand 81 states. [2018-12-02 05:16:06,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:16:06,431 INFO L93 Difference]: Finished difference Result 2040 states and 2044 transitions. [2018-12-02 05:16:06,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-02 05:16:06,432 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1885 [2018-12-02 05:16:06,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:16:06,435 INFO L225 Difference]: With dead ends: 2040 [2018-12-02 05:16:06,435 INFO L226 Difference]: Without dead ends: 2040 [2018-12-02 05:16:06,436 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3872 GetRequests, 3693 SyntacticMatches, 51 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5263 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=4227, Invalid=12543, Unknown=0, NotChecked=0, Total=16770 [2018-12-02 05:16:06,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2040 states. [2018-12-02 05:16:06,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2040 to 2030. [2018-12-02 05:16:06,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2030 states. [2018-12-02 05:16:06,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2030 states to 2030 states and 2034 transitions. [2018-12-02 05:16:06,445 INFO L78 Accepts]: Start accepts. Automaton has 2030 states and 2034 transitions. Word has length 1885 [2018-12-02 05:16:06,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:16:06,446 INFO L480 AbstractCegarLoop]: Abstraction has 2030 states and 2034 transitions. [2018-12-02 05:16:06,446 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-12-02 05:16:06,446 INFO L276 IsEmpty]: Start isEmpty. Operand 2030 states and 2034 transitions. [2018-12-02 05:16:06,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2017 [2018-12-02 05:16:06,460 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:16:06,460 INFO L402 BasicCegarLoop]: trace histogram [349, 349, 348, 348, 348, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:16:06,460 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:16:06,461 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:16:06,461 INFO L82 PathProgramCache]: Analyzing trace with hash 924657132, now seen corresponding path program 62 times [2018-12-02 05:16:06,461 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:16:06,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:06,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:16:06,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:06,461 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:16:06,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:16:08,566 INFO L134 CoverageAnalysis]: Checked inductivity of 314418 backedges. 41992 proven. 1575 refuted. 0 times theorem prover too weak. 270851 trivial. 0 not checked. [2018-12-02 05:16:08,567 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:08,567 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:16:08,567 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:16:08,567 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:16:08,567 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:08,567 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:16:08,574 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:16:08,575 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:16:09,592 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-12-02 05:16:09,592 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:16:09,608 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:16:11,972 INFO L134 CoverageAnalysis]: Checked inductivity of 314418 backedges. 77480 proven. 4454 refuted. 0 times theorem prover too weak. 232484 trivial. 0 not checked. [2018-12-02 05:16:11,972 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:16:15,168 INFO L134 CoverageAnalysis]: Checked inductivity of 314418 backedges. 77480 proven. 4454 refuted. 0 times theorem prover too weak. 232484 trivial. 0 not checked. [2018-12-02 05:16:15,184 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:16:15,185 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 57, 57] total 137 [2018-12-02 05:16:15,185 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:16:15,185 INFO L459 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-12-02 05:16:15,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-12-02 05:16:15,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2551, Invalid=16081, Unknown=0, NotChecked=0, Total=18632 [2018-12-02 05:16:15,186 INFO L87 Difference]: Start difference. First operand 2030 states and 2034 transitions. Second operand 86 states. [2018-12-02 05:16:22,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:16:22,554 INFO L93 Difference]: Finished difference Result 2192 states and 2198 transitions. [2018-12-02 05:16:22,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2018-12-02 05:16:22,554 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 2016 [2018-12-02 05:16:22,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:16:22,557 INFO L225 Difference]: With dead ends: 2192 [2018-12-02 05:16:22,557 INFO L226 Difference]: Without dead ends: 2192 [2018-12-02 05:16:22,559 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4144 GetRequests, 3921 SyntacticMatches, 5 SemanticMatches, 218 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13121 ImplicationChecksByTransitivity, 8.5s TimeCoverageRelationStatistics Valid=8886, Invalid=39294, Unknown=0, NotChecked=0, Total=48180 [2018-12-02 05:16:22,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2192 states. [2018-12-02 05:16:22,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2192 to 2041. [2018-12-02 05:16:22,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2041 states. [2018-12-02 05:16:22,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2041 states to 2041 states and 2046 transitions. [2018-12-02 05:16:22,568 INFO L78 Accepts]: Start accepts. Automaton has 2041 states and 2046 transitions. Word has length 2016 [2018-12-02 05:16:22,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:16:22,569 INFO L480 AbstractCegarLoop]: Abstraction has 2041 states and 2046 transitions. [2018-12-02 05:16:22,569 INFO L481 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-12-02 05:16:22,569 INFO L276 IsEmpty]: Start isEmpty. Operand 2041 states and 2046 transitions. [2018-12-02 05:16:22,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2027 [2018-12-02 05:16:22,583 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:16:22,583 INFO L402 BasicCegarLoop]: trace histogram [351, 351, 350, 350, 350, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:16:22,584 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:16:22,584 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:16:22,584 INFO L82 PathProgramCache]: Analyzing trace with hash -1291341978, now seen corresponding path program 63 times [2018-12-02 05:16:22,584 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:16:22,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:22,584 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:16:22,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:22,584 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:16:22,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:16:24,756 INFO L134 CoverageAnalysis]: Checked inductivity of 317957 backedges. 43764 proven. 1703 refuted. 0 times theorem prover too weak. 272490 trivial. 0 not checked. [2018-12-02 05:16:24,756 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:24,756 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:16:24,756 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:16:24,757 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:16:24,757 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:24,757 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:16:24,762 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:16:24,762 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:16:25,015 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:16:25,015 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:16:25,032 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:16:27,331 INFO L134 CoverageAnalysis]: Checked inductivity of 317957 backedges. 45226 proven. 5632 refuted. 0 times theorem prover too weak. 267099 trivial. 0 not checked. [2018-12-02 05:16:27,331 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:16:29,715 INFO L134 CoverageAnalysis]: Checked inductivity of 317957 backedges. 45226 proven. 5632 refuted. 0 times theorem prover too weak. 267099 trivial. 0 not checked. [2018-12-02 05:16:29,731 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:16:29,732 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 59, 59] total 119 [2018-12-02 05:16:29,732 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:16:29,732 INFO L459 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-12-02 05:16:29,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-12-02 05:16:29,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1984, Invalid=12058, Unknown=0, NotChecked=0, Total=14042 [2018-12-02 05:16:29,733 INFO L87 Difference]: Start difference. First operand 2041 states and 2046 transitions. Second operand 89 states. [2018-12-02 05:16:34,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:16:34,426 INFO L93 Difference]: Finished difference Result 2357 states and 2368 transitions. [2018-12-02 05:16:34,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2018-12-02 05:16:34,426 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 2026 [2018-12-02 05:16:34,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:16:34,428 INFO L225 Difference]: With dead ends: 2357 [2018-12-02 05:16:34,429 INFO L226 Difference]: Without dead ends: 2357 [2018-12-02 05:16:34,430 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4194 GetRequests, 3962 SyntacticMatches, 28 SemanticMatches, 204 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12218 ImplicationChecksByTransitivity, 6.2s TimeCoverageRelationStatistics Valid=5562, Invalid=36668, Unknown=0, NotChecked=0, Total=42230 [2018-12-02 05:16:34,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2357 states. [2018-12-02 05:16:34,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2357 to 2335. [2018-12-02 05:16:34,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2335 states. [2018-12-02 05:16:34,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2335 states to 2335 states and 2346 transitions. [2018-12-02 05:16:34,440 INFO L78 Accepts]: Start accepts. Automaton has 2335 states and 2346 transitions. Word has length 2026 [2018-12-02 05:16:34,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:16:34,441 INFO L480 AbstractCegarLoop]: Abstraction has 2335 states and 2346 transitions. [2018-12-02 05:16:34,441 INFO L481 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-12-02 05:16:34,441 INFO L276 IsEmpty]: Start isEmpty. Operand 2335 states and 2346 transitions. [2018-12-02 05:16:34,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2163 [2018-12-02 05:16:34,457 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:16:34,458 INFO L402 BasicCegarLoop]: trace histogram [376, 376, 375, 375, 375, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:16:34,458 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:16:34,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:16:34,458 INFO L82 PathProgramCache]: Analyzing trace with hash -926992273, now seen corresponding path program 64 times [2018-12-02 05:16:34,458 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:16:34,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:34,459 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:16:34,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:34,459 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:16:34,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:16:36,605 INFO L134 CoverageAnalysis]: Checked inductivity of 364525 backedges. 87066 proven. 10120 refuted. 0 times theorem prover too weak. 267339 trivial. 0 not checked. [2018-12-02 05:16:36,605 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:36,605 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:16:36,606 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:16:36,606 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:16:36,606 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:36,606 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:16:36,611 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:16:36,611 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:16:36,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:16:36,932 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:16:38,652 INFO L134 CoverageAnalysis]: Checked inductivity of 364525 backedges. 125355 proven. 1404 refuted. 0 times theorem prover too weak. 237766 trivial. 0 not checked. [2018-12-02 05:16:38,652 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:16:41,128 INFO L134 CoverageAnalysis]: Checked inductivity of 364525 backedges. 87416 proven. 4457 refuted. 0 times theorem prover too weak. 272652 trivial. 0 not checked. [2018-12-02 05:16:41,145 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:16:41,146 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 52, 52] total 107 [2018-12-02 05:16:41,146 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:16:41,147 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-12-02 05:16:41,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-12-02 05:16:41,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2414, Invalid=8928, Unknown=0, NotChecked=0, Total=11342 [2018-12-02 05:16:41,148 INFO L87 Difference]: Start difference. First operand 2335 states and 2346 transitions. Second operand 82 states. [2018-12-02 05:16:42,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:16:42,977 INFO L93 Difference]: Finished difference Result 2193 states and 2198 transitions. [2018-12-02 05:16:42,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2018-12-02 05:16:42,977 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 2162 [2018-12-02 05:16:42,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:16:42,979 INFO L225 Difference]: With dead ends: 2193 [2018-12-02 05:16:42,979 INFO L226 Difference]: Without dead ends: 2184 [2018-12-02 05:16:42,980 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4432 GetRequests, 4249 SyntacticMatches, 26 SemanticMatches, 157 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9203 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=5895, Invalid=19227, Unknown=0, NotChecked=0, Total=25122 [2018-12-02 05:16:42,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2184 states. [2018-12-02 05:16:42,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2184 to 2181. [2018-12-02 05:16:42,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2181 states. [2018-12-02 05:16:42,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2181 states to 2181 states and 2186 transitions. [2018-12-02 05:16:42,990 INFO L78 Accepts]: Start accepts. Automaton has 2181 states and 2186 transitions. Word has length 2162 [2018-12-02 05:16:42,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:16:42,990 INFO L480 AbstractCegarLoop]: Abstraction has 2181 states and 2186 transitions. [2018-12-02 05:16:42,990 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-12-02 05:16:42,990 INFO L276 IsEmpty]: Start isEmpty. Operand 2181 states and 2186 transitions. [2018-12-02 05:16:43,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2168 [2018-12-02 05:16:43,007 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:16:43,007 INFO L402 BasicCegarLoop]: trace histogram [377, 377, 376, 376, 376, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:16:43,007 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:16:43,007 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:16:43,007 INFO L82 PathProgramCache]: Analyzing trace with hash 515644234, now seen corresponding path program 65 times [2018-12-02 05:16:43,008 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:16:43,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:43,008 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:16:43,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:16:43,008 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:16:43,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:16:45,230 INFO L134 CoverageAnalysis]: Checked inductivity of 366428 backedges. 91891 proven. 7204 refuted. 0 times theorem prover too weak. 267333 trivial. 0 not checked. [2018-12-02 05:16:45,230 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:45,230 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:16:45,231 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:16:45,231 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:16:45,231 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:16:45,231 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:16:45,241 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:16:45,241 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:16:46,246 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-12-02 05:16:46,246 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:16:46,262 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:16:46,264 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:16:46,266 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:16:46,270 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:16:46,270 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:16:46,278 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:16:46,286 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:16:46,286 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:16:52,957 INFO L134 CoverageAnalysis]: Checked inductivity of 366428 backedges. 87075 proven. 5057 refuted. 0 times theorem prover too weak. 274296 trivial. 0 not checked. [2018-12-02 05:16:52,957 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:16:56,961 INFO L134 CoverageAnalysis]: Checked inductivity of 366428 backedges. 86929 proven. 5203 refuted. 0 times theorem prover too weak. 274296 trivial. 0 not checked. [2018-12-02 05:16:56,979 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:16:56,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 37, 35] total 128 [2018-12-02 05:16:56,979 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:16:56,980 INFO L459 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-12-02 05:16:56,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-12-02 05:16:56,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2721, Invalid=13535, Unknown=0, NotChecked=0, Total=16256 [2018-12-02 05:16:56,981 INFO L87 Difference]: Start difference. First operand 2181 states and 2186 transitions. Second operand 94 states. [2018-12-02 05:17:09,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:17:09,405 INFO L93 Difference]: Finished difference Result 2194 states and 2197 transitions. [2018-12-02 05:17:09,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 165 states. [2018-12-02 05:17:09,406 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2167 [2018-12-02 05:17:09,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:17:09,410 INFO L225 Difference]: With dead ends: 2194 [2018-12-02 05:17:09,410 INFO L226 Difference]: Without dead ends: 2188 [2018-12-02 05:17:09,415 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4552 GetRequests, 4217 SyntacticMatches, 49 SemanticMatches, 286 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31760 ImplicationChecksByTransitivity, 13.0s TimeCoverageRelationStatistics Valid=14484, Invalid=68172, Unknown=0, NotChecked=0, Total=82656 [2018-12-02 05:17:09,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2188 states. [2018-12-02 05:17:09,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2188 to 2181. [2018-12-02 05:17:09,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2181 states. [2018-12-02 05:17:09,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2181 states to 2181 states and 2184 transitions. [2018-12-02 05:17:09,434 INFO L78 Accepts]: Start accepts. Automaton has 2181 states and 2184 transitions. Word has length 2167 [2018-12-02 05:17:09,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:17:09,435 INFO L480 AbstractCegarLoop]: Abstraction has 2181 states and 2184 transitions. [2018-12-02 05:17:09,435 INFO L481 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-12-02 05:17:09,435 INFO L276 IsEmpty]: Start isEmpty. Operand 2181 states and 2184 transitions. [2018-12-02 05:17:09,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2173 [2018-12-02 05:17:09,456 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:17:09,456 INFO L402 BasicCegarLoop]: trace histogram [378, 378, 377, 377, 377, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:17:09,456 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:17:09,456 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:17:09,456 INFO L82 PathProgramCache]: Analyzing trace with hash 1279424361, now seen corresponding path program 66 times [2018-12-02 05:17:09,456 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:17:09,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:09,457 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:17:09,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:09,457 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:17:09,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:17:11,560 INFO L134 CoverageAnalysis]: Checked inductivity of 368336 backedges. 50808 proven. 1903 refuted. 0 times theorem prover too weak. 315625 trivial. 0 not checked. [2018-12-02 05:17:11,560 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:11,560 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:17:11,561 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:17:11,561 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:17:11,561 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:11,561 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:17:11,566 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:17:11,566 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:17:11,838 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:17:11,838 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:17:11,859 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:17:14,027 INFO L134 CoverageAnalysis]: Checked inductivity of 368336 backedges. 50611 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2018-12-02 05:17:14,027 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:17:16,007 INFO L134 CoverageAnalysis]: Checked inductivity of 368336 backedges. 50611 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2018-12-02 05:17:16,023 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:17:16,024 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 61, 61] total 94 [2018-12-02 05:17:16,024 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:17:16,025 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-12-02 05:17:16,025 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-12-02 05:17:16,025 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1742, Invalid=7000, Unknown=0, NotChecked=0, Total=8742 [2018-12-02 05:17:16,025 INFO L87 Difference]: Start difference. First operand 2181 states and 2184 transitions. Second operand 91 states. [2018-12-02 05:17:18,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:17:18,207 INFO L93 Difference]: Finished difference Result 2337 states and 2341 transitions. [2018-12-02 05:17:18,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-12-02 05:17:18,208 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2172 [2018-12-02 05:17:18,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:17:18,211 INFO L225 Difference]: With dead ends: 2337 [2018-12-02 05:17:18,211 INFO L226 Difference]: Without dead ends: 2337 [2018-12-02 05:17:18,212 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4456 GetRequests, 4252 SyntacticMatches, 57 SemanticMatches, 147 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7221 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=4838, Invalid=17214, Unknown=0, NotChecked=0, Total=22052 [2018-12-02 05:17:18,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2337 states. [2018-12-02 05:17:18,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2337 to 2327. [2018-12-02 05:17:18,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2327 states. [2018-12-02 05:17:18,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2327 states to 2327 states and 2331 transitions. [2018-12-02 05:17:18,224 INFO L78 Accepts]: Start accepts. Automaton has 2327 states and 2331 transitions. Word has length 2172 [2018-12-02 05:17:18,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:17:18,225 INFO L480 AbstractCegarLoop]: Abstraction has 2327 states and 2331 transitions. [2018-12-02 05:17:18,225 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-12-02 05:17:18,225 INFO L276 IsEmpty]: Start isEmpty. Operand 2327 states and 2331 transitions. [2018-12-02 05:17:18,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2314 [2018-12-02 05:17:18,244 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:17:18,244 INFO L402 BasicCegarLoop]: trace histogram [404, 404, 403, 403, 403, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:17:18,244 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:17:18,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:17:18,245 INFO L82 PathProgramCache]: Analyzing trace with hash -1921720281, now seen corresponding path program 67 times [2018-12-02 05:17:18,245 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:17:18,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:18,245 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:17:18,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:18,245 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:17:18,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:17:20,792 INFO L134 CoverageAnalysis]: Checked inductivity of 420381 backedges. 140744 proven. 5262 refuted. 0 times theorem prover too weak. 274375 trivial. 0 not checked. [2018-12-02 05:17:20,793 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:20,793 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:17:20,793 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:17:20,793 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:17:20,793 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:20,793 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:17:20,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:17:20,799 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:17:21,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:17:21,152 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:17:23,675 INFO L134 CoverageAnalysis]: Checked inductivity of 420381 backedges. 101244 proven. 1651 refuted. 0 times theorem prover too weak. 317486 trivial. 0 not checked. [2018-12-02 05:17:23,675 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:17:26,607 INFO L134 CoverageAnalysis]: Checked inductivity of 420381 backedges. 101244 proven. 1651 refuted. 0 times theorem prover too weak. 317486 trivial. 0 not checked. [2018-12-02 05:17:26,624 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:17:26,624 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 56, 56] total 138 [2018-12-02 05:17:26,624 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:17:26,625 INFO L459 AbstractCegarLoop]: Interpolant automaton has 111 states [2018-12-02 05:17:26,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 111 interpolants. [2018-12-02 05:17:26,626 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3163, Invalid=15743, Unknown=0, NotChecked=0, Total=18906 [2018-12-02 05:17:26,626 INFO L87 Difference]: Start difference. First operand 2327 states and 2331 transitions. Second operand 111 states. [2018-12-02 05:17:31,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:17:31,319 INFO L93 Difference]: Finished difference Result 2338 states and 2340 transitions. [2018-12-02 05:17:31,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2018-12-02 05:17:31,319 INFO L78 Accepts]: Start accepts. Automaton has 111 states. Word has length 2313 [2018-12-02 05:17:31,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:17:31,322 INFO L225 Difference]: With dead ends: 2338 [2018-12-02 05:17:31,323 INFO L226 Difference]: Without dead ends: 2332 [2018-12-02 05:17:31,324 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4765 GetRequests, 4522 SyntacticMatches, 28 SemanticMatches, 215 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20752 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=8227, Invalid=38645, Unknown=0, NotChecked=0, Total=46872 [2018-12-02 05:17:31,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2332 states. [2018-12-02 05:17:31,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2332 to 2327. [2018-12-02 05:17:31,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2327 states. [2018-12-02 05:17:31,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2327 states to 2327 states and 2329 transitions. [2018-12-02 05:17:31,334 INFO L78 Accepts]: Start accepts. Automaton has 2327 states and 2329 transitions. Word has length 2313 [2018-12-02 05:17:31,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:17:31,335 INFO L480 AbstractCegarLoop]: Abstraction has 2327 states and 2329 transitions. [2018-12-02 05:17:31,335 INFO L481 AbstractCegarLoop]: Interpolant automaton has 111 states. [2018-12-02 05:17:31,336 INFO L276 IsEmpty]: Start isEmpty. Operand 2327 states and 2329 transitions. [2018-12-02 05:17:31,355 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2319 [2018-12-02 05:17:31,355 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:17:31,356 INFO L402 BasicCegarLoop]: trace histogram [405, 405, 404, 404, 404, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:17:31,356 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:17:31,356 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:17:31,356 INFO L82 PathProgramCache]: Analyzing trace with hash 1065563308, now seen corresponding path program 68 times [2018-12-02 05:17:31,356 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:17:31,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:31,357 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:17:31,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:31,357 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:17:31,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:17:34,020 INFO L134 CoverageAnalysis]: Checked inductivity of 422425 backedges. 52780 proven. 1836 refuted. 0 times theorem prover too weak. 367809 trivial. 0 not checked. [2018-12-02 05:17:34,020 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:34,020 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:17:34,020 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:17:34,020 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:17:34,020 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:34,020 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:17:34,026 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:17:34,026 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:17:35,864 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-12-02 05:17:35,864 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:17:35,881 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:17:35,884 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:17:35,898 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:17:35,904 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:17:35,904 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:17:35,910 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:17:35,916 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:17:35,916 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:17:41,731 INFO L134 CoverageAnalysis]: Checked inductivity of 422425 backedges. 52780 proven. 1836 refuted. 0 times theorem prover too weak. 367809 trivial. 0 not checked. [2018-12-02 05:17:41,731 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:17:44,917 INFO L134 CoverageAnalysis]: Checked inductivity of 422425 backedges. 52780 proven. 1836 refuted. 0 times theorem prover too weak. 367809 trivial. 0 not checked. [2018-12-02 05:17:44,934 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:17:44,935 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 33, 32] total 65 [2018-12-02 05:17:44,935 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:17:44,935 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-02 05:17:44,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-02 05:17:44,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1493, Invalid=2797, Unknown=0, NotChecked=0, Total=4290 [2018-12-02 05:17:44,936 INFO L87 Difference]: Start difference. First operand 2327 states and 2329 transitions. Second operand 35 states. [2018-12-02 05:17:45,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:17:45,727 INFO L93 Difference]: Finished difference Result 2340 states and 2343 transitions. [2018-12-02 05:17:45,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-02 05:17:45,728 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 2318 [2018-12-02 05:17:45,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:17:45,730 INFO L225 Difference]: With dead ends: 2340 [2018-12-02 05:17:45,730 INFO L226 Difference]: Without dead ends: 2340 [2018-12-02 05:17:45,731 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4695 GetRequests, 4549 SyntacticMatches, 54 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1817 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2982, Invalid=5760, Unknown=0, NotChecked=0, Total=8742 [2018-12-02 05:17:45,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2340 states. [2018-12-02 05:17:45,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2340 to 2332. [2018-12-02 05:17:45,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2332 states. [2018-12-02 05:17:45,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2332 states to 2332 states and 2335 transitions. [2018-12-02 05:17:45,741 INFO L78 Accepts]: Start accepts. Automaton has 2332 states and 2335 transitions. Word has length 2318 [2018-12-02 05:17:45,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:17:45,742 INFO L480 AbstractCegarLoop]: Abstraction has 2332 states and 2335 transitions. [2018-12-02 05:17:45,742 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-02 05:17:45,742 INFO L276 IsEmpty]: Start isEmpty. Operand 2332 states and 2335 transitions. [2018-12-02 05:17:45,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2324 [2018-12-02 05:17:45,761 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:17:45,761 INFO L402 BasicCegarLoop]: trace histogram [406, 406, 405, 405, 405, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:17:45,761 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:17:45,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:17:45,761 INFO L82 PathProgramCache]: Analyzing trace with hash -648088735, now seen corresponding path program 69 times [2018-12-02 05:17:45,761 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:17:45,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:45,762 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:17:45,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:45,762 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:17:45,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:17:48,094 INFO L134 CoverageAnalysis]: Checked inductivity of 424474 backedges. 56610 proven. 2057 refuted. 0 times theorem prover too weak. 365807 trivial. 0 not checked. [2018-12-02 05:17:48,094 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:48,094 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:17:48,095 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:17:48,095 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:17:48,095 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:48,095 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:17:48,102 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:17:48,102 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:17:48,394 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:17:48,395 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:17:48,412 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:17:50,809 INFO L134 CoverageAnalysis]: Checked inductivity of 424474 backedges. 56406 proven. 6543 refuted. 0 times theorem prover too weak. 361525 trivial. 0 not checked. [2018-12-02 05:17:50,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:17:52,973 INFO L134 CoverageAnalysis]: Checked inductivity of 424474 backedges. 56406 proven. 6543 refuted. 0 times theorem prover too weak. 361525 trivial. 0 not checked. [2018-12-02 05:17:52,989 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:17:52,990 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 63, 63] total 97 [2018-12-02 05:17:52,990 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:17:52,990 INFO L459 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-12-02 05:17:52,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-12-02 05:17:52,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1861, Invalid=7451, Unknown=0, NotChecked=0, Total=9312 [2018-12-02 05:17:52,991 INFO L87 Difference]: Start difference. First operand 2332 states and 2335 transitions. Second operand 94 states. [2018-12-02 05:17:54,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:17:54,698 INFO L93 Difference]: Finished difference Result 2493 states and 2497 transitions. [2018-12-02 05:17:54,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-12-02 05:17:54,699 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2323 [2018-12-02 05:17:54,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:17:54,702 INFO L225 Difference]: With dead ends: 2493 [2018-12-02 05:17:54,702 INFO L226 Difference]: Without dead ends: 2493 [2018-12-02 05:17:54,703 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4762 GetRequests, 4551 SyntacticMatches, 59 SemanticMatches, 152 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7713 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=5182, Invalid=18380, Unknown=0, NotChecked=0, Total=23562 [2018-12-02 05:17:54,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2493 states. [2018-12-02 05:17:54,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2493 to 2483. [2018-12-02 05:17:54,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2483 states. [2018-12-02 05:17:54,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2483 states to 2483 states and 2487 transitions. [2018-12-02 05:17:54,714 INFO L78 Accepts]: Start accepts. Automaton has 2483 states and 2487 transitions. Word has length 2323 [2018-12-02 05:17:54,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:17:54,715 INFO L480 AbstractCegarLoop]: Abstraction has 2483 states and 2487 transitions. [2018-12-02 05:17:54,715 INFO L481 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-12-02 05:17:54,715 INFO L276 IsEmpty]: Start isEmpty. Operand 2483 states and 2487 transitions. [2018-12-02 05:17:54,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2470 [2018-12-02 05:17:54,735 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:17:54,736 INFO L402 BasicCegarLoop]: trace histogram [433, 433, 432, 432, 432, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:17:54,736 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:17:54,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:17:54,736 INFO L82 PathProgramCache]: Analyzing trace with hash 502213310, now seen corresponding path program 70 times [2018-12-02 05:17:54,736 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:17:54,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:54,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:17:54,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:17:54,737 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:17:54,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:17:57,451 INFO L134 CoverageAnalysis]: Checked inductivity of 482409 backedges. 112422 proven. 8355 refuted. 0 times theorem prover too weak. 361632 trivial. 0 not checked. [2018-12-02 05:17:57,451 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:57,451 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:17:57,452 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:17:57,452 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:17:57,452 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:17:57,452 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:17:57,458 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:17:57,458 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:17:57,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:17:57,859 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:18:00,106 INFO L134 CoverageAnalysis]: Checked inductivity of 482409 backedges. 112820 proven. 1782 refuted. 0 times theorem prover too weak. 367807 trivial. 0 not checked. [2018-12-02 05:18:00,106 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:18:03,004 INFO L134 CoverageAnalysis]: Checked inductivity of 482409 backedges. 112820 proven. 1782 refuted. 0 times theorem prover too weak. 367807 trivial. 0 not checked. [2018-12-02 05:18:03,021 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:18:03,022 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 58, 58] total 119 [2018-12-02 05:18:03,022 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:18:03,023 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-12-02 05:18:03,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-12-02 05:18:03,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2996, Invalid=11046, Unknown=0, NotChecked=0, Total=14042 [2018-12-02 05:18:03,024 INFO L87 Difference]: Start difference. First operand 2483 states and 2487 transitions. Second operand 91 states. [2018-12-02 05:18:05,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:18:05,983 INFO L93 Difference]: Finished difference Result 2494 states and 2496 transitions. [2018-12-02 05:18:05,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-12-02 05:18:05,983 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2469 [2018-12-02 05:18:05,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:18:05,987 INFO L225 Difference]: With dead ends: 2494 [2018-12-02 05:18:05,987 INFO L226 Difference]: Without dead ends: 2488 [2018-12-02 05:18:05,989 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5058 GetRequests, 4854 SyntacticMatches, 29 SemanticMatches, 175 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11528 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=7314, Invalid=23838, Unknown=0, NotChecked=0, Total=31152 [2018-12-02 05:18:05,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2488 states. [2018-12-02 05:18:06,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2488 to 2483. [2018-12-02 05:18:06,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2483 states. [2018-12-02 05:18:06,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2483 states to 2483 states and 2485 transitions. [2018-12-02 05:18:06,004 INFO L78 Accepts]: Start accepts. Automaton has 2483 states and 2485 transitions. Word has length 2469 [2018-12-02 05:18:06,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:18:06,005 INFO L480 AbstractCegarLoop]: Abstraction has 2483 states and 2485 transitions. [2018-12-02 05:18:06,005 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-12-02 05:18:06,005 INFO L276 IsEmpty]: Start isEmpty. Operand 2483 states and 2485 transitions. [2018-12-02 05:18:06,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2475 [2018-12-02 05:18:06,028 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:18:06,028 INFO L402 BasicCegarLoop]: trace histogram [434, 434, 433, 433, 433, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:18:06,028 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:18:06,028 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:18:06,028 INFO L82 PathProgramCache]: Analyzing trace with hash -971898775, now seen corresponding path program 71 times [2018-12-02 05:18:06,028 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:18:06,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:06,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:18:06,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:06,029 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:18:06,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:18:08,957 INFO L134 CoverageAnalysis]: Checked inductivity of 484599 backedges. 58725 proven. 1974 refuted. 0 times theorem prover too weak. 423900 trivial. 0 not checked. [2018-12-02 05:18:08,958 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:08,958 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:18:08,958 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:18:08,958 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:18:08,958 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:08,958 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:18:08,967 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:18:08,967 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:18:12,065 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-12-02 05:18:12,065 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:18:12,083 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:18:12,085 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:18:12,087 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:18:12,092 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:18:12,092 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:18:12,097 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:18:12,102 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:18:12,103 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:18:18,640 INFO L134 CoverageAnalysis]: Checked inductivity of 484599 backedges. 58725 proven. 1974 refuted. 0 times theorem prover too weak. 423900 trivial. 0 not checked. [2018-12-02 05:18:18,640 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:18:22,154 INFO L134 CoverageAnalysis]: Checked inductivity of 484599 backedges. 58725 proven. 1974 refuted. 0 times theorem prover too weak. 423900 trivial. 0 not checked. [2018-12-02 05:18:22,171 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:18:22,172 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 34, 33] total 67 [2018-12-02 05:18:22,172 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:18:22,172 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-12-02 05:18:22,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-12-02 05:18:22,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1563, Invalid=2993, Unknown=0, NotChecked=0, Total=4556 [2018-12-02 05:18:22,173 INFO L87 Difference]: Start difference. First operand 2483 states and 2485 transitions. Second operand 36 states. [2018-12-02 05:18:22,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:18:22,972 INFO L93 Difference]: Finished difference Result 2496 states and 2499 transitions. [2018-12-02 05:18:22,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-12-02 05:18:22,973 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 2474 [2018-12-02 05:18:22,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:18:22,976 INFO L225 Difference]: With dead ends: 2496 [2018-12-02 05:18:22,976 INFO L226 Difference]: Without dead ends: 2496 [2018-12-02 05:18:22,977 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5009 GetRequests, 4858 SyntacticMatches, 56 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1990 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=3124, Invalid=6188, Unknown=0, NotChecked=0, Total=9312 [2018-12-02 05:18:22,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2496 states. [2018-12-02 05:18:22,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2496 to 2488. [2018-12-02 05:18:22,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2488 states. [2018-12-02 05:18:22,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2488 states to 2488 states and 2491 transitions. [2018-12-02 05:18:22,993 INFO L78 Accepts]: Start accepts. Automaton has 2488 states and 2491 transitions. Word has length 2474 [2018-12-02 05:18:22,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:18:22,995 INFO L480 AbstractCegarLoop]: Abstraction has 2488 states and 2491 transitions. [2018-12-02 05:18:22,995 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-12-02 05:18:22,995 INFO L276 IsEmpty]: Start isEmpty. Operand 2488 states and 2491 transitions. [2018-12-02 05:18:23,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2480 [2018-12-02 05:18:23,024 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:18:23,025 INFO L402 BasicCegarLoop]: trace histogram [435, 435, 434, 434, 434, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:18:23,025 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:18:23,025 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:18:23,025 INFO L82 PathProgramCache]: Analyzing trace with hash -438635068, now seen corresponding path program 72 times [2018-12-02 05:18:23,025 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:18:23,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:23,026 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:18:23,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:23,026 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:18:23,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:18:25,611 INFO L134 CoverageAnalysis]: Checked inductivity of 486794 backedges. 62837 proven. 2217 refuted. 0 times theorem prover too weak. 421740 trivial. 0 not checked. [2018-12-02 05:18:25,611 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:25,611 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:18:25,611 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:18:25,611 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:18:25,611 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:25,612 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:18:25,617 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:18:25,617 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:18:25,932 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:18:25,932 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:18:25,951 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:18:28,621 INFO L134 CoverageAnalysis]: Checked inductivity of 486794 backedges. 62626 proven. 7024 refuted. 0 times theorem prover too weak. 417144 trivial. 0 not checked. [2018-12-02 05:18:28,621 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:18:31,013 INFO L134 CoverageAnalysis]: Checked inductivity of 486794 backedges. 62626 proven. 7024 refuted. 0 times theorem prover too weak. 417144 trivial. 0 not checked. [2018-12-02 05:18:31,029 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:18:31,030 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 65, 65] total 100 [2018-12-02 05:18:31,030 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:18:31,030 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-12-02 05:18:31,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-12-02 05:18:31,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1984, Invalid=7916, Unknown=0, NotChecked=0, Total=9900 [2018-12-02 05:18:31,031 INFO L87 Difference]: Start difference. First operand 2488 states and 2491 transitions. Second operand 97 states. [2018-12-02 05:18:33,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:18:33,212 INFO L93 Difference]: Finished difference Result 2654 states and 2658 transitions. [2018-12-02 05:18:33,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-12-02 05:18:33,213 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 2479 [2018-12-02 05:18:33,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:18:33,216 INFO L225 Difference]: With dead ends: 2654 [2018-12-02 05:18:33,216 INFO L226 Difference]: Without dead ends: 2654 [2018-12-02 05:18:33,217 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5078 GetRequests, 4860 SyntacticMatches, 61 SemanticMatches, 157 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8221 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=5538, Invalid=19584, Unknown=0, NotChecked=0, Total=25122 [2018-12-02 05:18:33,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2654 states. [2018-12-02 05:18:33,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2654 to 2644. [2018-12-02 05:18:33,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2644 states. [2018-12-02 05:18:33,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2644 states to 2644 states and 2648 transitions. [2018-12-02 05:18:33,228 INFO L78 Accepts]: Start accepts. Automaton has 2644 states and 2648 transitions. Word has length 2479 [2018-12-02 05:18:33,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:18:33,229 INFO L480 AbstractCegarLoop]: Abstraction has 2644 states and 2648 transitions. [2018-12-02 05:18:33,229 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-12-02 05:18:33,229 INFO L276 IsEmpty]: Start isEmpty. Operand 2644 states and 2648 transitions. [2018-12-02 05:18:33,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2631 [2018-12-02 05:18:33,252 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:18:33,252 INFO L402 BasicCegarLoop]: trace histogram [463, 463, 462, 462, 462, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:18:33,253 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:18:33,253 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:18:33,253 INFO L82 PathProgramCache]: Analyzing trace with hash 1393501900, now seen corresponding path program 73 times [2018-12-02 05:18:33,253 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:18:33,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:33,253 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:18:33,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:33,253 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:18:33,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:18:36,380 INFO L134 CoverageAnalysis]: Checked inductivity of 551047 backedges. 174981 proven. 6087 refuted. 0 times theorem prover too weak. 369979 trivial. 0 not checked. [2018-12-02 05:18:36,380 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:36,381 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:18:36,381 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:18:36,381 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:18:36,381 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:36,381 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:18:36,388 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:18:36,388 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:18:36,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:18:36,786 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:18:39,859 INFO L134 CoverageAnalysis]: Checked inductivity of 551047 backedges. 125245 proven. 1918 refuted. 0 times theorem prover too weak. 423884 trivial. 0 not checked. [2018-12-02 05:18:39,859 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:18:43,700 INFO L134 CoverageAnalysis]: Checked inductivity of 551047 backedges. 125245 proven. 1918 refuted. 0 times theorem prover too weak. 423884 trivial. 0 not checked. [2018-12-02 05:18:43,717 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:18:43,718 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 60, 60] total 148 [2018-12-02 05:18:43,718 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:18:43,718 INFO L459 AbstractCegarLoop]: Interpolant automaton has 119 states [2018-12-02 05:18:43,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 119 interpolants. [2018-12-02 05:18:43,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3629, Invalid=18127, Unknown=0, NotChecked=0, Total=21756 [2018-12-02 05:18:43,719 INFO L87 Difference]: Start difference. First operand 2644 states and 2648 transitions. Second operand 119 states. [2018-12-02 05:18:50,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:18:50,827 INFO L93 Difference]: Finished difference Result 2655 states and 2657 transitions. [2018-12-02 05:18:50,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 116 states. [2018-12-02 05:18:50,828 INFO L78 Accepts]: Start accepts. Automaton has 119 states. Word has length 2630 [2018-12-02 05:18:50,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:18:50,836 INFO L225 Difference]: With dead ends: 2655 [2018-12-02 05:18:50,836 INFO L226 Difference]: Without dead ends: 2649 [2018-12-02 05:18:50,841 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5409 GetRequests, 5148 SyntacticMatches, 30 SemanticMatches, 231 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24086 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=9446, Invalid=44610, Unknown=0, NotChecked=0, Total=54056 [2018-12-02 05:18:50,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2649 states. [2018-12-02 05:18:50,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2649 to 2644. [2018-12-02 05:18:50,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2644 states. [2018-12-02 05:18:50,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2644 states to 2644 states and 2646 transitions. [2018-12-02 05:18:50,858 INFO L78 Accepts]: Start accepts. Automaton has 2644 states and 2646 transitions. Word has length 2630 [2018-12-02 05:18:50,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:18:50,859 INFO L480 AbstractCegarLoop]: Abstraction has 2644 states and 2646 transitions. [2018-12-02 05:18:50,859 INFO L481 AbstractCegarLoop]: Interpolant automaton has 119 states. [2018-12-02 05:18:50,859 INFO L276 IsEmpty]: Start isEmpty. Operand 2644 states and 2646 transitions. [2018-12-02 05:18:50,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2636 [2018-12-02 05:18:50,884 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:18:50,885 INFO L402 BasicCegarLoop]: trace histogram [464, 464, 463, 463, 463, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:18:50,885 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:18:50,885 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:18:50,885 INFO L82 PathProgramCache]: Analyzing trace with hash 1734616487, now seen corresponding path program 74 times [2018-12-02 05:18:50,885 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:18:50,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:50,886 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:18:50,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:18:50,886 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:18:51,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:18:54,218 INFO L134 CoverageAnalysis]: Checked inductivity of 553388 backedges. 65100 proven. 2117 refuted. 0 times theorem prover too weak. 486171 trivial. 0 not checked. [2018-12-02 05:18:54,218 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:54,218 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:18:54,218 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:18:54,218 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:18:54,218 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:18:54,218 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:18:54,224 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:18:54,224 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:18:57,871 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-12-02 05:18:57,871 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:18:57,891 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:18:57,893 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:18:57,895 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:18:57,899 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:18:57,899 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:18:57,905 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:18:57,911 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:18:57,911 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:19:05,241 INFO L134 CoverageAnalysis]: Checked inductivity of 553388 backedges. 65100 proven. 2117 refuted. 0 times theorem prover too weak. 486171 trivial. 0 not checked. [2018-12-02 05:19:05,241 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:19:09,180 INFO L134 CoverageAnalysis]: Checked inductivity of 553388 backedges. 65100 proven. 2117 refuted. 0 times theorem prover too weak. 486171 trivial. 0 not checked. [2018-12-02 05:19:09,198 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:19:09,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 35, 34] total 69 [2018-12-02 05:19:09,199 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:19:09,199 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-02 05:19:09,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-02 05:19:09,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1633, Invalid=3197, Unknown=0, NotChecked=0, Total=4830 [2018-12-02 05:19:09,200 INFO L87 Difference]: Start difference. First operand 2644 states and 2646 transitions. Second operand 37 states. [2018-12-02 05:19:10,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:19:10,159 INFO L93 Difference]: Finished difference Result 2657 states and 2660 transitions. [2018-12-02 05:19:10,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-12-02 05:19:10,159 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 2635 [2018-12-02 05:19:10,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:19:10,163 INFO L225 Difference]: With dead ends: 2657 [2018-12-02 05:19:10,163 INFO L226 Difference]: Without dead ends: 2657 [2018-12-02 05:19:10,164 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5333 GetRequests, 5177 SyntacticMatches, 58 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2172 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=3266, Invalid=6634, Unknown=0, NotChecked=0, Total=9900 [2018-12-02 05:19:10,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2657 states. [2018-12-02 05:19:10,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2657 to 2649. [2018-12-02 05:19:10,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2649 states. [2018-12-02 05:19:10,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2649 states to 2649 states and 2652 transitions. [2018-12-02 05:19:10,178 INFO L78 Accepts]: Start accepts. Automaton has 2649 states and 2652 transitions. Word has length 2635 [2018-12-02 05:19:10,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:19:10,180 INFO L480 AbstractCegarLoop]: Abstraction has 2649 states and 2652 transitions. [2018-12-02 05:19:10,180 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-02 05:19:10,180 INFO L276 IsEmpty]: Start isEmpty. Operand 2649 states and 2652 transitions. [2018-12-02 05:19:10,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2641 [2018-12-02 05:19:10,207 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:19:10,207 INFO L402 BasicCegarLoop]: trace histogram [465, 465, 464, 464, 464, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:19:10,207 INFO L423 AbstractCegarLoop]: === Iteration 88 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:19:10,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:19:10,207 INFO L82 PathProgramCache]: Analyzing trace with hash -723228858, now seen corresponding path program 75 times [2018-12-02 05:19:10,207 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:19:10,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:10,208 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:19:10,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:10,208 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:19:10,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:19:13,100 INFO L134 CoverageAnalysis]: Checked inductivity of 555734 backedges. 69504 proven. 2383 refuted. 0 times theorem prover too weak. 483847 trivial. 0 not checked. [2018-12-02 05:19:13,100 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:13,100 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:19:13,101 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:19:13,101 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:19:13,101 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:13,101 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:19:13,106 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:19:13,107 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:19:13,442 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:19:13,442 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:19:13,462 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:19:16,353 INFO L134 CoverageAnalysis]: Checked inductivity of 555734 backedges. 69286 proven. 7522 refuted. 0 times theorem prover too weak. 478926 trivial. 0 not checked. [2018-12-02 05:19:16,353 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:19:18,994 INFO L134 CoverageAnalysis]: Checked inductivity of 555734 backedges. 69286 proven. 7522 refuted. 0 times theorem prover too weak. 478926 trivial. 0 not checked. [2018-12-02 05:19:19,011 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:19:19,012 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 67, 67] total 103 [2018-12-02 05:19:19,012 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:19:19,013 INFO L459 AbstractCegarLoop]: Interpolant automaton has 100 states [2018-12-02 05:19:19,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2018-12-02 05:19:19,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2111, Invalid=8395, Unknown=0, NotChecked=0, Total=10506 [2018-12-02 05:19:19,013 INFO L87 Difference]: Start difference. First operand 2649 states and 2652 transitions. Second operand 100 states. [2018-12-02 05:19:20,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:19:20,958 INFO L93 Difference]: Finished difference Result 2820 states and 2824 transitions. [2018-12-02 05:19:20,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-12-02 05:19:20,958 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 2640 [2018-12-02 05:19:20,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:19:20,961 INFO L225 Difference]: With dead ends: 2820 [2018-12-02 05:19:20,961 INFO L226 Difference]: Without dead ends: 2820 [2018-12-02 05:19:20,962 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5404 GetRequests, 5179 SyntacticMatches, 63 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8745 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=5906, Invalid=20826, Unknown=0, NotChecked=0, Total=26732 [2018-12-02 05:19:20,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2820 states. [2018-12-02 05:19:20,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2820 to 2810. [2018-12-02 05:19:20,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2810 states. [2018-12-02 05:19:20,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2810 states to 2810 states and 2814 transitions. [2018-12-02 05:19:20,974 INFO L78 Accepts]: Start accepts. Automaton has 2810 states and 2814 transitions. Word has length 2640 [2018-12-02 05:19:20,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:19:20,975 INFO L480 AbstractCegarLoop]: Abstraction has 2810 states and 2814 transitions. [2018-12-02 05:19:20,975 INFO L481 AbstractCegarLoop]: Interpolant automaton has 100 states. [2018-12-02 05:19:20,975 INFO L276 IsEmpty]: Start isEmpty. Operand 2810 states and 2814 transitions. [2018-12-02 05:19:21,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2797 [2018-12-02 05:19:21,001 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:19:21,001 INFO L402 BasicCegarLoop]: trace histogram [494, 494, 493, 493, 493, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:19:21,002 INFO L423 AbstractCegarLoop]: === Iteration 89 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:19:21,002 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:19:21,002 INFO L82 PathProgramCache]: Analyzing trace with hash -748474429, now seen corresponding path program 76 times [2018-12-02 05:19:21,002 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:19:21,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:21,002 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:19:21,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:21,002 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:19:21,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:19:24,291 INFO L134 CoverageAnalysis]: Checked inductivity of 626748 backedges. 138119 proven. 9590 refuted. 0 times theorem prover too weak. 479039 trivial. 0 not checked. [2018-12-02 05:19:24,291 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:24,291 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:19:24,291 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:19:24,292 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:19:24,292 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:24,292 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:19:24,297 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:19:24,298 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:19:24,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:19:24,712 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:19:27,412 INFO L134 CoverageAnalysis]: Checked inductivity of 626748 backedges. 138549 proven. 2059 refuted. 0 times theorem prover too weak. 486140 trivial. 0 not checked. [2018-12-02 05:19:27,412 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:19:30,923 INFO L134 CoverageAnalysis]: Checked inductivity of 626748 backedges. 138549 proven. 2059 refuted. 0 times theorem prover too weak. 486140 trivial. 0 not checked. [2018-12-02 05:19:30,941 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:19:30,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 62, 62] total 127 [2018-12-02 05:19:30,941 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:19:30,942 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-12-02 05:19:30,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-12-02 05:19:30,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3419, Invalid=12583, Unknown=0, NotChecked=0, Total=16002 [2018-12-02 05:19:30,943 INFO L87 Difference]: Start difference. First operand 2810 states and 2814 transitions. Second operand 97 states. [2018-12-02 05:19:35,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:19:35,597 INFO L93 Difference]: Finished difference Result 2821 states and 2823 transitions. [2018-12-02 05:19:35,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2018-12-02 05:19:35,597 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 2796 [2018-12-02 05:19:35,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:19:35,606 INFO L225 Difference]: With dead ends: 2821 [2018-12-02 05:19:35,606 INFO L226 Difference]: Without dead ends: 2815 [2018-12-02 05:19:35,610 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5720 GetRequests, 5502 SyntacticMatches, 31 SemanticMatches, 187 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13223 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=8345, Invalid=27187, Unknown=0, NotChecked=0, Total=35532 [2018-12-02 05:19:35,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2815 states. [2018-12-02 05:19:35,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2815 to 2810. [2018-12-02 05:19:35,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2810 states. [2018-12-02 05:19:35,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2810 states to 2810 states and 2812 transitions. [2018-12-02 05:19:35,629 INFO L78 Accepts]: Start accepts. Automaton has 2810 states and 2812 transitions. Word has length 2796 [2018-12-02 05:19:35,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:19:35,630 INFO L480 AbstractCegarLoop]: Abstraction has 2810 states and 2812 transitions. [2018-12-02 05:19:35,630 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-12-02 05:19:35,630 INFO L276 IsEmpty]: Start isEmpty. Operand 2810 states and 2812 transitions. [2018-12-02 05:19:35,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2802 [2018-12-02 05:19:35,656 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:19:35,656 INFO L402 BasicCegarLoop]: trace histogram [495, 495, 494, 494, 494, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:19:35,657 INFO L423 AbstractCegarLoop]: === Iteration 90 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:19:35,657 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:19:35,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1476709892, now seen corresponding path program 77 times [2018-12-02 05:19:35,657 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:19:35,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:35,657 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:19:35,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:35,657 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:19:35,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:19:39,283 INFO L134 CoverageAnalysis]: Checked inductivity of 629245 backedges. 71920 proven. 2265 refuted. 0 times theorem prover too weak. 555060 trivial. 0 not checked. [2018-12-02 05:19:39,283 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:39,284 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:19:39,284 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:19:39,284 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:19:39,284 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:39,284 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:19:39,290 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:19:39,290 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:19:41,388 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-12-02 05:19:41,388 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:19:41,408 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:19:41,410 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:19:41,414 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:19:41,423 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:19:41,423 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:19:41,431 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:19:41,437 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:19:41,437 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:19:49,970 INFO L134 CoverageAnalysis]: Checked inductivity of 629245 backedges. 71920 proven. 2265 refuted. 0 times theorem prover too weak. 555060 trivial. 0 not checked. [2018-12-02 05:19:49,970 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:19:54,542 INFO L134 CoverageAnalysis]: Checked inductivity of 629245 backedges. 71920 proven. 2265 refuted. 0 times theorem prover too weak. 555060 trivial. 0 not checked. [2018-12-02 05:19:54,560 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:19:54,561 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 36, 35] total 71 [2018-12-02 05:19:54,561 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:19:54,562 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-02 05:19:54,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-02 05:19:54,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1703, Invalid=3409, Unknown=0, NotChecked=0, Total=5112 [2018-12-02 05:19:54,562 INFO L87 Difference]: Start difference. First operand 2810 states and 2812 transitions. Second operand 38 states. [2018-12-02 05:19:55,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:19:55,512 INFO L93 Difference]: Finished difference Result 2823 states and 2826 transitions. [2018-12-02 05:19:55,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-02 05:19:55,512 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 2801 [2018-12-02 05:19:55,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:19:55,515 INFO L225 Difference]: With dead ends: 2823 [2018-12-02 05:19:55,516 INFO L226 Difference]: Without dead ends: 2823 [2018-12-02 05:19:55,516 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5667 GetRequests, 5506 SyntacticMatches, 60 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2363 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=3408, Invalid=7098, Unknown=0, NotChecked=0, Total=10506 [2018-12-02 05:19:55,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2823 states. [2018-12-02 05:19:55,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2823 to 2815. [2018-12-02 05:19:55,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2815 states. [2018-12-02 05:19:55,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2815 states to 2815 states and 2818 transitions. [2018-12-02 05:19:55,529 INFO L78 Accepts]: Start accepts. Automaton has 2815 states and 2818 transitions. Word has length 2801 [2018-12-02 05:19:55,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:19:55,530 INFO L480 AbstractCegarLoop]: Abstraction has 2815 states and 2818 transitions. [2018-12-02 05:19:55,530 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-02 05:19:55,530 INFO L276 IsEmpty]: Start isEmpty. Operand 2815 states and 2818 transitions. [2018-12-02 05:19:55,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2807 [2018-12-02 05:19:55,557 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:19:55,558 INFO L402 BasicCegarLoop]: trace histogram [496, 496, 495, 495, 495, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:19:55,558 INFO L423 AbstractCegarLoop]: === Iteration 91 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:19:55,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:19:55,558 INFO L82 PathProgramCache]: Analyzing trace with hash -1793101559, now seen corresponding path program 78 times [2018-12-02 05:19:55,558 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:19:55,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:55,559 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:19:55,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:19:55,559 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:19:55,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:19:58,763 INFO L134 CoverageAnalysis]: Checked inductivity of 631747 backedges. 76626 proven. 2555 refuted. 0 times theorem prover too weak. 552566 trivial. 0 not checked. [2018-12-02 05:19:58,764 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:58,764 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:19:58,764 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:19:58,764 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:19:58,764 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:19:58,764 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:19:58,770 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:19:58,770 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:19:59,127 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:19:59,127 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:19:59,151 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:20:02,374 INFO L134 CoverageAnalysis]: Checked inductivity of 631747 backedges. 76401 proven. 8037 refuted. 0 times theorem prover too weak. 547309 trivial. 0 not checked. [2018-12-02 05:20:02,374 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:20:05,306 INFO L134 CoverageAnalysis]: Checked inductivity of 631747 backedges. 76401 proven. 8037 refuted. 0 times theorem prover too weak. 547309 trivial. 0 not checked. [2018-12-02 05:20:05,323 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:20:05,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 69, 69] total 106 [2018-12-02 05:20:05,324 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:20:05,325 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-12-02 05:20:05,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-12-02 05:20:05,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2242, Invalid=8888, Unknown=0, NotChecked=0, Total=11130 [2018-12-02 05:20:05,325 INFO L87 Difference]: Start difference. First operand 2815 states and 2818 transitions. Second operand 103 states. [2018-12-02 05:20:07,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:20:07,758 INFO L93 Difference]: Finished difference Result 2991 states and 2995 transitions. [2018-12-02 05:20:07,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-12-02 05:20:07,758 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 2806 [2018-12-02 05:20:07,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:20:07,761 INFO L225 Difference]: With dead ends: 2991 [2018-12-02 05:20:07,762 INFO L226 Difference]: Without dead ends: 2991 [2018-12-02 05:20:07,763 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5740 GetRequests, 5508 SyntacticMatches, 65 SemanticMatches, 167 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9285 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=6286, Invalid=22106, Unknown=0, NotChecked=0, Total=28392 [2018-12-02 05:20:07,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2991 states. [2018-12-02 05:20:07,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2991 to 2981. [2018-12-02 05:20:07,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2981 states. [2018-12-02 05:20:07,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2981 states to 2981 states and 2985 transitions. [2018-12-02 05:20:07,776 INFO L78 Accepts]: Start accepts. Automaton has 2981 states and 2985 transitions. Word has length 2806 [2018-12-02 05:20:07,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:20:07,777 INFO L480 AbstractCegarLoop]: Abstraction has 2981 states and 2985 transitions. [2018-12-02 05:20:07,777 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-12-02 05:20:07,777 INFO L276 IsEmpty]: Start isEmpty. Operand 2981 states and 2985 transitions. [2018-12-02 05:20:07,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2968 [2018-12-02 05:20:07,806 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:20:07,807 INFO L402 BasicCegarLoop]: trace histogram [526, 526, 525, 525, 525, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:20:07,807 INFO L423 AbstractCegarLoop]: === Iteration 92 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:20:07,807 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:20:07,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1530460487, now seen corresponding path program 79 times [2018-12-02 05:20:07,807 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:20:07,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:20:07,808 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:20:07,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:20:07,808 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:20:08,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:20:11,633 INFO L134 CoverageAnalysis]: Checked inductivity of 709980 backedges. 214362 proven. 6972 refuted. 0 times theorem prover too weak. 488646 trivial. 0 not checked. [2018-12-02 05:20:11,633 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:20:11,633 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:20:11,633 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:20:11,633 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:20:11,633 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:20:11,633 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:20:11,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:20:11,642 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:20:12,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:20:12,087 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:20:15,764 INFO L134 CoverageAnalysis]: Checked inductivity of 709980 backedges. 152762 proven. 2205 refuted. 0 times theorem prover too weak. 555013 trivial. 0 not checked. [2018-12-02 05:20:15,765 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:20:20,092 INFO L134 CoverageAnalysis]: Checked inductivity of 709980 backedges. 152762 proven. 2205 refuted. 0 times theorem prover too weak. 555013 trivial. 0 not checked. [2018-12-02 05:20:20,110 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:20:20,110 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 64, 64] total 158 [2018-12-02 05:20:20,110 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:20:20,111 INFO L459 AbstractCegarLoop]: Interpolant automaton has 127 states [2018-12-02 05:20:20,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2018-12-02 05:20:20,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4127, Invalid=20679, Unknown=0, NotChecked=0, Total=24806 [2018-12-02 05:20:20,112 INFO L87 Difference]: Start difference. First operand 2981 states and 2985 transitions. Second operand 127 states. [2018-12-02 05:20:25,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:20:25,636 INFO L93 Difference]: Finished difference Result 2992 states and 2994 transitions. [2018-12-02 05:20:25,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 124 states. [2018-12-02 05:20:25,637 INFO L78 Accepts]: Start accepts. Automaton has 127 states. Word has length 2967 [2018-12-02 05:20:25,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:20:25,639 INFO L225 Difference]: With dead ends: 2992 [2018-12-02 05:20:25,640 INFO L226 Difference]: Without dead ends: 2986 [2018-12-02 05:20:25,641 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6093 GetRequests, 5814 SyntacticMatches, 32 SemanticMatches, 247 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27668 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=10749, Invalid=51003, Unknown=0, NotChecked=0, Total=61752 [2018-12-02 05:20:25,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2986 states. [2018-12-02 05:20:25,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2986 to 2981. [2018-12-02 05:20:25,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2981 states. [2018-12-02 05:20:25,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2981 states to 2981 states and 2983 transitions. [2018-12-02 05:20:25,660 INFO L78 Accepts]: Start accepts. Automaton has 2981 states and 2983 transitions. Word has length 2967 [2018-12-02 05:20:25,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:20:25,662 INFO L480 AbstractCegarLoop]: Abstraction has 2981 states and 2983 transitions. [2018-12-02 05:20:25,662 INFO L481 AbstractCegarLoop]: Interpolant automaton has 127 states. [2018-12-02 05:20:25,662 INFO L276 IsEmpty]: Start isEmpty. Operand 2981 states and 2983 transitions. [2018-12-02 05:20:25,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2973 [2018-12-02 05:20:25,691 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:20:25,691 INFO L402 BasicCegarLoop]: trace histogram [527, 527, 526, 526, 526, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:20:25,691 INFO L423 AbstractCegarLoop]: === Iteration 93 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:20:25,691 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:20:25,692 INFO L82 PathProgramCache]: Analyzing trace with hash 390914188, now seen corresponding path program 80 times [2018-12-02 05:20:25,692 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:20:25,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:20:25,692 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:20:25,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:20:25,692 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:20:25,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:20:29,682 INFO L134 CoverageAnalysis]: Checked inductivity of 712638 backedges. 79200 proven. 2418 refuted. 0 times theorem prover too weak. 631020 trivial. 0 not checked. [2018-12-02 05:20:29,682 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:20:29,682 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:20:29,682 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:20:29,682 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:20:29,682 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:20:29,682 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:20:29,690 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 05:20:29,690 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 05:20:32,344 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 32 check-sat command(s) [2018-12-02 05:20:32,344 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:20:32,365 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:20:32,367 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 05:20:32,369 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 05:20:32,373 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-02 05:20:32,373 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-02 05:20:32,379 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-02 05:20:32,387 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-02 05:20:32,387 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-02 05:20:41,684 INFO L134 CoverageAnalysis]: Checked inductivity of 712638 backedges. 79200 proven. 2418 refuted. 0 times theorem prover too weak. 631020 trivial. 0 not checked. [2018-12-02 05:20:41,684 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:20:46,319 INFO L134 CoverageAnalysis]: Checked inductivity of 712638 backedges. 79200 proven. 2418 refuted. 0 times theorem prover too weak. 631020 trivial. 0 not checked. [2018-12-02 05:20:46,338 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:20:46,339 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 37, 36] total 73 [2018-12-02 05:20:46,339 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:20:46,339 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-12-02 05:20:46,340 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-12-02 05:20:46,340 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1773, Invalid=3629, Unknown=0, NotChecked=0, Total=5402 [2018-12-02 05:20:46,340 INFO L87 Difference]: Start difference. First operand 2981 states and 2983 transitions. Second operand 39 states. [2018-12-02 05:20:47,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:20:47,234 INFO L93 Difference]: Finished difference Result 2994 states and 2997 transitions. [2018-12-02 05:20:47,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-12-02 05:20:47,234 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 2972 [2018-12-02 05:20:47,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:20:47,237 INFO L225 Difference]: With dead ends: 2994 [2018-12-02 05:20:47,237 INFO L226 Difference]: Without dead ends: 2994 [2018-12-02 05:20:47,238 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6011 GetRequests, 5845 SyntacticMatches, 62 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2562 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=3550, Invalid=7580, Unknown=0, NotChecked=0, Total=11130 [2018-12-02 05:20:47,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2994 states. [2018-12-02 05:20:47,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2994 to 2986. [2018-12-02 05:20:47,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2986 states. [2018-12-02 05:20:47,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2986 states to 2986 states and 2989 transitions. [2018-12-02 05:20:47,250 INFO L78 Accepts]: Start accepts. Automaton has 2986 states and 2989 transitions. Word has length 2972 [2018-12-02 05:20:47,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:20:47,251 INFO L480 AbstractCegarLoop]: Abstraction has 2986 states and 2989 transitions. [2018-12-02 05:20:47,251 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-12-02 05:20:47,251 INFO L276 IsEmpty]: Start isEmpty. Operand 2986 states and 2989 transitions. [2018-12-02 05:20:47,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2978 [2018-12-02 05:20:47,287 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:20:47,288 INFO L402 BasicCegarLoop]: trace histogram [528, 528, 527, 527, 527, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:20:47,288 INFO L423 AbstractCegarLoop]: === Iteration 94 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:20:47,288 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:20:47,288 INFO L82 PathProgramCache]: Analyzing trace with hash -1037716607, now seen corresponding path program 81 times [2018-12-02 05:20:47,288 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:20:47,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:20:47,289 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:20:47,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:20:47,289 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:20:47,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:20:50,835 INFO L134 CoverageAnalysis]: Checked inductivity of 715301 backedges. 84218 proven. 2733 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2018-12-02 05:20:50,835 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:20:50,835 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:20:50,835 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:20:50,836 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:20:50,836 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:20:50,836 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:20:50,841 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 05:20:50,841 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 05:20:51,234 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 05:20:51,234 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 05:20:51,257 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:20:54,742 INFO L134 CoverageAnalysis]: Checked inductivity of 715301 backedges. 83986 proven. 8569 refuted. 0 times theorem prover too weak. 622746 trivial. 0 not checked. [2018-12-02 05:20:54,742 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:20:57,953 INFO L134 CoverageAnalysis]: Checked inductivity of 715301 backedges. 83986 proven. 8569 refuted. 0 times theorem prover too weak. 622746 trivial. 0 not checked. [2018-12-02 05:20:57,970 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:20:57,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 71, 71] total 109 [2018-12-02 05:20:57,971 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:20:57,972 INFO L459 AbstractCegarLoop]: Interpolant automaton has 106 states [2018-12-02 05:20:57,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 106 interpolants. [2018-12-02 05:20:57,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2377, Invalid=9395, Unknown=0, NotChecked=0, Total=11772 [2018-12-02 05:20:57,972 INFO L87 Difference]: Start difference. First operand 2986 states and 2989 transitions. Second operand 106 states. [2018-12-02 05:21:01,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:21:01,025 INFO L93 Difference]: Finished difference Result 3167 states and 3171 transitions. [2018-12-02 05:21:01,025 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2018-12-02 05:21:01,025 INFO L78 Accepts]: Start accepts. Automaton has 106 states. Word has length 2977 [2018-12-02 05:21:01,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:21:01,029 INFO L225 Difference]: With dead ends: 3167 [2018-12-02 05:21:01,029 INFO L226 Difference]: Without dead ends: 3167 [2018-12-02 05:21:01,030 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6086 GetRequests, 5847 SyntacticMatches, 67 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9841 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=6678, Invalid=23424, Unknown=0, NotChecked=0, Total=30102 [2018-12-02 05:21:01,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3167 states. [2018-12-02 05:21:01,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3167 to 3157. [2018-12-02 05:21:01,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3157 states. [2018-12-02 05:21:01,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3157 states to 3157 states and 3161 transitions. [2018-12-02 05:21:01,042 INFO L78 Accepts]: Start accepts. Automaton has 3157 states and 3161 transitions. Word has length 2977 [2018-12-02 05:21:01,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:21:01,043 INFO L480 AbstractCegarLoop]: Abstraction has 3157 states and 3161 transitions. [2018-12-02 05:21:01,043 INFO L481 AbstractCegarLoop]: Interpolant automaton has 106 states. [2018-12-02 05:21:01,043 INFO L276 IsEmpty]: Start isEmpty. Operand 3157 states and 3161 transitions. [2018-12-02 05:21:01,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3144 [2018-12-02 05:21:01,075 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:21:01,076 INFO L402 BasicCegarLoop]: trace histogram [559, 559, 558, 558, 558, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:21:01,076 INFO L423 AbstractCegarLoop]: === Iteration 95 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:21:01,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:21:01,077 INFO L82 PathProgramCache]: Analyzing trace with hash -2065956834, now seen corresponding path program 82 times [2018-12-02 05:21:01,077 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:21:01,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:21:01,077 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 05:21:01,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:21:01,077 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:21:01,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:21:05,075 INFO L134 CoverageAnalysis]: Checked inductivity of 801226 backedges. 167452 proven. 10909 refuted. 0 times theorem prover too weak. 622865 trivial. 0 not checked. [2018-12-02 05:21:05,075 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:21:05,076 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 05:21:05,076 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 05:21:05,076 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 05:21:05,076 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 05:21:05,076 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 05:21:05,082 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:21:05,082 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 05:21:05,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 05:21:05,547 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 05:21:08,843 INFO L134 CoverageAnalysis]: Checked inductivity of 801226 backedges. 167914 proven. 2356 refuted. 0 times theorem prover too weak. 630956 trivial. 0 not checked. [2018-12-02 05:21:08,843 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 05:21:12,997 INFO L134 CoverageAnalysis]: Checked inductivity of 801226 backedges. 167914 proven. 2356 refuted. 0 times theorem prover too weak. 630956 trivial. 0 not checked. [2018-12-02 05:21:13,015 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 05:21:13,016 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 66, 66] total 135 [2018-12-02 05:21:13,016 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 05:21:13,016 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-12-02 05:21:13,017 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-12-02 05:21:13,017 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3870, Invalid=14220, Unknown=0, NotChecked=0, Total=18090 [2018-12-02 05:21:13,017 INFO L87 Difference]: Start difference. First operand 3157 states and 3161 transitions. Second operand 103 states. [2018-12-02 05:21:16,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 05:21:16,313 INFO L93 Difference]: Finished difference Result 3168 states and 3170 transitions. [2018-12-02 05:21:16,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2018-12-02 05:21:16,313 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 3143 [2018-12-02 05:21:16,315 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 05:21:16,317 INFO L225 Difference]: With dead ends: 3168 [2018-12-02 05:21:16,317 INFO L226 Difference]: Without dead ends: 3162 [2018-12-02 05:21:16,319 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6422 GetRequests, 6190 SyntacticMatches, 33 SemanticMatches, 199 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15034 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=9444, Invalid=30756, Unknown=0, NotChecked=0, Total=40200 [2018-12-02 05:21:16,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3162 states. [2018-12-02 05:21:16,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3162 to 3157. [2018-12-02 05:21:16,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3157 states. [2018-12-02 05:21:16,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3157 states to 3157 states and 3159 transitions. [2018-12-02 05:21:16,342 INFO L78 Accepts]: Start accepts. Automaton has 3157 states and 3159 transitions. Word has length 3143 [2018-12-02 05:21:16,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 05:21:16,343 INFO L480 AbstractCegarLoop]: Abstraction has 3157 states and 3159 transitions. [2018-12-02 05:21:16,343 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-12-02 05:21:16,343 INFO L276 IsEmpty]: Start isEmpty. Operand 3157 states and 3159 transitions. [2018-12-02 05:21:16,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3149 [2018-12-02 05:21:16,375 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 05:21:16,375 INFO L402 BasicCegarLoop]: trace histogram [560, 560, 559, 559, 559, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 05:21:16,376 INFO L423 AbstractCegarLoop]: === Iteration 96 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-02 05:21:16,376 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 05:21:16,376 INFO L82 PathProgramCache]: Analyzing trace with hash 2091587081, now seen corresponding path program 83 times [2018-12-02 05:21:16,376 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 05:21:16,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:21:16,377 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 05:21:16,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 05:21:16,377 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 05:21:17,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 05:21:18,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 05:21:18,689 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 05:21:18,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 05:21:18 BoogieIcfgContainer [2018-12-02 05:21:18,973 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 05:21:18,974 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 05:21:18,974 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 05:21:18,974 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 05:21:18,974 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 05:11:51" (3/4) ... [2018-12-02 05:21:18,976 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-02 05:21:19,207 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_4792c070-7503-409b-b809-312d74fc4287/bin-2019/utaipan/witness.graphml [2018-12-02 05:21:19,208 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 05:21:19,208 INFO L168 Benchmark]: Toolchain (without parser) took 568125.18 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 955.1 MB in the beginning and 2.0 GB in the end (delta: -1.1 GB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. [2018-12-02 05:21:19,209 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 981.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 05:21:19,209 INFO L168 Benchmark]: CACSL2BoogieTranslator took 131.41 ms. Allocated memory is still 1.0 GB. Free memory was 955.1 MB in the beginning and 944.3 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-12-02 05:21:19,210 INFO L168 Benchmark]: Boogie Procedure Inliner took 12.94 ms. Allocated memory is still 1.0 GB. Free memory is still 944.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 05:21:19,210 INFO L168 Benchmark]: Boogie Preprocessor took 44.01 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 125.8 MB). Free memory was 944.3 MB in the beginning and 1.1 GB in the end (delta: -176.8 MB). Peak memory consumption was 15.8 MB. Max. memory is 11.5 GB. [2018-12-02 05:21:19,210 INFO L168 Benchmark]: RCFGBuilder took 154.74 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 24.5 MB). Peak memory consumption was 24.5 MB. Max. memory is 11.5 GB. [2018-12-02 05:21:19,210 INFO L168 Benchmark]: TraceAbstraction took 567545.24 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: -1.0 GB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. [2018-12-02 05:21:19,210 INFO L168 Benchmark]: Witness Printer took 233.95 ms. Allocated memory is still 5.0 GB. Free memory was 2.1 GB in the beginning and 2.0 GB in the end (delta: 82.5 MB). Peak memory consumption was 82.5 MB. Max. memory is 11.5 GB. [2018-12-02 05:21:19,211 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 981.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 131.41 ms. Allocated memory is still 1.0 GB. Free memory was 955.1 MB in the beginning and 944.3 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 12.94 ms. Allocated memory is still 1.0 GB. Free memory is still 944.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.01 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 125.8 MB). Free memory was 944.3 MB in the beginning and 1.1 GB in the end (delta: -176.8 MB). Peak memory consumption was 15.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 154.74 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 24.5 MB). Peak memory consumption was 24.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 567545.24 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: -1.0 GB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. * Witness Printer took 233.95 ms. Allocated memory is still 5.0 GB. Free memory was 2.1 GB in the beginning and 2.0 GB in the end (delta: 82.5 MB). Peak memory consumption was 82.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L24] int i, b[32]; [L25] char mask[32]; [L26] i = 0 VAL [b={157:0}, i=0, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=0, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=0, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=0, b={140:0}, b={140:0}, i=0, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={140:0}, b={140:0}, i=0, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={140:0}, b={140:0}, i=0, size=0] [L18] EXPR b[i] VAL [\old(size)=0, b={140:0}, b={140:0}, b[i]=148, i=0, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={140:0}, b={140:0}, i=1, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={140:0}, b={140:0}, i=1, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={140:0}, b={140:0}, i=1, size=0] [L18] EXPR b[i] VAL [\old(size)=0, b={140:0}, b={140:0}, b[i]=162, i=1, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={140:0}, b={140:0}, i=2, size=0] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=0, b={140:0}, b={140:0}, i=2, size=0] [L20] return i; VAL [\old(size)=0, \result=2, b={140:0}, b={140:0}, i=2, size=0] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=2, i=0, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=2, i=0, mask={140:0}] [L26] i++ VAL [b={157:0}, i=1, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=1, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=1, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=148, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=162, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=143, i=2, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=3, size=1] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=1, b={140:0}, b={140:0}, i=3, size=1] [L20] return i; VAL [\old(size)=1, \result=3, b={140:0}, b={140:0}, i=3, size=1] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=3, i=1, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=3, i=1, mask={140:0}] [L26] i++ VAL [b={157:0}, i=2, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=2, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=2, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=148, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=162, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=143, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=131, i=3, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=4, size=2] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=2, b={140:0}, b={140:0}, i=4, size=2] [L20] return i; VAL [\old(size)=2, \result=4, b={140:0}, b={140:0}, i=4, size=2] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=4, i=2, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=4, i=2, mask={140:0}] [L26] i++ VAL [b={157:0}, i=3, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=3, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=3, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=148, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=162, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=143, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=131, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=130, i=4, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=5, size=3] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=3, b={140:0}, b={140:0}, i=5, size=3] [L20] return i; VAL [\old(size)=3, \result=5, b={140:0}, b={140:0}, i=5, size=3] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=5, i=3, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=5, i=3, mask={140:0}] [L26] i++ VAL [b={157:0}, i=4, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=4, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=4, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=148, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=162, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=143, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=131, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=130, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=139, i=5, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=6, size=4] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=4, b={140:0}, b={140:0}, i=6, size=4] [L20] return i; VAL [\old(size)=4, \result=6, b={140:0}, b={140:0}, i=6, size=4] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=6, i=4, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=6, i=4, mask={140:0}] [L26] i++ VAL [b={157:0}, i=5, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=5, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=5, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=148, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=162, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=143, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=131, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=130, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=139, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=129, i=6, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=7, size=5] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=5, b={140:0}, b={140:0}, i=7, size=5] [L20] return i; VAL [\old(size)=5, \result=7, b={140:0}, b={140:0}, i=7, size=5] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=7, i=5, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=7, i=5, mask={140:0}] [L26] i++ VAL [b={157:0}, i=6, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=6, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=6, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=148, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=162, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=143, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=131, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=130, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=139, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=129, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=149, i=7, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=8, size=6] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=6, b={140:0}, b={140:0}, i=8, size=6] [L20] return i; VAL [\old(size)=6, \result=8, b={140:0}, b={140:0}, i=8, size=6] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=8, i=6, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=8, i=6, mask={140:0}] [L26] i++ VAL [b={157:0}, i=7, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=7, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=7, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=148, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=162, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=143, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=131, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=130, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=139, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=129, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=149, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=155, i=8, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=9, size=7] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=7, b={140:0}, b={140:0}, i=9, size=7] [L20] return i; VAL [\old(size)=7, \result=9, b={140:0}, b={140:0}, i=9, size=7] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=9, i=7, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=9, i=7, mask={140:0}] [L26] i++ VAL [b={157:0}, i=8, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=8, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=8, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=148, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=162, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=143, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=131, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=130, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=139, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=129, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=149, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=155, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=135, i=9, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=10, size=8] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=8, b={140:0}, b={140:0}, i=10, size=8] [L20] return i; VAL [\old(size)=8, \result=10, b={140:0}, b={140:0}, i=10, size=8] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=10, i=8, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=10, i=8, mask={140:0}] [L26] i++ VAL [b={157:0}, i=9, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=9, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=9, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=148, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=162, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=143, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=131, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=130, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=139, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=129, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=149, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=155, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=135, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=150, i=10, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=11, size=9] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=9, b={140:0}, b={140:0}, i=11, size=9] [L20] return i; VAL [\old(size)=9, \result=11, b={140:0}, b={140:0}, i=11, size=9] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=11, i=9, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=11, i=9, mask={140:0}] [L26] i++ VAL [b={157:0}, i=10, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=10, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=10, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=148, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=162, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=143, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=131, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=130, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=139, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=129, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=149, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=155, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=135, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=146, i=11, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=12, size=10] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=10, b={140:0}, b={140:0}, i=12, size=10] [L20] return i; VAL [\old(size)=10, \result=12, b={140:0}, b={140:0}, i=12, size=10] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=12, i=10, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=12, i=10, mask={140:0}] [L26] i++ VAL [b={157:0}, i=11, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=11, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=11, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=148, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=162, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=143, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=131, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=130, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=139, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=129, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=149, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=155, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=135, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=146, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=151, i=12, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=13, size=11] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=11, b={140:0}, b={140:0}, i=13, size=11] [L20] return i; VAL [\old(size)=11, \result=13, b={140:0}, b={140:0}, i=13, size=11] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=13, i=11, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=13, i=11, mask={140:0}] [L26] i++ VAL [b={157:0}, i=12, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=12, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=12, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=148, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=162, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=143, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=131, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=130, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=139, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=129, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=149, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=155, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=135, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=146, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=151, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=158, i=13, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=14, size=12] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=12, b={140:0}, b={140:0}, i=14, size=12] [L20] return i; VAL [\old(size)=12, \result=14, b={140:0}, b={140:0}, i=14, size=12] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=14, i=12, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=14, i=12, mask={140:0}] [L26] i++ VAL [b={157:0}, i=13, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=13, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=13, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=148, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=162, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=143, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=131, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=130, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=139, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=129, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=149, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=155, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=135, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=146, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=151, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=158, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=154, i=14, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=15, size=13] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=13, b={140:0}, b={140:0}, i=15, size=13] [L20] return i; VAL [\old(size)=13, \result=15, b={140:0}, b={140:0}, i=15, size=13] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=15, i=13, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=15, i=13, mask={140:0}] [L26] i++ VAL [b={157:0}, i=14, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=14, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=14, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=148, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=162, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=143, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=131, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=130, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=139, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=129, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=149, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=155, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=135, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=146, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=151, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=158, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=154, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=136, i=15, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=16, size=14] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=14, b={140:0}, b={140:0}, i=16, size=14] [L20] return i; VAL [\old(size)=14, \result=16, b={140:0}, b={140:0}, i=16, size=14] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=16, i=14, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=16, i=14, mask={140:0}] [L26] i++ VAL [b={157:0}, i=15, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=15, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=15, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=148, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=162, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=143, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=131, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=130, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=139, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=129, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=149, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=155, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=135, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=146, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=151, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=158, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=154, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=136, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=138, i=16, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=17, size=15] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=15, b={140:0}, b={140:0}, i=17, size=15] [L20] return i; VAL [\old(size)=15, \result=17, b={140:0}, b={140:0}, i=17, size=15] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=17, i=15, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=17, i=15, mask={140:0}] [L26] i++ VAL [b={157:0}, i=16, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=16, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=16, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=148, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=162, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=143, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=131, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=130, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=139, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=129, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=149, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=155, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=135, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=146, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=151, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=158, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=154, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=136, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=138, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=152, i=17, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=18, size=16] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=16, b={140:0}, b={140:0}, i=18, size=16] [L20] return i; VAL [\old(size)=16, \result=18, b={140:0}, b={140:0}, i=18, size=16] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=18, i=16, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=18, i=16, mask={140:0}] [L26] i++ VAL [b={157:0}, i=17, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=17, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=17, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=148, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=162, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=143, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=131, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=130, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=139, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=129, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=149, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=155, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=135, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=146, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=151, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=158, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=154, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=136, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=138, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=152, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=141, i=18, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=19, size=17] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=17, b={140:0}, b={140:0}, i=19, size=17] [L20] return i; VAL [\old(size)=17, \result=19, b={140:0}, b={140:0}, i=19, size=17] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=19, i=17, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=19, i=17, mask={140:0}] [L26] i++ VAL [b={157:0}, i=18, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=18, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=18, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=148, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=162, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=143, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=131, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=130, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=139, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=129, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=149, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=155, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=135, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=146, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=151, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=158, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=154, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=136, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=138, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=152, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=141, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=132, i=19, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=20, size=18] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=18, b={140:0}, b={140:0}, i=20, size=18] [L20] return i; VAL [\old(size)=18, \result=20, b={140:0}, b={140:0}, i=20, size=18] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=20, i=18, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=20, i=18, mask={140:0}] [L26] i++ VAL [b={157:0}, i=19, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=19, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=19, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=148, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=162, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=143, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=131, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=130, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=139, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=129, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=149, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=155, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=135, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=146, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=151, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=158, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=154, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=136, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=138, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=152, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=141, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=132, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=133, i=20, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=21, size=19] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=19, b={140:0}, b={140:0}, i=21, size=19] [L20] return i; VAL [\old(size)=19, \result=21, b={140:0}, b={140:0}, i=21, size=19] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=21, i=19, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=21, i=19, mask={140:0}] [L26] i++ VAL [b={157:0}, i=20, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=20, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=20, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=148, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=162, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=143, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=131, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=130, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=139, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=129, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=149, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=155, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=135, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=146, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=151, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=158, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=154, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=136, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=138, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=152, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=141, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=132, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=133, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=137, i=21, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=22, size=20] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=20, b={140:0}, b={140:0}, i=22, size=20] [L20] return i; VAL [\old(size)=20, \result=22, b={140:0}, b={140:0}, i=22, size=20] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=22, i=20, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=22, i=20, mask={140:0}] [L26] i++ VAL [b={157:0}, i=21, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=21, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=21, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=148, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=162, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=143, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=131, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=130, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=139, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=129, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=149, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=155, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=135, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=146, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=151, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=158, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=154, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=136, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=138, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=152, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=141, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=132, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=133, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=137, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=159, i=22, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=23, size=21] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=21, b={140:0}, b={140:0}, i=23, size=21] [L20] return i; VAL [\old(size)=21, \result=23, b={140:0}, b={140:0}, i=23, size=21] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=23, i=21, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=23, i=21, mask={140:0}] [L26] i++ VAL [b={157:0}, i=22, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=22, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=22, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=148, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=162, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=143, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=131, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=130, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=139, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=129, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=149, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=155, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=135, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=146, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=151, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=158, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=154, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=136, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=138, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=152, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=141, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=132, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=133, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=137, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=159, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=163, i=23, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=24, size=22] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=22, b={140:0}, b={140:0}, i=24, size=22] [L20] return i; VAL [\old(size)=22, \result=24, b={140:0}, b={140:0}, i=24, size=22] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=24, i=22, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=24, i=22, mask={140:0}] [L26] i++ VAL [b={157:0}, i=23, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=23, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=23, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=148, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=162, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=143, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=131, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=130, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=139, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=129, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=149, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=155, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=135, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=146, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=151, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=158, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=154, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=136, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=138, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=152, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=141, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=132, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=133, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=137, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=159, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=163, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=144, i=24, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=25, size=23] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=23, b={140:0}, b={140:0}, i=25, size=23] [L20] return i; VAL [\old(size)=23, \result=25, b={140:0}, b={140:0}, i=25, size=23] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=25, i=23, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=25, i=23, mask={140:0}] [L26] i++ VAL [b={157:0}, i=24, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=24, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=24, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=148, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=162, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=143, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=131, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=130, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=139, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=129, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=149, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=155, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=135, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=146, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=151, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=158, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=154, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=136, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=138, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=152, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=141, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=132, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=133, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=137, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=159, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=163, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=144, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=153, i=25, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=26, size=24] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=24, b={140:0}, b={140:0}, i=26, size=24] [L20] return i; VAL [\old(size)=24, \result=26, b={140:0}, b={140:0}, i=26, size=24] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=26, i=24, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=26, i=24, mask={140:0}] [L26] i++ VAL [b={157:0}, i=25, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=25, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=25, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=148, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=162, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=143, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=131, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=130, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=139, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=129, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=149, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=155, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=135, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=146, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=151, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=158, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=154, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=136, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=138, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=152, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=141, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=132, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=133, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=137, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=159, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=163, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=144, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=153, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=145, i=26, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=27, size=25] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=25, b={140:0}, b={140:0}, i=27, size=25] [L20] return i; VAL [\old(size)=25, \result=27, b={140:0}, b={140:0}, i=27, size=25] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=27, i=25, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=27, i=25, mask={140:0}] [L26] i++ VAL [b={157:0}, i=26, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=26, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=26, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=148, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=162, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=143, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=131, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=130, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=139, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=129, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=149, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=155, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=135, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=146, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=151, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=158, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=154, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=136, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=138, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=152, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=141, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=132, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=133, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=137, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=159, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=163, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=144, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=153, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=145, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=164, i=27, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=28, size=26] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=26, b={140:0}, b={140:0}, i=28, size=26] [L20] return i; VAL [\old(size)=26, \result=28, b={140:0}, b={140:0}, i=28, size=26] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=28, i=26, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=28, i=26, mask={140:0}] [L26] i++ VAL [b={157:0}, i=27, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=27, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=27, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=148, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=162, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=143, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=131, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=130, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=139, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=129, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=149, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=155, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=135, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=146, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=151, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=158, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=154, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=136, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=138, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=152, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=141, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=132, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=133, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=137, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=159, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=163, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=144, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=153, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=145, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=164, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=160, i=28, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=29, size=27] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=27, b={140:0}, b={140:0}, i=29, size=27] [L20] return i; VAL [\old(size)=27, \result=29, b={140:0}, b={140:0}, i=29, size=27] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=29, i=27, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=29, i=27, mask={140:0}] [L26] i++ VAL [b={157:0}, i=28, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=28, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=28, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=148, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=162, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=143, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=131, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=130, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=139, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=129, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=149, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=155, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=135, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=146, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=151, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=158, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=154, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=136, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=138, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=152, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=141, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=132, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=133, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=137, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=159, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=163, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=144, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=153, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=145, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=164, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=160, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=142, i=29, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=30, size=28] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=28, b={140:0}, b={140:0}, i=30, size=28] [L20] return i; VAL [\old(size)=28, \result=30, b={140:0}, b={140:0}, i=30, size=28] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=30, i=28, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=30, i=28, mask={140:0}] [L26] i++ VAL [b={157:0}, i=29, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=29, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=29, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=148, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=162, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=143, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=131, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=130, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=139, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=129, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=149, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=155, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=135, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=146, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=151, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=158, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=154, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=136, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=138, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=152, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=141, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=132, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=133, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=137, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=159, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=163, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=144, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=153, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=145, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=164, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=160, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=142, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=161, i=30, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=31, size=29] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=29, b={140:0}, b={140:0}, i=31, size=29] [L20] return i; VAL [\old(size)=29, \result=31, b={140:0}, b={140:0}, i=31, size=29] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=31, i=29, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=31, i=29, mask={140:0}] [L26] i++ VAL [b={157:0}, i=30, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=30, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=30, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=148, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=162, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=143, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=131, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=130, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=139, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=129, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=149, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=155, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=135, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=146, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=151, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=158, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=154, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=136, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=138, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=152, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=141, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=132, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=133, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=137, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=159, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=163, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=144, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=153, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=145, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=164, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=160, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=142, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=161, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=134, i=31, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=32, size=30] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=30, b={140:0}, b={140:0}, i=32, size=30] [L20] return i; VAL [\old(size)=30, \result=32, b={140:0}, b={140:0}, i=32, size=30] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=32, i=30, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=32, i=30, mask={140:0}] [L26] i++ VAL [b={157:0}, i=31, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=31, mask={140:0}] [L27] CALL foo(mask, i) VAL [\old(size)=31, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=148, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=162, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=143, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=131, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=130, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=139, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=129, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=149, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=155, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=135, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=146, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=151, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=158, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=154, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=136, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=138, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=152, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=141, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=132, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=133, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=137, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=159, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=163, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=144, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=153, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=145, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=164, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=160, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=142, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=161, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=134, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L18] a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L18] b[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 40 locations, 8 error locations. UNSAFE Result, 567.5s OverallTime, 96 OverallIterations, 560 TraceHistogramMax, 165.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3357 SDtfs, 45586 SDslu, 44767 SDs, 0 SdLazy, 191203 SolverSat, 6196 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 64.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 213534 GetRequests, 201743 SyntacticMatches, 2257 SemanticMatches, 9534 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 492958 ImplicationChecksByTransitivity, 205.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3157occurred in iteration=94, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.5s AbstIntTime, 6 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 95 MinimizatonAttempts, 1230 StatesRemovedByMinimization, 93 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 3.9s SsaConstructionTime, 35.8s SatisfiabilityAnalysisTime, 298.8s InterpolantComputationTime, 210401 NumberOfCodeBlocks, 187100 NumberOfCodeBlocksAsserted, 664 NumberOfCheckSat, 310559 ConstructedInterpolants, 25752 QuantifiedInterpolants, 1355035892 SizeOfPredicates, 412 NumberOfNonLiveVariables, 205025 ConjunctsInSsa, 3414 ConjunctsInUnsatCore, 273 InterpolantComputations, 8 PerfectInterpolantSequences, 45548001/46005098 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...