./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/config/TaipanMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -s /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 04:05:06,299 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 04:05:06,300 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 04:05:06,307 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 04:05:06,307 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 04:05:06,307 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 04:05:06,308 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 04:05:06,309 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 04:05:06,310 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 04:05:06,310 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 04:05:06,311 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 04:05:06,311 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 04:05:06,311 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 04:05:06,312 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 04:05:06,312 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 04:05:06,313 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 04:05:06,313 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 04:05:06,314 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 04:05:06,315 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 04:05:06,315 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 04:05:06,316 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 04:05:06,317 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 04:05:06,318 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 04:05:06,318 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 04:05:06,318 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 04:05:06,319 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 04:05:06,319 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 04:05:06,319 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 04:05:06,320 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 04:05:06,320 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 04:05:06,321 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 04:05:06,321 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 04:05:06,321 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 04:05:06,321 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 04:05:06,322 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 04:05:06,322 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 04:05:06,322 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf [2018-12-02 04:05:06,329 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 04:05:06,330 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 04:05:06,330 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 04:05:06,330 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 04:05:06,330 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-02 04:05:06,330 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-02 04:05:06,330 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-02 04:05:06,330 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-02 04:05:06,331 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-02 04:05:06,331 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-02 04:05:06,331 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-02 04:05:06,331 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-02 04:05:06,331 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-02 04:05:06,331 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-02 04:05:06,331 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-02 04:05:06,331 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 04:05:06,331 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-02 04:05:06,332 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 04:05:06,332 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 04:05:06,333 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:05:06,333 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 04:05:06,333 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 04:05:06,333 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-02 04:05:06,333 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 04:05:06,333 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 04:05:06,333 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2018-12-02 04:05:06,351 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 04:05:06,360 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 04:05:06,363 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 04:05:06,364 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 04:05:06,364 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 04:05:06,365 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-02 04:05:06,410 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/data/e95e9f592/65f7c2e40217430abb822d679c82828c/FLAG5dce079fe [2018-12-02 04:05:06,831 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 04:05:06,831 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-02 04:05:06,835 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/data/e95e9f592/65f7c2e40217430abb822d679c82828c/FLAG5dce079fe [2018-12-02 04:05:06,843 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/data/e95e9f592/65f7c2e40217430abb822d679c82828c [2018-12-02 04:05:06,845 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 04:05:06,846 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 04:05:06,846 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 04:05:06,847 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 04:05:06,849 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 04:05:06,849 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:06,851 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@750878c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06, skipping insertion in model container [2018-12-02 04:05:06,851 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:06,855 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 04:05:06,864 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 04:05:06,948 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:05:06,954 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 04:05:06,964 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:05:06,972 INFO L195 MainTranslator]: Completed translation [2018-12-02 04:05:06,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06 WrapperNode [2018-12-02 04:05:06,973 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 04:05:06,973 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 04:05:06,973 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 04:05:06,973 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 04:05:06,978 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:06,983 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:06,987 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 04:05:06,987 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 04:05:06,987 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 04:05:06,987 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 04:05:06,992 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:06,993 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:06,994 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:06,994 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:07,031 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:07,034 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:07,035 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... [2018-12-02 04:05:07,036 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 04:05:07,036 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 04:05:07,036 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 04:05:07,036 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 04:05:07,037 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:05:07,067 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-02 04:05:07,067 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 04:05:07,067 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 04:05:07,068 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-02 04:05:07,068 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-12-02 04:05:07,068 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-12-02 04:05:07,068 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 04:05:07,068 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 04:05:07,068 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-02 04:05:07,068 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 04:05:07,068 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 04:05:07,068 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-02 04:05:07,183 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 04:05:07,184 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-12-02 04:05:07,184 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:05:07 BoogieIcfgContainer [2018-12-02 04:05:07,184 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 04:05:07,184 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 04:05:07,184 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 04:05:07,186 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 04:05:07,187 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 04:05:06" (1/3) ... [2018-12-02 04:05:07,187 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6d5803be and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:05:07, skipping insertion in model container [2018-12-02 04:05:07,187 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:05:06" (2/3) ... [2018-12-02 04:05:07,187 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6d5803be and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:05:07, skipping insertion in model container [2018-12-02 04:05:07,187 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:05:07" (3/3) ... [2018-12-02 04:05:07,188 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-02 04:05:07,194 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 04:05:07,199 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-12-02 04:05:07,208 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-12-02 04:05:07,222 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 04:05:07,222 INFO L383 AbstractCegarLoop]: Hoare is false [2018-12-02 04:05:07,222 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 04:05:07,223 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 04:05:07,223 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 04:05:07,223 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 04:05:07,223 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 04:05:07,223 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 04:05:07,231 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2018-12-02 04:05:07,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-12-02 04:05:07,236 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:07,236 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:07,238 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:07,241 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:07,241 INFO L82 PathProgramCache]: Analyzing trace with hash 1909189377, now seen corresponding path program 1 times [2018-12-02 04:05:07,242 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:07,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:07,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,270 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:07,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:07,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:07,325 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:07,325 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:05:07,325 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:07,328 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:05:07,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:05:07,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:07,337 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 3 states. [2018-12-02 04:05:07,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:07,380 INFO L93 Difference]: Finished difference Result 58 states and 63 transitions. [2018-12-02 04:05:07,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:05:07,381 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 10 [2018-12-02 04:05:07,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:07,387 INFO L225 Difference]: With dead ends: 58 [2018-12-02 04:05:07,387 INFO L226 Difference]: Without dead ends: 54 [2018-12-02 04:05:07,388 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:07,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-12-02 04:05:07,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 39. [2018-12-02 04:05:07,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-02 04:05:07,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 42 transitions. [2018-12-02 04:05:07,411 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 42 transitions. Word has length 10 [2018-12-02 04:05:07,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:07,411 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 42 transitions. [2018-12-02 04:05:07,411 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:05:07,412 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 42 transitions. [2018-12-02 04:05:07,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-12-02 04:05:07,412 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:07,412 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:07,412 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:07,412 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:07,412 INFO L82 PathProgramCache]: Analyzing trace with hash -941983064, now seen corresponding path program 1 times [2018-12-02 04:05:07,412 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:07,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,413 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:07,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,413 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:07,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:07,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:07,437 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:07,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 04:05:07,438 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:07,438 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:05:07,439 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:05:07,439 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:07,439 INFO L87 Difference]: Start difference. First operand 39 states and 42 transitions. Second operand 3 states. [2018-12-02 04:05:07,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:07,462 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-12-02 04:05:07,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:05:07,462 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-12-02 04:05:07,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:07,464 INFO L225 Difference]: With dead ends: 49 [2018-12-02 04:05:07,464 INFO L226 Difference]: Without dead ends: 49 [2018-12-02 04:05:07,464 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:07,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-12-02 04:05:07,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 41. [2018-12-02 04:05:07,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-12-02 04:05:07,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2018-12-02 04:05:07,467 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 11 [2018-12-02 04:05:07,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:07,467 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2018-12-02 04:05:07,467 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:05:07,468 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2018-12-02 04:05:07,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-02 04:05:07,468 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:07,468 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:07,468 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:07,468 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:07,469 INFO L82 PathProgramCache]: Analyzing trace with hash 863296133, now seen corresponding path program 1 times [2018-12-02 04:05:07,469 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:07,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,469 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:07,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,470 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:07,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:07,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:07,509 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:07,509 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 04:05:07,509 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:07,510 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:05:07,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:05:07,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:05:07,510 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 5 states. [2018-12-02 04:05:07,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:07,556 INFO L93 Difference]: Finished difference Result 40 states and 44 transitions. [2018-12-02 04:05:07,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:05:07,556 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 12 [2018-12-02 04:05:07,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:07,557 INFO L225 Difference]: With dead ends: 40 [2018-12-02 04:05:07,557 INFO L226 Difference]: Without dead ends: 40 [2018-12-02 04:05:07,557 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:05:07,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-12-02 04:05:07,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-12-02 04:05:07,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-12-02 04:05:07,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2018-12-02 04:05:07,560 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 12 [2018-12-02 04:05:07,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:07,560 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2018-12-02 04:05:07,560 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:05:07,560 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2018-12-02 04:05:07,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-02 04:05:07,561 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:07,561 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:07,561 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:07,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:07,561 INFO L82 PathProgramCache]: Analyzing trace with hash 863296134, now seen corresponding path program 1 times [2018-12-02 04:05:07,561 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:07,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:07,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,562 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:07,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:07,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:07,634 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:07,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:05:07,634 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:07,635 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:05:07,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:05:07,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:05:07,635 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 6 states. [2018-12-02 04:05:07,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:07,701 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-12-02 04:05:07,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:05:07,701 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 12 [2018-12-02 04:05:07,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:07,702 INFO L225 Difference]: With dead ends: 42 [2018-12-02 04:05:07,702 INFO L226 Difference]: Without dead ends: 42 [2018-12-02 04:05:07,702 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:05:07,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-12-02 04:05:07,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 39. [2018-12-02 04:05:07,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-02 04:05:07,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 43 transitions. [2018-12-02 04:05:07,705 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 43 transitions. Word has length 12 [2018-12-02 04:05:07,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:07,705 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 43 transitions. [2018-12-02 04:05:07,705 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:05:07,706 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 43 transitions. [2018-12-02 04:05:07,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-12-02 04:05:07,706 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:07,706 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:07,706 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:07,706 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:07,706 INFO L82 PathProgramCache]: Analyzing trace with hash 143250926, now seen corresponding path program 1 times [2018-12-02 04:05:07,707 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:07,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,707 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:07,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,708 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:07,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:07,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:07,742 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:07,742 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 04:05:07,743 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:07,743 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:05:07,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:05:07,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:07,744 INFO L87 Difference]: Start difference. First operand 39 states and 43 transitions. Second operand 3 states. [2018-12-02 04:05:07,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:07,754 INFO L93 Difference]: Finished difference Result 37 states and 41 transitions. [2018-12-02 04:05:07,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:05:07,754 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-12-02 04:05:07,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:07,754 INFO L225 Difference]: With dead ends: 37 [2018-12-02 04:05:07,754 INFO L226 Difference]: Without dead ends: 37 [2018-12-02 04:05:07,755 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:07,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-12-02 04:05:07,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2018-12-02 04:05:07,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-12-02 04:05:07,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 41 transitions. [2018-12-02 04:05:07,757 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 41 transitions. Word has length 15 [2018-12-02 04:05:07,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:07,757 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 41 transitions. [2018-12-02 04:05:07,757 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:05:07,757 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 41 transitions. [2018-12-02 04:05:07,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-12-02 04:05:07,757 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:07,757 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:07,757 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:07,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:07,758 INFO L82 PathProgramCache]: Analyzing trace with hash 143250927, now seen corresponding path program 1 times [2018-12-02 04:05:07,758 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:07,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:07,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,758 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:07,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:07,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:07,790 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:07,790 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 04:05:07,790 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:07,790 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:05:07,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:05:07,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:05:07,791 INFO L87 Difference]: Start difference. First operand 37 states and 41 transitions. Second operand 6 states. [2018-12-02 04:05:07,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:07,842 INFO L93 Difference]: Finished difference Result 56 states and 61 transitions. [2018-12-02 04:05:07,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:05:07,842 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-12-02 04:05:07,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:07,843 INFO L225 Difference]: With dead ends: 56 [2018-12-02 04:05:07,843 INFO L226 Difference]: Without dead ends: 56 [2018-12-02 04:05:07,843 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:05:07,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-12-02 04:05:07,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 41. [2018-12-02 04:05:07,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-12-02 04:05:07,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 46 transitions. [2018-12-02 04:05:07,846 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 46 transitions. Word has length 15 [2018-12-02 04:05:07,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:07,846 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 46 transitions. [2018-12-02 04:05:07,846 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:05:07,846 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 46 transitions. [2018-12-02 04:05:07,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-12-02 04:05:07,847 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:07,847 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:07,847 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:07,847 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:07,847 INFO L82 PathProgramCache]: Analyzing trace with hash 1623425863, now seen corresponding path program 1 times [2018-12-02 04:05:07,848 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:07,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,848 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:07,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:07,848 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:07,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:07,871 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:07,871 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:07,871 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:07,871 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 17 with the following transitions: [2018-12-02 04:05:07,872 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [10], [11], [12], [13], [16], [18], [27], [35], [73], [74], [75], [77] [2018-12-02 04:05:07,892 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:05:07,893 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:05:07,998 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:05:07,999 INFO L272 AbstractInterpreter]: Visited 15 different actions 27 times. Merged at 5 different actions 10 times. Never widened. Performed 153 root evaluator evaluations with a maximum evaluation depth of 3. Performed 153 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 20 variables. [2018-12-02 04:05:08,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:08,005 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:05:08,005 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:08,005 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:08,012 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:08,012 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:08,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:08,029 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:08,041 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:08,041 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:08,059 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:08,072 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:08,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 5 [2018-12-02 04:05:08,073 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:08,073 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:05:08,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:05:08,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:05:08,074 INFO L87 Difference]: Start difference. First operand 41 states and 46 transitions. Second operand 4 states. [2018-12-02 04:05:08,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:08,100 INFO L93 Difference]: Finished difference Result 52 states and 59 transitions. [2018-12-02 04:05:08,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 04:05:08,100 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-12-02 04:05:08,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:08,101 INFO L225 Difference]: With dead ends: 52 [2018-12-02 04:05:08,101 INFO L226 Difference]: Without dead ends: 52 [2018-12-02 04:05:08,101 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:05:08,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-12-02 04:05:08,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 46. [2018-12-02 04:05:08,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-12-02 04:05:08,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2018-12-02 04:05:08,106 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 16 [2018-12-02 04:05:08,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:08,106 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2018-12-02 04:05:08,107 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:05:08,107 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2018-12-02 04:05:08,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-12-02 04:05:08,107 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:08,107 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:08,108 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:08,108 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:08,108 INFO L82 PathProgramCache]: Analyzing trace with hash 2121234190, now seen corresponding path program 1 times [2018-12-02 04:05:08,108 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:08,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,109 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:08,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,109 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:08,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:08,152 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:08,153 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:08,153 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:08,153 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 21 with the following transitions: [2018-12-02 04:05:08,153 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [35], [37], [40], [73], [74], [75], [77], [78] [2018-12-02 04:05:08,154 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:05:08,154 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:05:08,198 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:05:08,198 INFO L272 AbstractInterpreter]: Visited 20 different actions 43 times. Merged at 11 different actions 21 times. Never widened. Performed 219 root evaluator evaluations with a maximum evaluation depth of 4. Performed 219 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 1 fixpoints after 1 different actions. Largest state had 21 variables. [2018-12-02 04:05:08,200 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:08,200 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:05:08,200 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:08,200 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:08,209 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:08,209 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:08,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:08,219 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:08,267 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:08,267 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:08,325 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:08,340 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:08,340 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 11 [2018-12-02 04:05:08,340 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:08,340 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-02 04:05:08,340 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-02 04:05:08,340 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-12-02 04:05:08,341 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand 9 states. [2018-12-02 04:05:08,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:08,425 INFO L93 Difference]: Finished difference Result 64 states and 68 transitions. [2018-12-02 04:05:08,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-02 04:05:08,425 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 20 [2018-12-02 04:05:08,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:08,426 INFO L225 Difference]: With dead ends: 64 [2018-12-02 04:05:08,426 INFO L226 Difference]: Without dead ends: 58 [2018-12-02 04:05:08,426 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 32 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=104, Unknown=0, NotChecked=0, Total=156 [2018-12-02 04:05:08,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-12-02 04:05:08,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 42. [2018-12-02 04:05:08,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-12-02 04:05:08,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 45 transitions. [2018-12-02 04:05:08,428 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 45 transitions. Word has length 20 [2018-12-02 04:05:08,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:08,428 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 45 transitions. [2018-12-02 04:05:08,428 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-02 04:05:08,429 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 45 transitions. [2018-12-02 04:05:08,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-12-02 04:05:08,429 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:08,429 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:08,429 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:08,429 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:08,429 INFO L82 PathProgramCache]: Analyzing trace with hash -1483602424, now seen corresponding path program 2 times [2018-12-02 04:05:08,429 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:08,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:08,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,430 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:08,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:08,467 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:05:08,467 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:08,467 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:08,467 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:08,467 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:08,467 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:08,467 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:08,473 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:08,473 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:08,482 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-02 04:05:08,482 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:08,484 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:08,524 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-02 04:05:08,524 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:08,584 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-02 04:05:08,598 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:08,598 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 18 [2018-12-02 04:05:08,598 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:08,598 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-02 04:05:08,598 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-02 04:05:08,598 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=247, Unknown=0, NotChecked=0, Total=306 [2018-12-02 04:05:08,599 INFO L87 Difference]: Start difference. First operand 42 states and 45 transitions. Second operand 12 states. [2018-12-02 04:05:08,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:08,694 INFO L93 Difference]: Finished difference Result 70 states and 73 transitions. [2018-12-02 04:05:08,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-02 04:05:08,694 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 21 [2018-12-02 04:05:08,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:08,695 INFO L225 Difference]: With dead ends: 70 [2018-12-02 04:05:08,695 INFO L226 Difference]: Without dead ends: 70 [2018-12-02 04:05:08,695 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=113, Invalid=349, Unknown=0, NotChecked=0, Total=462 [2018-12-02 04:05:08,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-12-02 04:05:08,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 58. [2018-12-02 04:05:08,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-12-02 04:05:08,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 61 transitions. [2018-12-02 04:05:08,698 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 61 transitions. Word has length 21 [2018-12-02 04:05:08,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:08,698 INFO L480 AbstractCegarLoop]: Abstraction has 58 states and 61 transitions. [2018-12-02 04:05:08,698 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-02 04:05:08,698 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 61 transitions. [2018-12-02 04:05:08,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-02 04:05:08,699 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:08,699 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:08,699 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:08,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:08,699 INFO L82 PathProgramCache]: Analyzing trace with hash -523456177, now seen corresponding path program 2 times [2018-12-02 04:05:08,700 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:08,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,700 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:08,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,700 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:08,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:08,722 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 04:05:08,723 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:08,723 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 04:05:08,723 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:08,723 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:05:08,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:05:08,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:08,724 INFO L87 Difference]: Start difference. First operand 58 states and 61 transitions. Second operand 3 states. [2018-12-02 04:05:08,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:08,740 INFO L93 Difference]: Finished difference Result 62 states and 65 transitions. [2018-12-02 04:05:08,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:05:08,740 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-02 04:05:08,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:08,741 INFO L225 Difference]: With dead ends: 62 [2018-12-02 04:05:08,741 INFO L226 Difference]: Without dead ends: 62 [2018-12-02 04:05:08,741 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:05:08,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-12-02 04:05:08,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 60. [2018-12-02 04:05:08,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-12-02 04:05:08,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2018-12-02 04:05:08,743 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 63 transitions. Word has length 25 [2018-12-02 04:05:08,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:08,744 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 63 transitions. [2018-12-02 04:05:08,744 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:05:08,744 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 63 transitions. [2018-12-02 04:05:08,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-12-02 04:05:08,744 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:08,744 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:08,745 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:08,745 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:08,745 INFO L82 PathProgramCache]: Analyzing trace with hash 2020089664, now seen corresponding path program 1 times [2018-12-02 04:05:08,745 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:08,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:08,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:08,746 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:08,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:08,782 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-02 04:05:08,783 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:08,783 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:08,783 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 32 with the following transitions: [2018-12-02 04:05:08,783 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [33], [35], [37], [38], [41], [43], [47], [55], [58], [73], [74], [75], [77], [78] [2018-12-02 04:05:08,784 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:05:08,784 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:05:08,952 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:05:08,952 INFO L272 AbstractInterpreter]: Visited 26 different actions 202 times. Merged at 15 different actions 119 times. Widened at 2 different actions 4 times. Performed 1022 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1022 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 18 fixpoints after 5 different actions. Largest state had 21 variables. [2018-12-02 04:05:08,955 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:08,955 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:05:08,955 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:08,955 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:08,961 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:08,962 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:08,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:08,973 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:08,989 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 04:05:08,989 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:09,006 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 04:05:09,031 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:09,031 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 4, 4] total 10 [2018-12-02 04:05:09,031 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:09,031 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-02 04:05:09,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-02 04:05:09,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-12-02 04:05:09,032 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. Second operand 10 states. [2018-12-02 04:05:09,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:09,117 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2018-12-02 04:05:09,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-02 04:05:09,117 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 31 [2018-12-02 04:05:09,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:09,117 INFO L225 Difference]: With dead ends: 74 [2018-12-02 04:05:09,117 INFO L226 Difference]: Without dead ends: 74 [2018-12-02 04:05:09,118 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-12-02 04:05:09,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-12-02 04:05:09,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 49. [2018-12-02 04:05:09,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-12-02 04:05:09,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2018-12-02 04:05:09,120 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 50 transitions. Word has length 31 [2018-12-02 04:05:09,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:09,120 INFO L480 AbstractCegarLoop]: Abstraction has 49 states and 50 transitions. [2018-12-02 04:05:09,120 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-02 04:05:09,120 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 50 transitions. [2018-12-02 04:05:09,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-12-02 04:05:09,121 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:09,121 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:09,121 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:09,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:09,121 INFO L82 PathProgramCache]: Analyzing trace with hash -1710006518, now seen corresponding path program 1 times [2018-12-02 04:05:09,121 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:09,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:09,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:09,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:09,122 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:09,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:09,147 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-02 04:05:09,148 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:09,148 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:09,148 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 43 with the following transitions: [2018-12-02 04:05:09,148 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [11], [12], [13], [16], [18], [22], [23], [27], [35], [37], [38], [41], [43], [73], [74], [75], [77], [78] [2018-12-02 04:05:09,149 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:05:09,149 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:05:09,225 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:05:09,225 INFO L272 AbstractInterpreter]: Visited 23 different actions 177 times. Merged at 15 different actions 103 times. Widened at 1 different actions 3 times. Performed 891 root evaluator evaluations with a maximum evaluation depth of 4. Performed 891 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 13 fixpoints after 3 different actions. Largest state had 21 variables. [2018-12-02 04:05:09,228 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:09,228 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:05:09,228 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:09,228 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:09,237 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:09,237 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:09,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:09,250 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:09,260 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-02 04:05:09,260 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:09,291 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-02 04:05:09,306 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:09,306 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2018-12-02 04:05:09,307 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:09,307 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:05:09,307 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:05:09,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:05:09,307 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. Second operand 5 states. [2018-12-02 04:05:09,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:09,345 INFO L93 Difference]: Finished difference Result 60 states and 62 transitions. [2018-12-02 04:05:09,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:05:09,346 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-12-02 04:05:09,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:09,346 INFO L225 Difference]: With dead ends: 60 [2018-12-02 04:05:09,346 INFO L226 Difference]: Without dead ends: 60 [2018-12-02 04:05:09,346 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 79 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:05:09,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-12-02 04:05:09,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 54. [2018-12-02 04:05:09,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-12-02 04:05:09,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 56 transitions. [2018-12-02 04:05:09,348 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 56 transitions. Word has length 42 [2018-12-02 04:05:09,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:09,349 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 56 transitions. [2018-12-02 04:05:09,349 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:05:09,349 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 56 transitions. [2018-12-02 04:05:09,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-02 04:05:09,349 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:09,349 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:09,349 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:09,349 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:09,349 INFO L82 PathProgramCache]: Analyzing trace with hash -1860847279, now seen corresponding path program 1 times [2018-12-02 04:05:09,349 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:09,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:09,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:09,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:09,350 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:09,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:09,414 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 4 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-12-02 04:05:09,414 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:09,415 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:09,415 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 47 with the following transitions: [2018-12-02 04:05:09,415 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [35], [37], [38], [40], [41], [43], [73], [74], [75], [77], [78] [2018-12-02 04:05:09,416 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:05:09,416 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:05:09,492 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:05:09,492 INFO L272 AbstractInterpreter]: Visited 23 different actions 181 times. Merged at 15 different actions 107 times. Widened at 1 different actions 2 times. Performed 939 root evaluator evaluations with a maximum evaluation depth of 4. Performed 939 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 14 fixpoints after 3 different actions. Largest state had 21 variables. [2018-12-02 04:05:09,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:09,500 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:05:09,500 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:09,500 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:09,508 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:09,508 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:09,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:09,524 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:09,560 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:05:09,561 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:09,645 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:05:09,669 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:09,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 18 [2018-12-02 04:05:09,669 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:09,669 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-02 04:05:09,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-02 04:05:09,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2018-12-02 04:05:09,670 INFO L87 Difference]: Start difference. First operand 54 states and 56 transitions. Second operand 15 states. [2018-12-02 04:05:09,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:09,791 INFO L93 Difference]: Finished difference Result 62 states and 63 transitions. [2018-12-02 04:05:09,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-02 04:05:09,791 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 46 [2018-12-02 04:05:09,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:09,792 INFO L225 Difference]: With dead ends: 62 [2018-12-02 04:05:09,792 INFO L226 Difference]: Without dead ends: 59 [2018-12-02 04:05:09,792 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 84 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=125, Invalid=381, Unknown=0, NotChecked=0, Total=506 [2018-12-02 04:05:09,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-12-02 04:05:09,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 54. [2018-12-02 04:05:09,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-12-02 04:05:09,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-12-02 04:05:09,794 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 46 [2018-12-02 04:05:09,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:09,795 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-12-02 04:05:09,795 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-02 04:05:09,795 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-12-02 04:05:09,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 04:05:09,795 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:09,796 INFO L402 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:09,796 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:09,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:09,796 INFO L82 PathProgramCache]: Analyzing trace with hash -374076379, now seen corresponding path program 2 times [2018-12-02 04:05:09,796 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:09,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:09,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:09,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:09,797 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:09,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:09,839 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 55 proven. 7 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-02 04:05:09,839 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:09,839 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:09,839 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:09,839 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:09,839 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:09,840 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:09,846 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:09,846 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:09,857 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-02 04:05:09,857 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:09,858 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:09,897 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 48 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:05:09,897 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:09,968 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 39 proven. 14 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:05:09,983 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:09,983 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 8] total 21 [2018-12-02 04:05:09,983 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:09,983 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-02 04:05:09,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-02 04:05:09,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-12-02 04:05:09,983 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 14 states. [2018-12-02 04:05:10,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:10,084 INFO L93 Difference]: Finished difference Result 83 states and 84 transitions. [2018-12-02 04:05:10,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-12-02 04:05:10,084 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 47 [2018-12-02 04:05:10,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:10,085 INFO L225 Difference]: With dead ends: 83 [2018-12-02 04:05:10,085 INFO L226 Difference]: Without dead ends: 83 [2018-12-02 04:05:10,086 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 84 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 124 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=165, Invalid=537, Unknown=0, NotChecked=0, Total=702 [2018-12-02 04:05:10,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-12-02 04:05:10,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 78. [2018-12-02 04:05:10,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-12-02 04:05:10,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 79 transitions. [2018-12-02 04:05:10,089 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 79 transitions. Word has length 47 [2018-12-02 04:05:10,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:10,089 INFO L480 AbstractCegarLoop]: Abstraction has 78 states and 79 transitions. [2018-12-02 04:05:10,089 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-02 04:05:10,089 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 79 transitions. [2018-12-02 04:05:10,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-12-02 04:05:10,090 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:10,090 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:10,090 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:10,091 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:10,091 INFO L82 PathProgramCache]: Analyzing trace with hash -1743494932, now seen corresponding path program 2 times [2018-12-02 04:05:10,091 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:10,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:10,092 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:10,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:10,092 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:10,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:10,167 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 04:05:10,167 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:10,167 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:10,167 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:10,167 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:10,167 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:10,167 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:10,173 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:10,173 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:10,185 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-02 04:05:10,185 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:10,187 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:10,209 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-02 04:05:10,211 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 04:05:10,212 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-02 04:05:10,212 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 04:05:10,216 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 04:05:10,223 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-02 04:05:10,223 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-02 04:05:10,227 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-02 04:05:10,227 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-12-02 04:05:10,323 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 04:05:10,323 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:10,365 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-02 04:05:10,390 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:10,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 3] total 9 [2018-12-02 04:05:10,390 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:10,390 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-02 04:05:10,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-02 04:05:10,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2018-12-02 04:05:10,391 INFO L87 Difference]: Start difference. First operand 78 states and 79 transitions. Second operand 8 states. [2018-12-02 04:05:10,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:10,466 INFO L93 Difference]: Finished difference Result 82 states and 83 transitions. [2018-12-02 04:05:10,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:05:10,466 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-12-02 04:05:10,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:10,466 INFO L225 Difference]: With dead ends: 82 [2018-12-02 04:05:10,466 INFO L226 Difference]: Without dead ends: 82 [2018-12-02 04:05:10,467 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 94 SyntacticMatches, 4 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-12-02 04:05:10,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-12-02 04:05:10,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 80. [2018-12-02 04:05:10,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-12-02 04:05:10,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2018-12-02 04:05:10,469 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 81 transitions. Word has length 51 [2018-12-02 04:05:10,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:10,469 INFO L480 AbstractCegarLoop]: Abstraction has 80 states and 81 transitions. [2018-12-02 04:05:10,469 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-02 04:05:10,469 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 81 transitions. [2018-12-02 04:05:10,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-02 04:05:10,469 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:10,469 INFO L402 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:10,470 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:10,470 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:10,470 INFO L82 PathProgramCache]: Analyzing trace with hash 1240037378, now seen corresponding path program 3 times [2018-12-02 04:05:10,470 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:10,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:10,471 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:10,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:10,471 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:10,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:10,544 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 104 proven. 13 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2018-12-02 04:05:10,544 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:10,544 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:10,544 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:10,544 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:10,544 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:10,545 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:10,550 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:10,551 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:10,567 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:10,567 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:10,569 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:10,597 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 93 proven. 21 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-12-02 04:05:10,597 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:10,650 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 93 proven. 21 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-12-02 04:05:10,664 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:10,664 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 5, 5] total 17 [2018-12-02 04:05:10,664 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:10,665 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-02 04:05:10,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-02 04:05:10,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=244, Unknown=0, NotChecked=0, Total=306 [2018-12-02 04:05:10,665 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. Second operand 14 states. [2018-12-02 04:05:10,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:10,812 INFO L93 Difference]: Finished difference Result 132 states and 136 transitions. [2018-12-02 04:05:10,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-02 04:05:10,812 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 73 [2018-12-02 04:05:10,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:10,813 INFO L225 Difference]: With dead ends: 132 [2018-12-02 04:05:10,813 INFO L226 Difference]: Without dead ends: 132 [2018-12-02 04:05:10,814 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=144, Invalid=456, Unknown=0, NotChecked=0, Total=600 [2018-12-02 04:05:10,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-12-02 04:05:10,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 109. [2018-12-02 04:05:10,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-12-02 04:05:10,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 112 transitions. [2018-12-02 04:05:10,818 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 112 transitions. Word has length 73 [2018-12-02 04:05:10,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:10,818 INFO L480 AbstractCegarLoop]: Abstraction has 109 states and 112 transitions. [2018-12-02 04:05:10,818 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-02 04:05:10,818 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 112 transitions. [2018-12-02 04:05:10,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-12-02 04:05:10,819 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:10,819 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:10,819 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:10,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:10,819 INFO L82 PathProgramCache]: Analyzing trace with hash -976841143, now seen corresponding path program 3 times [2018-12-02 04:05:10,820 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:10,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:10,820 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:10,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:10,820 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:10,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:10,923 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 69 proven. 103 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-02 04:05:10,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:10,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:10,923 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:10,923 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:10,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:10,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:10,930 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:10,930 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:10,943 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:10,944 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:10,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:11,007 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 70 proven. 102 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-02 04:05:11,007 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:11,132 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 76 proven. 96 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-02 04:05:11,157 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:11,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2018-12-02 04:05:11,158 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:11,158 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-12-02 04:05:11,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-12-02 04:05:11,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=527, Unknown=0, NotChecked=0, Total=650 [2018-12-02 04:05:11,158 INFO L87 Difference]: Start difference. First operand 109 states and 112 transitions. Second operand 20 states. [2018-12-02 04:05:11,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:11,321 INFO L93 Difference]: Finished difference Result 127 states and 129 transitions. [2018-12-02 04:05:11,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-12-02 04:05:11,321 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 77 [2018-12-02 04:05:11,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:11,322 INFO L225 Difference]: With dead ends: 127 [2018-12-02 04:05:11,322 INFO L226 Difference]: Without dead ends: 121 [2018-12-02 04:05:11,322 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 137 SyntacticMatches, 7 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 265 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=249, Invalid=807, Unknown=0, NotChecked=0, Total=1056 [2018-12-02 04:05:11,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-12-02 04:05:11,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 114. [2018-12-02 04:05:11,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-12-02 04:05:11,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 116 transitions. [2018-12-02 04:05:11,325 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 116 transitions. Word has length 77 [2018-12-02 04:05:11,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:11,325 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 116 transitions. [2018-12-02 04:05:11,325 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-12-02 04:05:11,325 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 116 transitions. [2018-12-02 04:05:11,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-12-02 04:05:11,326 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:11,326 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:11,326 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:11,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:11,327 INFO L82 PathProgramCache]: Analyzing trace with hash -490807564, now seen corresponding path program 4 times [2018-12-02 04:05:11,327 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:11,327 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:11,327 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:11,327 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:11,327 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:11,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:11,380 INFO L134 CoverageAnalysis]: Checked inductivity of 236 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 226 trivial. 0 not checked. [2018-12-02 04:05:11,381 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:05:11,381 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:05:11,381 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:05:11,381 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:05:11,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:05:11,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:05:11,381 INFO L87 Difference]: Start difference. First operand 114 states and 116 transitions. Second operand 6 states. [2018-12-02 04:05:11,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:11,394 INFO L93 Difference]: Finished difference Result 113 states and 115 transitions. [2018-12-02 04:05:11,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:05:11,394 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 82 [2018-12-02 04:05:11,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:11,395 INFO L225 Difference]: With dead ends: 113 [2018-12-02 04:05:11,395 INFO L226 Difference]: Without dead ends: 113 [2018-12-02 04:05:11,395 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:05:11,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-12-02 04:05:11,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-12-02 04:05:11,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-12-02 04:05:11,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 115 transitions. [2018-12-02 04:05:11,398 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 115 transitions. Word has length 82 [2018-12-02 04:05:11,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:11,398 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 115 transitions. [2018-12-02 04:05:11,398 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:05:11,398 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 115 transitions. [2018-12-02 04:05:11,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-12-02 04:05:11,399 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:11,399 INFO L402 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:11,400 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:11,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:11,400 INFO L82 PathProgramCache]: Analyzing trace with hash 241027877, now seen corresponding path program 4 times [2018-12-02 04:05:11,400 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:11,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:11,401 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:11,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:11,401 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:11,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:11,506 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 250 proven. 28 refuted. 0 times theorem prover too weak. 222 trivial. 0 not checked. [2018-12-02 04:05:11,507 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:11,507 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:11,507 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:11,507 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:11,507 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:11,507 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:11,514 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:11,514 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:11,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:11,540 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:11,582 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 213 proven. 38 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-02 04:05:11,582 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:11,660 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 213 proven. 38 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-02 04:05:11,675 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:11,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6] total 22 [2018-12-02 04:05:11,675 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:11,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-12-02 04:05:11,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-12-02 04:05:11,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=417, Unknown=0, NotChecked=0, Total=506 [2018-12-02 04:05:11,676 INFO L87 Difference]: Start difference. First operand 113 states and 115 transitions. Second operand 18 states. [2018-12-02 04:05:11,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:11,885 INFO L93 Difference]: Finished difference Result 175 states and 181 transitions. [2018-12-02 04:05:11,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-02 04:05:11,885 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 109 [2018-12-02 04:05:11,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:11,886 INFO L225 Difference]: With dead ends: 175 [2018-12-02 04:05:11,886 INFO L226 Difference]: Without dead ends: 175 [2018-12-02 04:05:11,886 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 208 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 136 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=179, Invalid=691, Unknown=0, NotChecked=0, Total=870 [2018-12-02 04:05:11,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-12-02 04:05:11,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 149. [2018-12-02 04:05:11,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-12-02 04:05:11,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 153 transitions. [2018-12-02 04:05:11,889 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 153 transitions. Word has length 109 [2018-12-02 04:05:11,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:11,890 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 153 transitions. [2018-12-02 04:05:11,890 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-12-02 04:05:11,890 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 153 transitions. [2018-12-02 04:05:11,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-12-02 04:05:11,891 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:11,891 INFO L402 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:11,891 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:11,891 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:11,891 INFO L82 PathProgramCache]: Analyzing trace with hash -937043486, now seen corresponding path program 5 times [2018-12-02 04:05:11,892 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:11,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:11,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:11,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:11,892 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:11,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:12,028 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 553 proven. 153 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-02 04:05:12,029 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:12,029 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:12,029 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:12,029 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:12,029 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:12,029 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:12,035 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:12,035 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:12,065 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-12-02 04:05:12,065 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:12,067 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:12,130 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 375 proven. 60 refuted. 0 times theorem prover too weak. 520 trivial. 0 not checked. [2018-12-02 04:05:12,130 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:12,240 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 375 proven. 60 refuted. 0 times theorem prover too weak. 520 trivial. 0 not checked. [2018-12-02 04:05:12,255 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:12,255 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 8, 8] total 32 [2018-12-02 04:05:12,255 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:12,255 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-12-02 04:05:12,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-12-02 04:05:12,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=162, Invalid=830, Unknown=0, NotChecked=0, Total=992 [2018-12-02 04:05:12,256 INFO L87 Difference]: Start difference. First operand 149 states and 153 transitions. Second operand 25 states. [2018-12-02 04:05:12,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:12,632 INFO L93 Difference]: Finished difference Result 267 states and 278 transitions. [2018-12-02 04:05:12,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-02 04:05:12,632 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 145 [2018-12-02 04:05:12,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:12,633 INFO L225 Difference]: With dead ends: 267 [2018-12-02 04:05:12,633 INFO L226 Difference]: Without dead ends: 267 [2018-12-02 04:05:12,634 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 324 GetRequests, 277 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 414 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=567, Invalid=1785, Unknown=0, NotChecked=0, Total=2352 [2018-12-02 04:05:12,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-12-02 04:05:12,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 245. [2018-12-02 04:05:12,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-12-02 04:05:12,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 255 transitions. [2018-12-02 04:05:12,639 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 255 transitions. Word has length 145 [2018-12-02 04:05:12,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:12,639 INFO L480 AbstractCegarLoop]: Abstraction has 245 states and 255 transitions. [2018-12-02 04:05:12,639 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-12-02 04:05:12,639 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 255 transitions. [2018-12-02 04:05:12,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-12-02 04:05:12,640 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:12,641 INFO L402 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:12,641 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:12,641 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:12,641 INFO L82 PathProgramCache]: Analyzing trace with hash -714413016, now seen corresponding path program 6 times [2018-12-02 04:05:12,641 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:12,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:12,642 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:12,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:12,642 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:12,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:12,753 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 556 proven. 55 refuted. 0 times theorem prover too weak. 541 trivial. 0 not checked. [2018-12-02 04:05:12,753 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:12,753 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:12,753 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:12,753 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:12,753 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:12,753 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:12,759 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:12,759 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:12,781 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:12,781 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:12,783 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:12,917 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 506 proven. 262 refuted. 0 times theorem prover too weak. 384 trivial. 0 not checked. [2018-12-02 04:05:12,917 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:13,055 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 506 proven. 262 refuted. 0 times theorem prover too weak. 384 trivial. 0 not checked. [2018-12-02 04:05:13,069 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:13,069 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 19] total 31 [2018-12-02 04:05:13,069 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:13,070 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-02 04:05:13,070 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-02 04:05:13,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=763, Unknown=0, NotChecked=0, Total=930 [2018-12-02 04:05:13,070 INFO L87 Difference]: Start difference. First operand 245 states and 255 transitions. Second operand 28 states. [2018-12-02 04:05:13,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:13,409 INFO L93 Difference]: Finished difference Result 344 states and 358 transitions. [2018-12-02 04:05:13,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-02 04:05:13,409 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 155 [2018-12-02 04:05:13,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:13,410 INFO L225 Difference]: With dead ends: 344 [2018-12-02 04:05:13,410 INFO L226 Difference]: Without dead ends: 344 [2018-12-02 04:05:13,410 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 281 SyntacticMatches, 15 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 585 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=386, Invalid=1506, Unknown=0, NotChecked=0, Total=1892 [2018-12-02 04:05:13,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states. [2018-12-02 04:05:13,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 330. [2018-12-02 04:05:13,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 330 states. [2018-12-02 04:05:13,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 330 states to 330 states and 344 transitions. [2018-12-02 04:05:13,415 INFO L78 Accepts]: Start accepts. Automaton has 330 states and 344 transitions. Word has length 155 [2018-12-02 04:05:13,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:13,415 INFO L480 AbstractCegarLoop]: Abstraction has 330 states and 344 transitions. [2018-12-02 04:05:13,415 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-02 04:05:13,415 INFO L276 IsEmpty]: Start isEmpty. Operand 330 states and 344 transitions. [2018-12-02 04:05:13,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-12-02 04:05:13,416 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:13,416 INFO L402 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:13,416 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:13,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:13,417 INFO L82 PathProgramCache]: Analyzing trace with hash 1015841328, now seen corresponding path program 7 times [2018-12-02 04:05:13,417 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:13,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:13,417 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:13,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:13,417 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:13,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:13,547 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 814 proven. 295 refuted. 0 times theorem prover too weak. 569 trivial. 0 not checked. [2018-12-02 04:05:13,548 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:13,548 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:13,548 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:13,548 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:13,548 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:13,548 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:13,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:13,556 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:13,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:13,593 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:13,698 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 1103 proven. 34 refuted. 0 times theorem prover too weak. 541 trivial. 0 not checked. [2018-12-02 04:05:13,698 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:13,844 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 893 proven. 147 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2018-12-02 04:05:13,868 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:13,868 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 12, 12] total 34 [2018-12-02 04:05:13,868 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:13,869 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-02 04:05:13,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-02 04:05:13,869 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=180, Invalid=942, Unknown=0, NotChecked=0, Total=1122 [2018-12-02 04:05:13,869 INFO L87 Difference]: Start difference. First operand 330 states and 344 transitions. Second operand 29 states. [2018-12-02 04:05:14,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:14,269 INFO L93 Difference]: Finished difference Result 303 states and 311 transitions. [2018-12-02 04:05:14,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-02 04:05:14,269 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 186 [2018-12-02 04:05:14,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:14,270 INFO L225 Difference]: With dead ends: 303 [2018-12-02 04:05:14,271 INFO L226 Difference]: Without dead ends: 294 [2018-12-02 04:05:14,271 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 411 GetRequests, 353 SyntacticMatches, 6 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 860 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=495, Invalid=2367, Unknown=0, NotChecked=0, Total=2862 [2018-12-02 04:05:14,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2018-12-02 04:05:14,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 249. [2018-12-02 04:05:14,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 249 states. [2018-12-02 04:05:14,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 254 transitions. [2018-12-02 04:05:14,275 INFO L78 Accepts]: Start accepts. Automaton has 249 states and 254 transitions. Word has length 186 [2018-12-02 04:05:14,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:14,275 INFO L480 AbstractCegarLoop]: Abstraction has 249 states and 254 transitions. [2018-12-02 04:05:14,275 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-02 04:05:14,275 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 254 transitions. [2018-12-02 04:05:14,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-12-02 04:05:14,276 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:14,276 INFO L402 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:14,276 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:14,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:14,277 INFO L82 PathProgramCache]: Analyzing trace with hash 1382499467, now seen corresponding path program 8 times [2018-12-02 04:05:14,277 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:14,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:14,277 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:14,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:14,278 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:14,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:14,428 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 988 proven. 228 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2018-12-02 04:05:14,428 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:14,428 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:14,428 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:14,428 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:14,428 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:14,428 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:14,434 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:14,434 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:14,482 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-12-02 04:05:14,483 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:14,486 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:14,586 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 643 proven. 87 refuted. 0 times theorem prover too weak. 1075 trivial. 0 not checked. [2018-12-02 04:05:14,586 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:14,713 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 643 proven. 87 refuted. 0 times theorem prover too weak. 1075 trivial. 0 not checked. [2018-12-02 04:05:14,728 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:14,728 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 9, 9] total 36 [2018-12-02 04:05:14,728 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:14,728 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-02 04:05:14,729 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-02 04:05:14,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=206, Invalid=1054, Unknown=0, NotChecked=0, Total=1260 [2018-12-02 04:05:14,729 INFO L87 Difference]: Start difference. First operand 249 states and 254 transitions. Second operand 28 states. [2018-12-02 04:05:15,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:15,147 INFO L93 Difference]: Finished difference Result 355 states and 365 transitions. [2018-12-02 04:05:15,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-02 04:05:15,147 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 191 [2018-12-02 04:05:15,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:15,148 INFO L225 Difference]: With dead ends: 355 [2018-12-02 04:05:15,148 INFO L226 Difference]: Without dead ends: 355 [2018-12-02 04:05:15,149 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 421 GetRequests, 367 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 566 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=747, Invalid=2333, Unknown=0, NotChecked=0, Total=3080 [2018-12-02 04:05:15,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2018-12-02 04:05:15,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 301. [2018-12-02 04:05:15,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 301 states. [2018-12-02 04:05:15,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 309 transitions. [2018-12-02 04:05:15,154 INFO L78 Accepts]: Start accepts. Automaton has 301 states and 309 transitions. Word has length 191 [2018-12-02 04:05:15,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:15,154 INFO L480 AbstractCegarLoop]: Abstraction has 301 states and 309 transitions. [2018-12-02 04:05:15,154 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-02 04:05:15,154 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 309 transitions. [2018-12-02 04:05:15,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2018-12-02 04:05:15,155 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:15,156 INFO L402 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:15,156 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:15,156 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:15,156 INFO L82 PathProgramCache]: Analyzing trace with hash 938276997, now seen corresponding path program 9 times [2018-12-02 04:05:15,156 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:15,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:15,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:15,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:15,157 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:15,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:15,287 INFO L134 CoverageAnalysis]: Checked inductivity of 2074 backedges. 891 proven. 83 refuted. 0 times theorem prover too weak. 1100 trivial. 0 not checked. [2018-12-02 04:05:15,287 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:15,287 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:15,287 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:15,287 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:15,287 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:15,287 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:15,295 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:15,295 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:15,324 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:15,324 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:15,326 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:15,489 INFO L134 CoverageAnalysis]: Checked inductivity of 2074 backedges. 834 proven. 369 refuted. 0 times theorem prover too weak. 871 trivial. 0 not checked. [2018-12-02 04:05:15,490 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:15,677 INFO L134 CoverageAnalysis]: Checked inductivity of 2074 backedges. 834 proven. 369 refuted. 0 times theorem prover too weak. 871 trivial. 0 not checked. [2018-12-02 04:05:15,691 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:15,691 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 21, 21] total 34 [2018-12-02 04:05:15,692 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:15,692 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-02 04:05:15,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-02 04:05:15,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=920, Unknown=0, NotChecked=0, Total=1122 [2018-12-02 04:05:15,692 INFO L87 Difference]: Start difference. First operand 301 states and 309 transitions. Second operand 31 states. [2018-12-02 04:05:16,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:16,078 INFO L93 Difference]: Finished difference Result 405 states and 417 transitions. [2018-12-02 04:05:16,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-02 04:05:16,078 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 201 [2018-12-02 04:05:16,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:16,079 INFO L225 Difference]: With dead ends: 405 [2018-12-02 04:05:16,079 INFO L226 Difference]: Without dead ends: 405 [2018-12-02 04:05:16,079 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 434 GetRequests, 370 SyntacticMatches, 17 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 741 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=478, Invalid=1874, Unknown=0, NotChecked=0, Total=2352 [2018-12-02 04:05:16,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states. [2018-12-02 04:05:16,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 391. [2018-12-02 04:05:16,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 391 states. [2018-12-02 04:05:16,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 391 states and 403 transitions. [2018-12-02 04:05:16,084 INFO L78 Accepts]: Start accepts. Automaton has 391 states and 403 transitions. Word has length 201 [2018-12-02 04:05:16,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:16,085 INFO L480 AbstractCegarLoop]: Abstraction has 391 states and 403 transitions. [2018-12-02 04:05:16,085 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-02 04:05:16,085 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 403 transitions. [2018-12-02 04:05:16,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2018-12-02 04:05:16,085 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:16,086 INFO L402 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:16,086 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:16,086 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:16,086 INFO L82 PathProgramCache]: Analyzing trace with hash -951313496, now seen corresponding path program 10 times [2018-12-02 04:05:16,086 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:16,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:16,086 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:16,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:16,086 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:16,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:16,238 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1349 proven. 427 refuted. 0 times theorem prover too weak. 1149 trivial. 0 not checked. [2018-12-02 04:05:16,238 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:16,238 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:16,238 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:16,238 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:16,238 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:16,238 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:16,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:16,244 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:16,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:16,284 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:16,453 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1888 proven. 55 refuted. 0 times theorem prover too weak. 982 trivial. 0 not checked. [2018-12-02 04:05:16,453 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:16,671 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1475 proven. 220 refuted. 0 times theorem prover too weak. 1230 trivial. 0 not checked. [2018-12-02 04:05:16,686 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:16,686 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 14, 14] total 39 [2018-12-02 04:05:16,686 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:16,687 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-02 04:05:16,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-02 04:05:16,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=236, Invalid=1246, Unknown=0, NotChecked=0, Total=1482 [2018-12-02 04:05:16,687 INFO L87 Difference]: Start difference. First operand 391 states and 403 transitions. Second operand 33 states. [2018-12-02 04:05:17,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:17,106 INFO L93 Difference]: Finished difference Result 368 states and 376 transitions. [2018-12-02 04:05:17,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-12-02 04:05:17,106 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 237 [2018-12-02 04:05:17,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:17,107 INFO L225 Difference]: With dead ends: 368 [2018-12-02 04:05:17,107 INFO L226 Difference]: Without dead ends: 359 [2018-12-02 04:05:17,108 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 519 GetRequests, 451 SyntacticMatches, 7 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1245 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=660, Invalid=3246, Unknown=0, NotChecked=0, Total=3906 [2018-12-02 04:05:17,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 359 states. [2018-12-02 04:05:17,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 359 to 300. [2018-12-02 04:05:17,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 300 states. [2018-12-02 04:05:17,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 305 transitions. [2018-12-02 04:05:17,114 INFO L78 Accepts]: Start accepts. Automaton has 300 states and 305 transitions. Word has length 237 [2018-12-02 04:05:17,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:17,114 INFO L480 AbstractCegarLoop]: Abstraction has 300 states and 305 transitions. [2018-12-02 04:05:17,114 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-02 04:05:17,114 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 305 transitions. [2018-12-02 04:05:17,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-12-02 04:05:17,115 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:17,116 INFO L402 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 33, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:17,116 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:17,116 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:17,116 INFO L82 PathProgramCache]: Analyzing trace with hash 1428696967, now seen corresponding path program 11 times [2018-12-02 04:05:17,116 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:17,117 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:17,117 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:17,117 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:17,117 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:17,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:17,313 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1600 proven. 318 refuted. 0 times theorem prover too weak. 1175 trivial. 0 not checked. [2018-12-02 04:05:17,313 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:17,313 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:17,313 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:17,313 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:17,314 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:17,314 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:17,321 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:17,321 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:17,373 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-12-02 04:05:17,374 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:17,376 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:17,525 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1513 proven. 318 refuted. 0 times theorem prover too weak. 1262 trivial. 0 not checked. [2018-12-02 04:05:17,525 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:17,833 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1488 proven. 343 refuted. 0 times theorem prover too weak. 1262 trivial. 0 not checked. [2018-12-02 04:05:17,858 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:17,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 16, 16] total 47 [2018-12-02 04:05:17,858 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:17,859 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-02 04:05:17,859 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-02 04:05:17,859 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=368, Invalid=1794, Unknown=0, NotChecked=0, Total=2162 [2018-12-02 04:05:17,859 INFO L87 Difference]: Start difference. First operand 300 states and 305 transitions. Second operand 32 states. [2018-12-02 04:05:18,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:18,268 INFO L93 Difference]: Finished difference Result 362 states and 369 transitions. [2018-12-02 04:05:18,268 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-02 04:05:18,268 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 242 [2018-12-02 04:05:18,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:18,270 INFO L225 Difference]: With dead ends: 362 [2018-12-02 04:05:18,270 INFO L226 Difference]: Without dead ends: 362 [2018-12-02 04:05:18,271 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 527 GetRequests, 459 SyntacticMatches, 1 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1244 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1109, Invalid=3583, Unknown=0, NotChecked=0, Total=4692 [2018-12-02 04:05:18,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states. [2018-12-02 04:05:18,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 352. [2018-12-02 04:05:18,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2018-12-02 04:05:18,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 359 transitions. [2018-12-02 04:05:18,275 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 359 transitions. Word has length 242 [2018-12-02 04:05:18,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:18,275 INFO L480 AbstractCegarLoop]: Abstraction has 352 states and 359 transitions. [2018-12-02 04:05:18,276 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-02 04:05:18,276 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 359 transitions. [2018-12-02 04:05:18,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 248 [2018-12-02 04:05:18,277 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:18,277 INFO L402 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:18,277 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:18,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:18,277 INFO L82 PathProgramCache]: Analyzing trace with hash -300291550, now seen corresponding path program 12 times [2018-12-02 04:05:18,277 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:18,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:18,278 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:18,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:18,278 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:18,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:18,370 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1078 proven. 109 refuted. 0 times theorem prover too weak. 2079 trivial. 0 not checked. [2018-12-02 04:05:18,370 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:18,370 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:18,370 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:18,370 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:18,370 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:18,370 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:18,376 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:18,376 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:18,429 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:18,429 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:18,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:18,521 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1047 proven. 119 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-02 04:05:18,521 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:18,645 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1047 proven. 119 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-02 04:05:18,661 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:18,661 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9, 9] total 29 [2018-12-02 04:05:18,662 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:18,662 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-12-02 04:05:18,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-12-02 04:05:18,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=710, Unknown=0, NotChecked=0, Total=870 [2018-12-02 04:05:18,662 INFO L87 Difference]: Start difference. First operand 352 states and 359 transitions. Second operand 22 states. [2018-12-02 04:05:19,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:19,115 INFO L93 Difference]: Finished difference Result 481 states and 494 transitions. [2018-12-02 04:05:19,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-02 04:05:19,115 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 247 [2018-12-02 04:05:19,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:19,116 INFO L225 Difference]: With dead ends: 481 [2018-12-02 04:05:19,116 INFO L226 Difference]: Without dead ends: 481 [2018-12-02 04:05:19,117 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 518 GetRequests, 478 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 351 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=354, Invalid=1368, Unknown=0, NotChecked=0, Total=1722 [2018-12-02 04:05:19,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-12-02 04:05:19,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 452. [2018-12-02 04:05:19,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 452 states. [2018-12-02 04:05:19,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 452 states to 452 states and 464 transitions. [2018-12-02 04:05:19,122 INFO L78 Accepts]: Start accepts. Automaton has 452 states and 464 transitions. Word has length 247 [2018-12-02 04:05:19,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:19,123 INFO L480 AbstractCegarLoop]: Abstraction has 452 states and 464 transitions. [2018-12-02 04:05:19,123 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-12-02 04:05:19,123 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 464 transitions. [2018-12-02 04:05:19,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-12-02 04:05:19,125 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:19,125 INFO L402 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 41, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:19,125 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:19,125 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:19,125 INFO L82 PathProgramCache]: Analyzing trace with hash -1077850677, now seen corresponding path program 13 times [2018-12-02 04:05:19,125 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:19,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:19,126 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:19,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:19,126 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:19,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:19,363 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2076 proven. 584 refuted. 0 times theorem prover too weak. 2068 trivial. 0 not checked. [2018-12-02 04:05:19,363 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:19,363 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:19,363 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:19,363 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:19,363 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:19,363 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:19,369 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:19,369 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:19,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:19,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:19,637 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2964 proven. 81 refuted. 0 times theorem prover too weak. 1683 trivial. 0 not checked. [2018-12-02 04:05:19,637 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:19,878 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2260 proven. 308 refuted. 0 times theorem prover too weak. 2160 trivial. 0 not checked. [2018-12-02 04:05:19,892 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:19,893 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 16, 16] total 44 [2018-12-02 04:05:19,893 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:19,893 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-02 04:05:19,893 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-02 04:05:19,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=1592, Unknown=0, NotChecked=0, Total=1892 [2018-12-02 04:05:19,894 INFO L87 Difference]: Start difference. First operand 452 states and 464 transitions. Second operand 37 states. [2018-12-02 04:05:20,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:20,481 INFO L93 Difference]: Finished difference Result 372 states and 377 transitions. [2018-12-02 04:05:20,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-12-02 04:05:20,481 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 293 [2018-12-02 04:05:20,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:20,482 INFO L225 Difference]: With dead ends: 372 [2018-12-02 04:05:20,482 INFO L226 Difference]: Without dead ends: 363 [2018-12-02 04:05:20,483 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 637 GetRequests, 559 SyntacticMatches, 8 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1700 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=850, Invalid=4262, Unknown=0, NotChecked=0, Total=5112 [2018-12-02 04:05:20,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363 states. [2018-12-02 04:05:20,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363 to 356. [2018-12-02 04:05:20,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 356 states. [2018-12-02 04:05:20,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356 states to 356 states and 361 transitions. [2018-12-02 04:05:20,488 INFO L78 Accepts]: Start accepts. Automaton has 356 states and 361 transitions. Word has length 293 [2018-12-02 04:05:20,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:20,488 INFO L480 AbstractCegarLoop]: Abstraction has 356 states and 361 transitions. [2018-12-02 04:05:20,488 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-02 04:05:20,488 INFO L276 IsEmpty]: Start isEmpty. Operand 356 states and 361 transitions. [2018-12-02 04:05:20,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2018-12-02 04:05:20,489 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:20,489 INFO L402 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 42, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:20,489 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:20,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:20,490 INFO L82 PathProgramCache]: Analyzing trace with hash -1652634800, now seen corresponding path program 14 times [2018-12-02 04:05:20,490 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:20,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:20,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:20,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:20,490 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:20,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:20,716 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 2419 proven. 423 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-02 04:05:20,716 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:20,716 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:20,716 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:20,716 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:20,716 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:20,716 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:20,722 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:20,722 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:20,781 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-12-02 04:05:20,781 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:20,784 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:20,929 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 1491 proven. 156 refuted. 0 times theorem prover too weak. 3295 trivial. 0 not checked. [2018-12-02 04:05:20,929 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:21,111 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 1491 proven. 156 refuted. 0 times theorem prover too weak. 3295 trivial. 0 not checked. [2018-12-02 04:05:21,126 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:21,126 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 11, 11] total 44 [2018-12-02 04:05:21,126 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:21,127 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-12-02 04:05:21,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-12-02 04:05:21,127 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=312, Invalid=1580, Unknown=0, NotChecked=0, Total=1892 [2018-12-02 04:05:21,127 INFO L87 Difference]: Start difference. First operand 356 states and 361 transitions. Second operand 34 states. [2018-12-02 04:05:21,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:21,733 INFO L93 Difference]: Finished difference Result 431 states and 439 transitions. [2018-12-02 04:05:21,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-02 04:05:21,733 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 298 [2018-12-02 04:05:21,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:21,735 INFO L225 Difference]: With dead ends: 431 [2018-12-02 04:05:21,735 INFO L226 Difference]: Without dead ends: 431 [2018-12-02 04:05:21,736 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 645 GetRequests, 577 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 939 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1185, Invalid=3645, Unknown=0, NotChecked=0, Total=4830 [2018-12-02 04:05:21,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-12-02 04:05:21,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 418. [2018-12-02 04:05:21,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 418 states. [2018-12-02 04:05:21,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 418 states to 418 states and 426 transitions. [2018-12-02 04:05:21,741 INFO L78 Accepts]: Start accepts. Automaton has 418 states and 426 transitions. Word has length 298 [2018-12-02 04:05:21,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:21,741 INFO L480 AbstractCegarLoop]: Abstraction has 418 states and 426 transitions. [2018-12-02 04:05:21,741 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-12-02 04:05:21,741 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 426 transitions. [2018-12-02 04:05:21,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2018-12-02 04:05:21,743 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:21,743 INFO L402 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 44, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:21,743 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:21,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:21,744 INFO L82 PathProgramCache]: Analyzing trace with hash 699884682, now seen corresponding path program 15 times [2018-12-02 04:05:21,744 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:21,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:21,744 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:21,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:21,744 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:21,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:21,923 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1903 proven. 157 refuted. 0 times theorem prover too weak. 3325 trivial. 0 not checked. [2018-12-02 04:05:21,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:21,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:21,923 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:21,923 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:21,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:21,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:21,931 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:21,931 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:21,982 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:21,982 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:21,986 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:22,219 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1832 proven. 634 refuted. 0 times theorem prover too weak. 2919 trivial. 0 not checked. [2018-12-02 04:05:22,220 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:22,441 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1832 proven. 634 refuted. 0 times theorem prover too weak. 2919 trivial. 0 not checked. [2018-12-02 04:05:22,456 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:22,456 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 25, 25] total 40 [2018-12-02 04:05:22,456 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:22,456 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-02 04:05:22,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-02 04:05:22,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=284, Invalid=1276, Unknown=0, NotChecked=0, Total=1560 [2018-12-02 04:05:22,457 INFO L87 Difference]: Start difference. First operand 418 states and 426 transitions. Second operand 37 states. [2018-12-02 04:05:23,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:23,015 INFO L93 Difference]: Finished difference Result 542 states and 554 transitions. [2018-12-02 04:05:23,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-02 04:05:23,016 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 308 [2018-12-02 04:05:23,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:23,017 INFO L225 Difference]: With dead ends: 542 [2018-12-02 04:05:23,017 INFO L226 Difference]: Without dead ends: 542 [2018-12-02 04:05:23,017 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 578 SyntacticMatches, 21 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1101 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=698, Invalid=2724, Unknown=0, NotChecked=0, Total=3422 [2018-12-02 04:05:23,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 542 states. [2018-12-02 04:05:23,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 542 to 528. [2018-12-02 04:05:23,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 528 states. [2018-12-02 04:05:23,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 528 states to 528 states and 540 transitions. [2018-12-02 04:05:23,022 INFO L78 Accepts]: Start accepts. Automaton has 528 states and 540 transitions. Word has length 308 [2018-12-02 04:05:23,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:23,022 INFO L480 AbstractCegarLoop]: Abstraction has 528 states and 540 transitions. [2018-12-02 04:05:23,022 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-02 04:05:23,023 INFO L276 IsEmpty]: Start isEmpty. Operand 528 states and 540 transitions. [2018-12-02 04:05:23,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2018-12-02 04:05:23,024 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:23,024 INFO L402 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 51, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:23,024 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:23,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:23,024 INFO L82 PathProgramCache]: Analyzing trace with hash 602331853, now seen corresponding path program 16 times [2018-12-02 04:05:23,024 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:23,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:23,025 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:23,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:23,025 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:23,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:23,252 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 3025 proven. 766 refuted. 0 times theorem prover too weak. 3434 trivial. 0 not checked. [2018-12-02 04:05:23,252 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:23,252 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:23,252 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:23,252 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:23,252 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:23,252 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:23,258 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:23,258 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:23,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:23,313 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:23,531 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 4376 proven. 112 refuted. 0 times theorem prover too weak. 2737 trivial. 0 not checked. [2018-12-02 04:05:23,531 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:23,835 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 3278 proven. 411 refuted. 0 times theorem prover too weak. 3536 trivial. 0 not checked. [2018-12-02 04:05:23,850 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:23,850 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 18, 18] total 49 [2018-12-02 04:05:23,850 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:23,851 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-02 04:05:23,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-02 04:05:23,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=372, Invalid=1980, Unknown=0, NotChecked=0, Total=2352 [2018-12-02 04:05:23,851 INFO L87 Difference]: Start difference. First operand 528 states and 540 transitions. Second operand 41 states. [2018-12-02 04:05:24,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:24,535 INFO L93 Difference]: Finished difference Result 433 states and 438 transitions. [2018-12-02 04:05:24,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-02 04:05:24,535 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 354 [2018-12-02 04:05:24,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:24,536 INFO L225 Difference]: With dead ends: 433 [2018-12-02 04:05:24,536 INFO L226 Difference]: Without dead ends: 424 [2018-12-02 04:05:24,537 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 765 GetRequests, 677 SyntacticMatches, 9 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2225 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1065, Invalid=5415, Unknown=0, NotChecked=0, Total=6480 [2018-12-02 04:05:24,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states. [2018-12-02 04:05:24,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 417. [2018-12-02 04:05:24,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 417 states. [2018-12-02 04:05:24,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417 states to 417 states and 422 transitions. [2018-12-02 04:05:24,542 INFO L78 Accepts]: Start accepts. Automaton has 417 states and 422 transitions. Word has length 354 [2018-12-02 04:05:24,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:24,543 INFO L480 AbstractCegarLoop]: Abstraction has 417 states and 422 transitions. [2018-12-02 04:05:24,543 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-02 04:05:24,543 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 422 transitions. [2018-12-02 04:05:24,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 360 [2018-12-02 04:05:24,545 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:24,545 INFO L402 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 52, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:24,545 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:24,545 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:24,545 INFO L82 PathProgramCache]: Analyzing trace with hash -1109948414, now seen corresponding path program 17 times [2018-12-02 04:05:24,546 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:24,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:24,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:24,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:24,546 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:24,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:24,799 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 3475 proven. 543 refuted. 0 times theorem prover too weak. 3472 trivial. 0 not checked. [2018-12-02 04:05:24,799 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:24,799 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:24,799 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:24,799 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:24,799 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:24,799 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:24,805 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:24,805 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:24,876 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-12-02 04:05:24,876 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:24,879 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:25,030 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 2101 proven. 198 refuted. 0 times theorem prover too weak. 5191 trivial. 0 not checked. [2018-12-02 04:05:25,031 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:25,249 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 2101 proven. 198 refuted. 0 times theorem prover too weak. 5191 trivial. 0 not checked. [2018-12-02 04:05:25,263 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:25,264 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 12, 12] total 48 [2018-12-02 04:05:25,264 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:25,264 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-02 04:05:25,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-02 04:05:25,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=374, Invalid=1882, Unknown=0, NotChecked=0, Total=2256 [2018-12-02 04:05:25,265 INFO L87 Difference]: Start difference. First operand 417 states and 422 transitions. Second operand 37 states. [2018-12-02 04:05:25,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:25,949 INFO L93 Difference]: Finished difference Result 497 states and 505 transitions. [2018-12-02 04:05:25,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-12-02 04:05:25,949 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 359 [2018-12-02 04:05:25,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:25,950 INFO L225 Difference]: With dead ends: 497 [2018-12-02 04:05:25,950 INFO L226 Difference]: Without dead ends: 497 [2018-12-02 04:05:25,951 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 772 GetRequests, 697 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1160 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1443, Invalid=4409, Unknown=0, NotChecked=0, Total=5852 [2018-12-02 04:05:25,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 497 states. [2018-12-02 04:05:25,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 497 to 484. [2018-12-02 04:05:25,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-12-02 04:05:25,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 492 transitions. [2018-12-02 04:05:25,955 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 492 transitions. Word has length 359 [2018-12-02 04:05:25,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:25,955 INFO L480 AbstractCegarLoop]: Abstraction has 484 states and 492 transitions. [2018-12-02 04:05:25,955 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-02 04:05:25,955 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 492 transitions. [2018-12-02 04:05:25,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 370 [2018-12-02 04:05:25,956 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:25,957 INFO L402 BasicCegarLoop]: trace histogram [55, 54, 54, 54, 54, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:25,957 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:25,957 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:25,957 INFO L82 PathProgramCache]: Analyzing trace with hash 37339976, now seen corresponding path program 18 times [2018-12-02 04:05:25,957 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:25,957 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:25,957 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:25,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:25,958 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:25,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:26,141 INFO L134 CoverageAnalysis]: Checked inductivity of 8035 backedges. 2610 proven. 203 refuted. 0 times theorem prover too weak. 5222 trivial. 0 not checked. [2018-12-02 04:05:26,141 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:26,141 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:26,141 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:26,141 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:26,141 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:26,141 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:26,151 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:26,151 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:26,201 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:26,201 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:26,205 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:26,488 INFO L134 CoverageAnalysis]: Checked inductivity of 8035 backedges. 2532 proven. 792 refuted. 0 times theorem prover too weak. 4711 trivial. 0 not checked. [2018-12-02 04:05:26,488 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:26,737 INFO L134 CoverageAnalysis]: Checked inductivity of 8035 backedges. 2532 proven. 792 refuted. 0 times theorem prover too weak. 4711 trivial. 0 not checked. [2018-12-02 04:05:26,752 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:26,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 27, 27] total 43 [2018-12-02 04:05:26,752 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:26,752 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-12-02 04:05:26,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-12-02 04:05:26,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=331, Invalid=1475, Unknown=0, NotChecked=0, Total=1806 [2018-12-02 04:05:26,753 INFO L87 Difference]: Start difference. First operand 484 states and 492 transitions. Second operand 40 states. [2018-12-02 04:05:27,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:27,401 INFO L93 Difference]: Finished difference Result 618 states and 630 transitions. [2018-12-02 04:05:27,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-12-02 04:05:27,401 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 369 [2018-12-02 04:05:27,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:27,402 INFO L225 Difference]: With dead ends: 618 [2018-12-02 04:05:27,402 INFO L226 Difference]: Without dead ends: 618 [2018-12-02 04:05:27,403 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 782 GetRequests, 697 SyntacticMatches, 23 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1305 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=826, Invalid=3206, Unknown=0, NotChecked=0, Total=4032 [2018-12-02 04:05:27,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 618 states. [2018-12-02 04:05:27,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 618 to 604. [2018-12-02 04:05:27,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 604 states. [2018-12-02 04:05:27,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 604 states to 604 states and 616 transitions. [2018-12-02 04:05:27,410 INFO L78 Accepts]: Start accepts. Automaton has 604 states and 616 transitions. Word has length 369 [2018-12-02 04:05:27,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:27,410 INFO L480 AbstractCegarLoop]: Abstraction has 604 states and 616 transitions. [2018-12-02 04:05:27,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-12-02 04:05:27,410 INFO L276 IsEmpty]: Start isEmpty. Operand 604 states and 616 transitions. [2018-12-02 04:05:27,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 421 [2018-12-02 04:05:27,411 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:27,411 INFO L402 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 62, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:27,412 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:27,412 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:27,412 INFO L82 PathProgramCache]: Analyzing trace with hash -392113456, now seen corresponding path program 19 times [2018-12-02 04:05:27,412 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:27,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:27,412 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:27,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:27,412 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:27,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:27,679 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4226 proven. 973 refuted. 0 times theorem prover too weak. 5370 trivial. 0 not checked. [2018-12-02 04:05:27,679 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:27,679 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:27,680 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:27,680 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:27,680 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:27,680 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:27,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:27,686 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:27,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:27,753 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:28,021 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 6169 proven. 148 refuted. 0 times theorem prover too weak. 4252 trivial. 0 not checked. [2018-12-02 04:05:28,022 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:28,401 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4559 proven. 529 refuted. 0 times theorem prover too weak. 5481 trivial. 0 not checked. [2018-12-02 04:05:28,415 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:28,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 20, 20] total 54 [2018-12-02 04:05:28,416 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:28,416 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-12-02 04:05:28,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-12-02 04:05:28,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=452, Invalid=2410, Unknown=0, NotChecked=0, Total=2862 [2018-12-02 04:05:28,417 INFO L87 Difference]: Start difference. First operand 604 states and 616 transitions. Second operand 45 states. [2018-12-02 04:05:29,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:29,192 INFO L93 Difference]: Finished difference Result 499 states and 504 transitions. [2018-12-02 04:05:29,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-02 04:05:29,192 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 420 [2018-12-02 04:05:29,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:29,194 INFO L225 Difference]: With dead ends: 499 [2018-12-02 04:05:29,194 INFO L226 Difference]: Without dead ends: 490 [2018-12-02 04:05:29,195 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 903 GetRequests, 805 SyntacticMatches, 10 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2820 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1305, Invalid=6705, Unknown=0, NotChecked=0, Total=8010 [2018-12-02 04:05:29,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2018-12-02 04:05:29,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 483. [2018-12-02 04:05:29,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 483 states. [2018-12-02 04:05:29,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 483 states to 483 states and 488 transitions. [2018-12-02 04:05:29,199 INFO L78 Accepts]: Start accepts. Automaton has 483 states and 488 transitions. Word has length 420 [2018-12-02 04:05:29,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:29,199 INFO L480 AbstractCegarLoop]: Abstraction has 483 states and 488 transitions. [2018-12-02 04:05:29,200 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-12-02 04:05:29,200 INFO L276 IsEmpty]: Start isEmpty. Operand 483 states and 488 transitions. [2018-12-02 04:05:29,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 426 [2018-12-02 04:05:29,202 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:29,202 INFO L402 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 63, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:29,202 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:29,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:29,202 INFO L82 PathProgramCache]: Analyzing trace with hash 321506027, now seen corresponding path program 20 times [2018-12-02 04:05:29,203 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:29,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:29,203 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:29,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:29,203 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:29,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:29,484 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4798 proven. 678 refuted. 0 times theorem prover too weak. 5414 trivial. 0 not checked. [2018-12-02 04:05:29,484 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:29,484 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:29,485 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:29,485 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:29,485 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:29,485 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:29,492 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:29,492 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:29,578 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-12-02 04:05:29,578 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:29,582 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:29,777 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4600 proven. 678 refuted. 0 times theorem prover too weak. 5612 trivial. 0 not checked. [2018-12-02 04:05:29,777 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:30,194 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4563 proven. 715 refuted. 0 times theorem prover too weak. 5612 trivial. 0 not checked. [2018-12-02 04:05:30,209 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:30,209 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 19, 19] total 59 [2018-12-02 04:05:30,209 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:30,210 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-02 04:05:30,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-02 04:05:30,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=632, Invalid=2790, Unknown=0, NotChecked=0, Total=3422 [2018-12-02 04:05:30,210 INFO L87 Difference]: Start difference. First operand 483 states and 488 transitions. Second operand 41 states. [2018-12-02 04:05:30,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:30,808 INFO L93 Difference]: Finished difference Result 560 states and 567 transitions. [2018-12-02 04:05:30,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-12-02 04:05:30,809 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 425 [2018-12-02 04:05:30,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:30,810 INFO L225 Difference]: With dead ends: 560 [2018-12-02 04:05:30,810 INFO L226 Difference]: Without dead ends: 560 [2018-12-02 04:05:30,810 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 908 GetRequests, 819 SyntacticMatches, 1 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2210 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1979, Invalid=6031, Unknown=0, NotChecked=0, Total=8010 [2018-12-02 04:05:30,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 560 states. [2018-12-02 04:05:30,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 560 to 550. [2018-12-02 04:05:30,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2018-12-02 04:05:30,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 557 transitions. [2018-12-02 04:05:30,816 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 557 transitions. Word has length 425 [2018-12-02 04:05:30,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:30,816 INFO L480 AbstractCegarLoop]: Abstraction has 550 states and 557 transitions. [2018-12-02 04:05:30,816 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-02 04:05:30,816 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 557 transitions. [2018-12-02 04:05:30,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2018-12-02 04:05:30,819 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:30,819 INFO L402 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 64, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:30,819 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:30,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:30,819 INFO L82 PathProgramCache]: Analyzing trace with hash -867500726, now seen corresponding path program 21 times [2018-12-02 04:05:30,820 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:30,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:30,820 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:30,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:30,820 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:30,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:31,003 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2995 proven. 244 refuted. 0 times theorem prover too weak. 7977 trivial. 0 not checked. [2018-12-02 04:05:31,004 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:31,004 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:31,004 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:31,004 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:31,004 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:31,004 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:31,010 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:31,011 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:31,098 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:31,098 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:31,103 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:31,262 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2907 proven. 245 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-02 04:05:31,262 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:31,474 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2907 proven. 245 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-02 04:05:31,489 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:31,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 12, 12] total 39 [2018-12-02 04:05:31,490 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:31,490 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-02 04:05:31,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-02 04:05:31,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=269, Invalid=1291, Unknown=0, NotChecked=0, Total=1560 [2018-12-02 04:05:31,491 INFO L87 Difference]: Start difference. First operand 550 states and 557 transitions. Second operand 29 states. [2018-12-02 04:05:32,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:32,021 INFO L93 Difference]: Finished difference Result 709 states and 722 transitions. [2018-12-02 04:05:32,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-12-02 04:05:32,021 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 430 [2018-12-02 04:05:32,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:32,022 INFO L225 Difference]: With dead ends: 709 [2018-12-02 04:05:32,022 INFO L226 Difference]: Without dead ends: 709 [2018-12-02 04:05:32,022 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 891 GetRequests, 838 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 651 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=569, Invalid=2401, Unknown=0, NotChecked=0, Total=2970 [2018-12-02 04:05:32,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 709 states. [2018-12-02 04:05:32,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 709 to 680. [2018-12-02 04:05:32,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 680 states. [2018-12-02 04:05:32,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 692 transitions. [2018-12-02 04:05:32,027 INFO L78 Accepts]: Start accepts. Automaton has 680 states and 692 transitions. Word has length 430 [2018-12-02 04:05:32,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:32,027 INFO L480 AbstractCegarLoop]: Abstraction has 680 states and 692 transitions. [2018-12-02 04:05:32,027 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-02 04:05:32,027 INFO L276 IsEmpty]: Start isEmpty. Operand 680 states and 692 transitions. [2018-12-02 04:05:32,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 492 [2018-12-02 04:05:32,029 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:32,029 INFO L402 BasicCegarLoop]: trace histogram [75, 74, 74, 74, 74, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:32,029 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:32,029 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:32,029 INFO L82 PathProgramCache]: Analyzing trace with hash -666277688, now seen corresponding path program 22 times [2018-12-02 04:05:32,029 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:32,030 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:32,030 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:32,030 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:32,030 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:32,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:32,323 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 5709 proven. 1205 refuted. 0 times theorem prover too weak. 8014 trivial. 0 not checked. [2018-12-02 04:05:32,323 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:32,323 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:32,323 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:32,323 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:32,324 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:32,324 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:32,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:32,331 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:32,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:32,405 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:32,753 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 8388 proven. 189 refuted. 0 times theorem prover too weak. 6351 trivial. 0 not checked. [2018-12-02 04:05:32,753 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:33,159 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 6133 proven. 662 refuted. 0 times theorem prover too weak. 8133 trivial. 0 not checked. [2018-12-02 04:05:33,174 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:33,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 22, 22] total 59 [2018-12-02 04:05:33,174 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:33,174 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-02 04:05:33,174 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-02 04:05:33,175 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=2882, Unknown=0, NotChecked=0, Total=3422 [2018-12-02 04:05:33,175 INFO L87 Difference]: Start difference. First operand 680 states and 692 transitions. Second operand 49 states. [2018-12-02 04:05:34,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:34,012 INFO L93 Difference]: Finished difference Result 570 states and 575 transitions. [2018-12-02 04:05:34,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-12-02 04:05:34,012 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 491 [2018-12-02 04:05:34,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:34,013 INFO L225 Difference]: With dead ends: 570 [2018-12-02 04:05:34,013 INFO L226 Difference]: Without dead ends: 561 [2018-12-02 04:05:34,013 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1051 GetRequests, 943 SyntacticMatches, 11 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3485 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1570, Invalid=8132, Unknown=0, NotChecked=0, Total=9702 [2018-12-02 04:05:34,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states. [2018-12-02 04:05:34,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 554. [2018-12-02 04:05:34,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 554 states. [2018-12-02 04:05:34,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 559 transitions. [2018-12-02 04:05:34,018 INFO L78 Accepts]: Start accepts. Automaton has 554 states and 559 transitions. Word has length 491 [2018-12-02 04:05:34,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:34,018 INFO L480 AbstractCegarLoop]: Abstraction has 554 states and 559 transitions. [2018-12-02 04:05:34,018 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-02 04:05:34,018 INFO L276 IsEmpty]: Start isEmpty. Operand 554 states and 559 transitions. [2018-12-02 04:05:34,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2018-12-02 04:05:34,021 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:34,021 INFO L402 BasicCegarLoop]: trace histogram [76, 75, 75, 75, 75, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:34,021 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:34,022 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:34,022 INFO L82 PathProgramCache]: Analyzing trace with hash -1675425945, now seen corresponding path program 23 times [2018-12-02 04:05:34,022 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:34,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:34,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:34,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:34,023 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:34,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:34,351 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6418 proven. 828 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-02 04:05:34,351 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:34,352 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:34,352 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:34,352 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:34,352 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:34,352 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:34,357 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:34,358 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:34,439 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-12-02 04:05:34,439 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:34,443 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:34,685 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6173 proven. 828 refuted. 0 times theorem prover too weak. 8309 trivial. 0 not checked. [2018-12-02 04:05:34,685 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:35,162 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6132 proven. 869 refuted. 0 times theorem prover too weak. 8309 trivial. 0 not checked. [2018-12-02 04:05:35,177 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:35,177 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 20, 20] total 63 [2018-12-02 04:05:35,177 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:35,178 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-12-02 04:05:35,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-12-02 04:05:35,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=738, Invalid=3168, Unknown=0, NotChecked=0, Total=3906 [2018-12-02 04:05:35,178 INFO L87 Difference]: Start difference. First operand 554 states and 559 transitions. Second operand 44 states. [2018-12-02 04:05:35,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:35,936 INFO L93 Difference]: Finished difference Result 636 states and 643 transitions. [2018-12-02 04:05:35,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-12-02 04:05:35,936 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 496 [2018-12-02 04:05:35,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:35,937 INFO L225 Difference]: With dead ends: 636 [2018-12-02 04:05:35,937 INFO L226 Difference]: Without dead ends: 636 [2018-12-02 04:05:35,937 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1055 GetRequests, 959 SyntacticMatches, 1 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2592 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2327, Invalid=6985, Unknown=0, NotChecked=0, Total=9312 [2018-12-02 04:05:35,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states. [2018-12-02 04:05:35,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 626. [2018-12-02 04:05:35,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 626 states. [2018-12-02 04:05:35,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 633 transitions. [2018-12-02 04:05:35,941 INFO L78 Accepts]: Start accepts. Automaton has 626 states and 633 transitions. Word has length 496 [2018-12-02 04:05:35,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:35,941 INFO L480 AbstractCegarLoop]: Abstraction has 626 states and 633 transitions. [2018-12-02 04:05:35,941 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-12-02 04:05:35,942 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 633 transitions. [2018-12-02 04:05:35,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 502 [2018-12-02 04:05:35,943 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:35,943 INFO L402 BasicCegarLoop]: trace histogram [77, 76, 76, 76, 76, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:35,943 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:35,944 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:35,944 INFO L82 PathProgramCache]: Analyzing trace with hash -422752958, now seen corresponding path program 24 times [2018-12-02 04:05:35,944 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:35,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:35,944 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:35,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:35,944 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:35,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:36,124 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3876 proven. 301 refuted. 0 times theorem prover too weak. 11520 trivial. 0 not checked. [2018-12-02 04:05:36,124 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:36,124 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:36,124 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:36,124 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:36,124 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:36,124 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:36,130 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:36,130 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:36,279 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:36,279 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:36,284 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:36,464 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3825 proven. 297 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2018-12-02 04:05:36,464 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:36,707 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3825 proven. 297 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2018-12-02 04:05:36,722 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:36,722 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13, 13] total 41 [2018-12-02 04:05:36,722 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:36,723 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-02 04:05:36,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-02 04:05:36,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=1416, Unknown=0, NotChecked=0, Total=1722 [2018-12-02 04:05:36,723 INFO L87 Difference]: Start difference. First operand 626 states and 633 transitions. Second operand 30 states. [2018-12-02 04:05:37,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:37,404 INFO L93 Difference]: Finished difference Result 795 states and 808 transitions. [2018-12-02 04:05:37,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-12-02 04:05:37,404 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 501 [2018-12-02 04:05:37,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:37,405 INFO L225 Difference]: With dead ends: 795 [2018-12-02 04:05:37,405 INFO L226 Difference]: Without dead ends: 795 [2018-12-02 04:05:37,405 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1034 GetRequests, 978 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 745 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=632, Invalid=2674, Unknown=0, NotChecked=0, Total=3306 [2018-12-02 04:05:37,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 795 states. [2018-12-02 04:05:37,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 795 to 766. [2018-12-02 04:05:37,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2018-12-02 04:05:37,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 778 transitions. [2018-12-02 04:05:37,412 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 778 transitions. Word has length 501 [2018-12-02 04:05:37,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:37,413 INFO L480 AbstractCegarLoop]: Abstraction has 766 states and 778 transitions. [2018-12-02 04:05:37,413 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-02 04:05:37,413 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 778 transitions. [2018-12-02 04:05:37,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 568 [2018-12-02 04:05:37,416 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:37,416 INFO L402 BasicCegarLoop]: trace histogram [88, 87, 87, 87, 87, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:37,416 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:37,416 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:37,416 INFO L82 PathProgramCache]: Analyzing trace with hash -1064351445, now seen corresponding path program 25 times [2018-12-02 04:05:37,416 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:37,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:37,417 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:37,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:37,417 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:37,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:37,798 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 7504 proven. 1462 refuted. 0 times theorem prover too weak. 11519 trivial. 0 not checked. [2018-12-02 04:05:37,798 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:37,798 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:37,798 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:37,798 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:37,798 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:37,798 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:37,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:37,804 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:37,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:37,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:38,272 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 11078 proven. 235 refuted. 0 times theorem prover too weak. 9172 trivial. 0 not checked. [2018-12-02 04:05:38,272 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:38,806 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 8030 proven. 810 refuted. 0 times theorem prover too weak. 11645 trivial. 0 not checked. [2018-12-02 04:05:38,821 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:38,821 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 24, 24] total 64 [2018-12-02 04:05:38,821 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:38,822 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-12-02 04:05:38,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-12-02 04:05:38,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=636, Invalid=3396, Unknown=0, NotChecked=0, Total=4032 [2018-12-02 04:05:38,823 INFO L87 Difference]: Start difference. First operand 766 states and 778 transitions. Second operand 53 states. [2018-12-02 04:05:40,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:40,018 INFO L93 Difference]: Finished difference Result 646 states and 651 transitions. [2018-12-02 04:05:40,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-12-02 04:05:40,019 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 567 [2018-12-02 04:05:40,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:40,021 INFO L225 Difference]: With dead ends: 646 [2018-12-02 04:05:40,021 INFO L226 Difference]: Without dead ends: 637 [2018-12-02 04:05:40,022 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1209 GetRequests, 1091 SyntacticMatches, 12 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4220 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1860, Invalid=9696, Unknown=0, NotChecked=0, Total=11556 [2018-12-02 04:05:40,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 637 states. [2018-12-02 04:05:40,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 637 to 630. [2018-12-02 04:05:40,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 630 states. [2018-12-02 04:05:40,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 630 states to 630 states and 635 transitions. [2018-12-02 04:05:40,034 INFO L78 Accepts]: Start accepts. Automaton has 630 states and 635 transitions. Word has length 567 [2018-12-02 04:05:40,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:40,035 INFO L480 AbstractCegarLoop]: Abstraction has 630 states and 635 transitions. [2018-12-02 04:05:40,035 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-12-02 04:05:40,035 INFO L276 IsEmpty]: Start isEmpty. Operand 630 states and 635 transitions. [2018-12-02 04:05:40,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 573 [2018-12-02 04:05:40,041 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:40,042 INFO L402 BasicCegarLoop]: trace histogram [89, 88, 88, 88, 88, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:40,042 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:40,042 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:40,043 INFO L82 PathProgramCache]: Analyzing trace with hash -347201808, now seen corresponding path program 26 times [2018-12-02 04:05:40,043 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:40,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:40,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:40,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:40,044 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:40,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:40,427 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8365 proven. 993 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2018-12-02 04:05:40,427 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:40,427 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:40,427 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:40,427 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:40,427 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:40,427 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:40,434 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:40,434 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:40,531 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-12-02 04:05:40,531 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:40,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:40,837 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8068 proven. 993 refuted. 0 times theorem prover too weak. 11872 trivial. 0 not checked. [2018-12-02 04:05:40,837 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:41,396 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8023 proven. 1038 refuted. 0 times theorem prover too weak. 11872 trivial. 0 not checked. [2018-12-02 04:05:41,411 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:41,411 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 21, 21] total 67 [2018-12-02 04:05:41,411 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:41,411 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-12-02 04:05:41,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-12-02 04:05:41,412 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=853, Invalid=3569, Unknown=0, NotChecked=0, Total=4422 [2018-12-02 04:05:41,412 INFO L87 Difference]: Start difference. First operand 630 states and 635 transitions. Second operand 47 states. [2018-12-02 04:05:42,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:42,206 INFO L93 Difference]: Finished difference Result 717 states and 724 transitions. [2018-12-02 04:05:42,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-12-02 04:05:42,207 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 572 [2018-12-02 04:05:42,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:42,208 INFO L225 Difference]: With dead ends: 717 [2018-12-02 04:05:42,208 INFO L226 Difference]: Without dead ends: 717 [2018-12-02 04:05:42,208 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1212 GetRequests, 1109 SyntacticMatches, 1 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3004 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2704, Invalid=8008, Unknown=0, NotChecked=0, Total=10712 [2018-12-02 04:05:42,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 717 states. [2018-12-02 04:05:42,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 717 to 707. [2018-12-02 04:05:42,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 707 states. [2018-12-02 04:05:42,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 707 states to 707 states and 714 transitions. [2018-12-02 04:05:42,212 INFO L78 Accepts]: Start accepts. Automaton has 707 states and 714 transitions. Word has length 572 [2018-12-02 04:05:42,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:42,212 INFO L480 AbstractCegarLoop]: Abstraction has 707 states and 714 transitions. [2018-12-02 04:05:42,212 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-12-02 04:05:42,212 INFO L276 IsEmpty]: Start isEmpty. Operand 707 states and 714 transitions. [2018-12-02 04:05:42,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 578 [2018-12-02 04:05:42,214 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:42,214 INFO L402 BasicCegarLoop]: trace histogram [90, 89, 89, 89, 89, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:42,214 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:42,215 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:42,215 INFO L82 PathProgramCache]: Analyzing trace with hash 35953893, now seen corresponding path program 27 times [2018-12-02 04:05:42,215 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:42,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:42,215 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:42,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:42,215 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:42,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:42,451 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 5114 proven. 364 refuted. 0 times theorem prover too weak. 15908 trivial. 0 not checked. [2018-12-02 04:05:42,451 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:42,451 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:42,451 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:42,452 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:42,452 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:42,452 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:42,458 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:42,458 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:42,580 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:42,580 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:42,585 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:42,797 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 4917 proven. 354 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-02 04:05:42,797 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:43,109 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 4917 proven. 354 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-02 04:05:43,124 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:43,125 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 14, 14] total 47 [2018-12-02 04:05:43,125 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:43,125 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-02 04:05:43,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-02 04:05:43,125 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=1891, Unknown=0, NotChecked=0, Total=2256 [2018-12-02 04:05:43,125 INFO L87 Difference]: Start difference. First operand 707 states and 714 transitions. Second operand 35 states. [2018-12-02 04:05:43,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:43,783 INFO L93 Difference]: Finished difference Result 886 states and 899 transitions. [2018-12-02 04:05:43,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-12-02 04:05:43,783 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 577 [2018-12-02 04:05:43,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:43,784 INFO L225 Difference]: With dead ends: 886 [2018-12-02 04:05:43,784 INFO L226 Difference]: Without dead ends: 886 [2018-12-02 04:05:43,785 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1191 GetRequests, 1128 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 929 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=762, Invalid=3398, Unknown=0, NotChecked=0, Total=4160 [2018-12-02 04:05:43,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states. [2018-12-02 04:05:43,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 857. [2018-12-02 04:05:43,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 857 states. [2018-12-02 04:05:43,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 857 states to 857 states and 869 transitions. [2018-12-02 04:05:43,790 INFO L78 Accepts]: Start accepts. Automaton has 857 states and 869 transitions. Word has length 577 [2018-12-02 04:05:43,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:43,790 INFO L480 AbstractCegarLoop]: Abstraction has 857 states and 869 transitions. [2018-12-02 04:05:43,790 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-02 04:05:43,791 INFO L276 IsEmpty]: Start isEmpty. Operand 857 states and 869 transitions. [2018-12-02 04:05:43,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 649 [2018-12-02 04:05:43,793 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:43,793 INFO L402 BasicCegarLoop]: trace histogram [102, 101, 101, 101, 101, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:43,793 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:43,793 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:43,793 INFO L82 PathProgramCache]: Analyzing trace with hash 687118509, now seen corresponding path program 28 times [2018-12-02 04:05:43,793 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:43,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:43,794 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:43,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:43,794 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:43,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:44,201 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 9641 proven. 1744 refuted. 0 times theorem prover too weak. 16053 trivial. 0 not checked. [2018-12-02 04:05:44,202 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:44,202 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:44,202 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:44,202 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:44,202 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:44,202 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:44,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:44,215 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:44,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:44,309 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:44,755 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 14284 proven. 286 refuted. 0 times theorem prover too weak. 12868 trivial. 0 not checked. [2018-12-02 04:05:44,755 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:45,342 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 10280 proven. 973 refuted. 0 times theorem prover too weak. 16185 trivial. 0 not checked. [2018-12-02 04:05:45,357 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:45,357 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 26, 26] total 69 [2018-12-02 04:05:45,357 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:45,358 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-12-02 04:05:45,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-12-02 04:05:45,358 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=740, Invalid=3952, Unknown=0, NotChecked=0, Total=4692 [2018-12-02 04:05:45,358 INFO L87 Difference]: Start difference. First operand 857 states and 869 transitions. Second operand 57 states. [2018-12-02 04:05:46,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:46,430 INFO L93 Difference]: Finished difference Result 727 states and 732 transitions. [2018-12-02 04:05:46,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-12-02 04:05:46,430 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 648 [2018-12-02 04:05:46,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:46,431 INFO L225 Difference]: With dead ends: 727 [2018-12-02 04:05:46,431 INFO L226 Difference]: Without dead ends: 718 [2018-12-02 04:05:46,432 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1377 GetRequests, 1249 SyntacticMatches, 13 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5025 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=2175, Invalid=11397, Unknown=0, NotChecked=0, Total=13572 [2018-12-02 04:05:46,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states. [2018-12-02 04:05:46,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 711. [2018-12-02 04:05:46,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 711 states. [2018-12-02 04:05:46,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 716 transitions. [2018-12-02 04:05:46,436 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 716 transitions. Word has length 648 [2018-12-02 04:05:46,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:46,436 INFO L480 AbstractCegarLoop]: Abstraction has 711 states and 716 transitions. [2018-12-02 04:05:46,436 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-12-02 04:05:46,436 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 716 transitions. [2018-12-02 04:05:46,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 654 [2018-12-02 04:05:46,438 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:46,438 INFO L402 BasicCegarLoop]: trace histogram [103, 102, 102, 102, 102, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:46,439 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:46,439 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:46,439 INFO L82 PathProgramCache]: Analyzing trace with hash -1741773022, now seen corresponding path program 29 times [2018-12-02 04:05:46,439 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:46,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:46,439 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:46,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:46,439 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:46,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:46,863 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10669 proven. 1173 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-02 04:05:46,863 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:46,863 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:46,863 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:46,863 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:46,863 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:46,863 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:46,869 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:46,869 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:46,985 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-12-02 04:05:46,985 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:46,989 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:47,349 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10315 proven. 1173 refuted. 0 times theorem prover too weak. 16469 trivial. 0 not checked. [2018-12-02 04:05:47,349 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:47,981 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10266 proven. 1222 refuted. 0 times theorem prover too weak. 16469 trivial. 0 not checked. [2018-12-02 04:05:47,996 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:47,996 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 22, 22] total 71 [2018-12-02 04:05:47,997 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:47,997 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-02 04:05:47,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-02 04:05:47,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=977, Invalid=3993, Unknown=0, NotChecked=0, Total=4970 [2018-12-02 04:05:47,997 INFO L87 Difference]: Start difference. First operand 711 states and 716 transitions. Second operand 50 states. [2018-12-02 04:05:48,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:48,885 INFO L93 Difference]: Finished difference Result 803 states and 810 transitions. [2018-12-02 04:05:48,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-02 04:05:48,885 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 653 [2018-12-02 04:05:48,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:48,887 INFO L225 Difference]: With dead ends: 803 [2018-12-02 04:05:48,887 INFO L226 Difference]: Without dead ends: 803 [2018-12-02 04:05:48,887 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1379 GetRequests, 1269 SyntacticMatches, 1 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3446 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3110, Invalid=9100, Unknown=0, NotChecked=0, Total=12210 [2018-12-02 04:05:48,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 803 states. [2018-12-02 04:05:48,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 803 to 793. [2018-12-02 04:05:48,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 793 states. [2018-12-02 04:05:48,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 793 states to 793 states and 800 transitions. [2018-12-02 04:05:48,892 INFO L78 Accepts]: Start accepts. Automaton has 793 states and 800 transitions. Word has length 653 [2018-12-02 04:05:48,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:48,892 INFO L480 AbstractCegarLoop]: Abstraction has 793 states and 800 transitions. [2018-12-02 04:05:48,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-02 04:05:48,892 INFO L276 IsEmpty]: Start isEmpty. Operand 793 states and 800 transitions. [2018-12-02 04:05:48,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 659 [2018-12-02 04:05:48,894 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:48,895 INFO L402 BasicCegarLoop]: trace histogram [104, 103, 103, 103, 103, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:48,895 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:48,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:48,895 INFO L82 PathProgramCache]: Analyzing trace with hash 1104503271, now seen corresponding path program 30 times [2018-12-02 04:05:48,895 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:48,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:48,895 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:48,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:48,895 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:48,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:49,148 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6259 proven. 433 refuted. 0 times theorem prover too weak. 21789 trivial. 0 not checked. [2018-12-02 04:05:49,149 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:49,149 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:49,149 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:49,149 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:49,149 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:49,149 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:49,155 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:49,155 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:49,300 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:49,300 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:49,306 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:49,550 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6198 proven. 416 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-02 04:05:49,550 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:49,878 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6198 proven. 416 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-02 04:05:49,894 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:49,894 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15, 15] total 47 [2018-12-02 04:05:49,894 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:49,895 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-12-02 04:05:49,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-12-02 04:05:49,895 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1859, Unknown=0, NotChecked=0, Total=2256 [2018-12-02 04:05:49,895 INFO L87 Difference]: Start difference. First operand 793 states and 800 transitions. Second operand 34 states. [2018-12-02 04:05:50,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:50,799 INFO L93 Difference]: Finished difference Result 982 states and 995 transitions. [2018-12-02 04:05:50,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-02 04:05:50,800 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 658 [2018-12-02 04:05:50,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:50,801 INFO L225 Difference]: With dead ends: 982 [2018-12-02 04:05:50,801 INFO L226 Difference]: Without dead ends: 982 [2018-12-02 04:05:50,801 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1352 GetRequests, 1288 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 996 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=801, Invalid=3489, Unknown=0, NotChecked=0, Total=4290 [2018-12-02 04:05:50,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982 states. [2018-12-02 04:05:50,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982 to 953. [2018-12-02 04:05:50,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 953 states. [2018-12-02 04:05:50,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 953 states to 953 states and 965 transitions. [2018-12-02 04:05:50,808 INFO L78 Accepts]: Start accepts. Automaton has 953 states and 965 transitions. Word has length 658 [2018-12-02 04:05:50,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:50,809 INFO L480 AbstractCegarLoop]: Abstraction has 953 states and 965 transitions. [2018-12-02 04:05:50,809 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-12-02 04:05:50,809 INFO L276 IsEmpty]: Start isEmpty. Operand 953 states and 965 transitions. [2018-12-02 04:05:50,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 735 [2018-12-02 04:05:50,812 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:50,812 INFO L402 BasicCegarLoop]: trace histogram [117, 116, 116, 116, 116, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:50,812 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:50,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:50,812 INFO L82 PathProgramCache]: Analyzing trace with hash -402943376, now seen corresponding path program 31 times [2018-12-02 04:05:50,812 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:50,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:50,813 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:50,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:50,813 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:50,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:51,297 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 12150 proven. 2051 refuted. 0 times theorem prover too weak. 21799 trivial. 0 not checked. [2018-12-02 04:05:51,297 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:51,297 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:51,298 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:51,298 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:51,298 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:51,298 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:51,306 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:51,306 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:51,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:51,412 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:51,943 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 18051 proven. 342 refuted. 0 times theorem prover too weak. 17607 trivial. 0 not checked. [2018-12-02 04:05:51,943 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:52,584 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 12913 proven. 1151 refuted. 0 times theorem prover too weak. 21936 trivial. 0 not checked. [2018-12-02 04:05:52,599 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:52,600 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 28, 28] total 74 [2018-12-02 04:05:52,600 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:52,601 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-12-02 04:05:52,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-12-02 04:05:52,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=852, Invalid=4550, Unknown=0, NotChecked=0, Total=5402 [2018-12-02 04:05:52,601 INFO L87 Difference]: Start difference. First operand 953 states and 965 transitions. Second operand 61 states. [2018-12-02 04:05:53,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:53,866 INFO L93 Difference]: Finished difference Result 813 states and 818 transitions. [2018-12-02 04:05:53,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-12-02 04:05:53,866 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 734 [2018-12-02 04:05:53,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:53,867 INFO L225 Difference]: With dead ends: 813 [2018-12-02 04:05:53,867 INFO L226 Difference]: Without dead ends: 804 [2018-12-02 04:05:53,868 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1555 GetRequests, 1417 SyntacticMatches, 14 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5900 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2515, Invalid=13235, Unknown=0, NotChecked=0, Total=15750 [2018-12-02 04:05:53,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 804 states. [2018-12-02 04:05:53,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 804 to 797. [2018-12-02 04:05:53,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 797 states. [2018-12-02 04:05:53,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 802 transitions. [2018-12-02 04:05:53,872 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 802 transitions. Word has length 734 [2018-12-02 04:05:53,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:53,872 INFO L480 AbstractCegarLoop]: Abstraction has 797 states and 802 transitions. [2018-12-02 04:05:53,872 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-12-02 04:05:53,873 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 802 transitions. [2018-12-02 04:05:53,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 740 [2018-12-02 04:05:53,875 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:53,875 INFO L402 BasicCegarLoop]: trace histogram [118, 117, 117, 117, 117, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:53,875 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:53,875 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:53,876 INFO L82 PathProgramCache]: Analyzing trace with hash 79086155, now seen corresponding path program 32 times [2018-12-02 04:05:53,876 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:53,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:53,876 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:53,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:53,876 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:53,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:54,351 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 13360 proven. 1368 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-02 04:05:54,351 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:54,351 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:54,352 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:54,352 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:54,352 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:54,352 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:54,357 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:05:54,357 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:05:54,489 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-12-02 04:05:54,489 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:54,493 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:54,890 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 12944 proven. 1368 refuted. 0 times theorem prover too weak. 22283 trivial. 0 not checked. [2018-12-02 04:05:54,890 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:55,596 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 12891 proven. 1421 refuted. 0 times theorem prover too weak. 22283 trivial. 0 not checked. [2018-12-02 04:05:55,611 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:55,611 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 23, 23] total 75 [2018-12-02 04:05:55,611 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:55,611 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-12-02 04:05:55,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-12-02 04:05:55,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1110, Invalid=4440, Unknown=0, NotChecked=0, Total=5550 [2018-12-02 04:05:55,612 INFO L87 Difference]: Start difference. First operand 797 states and 802 transitions. Second operand 53 states. [2018-12-02 04:05:56,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:56,522 INFO L93 Difference]: Finished difference Result 894 states and 901 transitions. [2018-12-02 04:05:56,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-02 04:05:56,523 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 739 [2018-12-02 04:05:56,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:56,524 INFO L225 Difference]: With dead ends: 894 [2018-12-02 04:05:56,524 INFO L226 Difference]: Without dead ends: 894 [2018-12-02 04:05:56,525 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1556 GetRequests, 1439 SyntacticMatches, 1 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3918 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3545, Invalid=10261, Unknown=0, NotChecked=0, Total=13806 [2018-12-02 04:05:56,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 894 states. [2018-12-02 04:05:56,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 894 to 884. [2018-12-02 04:05:56,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 884 states. [2018-12-02 04:05:56,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 884 states to 884 states and 891 transitions. [2018-12-02 04:05:56,530 INFO L78 Accepts]: Start accepts. Automaton has 884 states and 891 transitions. Word has length 739 [2018-12-02 04:05:56,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:56,530 INFO L480 AbstractCegarLoop]: Abstraction has 884 states and 891 transitions. [2018-12-02 04:05:56,530 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-12-02 04:05:56,530 INFO L276 IsEmpty]: Start isEmpty. Operand 884 states and 891 transitions. [2018-12-02 04:05:56,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 745 [2018-12-02 04:05:56,532 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:56,533 INFO L402 BasicCegarLoop]: trace histogram [119, 118, 118, 118, 118, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:56,533 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:56,533 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:56,533 INFO L82 PathProgramCache]: Analyzing trace with hash 1460105962, now seen corresponding path program 33 times [2018-12-02 04:05:56,533 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:56,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:56,533 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:56,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:56,533 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:56,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:56,852 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7811 proven. 508 refuted. 0 times theorem prover too weak. 28876 trivial. 0 not checked. [2018-12-02 04:05:56,852 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:56,852 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:56,852 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:56,853 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:56,853 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:56,853 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:56,858 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:05:56,859 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:05:57,021 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:05:57,021 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:05:57,028 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:57,315 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7683 proven. 483 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2018-12-02 04:05:57,316 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:05:57,718 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7683 proven. 483 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2018-12-02 04:05:57,734 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:05:57,735 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 16, 16] total 51 [2018-12-02 04:05:57,735 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:05:57,735 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-02 04:05:57,735 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-02 04:05:57,735 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=451, Invalid=2201, Unknown=0, NotChecked=0, Total=2652 [2018-12-02 04:05:57,736 INFO L87 Difference]: Start difference. First operand 884 states and 891 transitions. Second operand 37 states. [2018-12-02 04:05:58,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:05:58,643 INFO L93 Difference]: Finished difference Result 1083 states and 1096 transitions. [2018-12-02 04:05:58,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-02 04:05:58,643 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 744 [2018-12-02 04:05:58,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:05:58,645 INFO L225 Difference]: With dead ends: 1083 [2018-12-02 04:05:58,645 INFO L226 Difference]: Without dead ends: 1083 [2018-12-02 04:05:58,645 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1527 GetRequests, 1458 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1161 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=911, Invalid=4059, Unknown=0, NotChecked=0, Total=4970 [2018-12-02 04:05:58,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1083 states. [2018-12-02 04:05:58,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1083 to 1054. [2018-12-02 04:05:58,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1054 states. [2018-12-02 04:05:58,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1054 states to 1054 states and 1066 transitions. [2018-12-02 04:05:58,652 INFO L78 Accepts]: Start accepts. Automaton has 1054 states and 1066 transitions. Word has length 744 [2018-12-02 04:05:58,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:05:58,652 INFO L480 AbstractCegarLoop]: Abstraction has 1054 states and 1066 transitions. [2018-12-02 04:05:58,652 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-02 04:05:58,652 INFO L276 IsEmpty]: Start isEmpty. Operand 1054 states and 1066 transitions. [2018-12-02 04:05:58,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 826 [2018-12-02 04:05:58,655 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:05:58,655 INFO L402 BasicCegarLoop]: trace histogram [133, 132, 132, 132, 132, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:05:58,656 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:05:58,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:05:58,656 INFO L82 PathProgramCache]: Analyzing trace with hash 1258137320, now seen corresponding path program 34 times [2018-12-02 04:05:58,656 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:05:58,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:58,656 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:05:58,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:05:58,656 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:05:58,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:59,231 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 15061 proven. 2383 refuted. 0 times theorem prover too weak. 28955 trivial. 0 not checked. [2018-12-02 04:05:59,231 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:59,231 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:05:59,231 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:05:59,231 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:05:59,231 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:05:59,231 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:05:59,237 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:05:59,237 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:05:59,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:05:59,358 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:05:59,957 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 22424 proven. 403 refuted. 0 times theorem prover too weak. 23572 trivial. 0 not checked. [2018-12-02 04:05:59,957 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:00,745 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 15959 proven. 1344 refuted. 0 times theorem prover too weak. 29096 trivial. 0 not checked. [2018-12-02 04:06:00,760 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:00,760 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 30, 30] total 79 [2018-12-02 04:06:00,760 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:00,761 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-02 04:06:00,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-02 04:06:00,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=972, Invalid=5190, Unknown=0, NotChecked=0, Total=6162 [2018-12-02 04:06:00,761 INFO L87 Difference]: Start difference. First operand 1054 states and 1066 transitions. Second operand 65 states. [2018-12-02 04:06:02,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:02,890 INFO L93 Difference]: Finished difference Result 904 states and 909 transitions. [2018-12-02 04:06:02,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-12-02 04:06:02,891 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 825 [2018-12-02 04:06:02,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:02,892 INFO L225 Difference]: With dead ends: 904 [2018-12-02 04:06:02,893 INFO L226 Difference]: Without dead ends: 895 [2018-12-02 04:06:02,894 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1743 GetRequests, 1595 SyntacticMatches, 15 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6845 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2880, Invalid=15210, Unknown=0, NotChecked=0, Total=18090 [2018-12-02 04:06:02,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 895 states. [2018-12-02 04:06:02,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 895 to 888. [2018-12-02 04:06:02,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 888 states. [2018-12-02 04:06:02,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 888 states to 888 states and 893 transitions. [2018-12-02 04:06:02,900 INFO L78 Accepts]: Start accepts. Automaton has 888 states and 893 transitions. Word has length 825 [2018-12-02 04:06:02,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:02,900 INFO L480 AbstractCegarLoop]: Abstraction has 888 states and 893 transitions. [2018-12-02 04:06:02,900 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-02 04:06:02,900 INFO L276 IsEmpty]: Start isEmpty. Operand 888 states and 893 transitions. [2018-12-02 04:06:02,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 831 [2018-12-02 04:06:02,904 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:02,904 INFO L402 BasicCegarLoop]: trace histogram [134, 133, 133, 133, 133, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:02,904 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:02,905 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:02,905 INFO L82 PathProgramCache]: Analyzing trace with hash 51252807, now seen corresponding path program 35 times [2018-12-02 04:06:02,905 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:02,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:02,905 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:02,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:02,905 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:02,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:03,492 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 16468 proven. 1578 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2018-12-02 04:06:03,493 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:03,493 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:03,493 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:03,493 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:03,493 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:03,493 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:03,501 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:06:03,501 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:06:03,664 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-12-02 04:06:03,664 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:03,669 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:04,143 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 15985 proven. 1578 refuted. 0 times theorem prover too weak. 29512 trivial. 0 not checked. [2018-12-02 04:06:04,143 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:04,952 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 15928 proven. 1635 refuted. 0 times theorem prover too weak. 29512 trivial. 0 not checked. [2018-12-02 04:06:04,967 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:04,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 24, 24] total 79 [2018-12-02 04:06:04,967 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:04,967 INFO L459 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-12-02 04:06:04,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-12-02 04:06:04,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1252, Invalid=4910, Unknown=0, NotChecked=0, Total=6162 [2018-12-02 04:06:04,968 INFO L87 Difference]: Start difference. First operand 888 states and 893 transitions. Second operand 56 states. [2018-12-02 04:06:05,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:05,995 INFO L93 Difference]: Finished difference Result 990 states and 997 transitions. [2018-12-02 04:06:05,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-12-02 04:06:05,996 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 830 [2018-12-02 04:06:05,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:05,997 INFO L225 Difference]: With dead ends: 990 [2018-12-02 04:06:05,997 INFO L226 Difference]: Without dead ends: 990 [2018-12-02 04:06:05,998 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1743 GetRequests, 1619 SyntacticMatches, 1 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4420 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=4009, Invalid=11491, Unknown=0, NotChecked=0, Total=15500 [2018-12-02 04:06:05,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 990 states. [2018-12-02 04:06:06,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 990 to 980. [2018-12-02 04:06:06,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 980 states. [2018-12-02 04:06:06,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 980 states to 980 states and 987 transitions. [2018-12-02 04:06:06,004 INFO L78 Accepts]: Start accepts. Automaton has 980 states and 987 transitions. Word has length 830 [2018-12-02 04:06:06,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:06,005 INFO L480 AbstractCegarLoop]: Abstraction has 980 states and 987 transitions. [2018-12-02 04:06:06,005 INFO L481 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-12-02 04:06:06,005 INFO L276 IsEmpty]: Start isEmpty. Operand 980 states and 987 transitions. [2018-12-02 04:06:06,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 836 [2018-12-02 04:06:06,009 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:06,009 INFO L402 BasicCegarLoop]: trace histogram [135, 134, 134, 134, 134, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:06,009 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:06,009 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:06,009 INFO L82 PathProgramCache]: Analyzing trace with hash 1746428258, now seen corresponding path program 36 times [2018-12-02 04:06:06,009 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:06,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:06,010 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:06,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:06,010 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:06,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:06,375 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9458 proven. 589 refuted. 0 times theorem prover too weak. 37709 trivial. 0 not checked. [2018-12-02 04:06:06,375 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:06,375 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:06,375 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:06,375 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:06,375 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:06,375 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:06,382 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:06:06,382 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:06:06,755 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:06:06,755 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:06,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:07,111 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9387 proven. 555 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-02 04:06:07,111 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:07,533 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9387 proven. 555 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-02 04:06:07,549 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:07,550 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 17, 17] total 53 [2018-12-02 04:06:07,550 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:07,550 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-02 04:06:07,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-02 04:06:07,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=500, Invalid=2362, Unknown=0, NotChecked=0, Total=2862 [2018-12-02 04:06:07,551 INFO L87 Difference]: Start difference. First operand 980 states and 987 transitions. Second operand 38 states. [2018-12-02 04:06:08,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:08,621 INFO L93 Difference]: Finished difference Result 1189 states and 1202 transitions. [2018-12-02 04:06:08,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-12-02 04:06:08,621 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 835 [2018-12-02 04:06:08,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:08,623 INFO L225 Difference]: With dead ends: 1189 [2018-12-02 04:06:08,623 INFO L226 Difference]: Without dead ends: 1189 [2018-12-02 04:06:08,623 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1710 GetRequests, 1638 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1283 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=990, Invalid=4412, Unknown=0, NotChecked=0, Total=5402 [2018-12-02 04:06:08,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1189 states. [2018-12-02 04:06:08,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1189 to 1160. [2018-12-02 04:06:08,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1160 states. [2018-12-02 04:06:08,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1160 states to 1160 states and 1172 transitions. [2018-12-02 04:06:08,630 INFO L78 Accepts]: Start accepts. Automaton has 1160 states and 1172 transitions. Word has length 835 [2018-12-02 04:06:08,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:08,631 INFO L480 AbstractCegarLoop]: Abstraction has 1160 states and 1172 transitions. [2018-12-02 04:06:08,631 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-02 04:06:08,631 INFO L276 IsEmpty]: Start isEmpty. Operand 1160 states and 1172 transitions. [2018-12-02 04:06:08,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 922 [2018-12-02 04:06:08,635 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:08,635 INFO L402 BasicCegarLoop]: trace histogram [150, 149, 149, 149, 149, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:08,636 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:08,636 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:08,636 INFO L82 PathProgramCache]: Analyzing trace with hash 1328608651, now seen corresponding path program 37 times [2018-12-02 04:06:08,636 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:08,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:08,636 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:08,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:08,636 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:08,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:09,291 INFO L134 CoverageAnalysis]: Checked inductivity of 58878 backedges. 18404 proven. 2740 refuted. 0 times theorem prover too weak. 37734 trivial. 0 not checked. [2018-12-02 04:06:09,291 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:09,291 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:09,292 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:09,292 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:09,292 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:09,292 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:09,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:09,299 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:06:09,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:09,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:10,166 INFO L134 CoverageAnalysis]: Checked inductivity of 58878 backedges. 27448 proven. 469 refuted. 0 times theorem prover too weak. 30961 trivial. 0 not checked. [2018-12-02 04:06:10,166 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:11,041 INFO L134 CoverageAnalysis]: Checked inductivity of 58878 backedges. 19448 proven. 1552 refuted. 0 times theorem prover too weak. 37878 trivial. 0 not checked. [2018-12-02 04:06:11,057 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:11,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 32, 32] total 84 [2018-12-02 04:06:11,057 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:11,057 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-02 04:06:11,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-02 04:06:11,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1100, Invalid=5872, Unknown=0, NotChecked=0, Total=6972 [2018-12-02 04:06:11,058 INFO L87 Difference]: Start difference. First operand 1160 states and 1172 transitions. Second operand 69 states. [2018-12-02 04:06:12,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:12,473 INFO L93 Difference]: Finished difference Result 1000 states and 1005 transitions. [2018-12-02 04:06:12,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-12-02 04:06:12,473 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 921 [2018-12-02 04:06:12,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:12,475 INFO L225 Difference]: With dead ends: 1000 [2018-12-02 04:06:12,475 INFO L226 Difference]: Without dead ends: 991 [2018-12-02 04:06:12,476 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1941 GetRequests, 1783 SyntacticMatches, 16 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7860 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3270, Invalid=17322, Unknown=0, NotChecked=0, Total=20592 [2018-12-02 04:06:12,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states. [2018-12-02 04:06:12,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 984. [2018-12-02 04:06:12,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 984 states. [2018-12-02 04:06:12,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 984 states to 984 states and 989 transitions. [2018-12-02 04:06:12,481 INFO L78 Accepts]: Start accepts. Automaton has 984 states and 989 transitions. Word has length 921 [2018-12-02 04:06:12,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:12,481 INFO L480 AbstractCegarLoop]: Abstraction has 984 states and 989 transitions. [2018-12-02 04:06:12,482 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-02 04:06:12,482 INFO L276 IsEmpty]: Start isEmpty. Operand 984 states and 989 transitions. [2018-12-02 04:06:12,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 927 [2018-12-02 04:06:12,485 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:12,485 INFO L402 BasicCegarLoop]: trace histogram [151, 150, 150, 150, 150, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:12,486 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:12,486 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:12,486 INFO L82 PathProgramCache]: Analyzing trace with hash -848043632, now seen corresponding path program 38 times [2018-12-02 04:06:12,486 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:12,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:12,486 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:12,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:12,487 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:12,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:13,138 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 20023 proven. 1803 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-02 04:06:13,138 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:13,139 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:13,139 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:13,139 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:13,139 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:13,139 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:13,154 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:06:13,154 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:06:13,346 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-12-02 04:06:13,346 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:13,351 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:13,860 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 19468 proven. 1803 refuted. 0 times theorem prover too weak. 38369 trivial. 0 not checked. [2018-12-02 04:06:13,860 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:14,754 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 19407 proven. 1864 refuted. 0 times theorem prover too weak. 38369 trivial. 0 not checked. [2018-12-02 04:06:14,769 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:14,770 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 25, 25] total 83 [2018-12-02 04:06:14,770 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:14,770 INFO L459 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-12-02 04:06:14,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-12-02 04:06:14,771 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1403, Invalid=5403, Unknown=0, NotChecked=0, Total=6806 [2018-12-02 04:06:14,771 INFO L87 Difference]: Start difference. First operand 984 states and 989 transitions. Second operand 59 states. [2018-12-02 04:06:15,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:15,897 INFO L93 Difference]: Finished difference Result 1091 states and 1098 transitions. [2018-12-02 04:06:15,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-12-02 04:06:15,898 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 926 [2018-12-02 04:06:15,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:15,899 INFO L225 Difference]: With dead ends: 1091 [2018-12-02 04:06:15,899 INFO L226 Difference]: Without dead ends: 1091 [2018-12-02 04:06:15,900 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1940 GetRequests, 1809 SyntacticMatches, 1 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4952 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=4502, Invalid=12790, Unknown=0, NotChecked=0, Total=17292 [2018-12-02 04:06:15,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1091 states. [2018-12-02 04:06:15,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1091 to 1081. [2018-12-02 04:06:15,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1081 states. [2018-12-02 04:06:15,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1081 states to 1081 states and 1088 transitions. [2018-12-02 04:06:15,906 INFO L78 Accepts]: Start accepts. Automaton has 1081 states and 1088 transitions. Word has length 926 [2018-12-02 04:06:15,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:15,906 INFO L480 AbstractCegarLoop]: Abstraction has 1081 states and 1088 transitions. [2018-12-02 04:06:15,906 INFO L481 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-12-02 04:06:15,906 INFO L276 IsEmpty]: Start isEmpty. Operand 1081 states and 1088 transitions. [2018-12-02 04:06:15,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 932 [2018-12-02 04:06:15,910 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:15,910 INFO L402 BasicCegarLoop]: trace histogram [152, 151, 151, 151, 151, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:15,910 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:15,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:15,910 INFO L82 PathProgramCache]: Analyzing trace with hash 401870661, now seen corresponding path program 39 times [2018-12-02 04:06:15,910 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:15,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:15,911 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:15,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:15,911 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:15,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:16,539 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11956 proven. 676 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2018-12-02 04:06:16,539 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:16,539 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:16,539 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:16,539 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:16,539 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:16,539 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:16,545 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:06:16,545 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:06:16,891 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:06:16,891 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:16,900 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:17,332 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11325 proven. 632 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-02 04:06:17,332 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:17,993 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11325 proven. 632 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-02 04:06:18,010 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:18,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 18, 18] total 70 [2018-12-02 04:06:18,011 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:18,011 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-12-02 04:06:18,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-12-02 04:06:18,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=700, Invalid=4270, Unknown=0, NotChecked=0, Total=4970 [2018-12-02 04:06:18,011 INFO L87 Difference]: Start difference. First operand 1081 states and 1088 transitions. Second operand 54 states. [2018-12-02 04:06:19,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:19,286 INFO L93 Difference]: Finished difference Result 1296 states and 1309 transitions. [2018-12-02 04:06:19,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-12-02 04:06:19,286 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 931 [2018-12-02 04:06:19,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:19,289 INFO L225 Difference]: With dead ends: 1296 [2018-12-02 04:06:19,289 INFO L226 Difference]: Without dead ends: 1296 [2018-12-02 04:06:19,289 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1918 GetRequests, 1828 SyntacticMatches, 1 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1731 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1324, Invalid=6866, Unknown=0, NotChecked=0, Total=8190 [2018-12-02 04:06:19,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1296 states. [2018-12-02 04:06:19,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1296 to 1271. [2018-12-02 04:06:19,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1271 states. [2018-12-02 04:06:19,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1271 states to 1271 states and 1283 transitions. [2018-12-02 04:06:19,298 INFO L78 Accepts]: Start accepts. Automaton has 1271 states and 1283 transitions. Word has length 931 [2018-12-02 04:06:19,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:19,299 INFO L480 AbstractCegarLoop]: Abstraction has 1271 states and 1283 transitions. [2018-12-02 04:06:19,299 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-12-02 04:06:19,299 INFO L276 IsEmpty]: Start isEmpty. Operand 1271 states and 1283 transitions. [2018-12-02 04:06:19,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1023 [2018-12-02 04:06:19,305 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:19,305 INFO L402 BasicCegarLoop]: trace histogram [168, 167, 167, 167, 167, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:19,305 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:19,305 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:19,306 INFO L82 PathProgramCache]: Analyzing trace with hash -1689975411, now seen corresponding path program 40 times [2018-12-02 04:06:19,306 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:19,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:19,306 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:19,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:19,306 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:19,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:20,082 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 22209 proven. 3122 refuted. 0 times theorem prover too weak. 48364 trivial. 0 not checked. [2018-12-02 04:06:20,083 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:20,083 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:20,083 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:20,083 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:20,083 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:20,083 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:20,090 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:20,090 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:06:20,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:20,243 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:21,060 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 33168 proven. 540 refuted. 0 times theorem prover too weak. 39987 trivial. 0 not checked. [2018-12-02 04:06:21,060 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:22,078 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 23410 proven. 1775 refuted. 0 times theorem prover too weak. 48510 trivial. 0 not checked. [2018-12-02 04:06:22,093 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:22,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 34, 34] total 89 [2018-12-02 04:06:22,093 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:22,094 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-12-02 04:06:22,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-12-02 04:06:22,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1236, Invalid=6596, Unknown=0, NotChecked=0, Total=7832 [2018-12-02 04:06:22,094 INFO L87 Difference]: Start difference. First operand 1271 states and 1283 transitions. Second operand 73 states. [2018-12-02 04:06:23,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:23,929 INFO L93 Difference]: Finished difference Result 1101 states and 1106 transitions. [2018-12-02 04:06:23,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-12-02 04:06:23,929 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1022 [2018-12-02 04:06:23,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:23,931 INFO L225 Difference]: With dead ends: 1101 [2018-12-02 04:06:23,931 INFO L226 Difference]: Without dead ends: 1092 [2018-12-02 04:06:23,932 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2149 GetRequests, 1981 SyntacticMatches, 17 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8945 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3685, Invalid=19571, Unknown=0, NotChecked=0, Total=23256 [2018-12-02 04:06:23,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1092 states. [2018-12-02 04:06:23,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1092 to 1085. [2018-12-02 04:06:23,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1085 states. [2018-12-02 04:06:23,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1085 states to 1085 states and 1090 transitions. [2018-12-02 04:06:23,940 INFO L78 Accepts]: Start accepts. Automaton has 1085 states and 1090 transitions. Word has length 1022 [2018-12-02 04:06:23,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:23,940 INFO L480 AbstractCegarLoop]: Abstraction has 1085 states and 1090 transitions. [2018-12-02 04:06:23,940 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-12-02 04:06:23,940 INFO L276 IsEmpty]: Start isEmpty. Operand 1085 states and 1090 transitions. [2018-12-02 04:06:23,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1028 [2018-12-02 04:06:23,945 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:23,945 INFO L402 BasicCegarLoop]: trace histogram [169, 168, 168, 168, 168, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:23,945 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:23,945 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:23,945 INFO L82 PathProgramCache]: Analyzing trace with hash -697239742, now seen corresponding path program 41 times [2018-12-02 04:06:23,945 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:23,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:23,946 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:23,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:23,946 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:23,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:24,694 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 24055 proven. 2043 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-02 04:06:24,694 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:24,694 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:24,695 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:24,695 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:24,695 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:24,695 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:24,700 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:06:24,700 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:06:24,911 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-12-02 04:06:24,911 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:24,918 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:25,527 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 23423 proven. 2043 refuted. 0 times theorem prover too weak. 49082 trivial. 0 not checked. [2018-12-02 04:06:25,527 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:26,518 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 23358 proven. 2108 refuted. 0 times theorem prover too weak. 49082 trivial. 0 not checked. [2018-12-02 04:06:26,533 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:26,533 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 26, 26] total 87 [2018-12-02 04:06:26,533 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:26,534 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-02 04:06:26,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-02 04:06:26,534 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1561, Invalid=5921, Unknown=0, NotChecked=0, Total=7482 [2018-12-02 04:06:26,534 INFO L87 Difference]: Start difference. First operand 1085 states and 1090 transitions. Second operand 62 states. [2018-12-02 04:06:27,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:27,834 INFO L93 Difference]: Finished difference Result 1197 states and 1204 transitions. [2018-12-02 04:06:27,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-12-02 04:06:27,834 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1027 [2018-12-02 04:06:27,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:27,836 INFO L225 Difference]: With dead ends: 1197 [2018-12-02 04:06:27,836 INFO L226 Difference]: Without dead ends: 1197 [2018-12-02 04:06:27,837 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2147 GetRequests, 2009 SyntacticMatches, 1 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5529 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=5021, Invalid=14161, Unknown=0, NotChecked=0, Total=19182 [2018-12-02 04:06:27,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1197 states. [2018-12-02 04:06:27,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1197 to 1187. [2018-12-02 04:06:27,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1187 states. [2018-12-02 04:06:27,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1187 states to 1187 states and 1194 transitions. [2018-12-02 04:06:27,847 INFO L78 Accepts]: Start accepts. Automaton has 1187 states and 1194 transitions. Word has length 1027 [2018-12-02 04:06:27,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:27,847 INFO L480 AbstractCegarLoop]: Abstraction has 1187 states and 1194 transitions. [2018-12-02 04:06:27,847 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-02 04:06:27,847 INFO L276 IsEmpty]: Start isEmpty. Operand 1187 states and 1194 transitions. [2018-12-02 04:06:27,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1033 [2018-12-02 04:06:27,853 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:27,853 INFO L402 BasicCegarLoop]: trace histogram [170, 169, 169, 169, 169, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:27,853 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:27,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:27,853 INFO L82 PathProgramCache]: Analyzing trace with hash 548287687, now seen corresponding path program 42 times [2018-12-02 04:06:27,854 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:27,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:27,854 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:27,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:27,854 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:27,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:28,354 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13593 proven. 769 refuted. 0 times theorem prover too weak. 61044 trivial. 0 not checked. [2018-12-02 04:06:28,354 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:28,354 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:28,355 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:28,355 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:28,355 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:28,355 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:28,362 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:06:28,362 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:06:28,840 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:06:28,840 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:28,850 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:29,308 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13512 proven. 714 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-02 04:06:29,308 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:29,942 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13512 proven. 714 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-02 04:06:29,959 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:29,960 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19, 19] total 59 [2018-12-02 04:06:29,960 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:29,960 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-12-02 04:06:29,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-12-02 04:06:29,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=606, Invalid=2934, Unknown=0, NotChecked=0, Total=3540 [2018-12-02 04:06:29,961 INFO L87 Difference]: Start difference. First operand 1187 states and 1194 transitions. Second operand 42 states. [2018-12-02 04:06:31,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:31,238 INFO L93 Difference]: Finished difference Result 1416 states and 1429 transitions. [2018-12-02 04:06:31,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-12-02 04:06:31,239 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1032 [2018-12-02 04:06:31,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:31,242 INFO L225 Difference]: With dead ends: 1416 [2018-12-02 04:06:31,242 INFO L226 Difference]: Without dead ends: 1416 [2018-12-02 04:06:31,242 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2108 GetRequests, 2028 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1603 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1176, Invalid=5466, Unknown=0, NotChecked=0, Total=6642 [2018-12-02 04:06:31,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1416 states. [2018-12-02 04:06:31,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1416 to 1387. [2018-12-02 04:06:31,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1387 states. [2018-12-02 04:06:31,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1387 states to 1387 states and 1399 transitions. [2018-12-02 04:06:31,251 INFO L78 Accepts]: Start accepts. Automaton has 1387 states and 1399 transitions. Word has length 1032 [2018-12-02 04:06:31,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:31,252 INFO L480 AbstractCegarLoop]: Abstraction has 1387 states and 1399 transitions. [2018-12-02 04:06:31,252 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-12-02 04:06:31,252 INFO L276 IsEmpty]: Start isEmpty. Operand 1387 states and 1399 transitions. [2018-12-02 04:06:31,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1129 [2018-12-02 04:06:31,259 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:31,259 INFO L402 BasicCegarLoop]: trace histogram [187, 186, 186, 186, 186, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:31,259 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:31,259 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:31,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1455325456, now seen corresponding path program 43 times [2018-12-02 04:06:31,259 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:31,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:31,260 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:31,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:31,260 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:31,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:32,104 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 26506 proven. 3529 refuted. 0 times theorem prover too weak. 61088 trivial. 0 not checked. [2018-12-02 04:06:32,104 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:32,104 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:32,104 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:32,104 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:32,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:32,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:32,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:32,113 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:06:32,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:32,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:33,211 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 39629 proven. 616 refuted. 0 times theorem prover too weak. 50878 trivial. 0 not checked. [2018-12-02 04:06:33,211 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:34,368 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 27875 proven. 2013 refuted. 0 times theorem prover too weak. 61235 trivial. 0 not checked. [2018-12-02 04:06:34,384 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:34,384 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 36, 36] total 94 [2018-12-02 04:06:34,384 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:34,385 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-12-02 04:06:34,385 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-12-02 04:06:34,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1380, Invalid=7362, Unknown=0, NotChecked=0, Total=8742 [2018-12-02 04:06:34,385 INFO L87 Difference]: Start difference. First operand 1387 states and 1399 transitions. Second operand 77 states. [2018-12-02 04:06:36,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:36,230 INFO L93 Difference]: Finished difference Result 1207 states and 1212 transitions. [2018-12-02 04:06:36,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2018-12-02 04:06:36,230 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1128 [2018-12-02 04:06:36,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:36,232 INFO L225 Difference]: With dead ends: 1207 [2018-12-02 04:06:36,232 INFO L226 Difference]: Without dead ends: 1198 [2018-12-02 04:06:36,233 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2367 GetRequests, 2189 SyntacticMatches, 18 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10100 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4125, Invalid=21957, Unknown=0, NotChecked=0, Total=26082 [2018-12-02 04:06:36,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1198 states. [2018-12-02 04:06:36,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1198 to 1191. [2018-12-02 04:06:36,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1191 states. [2018-12-02 04:06:36,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1191 states to 1191 states and 1196 transitions. [2018-12-02 04:06:36,239 INFO L78 Accepts]: Start accepts. Automaton has 1191 states and 1196 transitions. Word has length 1128 [2018-12-02 04:06:36,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:36,240 INFO L480 AbstractCegarLoop]: Abstraction has 1191 states and 1196 transitions. [2018-12-02 04:06:36,240 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-12-02 04:06:36,240 INFO L276 IsEmpty]: Start isEmpty. Operand 1191 states and 1196 transitions. [2018-12-02 04:06:36,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1134 [2018-12-02 04:06:36,245 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:36,246 INFO L402 BasicCegarLoop]: trace histogram [188, 187, 187, 187, 187, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:36,246 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:36,246 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:36,246 INFO L82 PathProgramCache]: Analyzing trace with hash -1908118869, now seen corresponding path program 44 times [2018-12-02 04:06:36,246 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:36,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:36,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:36,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:36,247 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:36,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:37,105 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 28594 proven. 2298 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-02 04:06:37,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:37,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:37,105 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:37,105 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:37,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:37,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:37,111 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:06:37,111 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:06:37,349 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-12-02 04:06:37,349 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:37,356 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:38,051 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 27880 proven. 2298 refuted. 0 times theorem prover too weak. 61894 trivial. 0 not checked. [2018-12-02 04:06:38,051 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:39,250 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 27811 proven. 2367 refuted. 0 times theorem prover too weak. 61894 trivial. 0 not checked. [2018-12-02 04:06:39,265 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:39,265 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 27, 27] total 91 [2018-12-02 04:06:39,265 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:39,266 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-02 04:06:39,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-02 04:06:39,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1720, Invalid=6470, Unknown=0, NotChecked=0, Total=8190 [2018-12-02 04:06:39,267 INFO L87 Difference]: Start difference. First operand 1191 states and 1196 transitions. Second operand 65 states. [2018-12-02 04:06:40,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:40,496 INFO L93 Difference]: Finished difference Result 1308 states and 1315 transitions. [2018-12-02 04:06:40,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-12-02 04:06:40,496 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1133 [2018-12-02 04:06:40,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:40,498 INFO L225 Difference]: With dead ends: 1308 [2018-12-02 04:06:40,498 INFO L226 Difference]: Without dead ends: 1308 [2018-12-02 04:06:40,499 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2364 GetRequests, 2219 SyntacticMatches, 1 SemanticMatches, 144 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6157 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=5557, Invalid=15613, Unknown=0, NotChecked=0, Total=21170 [2018-12-02 04:06:40,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1308 states. [2018-12-02 04:06:40,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1308 to 1298. [2018-12-02 04:06:40,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1298 states. [2018-12-02 04:06:40,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1298 states to 1298 states and 1305 transitions. [2018-12-02 04:06:40,505 INFO L78 Accepts]: Start accepts. Automaton has 1298 states and 1305 transitions. Word has length 1133 [2018-12-02 04:06:40,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:40,505 INFO L480 AbstractCegarLoop]: Abstraction has 1298 states and 1305 transitions. [2018-12-02 04:06:40,505 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-02 04:06:40,505 INFO L276 IsEmpty]: Start isEmpty. Operand 1298 states and 1305 transitions. [2018-12-02 04:06:40,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1139 [2018-12-02 04:06:40,510 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:40,511 INFO L402 BasicCegarLoop]: trace histogram [189, 188, 188, 188, 188, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:40,511 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:40,511 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:40,511 INFO L82 PathProgramCache]: Analyzing trace with hash -1485351030, now seen corresponding path program 45 times [2018-12-02 04:06:40,511 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:40,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:40,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:40,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:40,511 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:40,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:41,106 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 16131 proven. 868 refuted. 0 times theorem prover too weak. 76027 trivial. 0 not checked. [2018-12-02 04:06:41,106 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:41,106 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:41,106 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:41,106 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:41,106 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:41,106 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:41,112 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:06:41,112 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:06:41,727 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:06:41,727 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:41,739 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:42,270 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 15963 proven. 801 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-02 04:06:42,270 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:42,927 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 15963 proven. 801 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-02 04:06:42,945 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:42,946 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 20, 20] total 63 [2018-12-02 04:06:42,946 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:42,946 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-12-02 04:06:42,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-12-02 04:06:42,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=661, Invalid=3371, Unknown=0, NotChecked=0, Total=4032 [2018-12-02 04:06:42,947 INFO L87 Difference]: Start difference. First operand 1298 states and 1305 transitions. Second operand 45 states. [2018-12-02 04:06:44,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:44,285 INFO L93 Difference]: Finished difference Result 1537 states and 1550 transitions. [2018-12-02 04:06:44,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-12-02 04:06:44,285 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 1138 [2018-12-02 04:06:44,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:44,288 INFO L225 Difference]: With dead ends: 1537 [2018-12-02 04:06:44,288 INFO L226 Difference]: Without dead ends: 1537 [2018-12-02 04:06:44,288 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2323 GetRequests, 2238 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1810 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1284, Invalid=6198, Unknown=0, NotChecked=0, Total=7482 [2018-12-02 04:06:44,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1537 states. [2018-12-02 04:06:44,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1537 to 1508. [2018-12-02 04:06:44,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1508 states. [2018-12-02 04:06:44,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1508 states to 1508 states and 1520 transitions. [2018-12-02 04:06:44,300 INFO L78 Accepts]: Start accepts. Automaton has 1508 states and 1520 transitions. Word has length 1138 [2018-12-02 04:06:44,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:44,300 INFO L480 AbstractCegarLoop]: Abstraction has 1508 states and 1520 transitions. [2018-12-02 04:06:44,300 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-12-02 04:06:44,300 INFO L276 IsEmpty]: Start isEmpty. Operand 1508 states and 1520 transitions. [2018-12-02 04:06:44,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1240 [2018-12-02 04:06:44,306 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:44,307 INFO L402 BasicCegarLoop]: trace histogram [207, 206, 206, 206, 206, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:44,307 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:44,307 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:44,307 INFO L82 PathProgramCache]: Analyzing trace with hash 775919112, now seen corresponding path program 46 times [2018-12-02 04:06:44,307 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:44,307 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:44,307 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:44,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:44,308 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:44,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:45,294 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 31325 proven. 3961 refuted. 0 times theorem prover too weak. 76164 trivial. 0 not checked. [2018-12-02 04:06:45,294 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:45,294 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:45,294 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:45,294 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:45,294 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:45,294 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:45,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:45,300 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:06:45,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:45,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:46,551 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 46876 proven. 697 refuted. 0 times theorem prover too weak. 63877 trivial. 0 not checked. [2018-12-02 04:06:46,552 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:47,868 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 32873 proven. 2266 refuted. 0 times theorem prover too weak. 76311 trivial. 0 not checked. [2018-12-02 04:06:47,884 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:47,884 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 38, 38] total 99 [2018-12-02 04:06:47,884 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:47,885 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-12-02 04:06:47,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-12-02 04:06:47,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1532, Invalid=8170, Unknown=0, NotChecked=0, Total=9702 [2018-12-02 04:06:47,885 INFO L87 Difference]: Start difference. First operand 1508 states and 1520 transitions. Second operand 81 states. [2018-12-02 04:06:49,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:49,586 INFO L93 Difference]: Finished difference Result 1318 states and 1323 transitions. [2018-12-02 04:06:49,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-12-02 04:06:49,586 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1239 [2018-12-02 04:06:49,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:49,588 INFO L225 Difference]: With dead ends: 1318 [2018-12-02 04:06:49,588 INFO L226 Difference]: Without dead ends: 1309 [2018-12-02 04:06:49,589 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2595 GetRequests, 2407 SyntacticMatches, 19 SemanticMatches, 169 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11325 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=4590, Invalid=24480, Unknown=0, NotChecked=0, Total=29070 [2018-12-02 04:06:49,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1309 states. [2018-12-02 04:06:49,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1309 to 1302. [2018-12-02 04:06:49,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1302 states. [2018-12-02 04:06:49,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1302 states to 1302 states and 1307 transitions. [2018-12-02 04:06:49,595 INFO L78 Accepts]: Start accepts. Automaton has 1302 states and 1307 transitions. Word has length 1239 [2018-12-02 04:06:49,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:49,596 INFO L480 AbstractCegarLoop]: Abstraction has 1302 states and 1307 transitions. [2018-12-02 04:06:49,596 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-12-02 04:06:49,596 INFO L276 IsEmpty]: Start isEmpty. Operand 1302 states and 1307 transitions. [2018-12-02 04:06:49,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1245 [2018-12-02 04:06:49,602 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:49,602 INFO L402 BasicCegarLoop]: trace histogram [208, 207, 207, 207, 207, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:49,602 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:49,603 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:49,603 INFO L82 PathProgramCache]: Analyzing trace with hash -1962245081, now seen corresponding path program 47 times [2018-12-02 04:06:49,603 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:49,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:49,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:06:49,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:49,604 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:49,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:50,603 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 33670 proven. 2568 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-02 04:06:50,603 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:50,603 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:50,603 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:50,603 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:50,603 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:50,603 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:50,613 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:06:50,613 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:06:50,901 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-12-02 04:06:50,901 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:50,909 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:51,661 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 18596 proven. 893 refuted. 0 times theorem prover too weak. 93011 trivial. 0 not checked. [2018-12-02 04:06:51,661 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:52,522 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 18596 proven. 893 refuted. 0 times theorem prover too weak. 93011 trivial. 0 not checked. [2018-12-02 04:06:52,537 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:52,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 22, 22] total 81 [2018-12-02 04:06:52,538 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:52,538 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-12-02 04:06:52,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-12-02 04:06:52,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1051, Invalid=5429, Unknown=0, NotChecked=0, Total=6480 [2018-12-02 04:06:52,539 INFO L87 Difference]: Start difference. First operand 1302 states and 1307 transitions. Second operand 67 states. [2018-12-02 04:06:55,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:55,606 INFO L93 Difference]: Finished difference Result 1432 states and 1440 transitions. [2018-12-02 04:06:55,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-02 04:06:55,606 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1244 [2018-12-02 04:06:55,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:55,608 INFO L225 Difference]: With dead ends: 1432 [2018-12-02 04:06:55,608 INFO L226 Difference]: Without dead ends: 1432 [2018-12-02 04:06:55,609 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2592 GetRequests, 2447 SyntacticMatches, 7 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4720 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=4767, Invalid=14693, Unknown=0, NotChecked=0, Total=19460 [2018-12-02 04:06:55,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1432 states. [2018-12-02 04:06:55,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1432 to 1419. [2018-12-02 04:06:55,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1419 states. [2018-12-02 04:06:55,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1419 states to 1419 states and 1427 transitions. [2018-12-02 04:06:55,615 INFO L78 Accepts]: Start accepts. Automaton has 1419 states and 1427 transitions. Word has length 1244 [2018-12-02 04:06:55,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:55,616 INFO L480 AbstractCegarLoop]: Abstraction has 1419 states and 1427 transitions. [2018-12-02 04:06:55,616 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-12-02 04:06:55,616 INFO L276 IsEmpty]: Start isEmpty. Operand 1419 states and 1427 transitions. [2018-12-02 04:06:55,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1255 [2018-12-02 04:06:55,622 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:55,623 INFO L402 BasicCegarLoop]: trace histogram [210, 209, 209, 209, 209, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:55,623 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:55,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:55,623 INFO L82 PathProgramCache]: Analyzing trace with hash 1445425069, now seen corresponding path program 48 times [2018-12-02 04:06:55,623 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:55,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:55,623 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:55,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:55,624 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:06:55,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:06:56,568 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20625 proven. 993 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-02 04:06:56,568 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:56,568 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:06:56,568 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:06:56,569 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:06:56,569 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:06:56,569 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:06:56,575 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:06:56,575 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:06:56,728 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:06:56,728 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:06:56,738 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:06:57,733 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20477 proven. 3307 refuted. 0 times theorem prover too weak. 90831 trivial. 0 not checked. [2018-12-02 04:06:57,733 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:06:58,618 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20477 proven. 3307 refuted. 0 times theorem prover too weak. 90831 trivial. 0 not checked. [2018-12-02 04:06:58,634 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:06:58,635 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 47, 47] total 73 [2018-12-02 04:06:58,635 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:06:58,635 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-12-02 04:06:58,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-12-02 04:06:58,636 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1021, Invalid=4235, Unknown=0, NotChecked=0, Total=5256 [2018-12-02 04:06:58,636 INFO L87 Difference]: Start difference. First operand 1419 states and 1427 transitions. Second operand 70 states. [2018-12-02 04:06:59,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:06:59,939 INFO L93 Difference]: Finished difference Result 1653 states and 1665 transitions. [2018-12-02 04:06:59,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-02 04:06:59,940 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1254 [2018-12-02 04:06:59,940 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:06:59,942 INFO L225 Difference]: With dead ends: 1653 [2018-12-02 04:06:59,942 INFO L226 Difference]: Without dead ends: 1653 [2018-12-02 04:06:59,942 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2592 GetRequests, 2437 SyntacticMatches, 43 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4225 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2766, Invalid=10116, Unknown=0, NotChecked=0, Total=12882 [2018-12-02 04:06:59,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1653 states. [2018-12-02 04:06:59,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1653 to 1639. [2018-12-02 04:06:59,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1639 states. [2018-12-02 04:06:59,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1639 states to 1639 states and 1651 transitions. [2018-12-02 04:06:59,950 INFO L78 Accepts]: Start accepts. Automaton has 1639 states and 1651 transitions. Word has length 1254 [2018-12-02 04:06:59,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:06:59,950 INFO L480 AbstractCegarLoop]: Abstraction has 1639 states and 1651 transitions. [2018-12-02 04:06:59,950 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-12-02 04:06:59,951 INFO L276 IsEmpty]: Start isEmpty. Operand 1639 states and 1651 transitions. [2018-12-02 04:06:59,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1356 [2018-12-02 04:06:59,958 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:06:59,958 INFO L402 BasicCegarLoop]: trace histogram [228, 227, 227, 227, 227, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:06:59,958 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:06:59,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:06:59,958 INFO L82 PathProgramCache]: Analyzing trace with hash -862088469, now seen corresponding path program 49 times [2018-12-02 04:06:59,958 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:06:59,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:59,959 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:06:59,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:06:59,959 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:00,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:01,096 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 36696 proven. 4418 refuted. 0 times theorem prover too weak. 93865 trivial. 0 not checked. [2018-12-02 04:07:01,096 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:01,096 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:01,096 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:01,096 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:01,096 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:01,096 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:01,103 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:07:01,103 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:07:01,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:01,295 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:02,503 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 54954 proven. 783 refuted. 0 times theorem prover too weak. 79242 trivial. 0 not checked. [2018-12-02 04:07:02,504 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:03,959 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 38434 proven. 2534 refuted. 0 times theorem prover too weak. 94011 trivial. 0 not checked. [2018-12-02 04:07:03,974 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:03,975 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 40, 40] total 104 [2018-12-02 04:07:03,975 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:03,975 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-12-02 04:07:03,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-12-02 04:07:03,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1692, Invalid=9020, Unknown=0, NotChecked=0, Total=10712 [2018-12-02 04:07:03,976 INFO L87 Difference]: Start difference. First operand 1639 states and 1651 transitions. Second operand 85 states. [2018-12-02 04:07:05,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:05,956 INFO L93 Difference]: Finished difference Result 1434 states and 1439 transitions. [2018-12-02 04:07:05,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-12-02 04:07:05,956 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1355 [2018-12-02 04:07:05,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:05,958 INFO L225 Difference]: With dead ends: 1434 [2018-12-02 04:07:05,959 INFO L226 Difference]: Without dead ends: 1425 [2018-12-02 04:07:05,960 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2833 GetRequests, 2635 SyntacticMatches, 20 SemanticMatches, 178 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12620 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=5080, Invalid=27140, Unknown=0, NotChecked=0, Total=32220 [2018-12-02 04:07:05,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1425 states. [2018-12-02 04:07:05,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1425 to 1418. [2018-12-02 04:07:05,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1418 states. [2018-12-02 04:07:05,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1418 states to 1418 states and 1423 transitions. [2018-12-02 04:07:05,969 INFO L78 Accepts]: Start accepts. Automaton has 1418 states and 1423 transitions. Word has length 1355 [2018-12-02 04:07:05,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:05,970 INFO L480 AbstractCegarLoop]: Abstraction has 1418 states and 1423 transitions. [2018-12-02 04:07:05,970 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-12-02 04:07:05,970 INFO L276 IsEmpty]: Start isEmpty. Operand 1418 states and 1423 transitions. [2018-12-02 04:07:05,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1361 [2018-12-02 04:07:05,980 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:05,981 INFO L402 BasicCegarLoop]: trace histogram [229, 228, 228, 228, 228, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:05,981 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:05,981 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:05,981 INFO L82 PathProgramCache]: Analyzing trace with hash -1077882064, now seen corresponding path program 50 times [2018-12-02 04:07:05,981 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:05,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:05,982 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:07:05,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:05,982 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:06,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:07,098 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 39313 proven. 2853 refuted. 0 times theorem prover too weak. 93969 trivial. 0 not checked. [2018-12-02 04:07:07,098 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:07,099 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:07,099 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:07,099 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:07,099 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:07,099 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:07,110 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:07:07,110 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:07:07,484 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-12-02 04:07:07,484 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:07:07,493 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:08,381 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 38420 proven. 2853 refuted. 0 times theorem prover too weak. 94862 trivial. 0 not checked. [2018-12-02 04:07:08,381 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:09,728 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 38343 proven. 2930 refuted. 0 times theorem prover too weak. 94862 trivial. 0 not checked. [2018-12-02 04:07:09,744 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:09,744 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 29, 29] total 99 [2018-12-02 04:07:09,744 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:09,745 INFO L459 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-12-02 04:07:09,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-12-02 04:07:09,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2041, Invalid=7661, Unknown=0, NotChecked=0, Total=9702 [2018-12-02 04:07:09,745 INFO L87 Difference]: Start difference. First operand 1418 states and 1423 transitions. Second operand 71 states. [2018-12-02 04:07:11,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:11,218 INFO L93 Difference]: Finished difference Result 1545 states and 1552 transitions. [2018-12-02 04:07:11,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-12-02 04:07:11,219 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1360 [2018-12-02 04:07:11,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:11,221 INFO L225 Difference]: With dead ends: 1545 [2018-12-02 04:07:11,221 INFO L226 Difference]: Without dead ends: 1545 [2018-12-02 04:07:11,222 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2828 GetRequests, 2669 SyntacticMatches, 1 SemanticMatches, 158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7527 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=6680, Invalid=18760, Unknown=0, NotChecked=0, Total=25440 [2018-12-02 04:07:11,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1545 states. [2018-12-02 04:07:11,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1545 to 1535. [2018-12-02 04:07:11,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1535 states. [2018-12-02 04:07:11,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1535 states to 1535 states and 1542 transitions. [2018-12-02 04:07:11,229 INFO L78 Accepts]: Start accepts. Automaton has 1535 states and 1542 transitions. Word has length 1360 [2018-12-02 04:07:11,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:11,230 INFO L480 AbstractCegarLoop]: Abstraction has 1535 states and 1542 transitions. [2018-12-02 04:07:11,230 INFO L481 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-12-02 04:07:11,230 INFO L276 IsEmpty]: Start isEmpty. Operand 1535 states and 1542 transitions. [2018-12-02 04:07:11,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1366 [2018-12-02 04:07:11,238 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:11,238 INFO L402 BasicCegarLoop]: trace histogram [230, 229, 229, 229, 229, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:11,238 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:11,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:11,239 INFO L82 PathProgramCache]: Analyzing trace with hash -1160826203, now seen corresponding path program 51 times [2018-12-02 04:07:11,239 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:11,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:11,239 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:07:11,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:11,239 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:11,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:12,057 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 22074 proven. 1084 refuted. 0 times theorem prover too weak. 114138 trivial. 0 not checked. [2018-12-02 04:07:12,057 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:12,057 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:12,057 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:12,057 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:12,057 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:12,057 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:12,063 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:07:12,063 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:07:12,823 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:07:12,823 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:07:12,839 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:13,598 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 21717 proven. 990 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-02 04:07:13,599 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:14,493 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 21717 proven. 990 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-02 04:07:14,511 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:14,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 22, 22] total 71 [2018-12-02 04:07:14,512 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:14,512 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-12-02 04:07:14,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-12-02 04:07:14,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=771, Invalid=4341, Unknown=0, NotChecked=0, Total=5112 [2018-12-02 04:07:14,513 INFO L87 Difference]: Start difference. First operand 1535 states and 1542 transitions. Second operand 51 states. [2018-12-02 04:07:16,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:16,375 INFO L93 Difference]: Finished difference Result 1794 states and 1807 transitions. [2018-12-02 04:07:16,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-12-02 04:07:16,376 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 1365 [2018-12-02 04:07:16,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:16,378 INFO L225 Difference]: With dead ends: 1794 [2018-12-02 04:07:16,378 INFO L226 Difference]: Without dead ends: 1794 [2018-12-02 04:07:16,379 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2783 GetRequests, 2688 SyntacticMatches, 0 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2260 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1497, Invalid=7815, Unknown=0, NotChecked=0, Total=9312 [2018-12-02 04:07:16,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1794 states. [2018-12-02 04:07:16,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1794 to 1765. [2018-12-02 04:07:16,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1765 states. [2018-12-02 04:07:16,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 1777 transitions. [2018-12-02 04:07:16,394 INFO L78 Accepts]: Start accepts. Automaton has 1765 states and 1777 transitions. Word has length 1365 [2018-12-02 04:07:16,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:16,394 INFO L480 AbstractCegarLoop]: Abstraction has 1765 states and 1777 transitions. [2018-12-02 04:07:16,394 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-12-02 04:07:16,395 INFO L276 IsEmpty]: Start isEmpty. Operand 1765 states and 1777 transitions. [2018-12-02 04:07:16,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1477 [2018-12-02 04:07:16,409 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:16,409 INFO L402 BasicCegarLoop]: trace histogram [250, 249, 249, 249, 249, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:16,410 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:16,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:16,410 INFO L82 PathProgramCache]: Analyzing trace with hash 1797808493, now seen corresponding path program 52 times [2018-12-02 04:07:16,410 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:16,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:16,411 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:07:16,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:16,411 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:16,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:17,642 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 42649 proven. 4900 refuted. 0 times theorem prover too weak. 114479 trivial. 0 not checked. [2018-12-02 04:07:17,642 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:17,642 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:17,642 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:17,642 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:17,642 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:17,642 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:17,648 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:07:17,648 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:07:17,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:17,863 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:19,234 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 63908 proven. 874 refuted. 0 times theorem prover too weak. 97246 trivial. 0 not checked. [2018-12-02 04:07:19,234 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:20,870 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 44588 proven. 2817 refuted. 0 times theorem prover too weak. 114623 trivial. 0 not checked. [2018-12-02 04:07:20,886 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:20,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 42, 42] total 109 [2018-12-02 04:07:20,887 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:20,887 INFO L459 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-12-02 04:07:20,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-12-02 04:07:20,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1860, Invalid=9912, Unknown=0, NotChecked=0, Total=11772 [2018-12-02 04:07:20,888 INFO L87 Difference]: Start difference. First operand 1765 states and 1777 transitions. Second operand 89 states. [2018-12-02 04:07:23,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:23,243 INFO L93 Difference]: Finished difference Result 1555 states and 1560 transitions. [2018-12-02 04:07:23,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 106 states. [2018-12-02 04:07:23,243 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 1476 [2018-12-02 04:07:23,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:23,245 INFO L225 Difference]: With dead ends: 1555 [2018-12-02 04:07:23,245 INFO L226 Difference]: Without dead ends: 1546 [2018-12-02 04:07:23,247 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3081 GetRequests, 2873 SyntacticMatches, 21 SemanticMatches, 187 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13985 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=5595, Invalid=29937, Unknown=0, NotChecked=0, Total=35532 [2018-12-02 04:07:23,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1546 states. [2018-12-02 04:07:23,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1546 to 1539. [2018-12-02 04:07:23,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2018-12-02 04:07:23,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 1544 transitions. [2018-12-02 04:07:23,254 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 1544 transitions. Word has length 1476 [2018-12-02 04:07:23,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:23,255 INFO L480 AbstractCegarLoop]: Abstraction has 1539 states and 1544 transitions. [2018-12-02 04:07:23,255 INFO L481 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-12-02 04:07:23,255 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 1544 transitions. [2018-12-02 04:07:23,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1482 [2018-12-02 04:07:23,264 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:23,265 INFO L402 BasicCegarLoop]: trace histogram [251, 250, 250, 250, 250, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:23,265 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:23,265 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:23,265 INFO L82 PathProgramCache]: Analyzing trace with hash -667535262, now seen corresponding path program 53 times [2018-12-02 04:07:23,265 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:23,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:23,266 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:07:23,266 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:23,266 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:23,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:24,566 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 45553 proven. 3153 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-02 04:07:24,566 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:24,566 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:24,566 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:24,566 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:24,566 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:24,566 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:24,572 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:07:24,573 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:07:25,028 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-12-02 04:07:25,028 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:07:25,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:26,033 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 44563 proven. 3153 refuted. 0 times theorem prover too weak. 115579 trivial. 0 not checked. [2018-12-02 04:07:26,034 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:27,632 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 44482 proven. 3234 refuted. 0 times theorem prover too weak. 115579 trivial. 0 not checked. [2018-12-02 04:07:27,648 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:27,648 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 30, 30] total 103 [2018-12-02 04:07:27,648 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:27,648 INFO L459 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-12-02 04:07:27,649 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-12-02 04:07:27,649 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2203, Invalid=8303, Unknown=0, NotChecked=0, Total=10506 [2018-12-02 04:07:27,649 INFO L87 Difference]: Start difference. First operand 1539 states and 1544 transitions. Second operand 74 states. [2018-12-02 04:07:29,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:29,981 INFO L93 Difference]: Finished difference Result 1671 states and 1678 transitions. [2018-12-02 04:07:29,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-12-02 04:07:29,982 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1481 [2018-12-02 04:07:29,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:29,984 INFO L225 Difference]: With dead ends: 1671 [2018-12-02 04:07:29,984 INFO L226 Difference]: Without dead ends: 1671 [2018-12-02 04:07:29,985 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3075 GetRequests, 2909 SyntacticMatches, 1 SemanticMatches, 165 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8269 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=7267, Invalid=20455, Unknown=0, NotChecked=0, Total=27722 [2018-12-02 04:07:29,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1671 states. [2018-12-02 04:07:29,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1671 to 1661. [2018-12-02 04:07:29,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1661 states. [2018-12-02 04:07:29,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1661 states to 1661 states and 1668 transitions. [2018-12-02 04:07:29,994 INFO L78 Accepts]: Start accepts. Automaton has 1661 states and 1668 transitions. Word has length 1481 [2018-12-02 04:07:29,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:29,994 INFO L480 AbstractCegarLoop]: Abstraction has 1661 states and 1668 transitions. [2018-12-02 04:07:29,994 INFO L481 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-12-02 04:07:29,994 INFO L276 IsEmpty]: Start isEmpty. Operand 1661 states and 1668 transitions. [2018-12-02 04:07:30,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1487 [2018-12-02 04:07:30,004 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:30,005 INFO L402 BasicCegarLoop]: trace histogram [252, 251, 251, 251, 251, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:30,005 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:30,005 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:30,005 INFO L82 PathProgramCache]: Analyzing trace with hash 9778855, now seen corresponding path program 54 times [2018-12-02 04:07:30,005 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:30,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:30,006 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:07:30,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:30,006 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:30,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:30,868 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25151 proven. 1201 refuted. 0 times theorem prover too weak. 138215 trivial. 0 not checked. [2018-12-02 04:07:30,868 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:30,868 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:30,868 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:30,868 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:30,868 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:30,868 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:30,877 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:07:30,877 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:07:31,943 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:07:31,943 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:07:31,960 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:32,778 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25050 proven. 1092 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-02 04:07:32,778 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:33,762 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25050 proven. 1092 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-02 04:07:33,781 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:33,781 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 23, 23] total 71 [2018-12-02 04:07:33,782 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:33,782 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-02 04:07:33,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-02 04:07:33,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=804, Invalid=4308, Unknown=0, NotChecked=0, Total=5112 [2018-12-02 04:07:33,782 INFO L87 Difference]: Start difference. First operand 1661 states and 1668 transitions. Second operand 50 states. [2018-12-02 04:07:35,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:35,794 INFO L93 Difference]: Finished difference Result 1930 states and 1943 transitions. [2018-12-02 04:07:35,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-12-02 04:07:35,794 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 1486 [2018-12-02 04:07:35,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:35,796 INFO L225 Difference]: With dead ends: 1930 [2018-12-02 04:07:35,796 INFO L226 Difference]: Without dead ends: 1930 [2018-12-02 04:07:35,797 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3024 GetRequests, 2928 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2305 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1502, Invalid=8004, Unknown=0, NotChecked=0, Total=9506 [2018-12-02 04:07:35,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1930 states. [2018-12-02 04:07:35,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1930 to 1901. [2018-12-02 04:07:35,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1901 states. [2018-12-02 04:07:35,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1901 states to 1901 states and 1913 transitions. [2018-12-02 04:07:35,805 INFO L78 Accepts]: Start accepts. Automaton has 1901 states and 1913 transitions. Word has length 1486 [2018-12-02 04:07:35,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:35,806 INFO L480 AbstractCegarLoop]: Abstraction has 1901 states and 1913 transitions. [2018-12-02 04:07:35,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-02 04:07:35,806 INFO L276 IsEmpty]: Start isEmpty. Operand 1901 states and 1913 transitions. [2018-12-02 04:07:35,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1603 [2018-12-02 04:07:35,816 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:35,816 INFO L402 BasicCegarLoop]: trace histogram [273, 272, 272, 272, 272, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:35,816 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:35,816 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:35,816 INFO L82 PathProgramCache]: Analyzing trace with hash 1962499760, now seen corresponding path program 55 times [2018-12-02 04:07:35,816 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:35,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:35,817 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:07:35,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:35,817 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:35,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:37,220 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 49214 proven. 5407 refuted. 0 times theorem prover too weak. 138309 trivial. 0 not checked. [2018-12-02 04:07:37,220 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:37,220 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:37,220 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:37,220 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:37,220 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:37,220 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:37,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:07:37,231 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:07:37,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:37,465 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:39,024 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 73783 proven. 970 refuted. 0 times theorem prover too weak. 118177 trivial. 0 not checked. [2018-12-02 04:07:39,024 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:40,893 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 51365 proven. 3115 refuted. 0 times theorem prover too weak. 138450 trivial. 0 not checked. [2018-12-02 04:07:40,908 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:40,909 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 44, 44] total 114 [2018-12-02 04:07:40,909 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:40,909 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-12-02 04:07:40,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-12-02 04:07:40,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2036, Invalid=10846, Unknown=0, NotChecked=0, Total=12882 [2018-12-02 04:07:40,910 INFO L87 Difference]: Start difference. First operand 1901 states and 1913 transitions. Second operand 93 states. [2018-12-02 04:07:44,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:44,407 INFO L93 Difference]: Finished difference Result 1681 states and 1686 transitions. [2018-12-02 04:07:44,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-12-02 04:07:44,408 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1602 [2018-12-02 04:07:44,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:44,413 INFO L225 Difference]: With dead ends: 1681 [2018-12-02 04:07:44,413 INFO L226 Difference]: Without dead ends: 1672 [2018-12-02 04:07:44,417 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3339 GetRequests, 3121 SyntacticMatches, 22 SemanticMatches, 196 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15420 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=6135, Invalid=32871, Unknown=0, NotChecked=0, Total=39006 [2018-12-02 04:07:44,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1672 states. [2018-12-02 04:07:44,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1672 to 1665. [2018-12-02 04:07:44,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1665 states. [2018-12-02 04:07:44,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1665 states to 1665 states and 1670 transitions. [2018-12-02 04:07:44,431 INFO L78 Accepts]: Start accepts. Automaton has 1665 states and 1670 transitions. Word has length 1602 [2018-12-02 04:07:44,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:44,432 INFO L480 AbstractCegarLoop]: Abstraction has 1665 states and 1670 transitions. [2018-12-02 04:07:44,432 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-12-02 04:07:44,432 INFO L276 IsEmpty]: Start isEmpty. Operand 1665 states and 1670 transitions. [2018-12-02 04:07:44,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1608 [2018-12-02 04:07:44,446 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:44,446 INFO L402 BasicCegarLoop]: trace histogram [274, 273, 273, 273, 273, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:44,446 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:44,447 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:44,447 INFO L82 PathProgramCache]: Analyzing trace with hash -1747254261, now seen corresponding path program 56 times [2018-12-02 04:07:44,447 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:44,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:44,447 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:07:44,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:44,448 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:44,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:45,863 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 52420 proven. 3468 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-02 04:07:45,864 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:45,864 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:45,864 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:45,864 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:45,864 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:45,864 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:45,871 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:07:45,871 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:07:46,416 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-12-02 04:07:46,416 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:07:46,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:47,470 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 28595 proven. 1199 refuted. 0 times theorem prover too weak. 164519 trivial. 0 not checked. [2018-12-02 04:07:47,470 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:48,653 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 28595 proven. 1199 refuted. 0 times theorem prover too weak. 164519 trivial. 0 not checked. [2018-12-02 04:07:48,669 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:48,670 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 25, 25] total 87 [2018-12-02 04:07:48,670 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:48,670 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-12-02 04:07:48,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-12-02 04:07:48,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1180, Invalid=6302, Unknown=0, NotChecked=0, Total=7482 [2018-12-02 04:07:48,671 INFO L87 Difference]: Start difference. First operand 1665 states and 1670 transitions. Second operand 76 states. [2018-12-02 04:07:51,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:51,355 INFO L93 Difference]: Finished difference Result 1810 states and 1818 transitions. [2018-12-02 04:07:51,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-02 04:07:51,355 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1607 [2018-12-02 04:07:51,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:51,357 INFO L225 Difference]: With dead ends: 1810 [2018-12-02 04:07:51,357 INFO L226 Difference]: Without dead ends: 1810 [2018-12-02 04:07:51,359 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3333 GetRequests, 3167 SyntacticMatches, 13 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6283 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=5733, Invalid=18137, Unknown=0, NotChecked=0, Total=23870 [2018-12-02 04:07:51,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1810 states. [2018-12-02 04:07:51,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1810 to 1797. [2018-12-02 04:07:51,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1797 states. [2018-12-02 04:07:51,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1797 states to 1797 states and 1805 transitions. [2018-12-02 04:07:51,367 INFO L78 Accepts]: Start accepts. Automaton has 1797 states and 1805 transitions. Word has length 1607 [2018-12-02 04:07:51,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:51,367 INFO L480 AbstractCegarLoop]: Abstraction has 1797 states and 1805 transitions. [2018-12-02 04:07:51,367 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-12-02 04:07:51,367 INFO L276 IsEmpty]: Start isEmpty. Operand 1797 states and 1805 transitions. [2018-12-02 04:07:51,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1618 [2018-12-02 04:07:51,377 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:51,378 INFO L402 BasicCegarLoop]: trace histogram [276, 275, 275, 275, 275, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:51,378 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:51,378 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:51,378 INFO L82 PathProgramCache]: Analyzing trace with hash -1712352251, now seen corresponding path program 57 times [2018-12-02 04:07:51,378 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:51,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:51,379 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:07:51,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:51,379 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:51,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:52,709 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31275 proven. 1347 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-02 04:07:52,710 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:52,710 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:52,710 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:52,710 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:52,710 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:52,710 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:52,717 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:07:52,718 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:07:52,919 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:07:52,919 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:07:52,932 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:07:54,349 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31106 proven. 4393 refuted. 0 times theorem prover too weak. 161595 trivial. 0 not checked. [2018-12-02 04:07:54,349 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:07:55,600 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31106 proven. 4393 refuted. 0 times theorem prover too weak. 161595 trivial. 0 not checked. [2018-12-02 04:07:55,616 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:07:55,617 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 53, 53] total 82 [2018-12-02 04:07:55,617 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:07:55,618 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-12-02 04:07:55,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-12-02 04:07:55,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1306, Invalid=5336, Unknown=0, NotChecked=0, Total=6642 [2018-12-02 04:07:55,619 INFO L87 Difference]: Start difference. First operand 1797 states and 1805 transitions. Second operand 79 states. [2018-12-02 04:07:57,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:07:57,226 INFO L93 Difference]: Finished difference Result 2061 states and 2073 transitions. [2018-12-02 04:07:57,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-02 04:07:57,226 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1617 [2018-12-02 04:07:57,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:07:57,229 INFO L225 Difference]: With dead ends: 2061 [2018-12-02 04:07:57,230 INFO L226 Difference]: Without dead ends: 2061 [2018-12-02 04:07:57,231 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3330 GetRequests, 3154 SyntacticMatches, 49 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5413 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3582, Invalid=12930, Unknown=0, NotChecked=0, Total=16512 [2018-12-02 04:07:57,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2061 states. [2018-12-02 04:07:57,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2061 to 2047. [2018-12-02 04:07:57,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2047 states. [2018-12-02 04:07:57,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 2059 transitions. [2018-12-02 04:07:57,243 INFO L78 Accepts]: Start accepts. Automaton has 2047 states and 2059 transitions. Word has length 1617 [2018-12-02 04:07:57,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:07:57,244 INFO L480 AbstractCegarLoop]: Abstraction has 2047 states and 2059 transitions. [2018-12-02 04:07:57,244 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-12-02 04:07:57,244 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 2059 transitions. [2018-12-02 04:07:57,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1734 [2018-12-02 04:07:57,257 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:07:57,258 INFO L402 BasicCegarLoop]: trace histogram [297, 296, 296, 296, 296, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:07:57,258 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:07:57,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:07:57,258 INFO L82 PathProgramCache]: Analyzing trace with hash -1388841432, now seen corresponding path program 58 times [2018-12-02 04:07:57,258 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:07:57,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:57,259 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:07:57,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:07:57,259 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:07:57,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:58,859 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 56421 proven. 5939 refuted. 0 times theorem prover too weak. 165673 trivial. 0 not checked. [2018-12-02 04:07:58,859 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:58,859 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:07:58,859 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:07:58,859 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:07:58,859 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:07:58,859 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:07:58,865 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:07:58,865 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:07:59,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:07:59,133 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:08:00,870 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 84624 proven. 1071 refuted. 0 times theorem prover too weak. 142338 trivial. 0 not checked. [2018-12-02 04:08:00,870 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:08:02,970 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 58795 proven. 3428 refuted. 0 times theorem prover too weak. 165810 trivial. 0 not checked. [2018-12-02 04:08:02,986 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:08:02,986 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 46, 46] total 119 [2018-12-02 04:08:02,987 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:08:02,987 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-12-02 04:08:02,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-12-02 04:08:02,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2220, Invalid=11822, Unknown=0, NotChecked=0, Total=14042 [2018-12-02 04:08:02,988 INFO L87 Difference]: Start difference. First operand 2047 states and 2059 transitions. Second operand 97 states. [2018-12-02 04:08:06,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:08:06,790 INFO L93 Difference]: Finished difference Result 1812 states and 1817 transitions. [2018-12-02 04:08:06,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 116 states. [2018-12-02 04:08:06,790 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 1733 [2018-12-02 04:08:06,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:08:06,793 INFO L225 Difference]: With dead ends: 1812 [2018-12-02 04:08:06,793 INFO L226 Difference]: Without dead ends: 1803 [2018-12-02 04:08:06,796 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3607 GetRequests, 3379 SyntacticMatches, 23 SemanticMatches, 205 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16925 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=6700, Invalid=35942, Unknown=0, NotChecked=0, Total=42642 [2018-12-02 04:08:06,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states. [2018-12-02 04:08:06,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1796. [2018-12-02 04:08:06,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1796 states. [2018-12-02 04:08:06,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1796 states to 1796 states and 1801 transitions. [2018-12-02 04:08:06,808 INFO L78 Accepts]: Start accepts. Automaton has 1796 states and 1801 transitions. Word has length 1733 [2018-12-02 04:08:06,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:08:06,808 INFO L480 AbstractCegarLoop]: Abstraction has 1796 states and 1801 transitions. [2018-12-02 04:08:06,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-12-02 04:08:06,808 INFO L276 IsEmpty]: Start isEmpty. Operand 1796 states and 1801 transitions. [2018-12-02 04:08:06,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1739 [2018-12-02 04:08:06,826 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:08:06,826 INFO L402 BasicCegarLoop]: trace histogram [298, 297, 297, 297, 297, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:08:06,826 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:08:06,826 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:08:06,826 INFO L82 PathProgramCache]: Analyzing trace with hash -1675122425, now seen corresponding path program 59 times [2018-12-02 04:08:06,826 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:08:06,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:06,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:08:06,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:06,827 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:08:06,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:08,410 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 59944 proven. 3798 refuted. 0 times theorem prover too weak. 165795 trivial. 0 not checked. [2018-12-02 04:08:08,411 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:08,411 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:08:08,411 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:08:08,411 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:08:08,411 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:08,411 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:08:08,417 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:08:08,417 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:08:09,185 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-12-02 04:08:09,185 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:08:09,196 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:08:10,387 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 32586 proven. 1311 refuted. 0 times theorem prover too weak. 195640 trivial. 0 not checked. [2018-12-02 04:08:10,387 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:08:11,690 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 32586 proven. 1311 refuted. 0 times theorem prover too weak. 195640 trivial. 0 not checked. [2018-12-02 04:08:11,707 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:08:11,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 26, 26] total 89 [2018-12-02 04:08:11,707 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:08:11,708 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-12-02 04:08:11,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-12-02 04:08:11,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1227, Invalid=6605, Unknown=0, NotChecked=0, Total=7832 [2018-12-02 04:08:11,708 INFO L87 Difference]: Start difference. First operand 1796 states and 1801 transitions. Second operand 79 states. [2018-12-02 04:08:13,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:08:13,880 INFO L93 Difference]: Finished difference Result 1946 states and 1954 transitions. [2018-12-02 04:08:13,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-12-02 04:08:13,881 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1738 [2018-12-02 04:08:13,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:08:13,883 INFO L225 Difference]: With dead ends: 1946 [2018-12-02 04:08:13,883 INFO L226 Difference]: Without dead ends: 1946 [2018-12-02 04:08:13,884 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3600 GetRequests, 3427 SyntacticMatches, 15 SemanticMatches, 158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6850 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=6075, Invalid=19365, Unknown=0, NotChecked=0, Total=25440 [2018-12-02 04:08:13,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1946 states. [2018-12-02 04:08:13,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1946 to 1933. [2018-12-02 04:08:13,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1933 states. [2018-12-02 04:08:13,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1933 states to 1933 states and 1941 transitions. [2018-12-02 04:08:13,892 INFO L78 Accepts]: Start accepts. Automaton has 1933 states and 1941 transitions. Word has length 1738 [2018-12-02 04:08:13,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:08:13,893 INFO L480 AbstractCegarLoop]: Abstraction has 1933 states and 1941 transitions. [2018-12-02 04:08:13,893 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-12-02 04:08:13,893 INFO L276 IsEmpty]: Start isEmpty. Operand 1933 states and 1941 transitions. [2018-12-02 04:08:13,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1749 [2018-12-02 04:08:13,904 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:08:13,904 INFO L402 BasicCegarLoop]: trace histogram [300, 299, 299, 299, 299, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:08:13,905 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:08:13,905 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:08:13,905 INFO L82 PathProgramCache]: Analyzing trace with hash 1749257613, now seen corresponding path program 60 times [2018-12-02 04:08:13,905 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:08:13,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:13,905 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:08:13,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:13,905 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:08:14,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:15,397 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35503 proven. 1477 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-02 04:08:15,398 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:15,398 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:08:15,398 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:08:15,398 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:08:15,398 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:15,398 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:08:15,404 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:08:15,404 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:08:15,632 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:08:15,632 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:08:15,645 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:08:17,239 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35327 proven. 4789 refuted. 0 times theorem prover too weak. 192444 trivial. 0 not checked. [2018-12-02 04:08:17,239 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:08:18,668 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35327 proven. 4789 refuted. 0 times theorem prover too weak. 192444 trivial. 0 not checked. [2018-12-02 04:08:18,684 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:08:18,685 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 55, 55] total 85 [2018-12-02 04:08:18,685 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:08:18,685 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-12-02 04:08:18,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-12-02 04:08:18,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1409, Invalid=5731, Unknown=0, NotChecked=0, Total=7140 [2018-12-02 04:08:18,686 INFO L87 Difference]: Start difference. First operand 1933 states and 1941 transitions. Second operand 82 states. [2018-12-02 04:08:20,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:08:20,756 INFO L93 Difference]: Finished difference Result 2207 states and 2219 transitions. [2018-12-02 04:08:20,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-12-02 04:08:20,756 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 1748 [2018-12-02 04:08:20,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:08:20,761 INFO L225 Difference]: With dead ends: 2207 [2018-12-02 04:08:20,761 INFO L226 Difference]: Without dead ends: 2207 [2018-12-02 04:08:20,762 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3596 GetRequests, 3413 SyntacticMatches, 51 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5841 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=3878, Invalid=13944, Unknown=0, NotChecked=0, Total=17822 [2018-12-02 04:08:20,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2207 states. [2018-12-02 04:08:20,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2207 to 2193. [2018-12-02 04:08:20,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2193 states. [2018-12-02 04:08:20,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2193 states to 2193 states and 2205 transitions. [2018-12-02 04:08:20,780 INFO L78 Accepts]: Start accepts. Automaton has 2193 states and 2205 transitions. Word has length 1748 [2018-12-02 04:08:20,781 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:08:20,781 INFO L480 AbstractCegarLoop]: Abstraction has 2193 states and 2205 transitions. [2018-12-02 04:08:20,781 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-12-02 04:08:20,781 INFO L276 IsEmpty]: Start isEmpty. Operand 2193 states and 2205 transitions. [2018-12-02 04:08:20,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1870 [2018-12-02 04:08:20,798 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:08:20,798 INFO L402 BasicCegarLoop]: trace histogram [322, 321, 321, 321, 321, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:08:20,798 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:08:20,799 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:08:20,799 INFO L82 PathProgramCache]: Analyzing trace with hash -299998901, now seen corresponding path program 61 times [2018-12-02 04:08:20,799 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:08:20,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:20,799 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:08:20,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:20,799 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:08:20,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:22,612 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 64300 proven. 6496 refuted. 0 times theorem prover too weak. 196904 trivial. 0 not checked. [2018-12-02 04:08:22,612 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:22,612 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:08:22,612 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:08:22,612 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:08:22,612 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:22,612 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:08:22,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:08:22,621 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:08:22,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:22,894 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:08:24,803 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 96476 proven. 1177 refuted. 0 times theorem prover too weak. 170047 trivial. 0 not checked. [2018-12-02 04:08:24,803 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:08:27,123 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 66908 proven. 3756 refuted. 0 times theorem prover too weak. 197036 trivial. 0 not checked. [2018-12-02 04:08:27,139 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:08:27,140 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 48, 48] total 124 [2018-12-02 04:08:27,140 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:08:27,140 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-12-02 04:08:27,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-12-02 04:08:27,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2412, Invalid=12840, Unknown=0, NotChecked=0, Total=15252 [2018-12-02 04:08:27,141 INFO L87 Difference]: Start difference. First operand 2193 states and 2205 transitions. Second operand 101 states. [2018-12-02 04:08:31,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:08:31,703 INFO L93 Difference]: Finished difference Result 1948 states and 1953 transitions. [2018-12-02 04:08:31,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-12-02 04:08:31,703 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 1869 [2018-12-02 04:08:31,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:08:31,707 INFO L225 Difference]: With dead ends: 1948 [2018-12-02 04:08:31,707 INFO L226 Difference]: Without dead ends: 1939 [2018-12-02 04:08:31,710 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3885 GetRequests, 3647 SyntacticMatches, 24 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18500 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=7290, Invalid=39150, Unknown=0, NotChecked=0, Total=46440 [2018-12-02 04:08:31,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1939 states. [2018-12-02 04:08:31,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1939 to 1932. [2018-12-02 04:08:31,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1932 states. [2018-12-02 04:08:31,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1932 states to 1932 states and 1937 transitions. [2018-12-02 04:08:31,725 INFO L78 Accepts]: Start accepts. Automaton has 1932 states and 1937 transitions. Word has length 1869 [2018-12-02 04:08:31,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:08:31,726 INFO L480 AbstractCegarLoop]: Abstraction has 1932 states and 1937 transitions. [2018-12-02 04:08:31,726 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-12-02 04:08:31,726 INFO L276 IsEmpty]: Start isEmpty. Operand 1932 states and 1937 transitions. [2018-12-02 04:08:31,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1875 [2018-12-02 04:08:31,743 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:08:31,743 INFO L402 BasicCegarLoop]: trace histogram [323, 322, 322, 322, 322, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:08:31,743 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:08:31,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:08:31,744 INFO L82 PathProgramCache]: Analyzing trace with hash 754168784, now seen corresponding path program 62 times [2018-12-02 04:08:31,744 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:08:31,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:31,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:08:31,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:31,744 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:08:31,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:33,583 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 68155 proven. 4143 refuted. 0 times theorem prover too weak. 197032 trivial. 0 not checked. [2018-12-02 04:08:33,583 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:33,584 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:08:33,584 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:08:33,584 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:08:33,584 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:33,584 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:08:33,589 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:08:33,590 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:08:34,268 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-12-02 04:08:34,268 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:08:34,280 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:08:35,602 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 36931 proven. 1428 refuted. 0 times theorem prover too weak. 230971 trivial. 0 not checked. [2018-12-02 04:08:35,602 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:08:37,087 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 36931 proven. 1428 refuted. 0 times theorem prover too weak. 230971 trivial. 0 not checked. [2018-12-02 04:08:37,104 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:08:37,104 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 27, 27] total 91 [2018-12-02 04:08:37,104 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:08:37,105 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-12-02 04:08:37,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-12-02 04:08:37,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=6914, Unknown=0, NotChecked=0, Total=8190 [2018-12-02 04:08:37,105 INFO L87 Difference]: Start difference. First operand 1932 states and 1937 transitions. Second operand 82 states. [2018-12-02 04:08:40,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:08:40,670 INFO L93 Difference]: Finished difference Result 2087 states and 2095 transitions. [2018-12-02 04:08:40,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-02 04:08:40,670 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 1874 [2018-12-02 04:08:40,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:08:40,672 INFO L225 Difference]: With dead ends: 2087 [2018-12-02 04:08:40,673 INFO L226 Difference]: Without dead ends: 2087 [2018-12-02 04:08:40,674 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3877 GetRequests, 3697 SyntacticMatches, 17 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7440 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=6427, Invalid=20633, Unknown=0, NotChecked=0, Total=27060 [2018-12-02 04:08:40,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2087 states. [2018-12-02 04:08:40,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2087 to 2074. [2018-12-02 04:08:40,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2074 states. [2018-12-02 04:08:40,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2074 states to 2074 states and 2082 transitions. [2018-12-02 04:08:40,684 INFO L78 Accepts]: Start accepts. Automaton has 2074 states and 2082 transitions. Word has length 1874 [2018-12-02 04:08:40,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:08:40,685 INFO L480 AbstractCegarLoop]: Abstraction has 2074 states and 2082 transitions. [2018-12-02 04:08:40,685 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-12-02 04:08:40,685 INFO L276 IsEmpty]: Start isEmpty. Operand 2074 states and 2082 transitions. [2018-12-02 04:08:40,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1885 [2018-12-02 04:08:40,699 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:08:40,699 INFO L402 BasicCegarLoop]: trace histogram [325, 324, 324, 324, 324, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:08:40,699 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:08:40,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:08:40,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1694558474, now seen corresponding path program 63 times [2018-12-02 04:08:40,700 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:08:40,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:40,700 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:08:40,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:40,700 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:08:40,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:42,401 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 40095 proven. 1613 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-02 04:08:42,401 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:42,401 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:08:42,401 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:08:42,401 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:08:42,401 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:42,401 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:08:42,407 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:08:42,407 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:08:42,635 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:08:42,635 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:08:42,650 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:08:44,432 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 39912 proven. 5202 refuted. 0 times theorem prover too weak. 227491 trivial. 0 not checked. [2018-12-02 04:08:44,432 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:08:46,000 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 39912 proven. 5202 refuted. 0 times theorem prover too weak. 227491 trivial. 0 not checked. [2018-12-02 04:08:46,016 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:08:46,017 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 57, 57] total 88 [2018-12-02 04:08:46,017 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:08:46,018 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-12-02 04:08:46,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-12-02 04:08:46,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1516, Invalid=6140, Unknown=0, NotChecked=0, Total=7656 [2018-12-02 04:08:46,019 INFO L87 Difference]: Start difference. First operand 2074 states and 2082 transitions. Second operand 85 states. [2018-12-02 04:08:47,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:08:47,567 INFO L93 Difference]: Finished difference Result 2358 states and 2370 transitions. [2018-12-02 04:08:47,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-02 04:08:47,568 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1884 [2018-12-02 04:08:47,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:08:47,570 INFO L225 Difference]: With dead ends: 2358 [2018-12-02 04:08:47,570 INFO L226 Difference]: Without dead ends: 2358 [2018-12-02 04:08:47,571 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3872 GetRequests, 3682 SyntacticMatches, 53 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6285 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=4186, Invalid=14996, Unknown=0, NotChecked=0, Total=19182 [2018-12-02 04:08:47,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2358 states. [2018-12-02 04:08:47,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2358 to 2344. [2018-12-02 04:08:47,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2344 states. [2018-12-02 04:08:47,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2344 states to 2344 states and 2356 transitions. [2018-12-02 04:08:47,583 INFO L78 Accepts]: Start accepts. Automaton has 2344 states and 2356 transitions. Word has length 1884 [2018-12-02 04:08:47,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:08:47,583 INFO L480 AbstractCegarLoop]: Abstraction has 2344 states and 2356 transitions. [2018-12-02 04:08:47,583 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-12-02 04:08:47,584 INFO L276 IsEmpty]: Start isEmpty. Operand 2344 states and 2356 transitions. [2018-12-02 04:08:47,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2011 [2018-12-02 04:08:47,599 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:08:47,599 INFO L402 BasicCegarLoop]: trace histogram [348, 347, 347, 347, 347, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:08:47,600 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:08:47,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:08:47,600 INFO L82 PathProgramCache]: Analyzing trace with hash -455283635, now seen corresponding path program 64 times [2018-12-02 04:08:47,600 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:08:47,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:47,600 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:08:47,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:08:47,600 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:08:47,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:49,573 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 72881 proven. 7078 refuted. 0 times theorem prover too weak. 232350 trivial. 0 not checked. [2018-12-02 04:08:49,573 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:49,573 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:08:49,573 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:08:49,573 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:08:49,573 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:08:49,573 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:08:49,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:08:49,579 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:08:49,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:08:49,867 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:08:51,975 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 109384 proven. 1288 refuted. 0 times theorem prover too weak. 201637 trivial. 0 not checked. [2018-12-02 04:08:51,975 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:08:54,503 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 75734 proven. 4099 refuted. 0 times theorem prover too weak. 232476 trivial. 0 not checked. [2018-12-02 04:08:54,519 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:08:54,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 50, 50] total 129 [2018-12-02 04:08:54,519 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:08:54,520 INFO L459 AbstractCegarLoop]: Interpolant automaton has 105 states [2018-12-02 04:08:54,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 105 interpolants. [2018-12-02 04:08:54,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2612, Invalid=13900, Unknown=0, NotChecked=0, Total=16512 [2018-12-02 04:08:54,521 INFO L87 Difference]: Start difference. First operand 2344 states and 2356 transitions. Second operand 105 states. [2018-12-02 04:09:00,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:09:00,397 INFO L93 Difference]: Finished difference Result 2089 states and 2094 transitions. [2018-12-02 04:09:00,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2018-12-02 04:09:00,398 INFO L78 Accepts]: Start accepts. Automaton has 105 states. Word has length 2010 [2018-12-02 04:09:00,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:09:00,400 INFO L225 Difference]: With dead ends: 2089 [2018-12-02 04:09:00,400 INFO L226 Difference]: Without dead ends: 2080 [2018-12-02 04:09:00,402 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4173 GetRequests, 3925 SyntacticMatches, 25 SemanticMatches, 223 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20145 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=7905, Invalid=42495, Unknown=0, NotChecked=0, Total=50400 [2018-12-02 04:09:00,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2080 states. [2018-12-02 04:09:00,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2080 to 2073. [2018-12-02 04:09:00,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2073 states. [2018-12-02 04:09:00,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2073 states to 2073 states and 2078 transitions. [2018-12-02 04:09:00,411 INFO L78 Accepts]: Start accepts. Automaton has 2073 states and 2078 transitions. Word has length 2010 [2018-12-02 04:09:00,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:09:00,411 INFO L480 AbstractCegarLoop]: Abstraction has 2073 states and 2078 transitions. [2018-12-02 04:09:00,411 INFO L481 AbstractCegarLoop]: Interpolant automaton has 105 states. [2018-12-02 04:09:00,411 INFO L276 IsEmpty]: Start isEmpty. Operand 2073 states and 2078 transitions. [2018-12-02 04:09:00,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2016 [2018-12-02 04:09:00,426 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:09:00,427 INFO L402 BasicCegarLoop]: trace histogram [349, 348, 348, 348, 348, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:09:00,427 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:09:00,427 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:09:00,427 INFO L82 PathProgramCache]: Analyzing trace with hash -2048382334, now seen corresponding path program 65 times [2018-12-02 04:09:00,427 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:09:00,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:00,428 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:09:00,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:00,428 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:09:00,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:02,394 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 77083 proven. 4503 refuted. 0 times theorem prover too weak. 232484 trivial. 0 not checked. [2018-12-02 04:09:02,394 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:02,394 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:09:02,394 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:09:02,394 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:09:02,395 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:02,395 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:09:02,400 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:09:02,401 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:09:03,542 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-12-02 04:09:03,542 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:09:03,555 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:09:05,177 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 75655 proven. 4503 refuted. 0 times theorem prover too weak. 233912 trivial. 0 not checked. [2018-12-02 04:09:05,178 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:09:07,465 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 75558 proven. 4600 refuted. 0 times theorem prover too weak. 233912 trivial. 0 not checked. [2018-12-02 04:09:07,482 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:09:07,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 34, 34] total 119 [2018-12-02 04:09:07,482 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:09:07,483 INFO L459 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-12-02 04:09:07,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-12-02 04:09:07,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2861, Invalid=11181, Unknown=0, NotChecked=0, Total=14042 [2018-12-02 04:09:07,484 INFO L87 Difference]: Start difference. First operand 2073 states and 2078 transitions. Second operand 86 states. [2018-12-02 04:09:10,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:09:10,391 INFO L93 Difference]: Finished difference Result 2225 states and 2232 transitions. [2018-12-02 04:09:10,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-12-02 04:09:10,391 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 2015 [2018-12-02 04:09:10,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:09:10,395 INFO L225 Difference]: With dead ends: 2225 [2018-12-02 04:09:10,395 INFO L226 Difference]: Without dead ends: 2225 [2018-12-02 04:09:10,398 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4163 GetRequests, 3969 SyntacticMatches, 1 SemanticMatches, 193 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11617 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=9785, Invalid=28045, Unknown=0, NotChecked=0, Total=37830 [2018-12-02 04:09:10,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2225 states. [2018-12-02 04:09:10,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2225 to 2215. [2018-12-02 04:09:10,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2215 states. [2018-12-02 04:09:10,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2215 states to 2215 states and 2222 transitions. [2018-12-02 04:09:10,415 INFO L78 Accepts]: Start accepts. Automaton has 2215 states and 2222 transitions. Word has length 2015 [2018-12-02 04:09:10,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:09:10,416 INFO L480 AbstractCegarLoop]: Abstraction has 2215 states and 2222 transitions. [2018-12-02 04:09:10,416 INFO L481 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-12-02 04:09:10,416 INFO L276 IsEmpty]: Start isEmpty. Operand 2215 states and 2222 transitions. [2018-12-02 04:09:10,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2021 [2018-12-02 04:09:10,435 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:09:10,435 INFO L402 BasicCegarLoop]: trace histogram [350, 349, 349, 349, 349, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:09:10,435 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:09:10,436 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:09:10,436 INFO L82 PathProgramCache]: Analyzing trace with hash 1794680711, now seen corresponding path program 66 times [2018-12-02 04:09:10,436 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:09:10,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:10,436 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:09:10,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:10,436 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:09:10,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:11,861 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41893 proven. 1729 refuted. 0 times theorem prover too weak. 272214 trivial. 0 not checked. [2018-12-02 04:09:11,861 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:11,861 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:09:11,861 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:09:11,861 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:09:11,861 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:11,861 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:09:11,867 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:09:11,867 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:09:12,549 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:09:12,549 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:09:12,572 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:09:13,896 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41772 proven. 1550 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2018-12-02 04:09:13,896 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:09:15,446 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41772 proven. 1550 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2018-12-02 04:09:15,468 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:09:15,468 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 27, 27] total 83 [2018-12-02 04:09:15,468 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:09:15,469 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-12-02 04:09:15,469 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-12-02 04:09:15,469 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=986, Invalid=5986, Unknown=0, NotChecked=0, Total=6972 [2018-12-02 04:09:15,469 INFO L87 Difference]: Start difference. First operand 2215 states and 2222 transitions. Second operand 58 states. [2018-12-02 04:09:17,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:09:17,420 INFO L93 Difference]: Finished difference Result 2524 states and 2537 transitions. [2018-12-02 04:09:17,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-12-02 04:09:17,420 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 2020 [2018-12-02 04:09:17,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:09:17,423 INFO L225 Difference]: With dead ends: 2524 [2018-12-02 04:09:17,423 INFO L226 Difference]: Without dead ends: 2524 [2018-12-02 04:09:17,423 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4100 GetRequests, 3988 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3087 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1780, Invalid=11102, Unknown=0, NotChecked=0, Total=12882 [2018-12-02 04:09:17,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2524 states. [2018-12-02 04:09:17,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2524 to 2495. [2018-12-02 04:09:17,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2495 states. [2018-12-02 04:09:17,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2495 states to 2495 states and 2507 transitions. [2018-12-02 04:09:17,435 INFO L78 Accepts]: Start accepts. Automaton has 2495 states and 2507 transitions. Word has length 2020 [2018-12-02 04:09:17,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:09:17,436 INFO L480 AbstractCegarLoop]: Abstraction has 2495 states and 2507 transitions. [2018-12-02 04:09:17,436 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-12-02 04:09:17,436 INFO L276 IsEmpty]: Start isEmpty. Operand 2495 states and 2507 transitions. [2018-12-02 04:09:17,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2157 [2018-12-02 04:09:17,453 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:09:17,453 INFO L402 BasicCegarLoop]: trace histogram [375, 374, 374, 374, 374, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:09:17,453 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:09:17,453 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:09:17,454 INFO L82 PathProgramCache]: Analyzing trace with hash 1596582736, now seen corresponding path program 67 times [2018-12-02 04:09:17,454 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:09:17,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:17,454 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:09:17,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:17,454 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:09:17,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:19,657 INFO L134 CoverageAnalysis]: Checked inductivity of 362253 backedges. 82194 proven. 7685 refuted. 0 times theorem prover too weak. 272374 trivial. 0 not checked. [2018-12-02 04:09:19,658 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:19,658 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:09:19,658 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:09:19,658 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:09:19,658 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:19,658 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:09:19,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:09:19,664 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:09:19,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:19,981 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:09:22,333 INFO L134 CoverageAnalysis]: Checked inductivity of 362253 backedges. 123393 proven. 1404 refuted. 0 times theorem prover too weak. 237456 trivial. 0 not checked. [2018-12-02 04:09:22,333 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:09:25,287 INFO L134 CoverageAnalysis]: Checked inductivity of 362253 backedges. 85303 proven. 4457 refuted. 0 times theorem prover too weak. 272493 trivial. 0 not checked. [2018-12-02 04:09:25,303 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:09:25,304 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 52, 52] total 134 [2018-12-02 04:09:25,304 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:09:25,305 INFO L459 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-12-02 04:09:25,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-12-02 04:09:25,305 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2820, Invalid=15002, Unknown=0, NotChecked=0, Total=17822 [2018-12-02 04:09:25,306 INFO L87 Difference]: Start difference. First operand 2495 states and 2507 transitions. Second operand 109 states. [2018-12-02 04:09:29,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:09:29,443 INFO L93 Difference]: Finished difference Result 2235 states and 2240 transitions. [2018-12-02 04:09:29,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-12-02 04:09:29,443 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2156 [2018-12-02 04:09:29,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:09:29,445 INFO L225 Difference]: With dead ends: 2235 [2018-12-02 04:09:29,445 INFO L226 Difference]: Without dead ends: 2226 [2018-12-02 04:09:29,447 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4471 GetRequests, 4213 SyntacticMatches, 26 SemanticMatches, 232 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21860 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=8545, Invalid=45977, Unknown=0, NotChecked=0, Total=54522 [2018-12-02 04:09:29,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2226 states. [2018-12-02 04:09:29,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2226 to 2219. [2018-12-02 04:09:29,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2219 states. [2018-12-02 04:09:29,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2219 states to 2219 states and 2224 transitions. [2018-12-02 04:09:29,457 INFO L78 Accepts]: Start accepts. Automaton has 2219 states and 2224 transitions. Word has length 2156 [2018-12-02 04:09:29,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:09:29,457 INFO L480 AbstractCegarLoop]: Abstraction has 2219 states and 2224 transitions. [2018-12-02 04:09:29,457 INFO L481 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-12-02 04:09:29,457 INFO L276 IsEmpty]: Start isEmpty. Operand 2219 states and 2224 transitions. [2018-12-02 04:09:29,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2162 [2018-12-02 04:09:29,474 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:09:29,474 INFO L402 BasicCegarLoop]: trace histogram [376, 375, 375, 375, 375, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:09:29,474 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:09:29,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:09:29,475 INFO L82 PathProgramCache]: Analyzing trace with hash 567594603, now seen corresponding path program 68 times [2018-12-02 04:09:29,475 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:09:29,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:29,475 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:09:29,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:29,475 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:09:29,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:31,713 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 86758 proven. 4878 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2018-12-02 04:09:31,713 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:31,713 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:09:31,714 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:09:31,714 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:09:31,714 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:31,714 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:09:31,720 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:09:31,721 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:09:33,339 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-12-02 04:09:33,339 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:09:33,353 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:09:35,012 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 46743 proven. 1677 refuted. 0 times theorem prover too weak. 315730 trivial. 0 not checked. [2018-12-02 04:09:35,012 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:09:36,807 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 46743 proven. 1677 refuted. 0 times theorem prover too weak. 315730 trivial. 0 not checked. [2018-12-02 04:09:36,826 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:09:36,826 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 29, 29] total 95 [2018-12-02 04:09:36,826 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:09:36,827 INFO L459 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-12-02 04:09:36,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-12-02 04:09:36,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1380, Invalid=7550, Unknown=0, NotChecked=0, Total=8930 [2018-12-02 04:09:36,827 INFO L87 Difference]: Start difference. First operand 2219 states and 2224 transitions. Second operand 88 states. [2018-12-02 04:09:40,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:09:40,204 INFO L93 Difference]: Finished difference Result 2384 states and 2392 transitions. [2018-12-02 04:09:40,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-12-02 04:09:40,205 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2161 [2018-12-02 04:09:40,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:09:40,209 INFO L225 Difference]: With dead ends: 2384 [2018-12-02 04:09:40,209 INFO L226 Difference]: Without dead ends: 2384 [2018-12-02 04:09:40,211 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4461 GetRequests, 4267 SyntacticMatches, 21 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8689 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=7161, Invalid=23289, Unknown=0, NotChecked=0, Total=30450 [2018-12-02 04:09:40,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2384 states. [2018-12-02 04:09:40,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2384 to 2371. [2018-12-02 04:09:40,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2371 states. [2018-12-02 04:09:40,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2371 states to 2371 states and 2379 transitions. [2018-12-02 04:09:40,228 INFO L78 Accepts]: Start accepts. Automaton has 2371 states and 2379 transitions. Word has length 2161 [2018-12-02 04:09:40,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:09:40,229 INFO L480 AbstractCegarLoop]: Abstraction has 2371 states and 2379 transitions. [2018-12-02 04:09:40,229 INFO L481 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-12-02 04:09:40,229 INFO L276 IsEmpty]: Start isEmpty. Operand 2371 states and 2379 transitions. [2018-12-02 04:09:40,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2172 [2018-12-02 04:09:40,248 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:09:40,248 INFO L402 BasicCegarLoop]: trace histogram [378, 377, 377, 377, 377, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:09:40,248 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:09:40,249 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:09:40,249 INFO L82 PathProgramCache]: Analyzing trace with hash 1011103077, now seen corresponding path program 69 times [2018-12-02 04:09:40,249 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:09:40,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:40,250 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:09:40,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:40,250 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:09:40,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:42,334 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50431 proven. 1903 refuted. 0 times theorem prover too weak. 315625 trivial. 0 not checked. [2018-12-02 04:09:42,334 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:42,334 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:09:42,334 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:09:42,335 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:09:42,335 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:42,335 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:09:42,340 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:09:42,340 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:09:42,637 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:09:42,637 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:09:42,653 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:09:44,796 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50234 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2018-12-02 04:09:44,797 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:09:46,725 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50234 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2018-12-02 04:09:46,742 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:09:46,743 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 61, 61] total 94 [2018-12-02 04:09:46,743 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:09:46,743 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-12-02 04:09:46,744 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-12-02 04:09:46,744 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1742, Invalid=7000, Unknown=0, NotChecked=0, Total=8742 [2018-12-02 04:09:46,744 INFO L87 Difference]: Start difference. First operand 2371 states and 2379 transitions. Second operand 91 states. [2018-12-02 04:09:49,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:09:49,552 INFO L93 Difference]: Finished difference Result 2675 states and 2687 transitions. [2018-12-02 04:09:49,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-12-02 04:09:49,552 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2171 [2018-12-02 04:09:49,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:09:49,557 INFO L225 Difference]: With dead ends: 2675 [2018-12-02 04:09:49,557 INFO L226 Difference]: Without dead ends: 2675 [2018-12-02 04:09:49,558 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4454 GetRequests, 4250 SyntacticMatches, 57 SemanticMatches, 147 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7221 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=4838, Invalid=17214, Unknown=0, NotChecked=0, Total=22052 [2018-12-02 04:09:49,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2675 states. [2018-12-02 04:09:49,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2675 to 2661. [2018-12-02 04:09:49,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2661 states. [2018-12-02 04:09:49,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2661 states to 2661 states and 2673 transitions. [2018-12-02 04:09:49,577 INFO L78 Accepts]: Start accepts. Automaton has 2661 states and 2673 transitions. Word has length 2171 [2018-12-02 04:09:49,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:09:49,578 INFO L480 AbstractCegarLoop]: Abstraction has 2661 states and 2673 transitions. [2018-12-02 04:09:49,578 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-12-02 04:09:49,578 INFO L276 IsEmpty]: Start isEmpty. Operand 2661 states and 2673 transitions. [2018-12-02 04:09:49,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2308 [2018-12-02 04:09:49,599 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:09:49,599 INFO L402 BasicCegarLoop]: trace histogram [403, 402, 402, 402, 402, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:09:49,599 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:09:49,599 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:09:49,599 INFO L82 PathProgramCache]: Analyzing trace with hash -706640056, now seen corresponding path program 70 times [2018-12-02 04:09:49,599 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:09:49,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:49,600 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:09:49,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:09:49,600 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:09:49,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:52,051 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 92269 proven. 8317 refuted. 0 times theorem prover too weak. 317354 trivial. 0 not checked. [2018-12-02 04:09:52,051 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:52,051 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:09:52,051 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:09:52,051 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:09:52,051 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:09:52,051 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:09:52,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:09:52,057 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:09:52,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:09:52,390 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:09:55,008 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 138548 proven. 1525 refuted. 0 times theorem prover too weak. 277867 trivial. 0 not checked. [2018-12-02 04:09:55,008 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:09:58,161 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 95645 proven. 4830 refuted. 0 times theorem prover too weak. 317465 trivial. 0 not checked. [2018-12-02 04:09:58,178 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:09:58,179 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 54, 54] total 139 [2018-12-02 04:09:58,179 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:09:58,180 INFO L459 AbstractCegarLoop]: Interpolant automaton has 113 states [2018-12-02 04:09:58,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2018-12-02 04:09:58,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3036, Invalid=16146, Unknown=0, NotChecked=0, Total=19182 [2018-12-02 04:09:58,181 INFO L87 Difference]: Start difference. First operand 2661 states and 2673 transitions. Second operand 113 states. [2018-12-02 04:10:04,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:10:04,881 INFO L93 Difference]: Finished difference Result 2386 states and 2391 transitions. [2018-12-02 04:10:04,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 136 states. [2018-12-02 04:10:04,881 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 2307 [2018-12-02 04:10:04,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:10:04,884 INFO L225 Difference]: With dead ends: 2386 [2018-12-02 04:10:04,884 INFO L226 Difference]: Without dead ends: 2377 [2018-12-02 04:10:04,887 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4779 GetRequests, 4511 SyntacticMatches, 27 SemanticMatches, 241 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23645 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=9210, Invalid=49596, Unknown=0, NotChecked=0, Total=58806 [2018-12-02 04:10:04,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2018-12-02 04:10:04,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 2370. [2018-12-02 04:10:04,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2370 states. [2018-12-02 04:10:04,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2370 states to 2370 states and 2375 transitions. [2018-12-02 04:10:04,897 INFO L78 Accepts]: Start accepts. Automaton has 2370 states and 2375 transitions. Word has length 2307 [2018-12-02 04:10:04,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:10:04,898 INFO L480 AbstractCegarLoop]: Abstraction has 2370 states and 2375 transitions. [2018-12-02 04:10:04,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 113 states. [2018-12-02 04:10:04,898 INFO L276 IsEmpty]: Start isEmpty. Operand 2370 states and 2375 transitions. [2018-12-02 04:10:04,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2313 [2018-12-02 04:10:04,918 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:10:04,918 INFO L402 BasicCegarLoop]: trace histogram [404, 403, 403, 403, 403, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:10:04,918 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:10:04,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:10:04,918 INFO L82 PathProgramCache]: Analyzing trace with hash 1323482343, now seen corresponding path program 71 times [2018-12-02 04:10:04,918 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:10:04,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:04,919 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:10:04,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:04,919 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:10:05,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:10:07,419 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 97210 proven. 5268 refuted. 0 times theorem prover too weak. 317500 trivial. 0 not checked. [2018-12-02 04:10:07,419 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:07,419 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:10:07,419 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:10:07,419 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:10:07,419 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:07,419 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:10:07,425 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:10:07,425 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:10:09,177 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-12-02 04:10:09,177 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:10:09,191 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:10:11,199 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 95533 proven. 5268 refuted. 0 times theorem prover too weak. 319177 trivial. 0 not checked. [2018-12-02 04:10:11,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:10:13,830 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 95428 proven. 5373 refuted. 0 times theorem prover too weak. 319177 trivial. 0 not checked. [2018-12-02 04:10:13,848 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:10:13,848 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 36, 36] total 127 [2018-12-02 04:10:13,848 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:10:13,849 INFO L459 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-12-02 04:10:13,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-12-02 04:10:13,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3196, Invalid=12806, Unknown=0, NotChecked=0, Total=16002 [2018-12-02 04:10:13,850 INFO L87 Difference]: Start difference. First operand 2370 states and 2375 transitions. Second operand 92 states. [2018-12-02 04:10:16,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:10:16,363 INFO L93 Difference]: Finished difference Result 2532 states and 2539 transitions. [2018-12-02 04:10:16,363 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-12-02 04:10:16,363 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2312 [2018-12-02 04:10:16,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:10:16,366 INFO L225 Difference]: With dead ends: 2532 [2018-12-02 04:10:16,366 INFO L226 Difference]: Without dead ends: 2532 [2018-12-02 04:10:16,368 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4767 GetRequests, 4559 SyntacticMatches, 1 SemanticMatches, 207 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13519 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=11146, Invalid=32326, Unknown=0, NotChecked=0, Total=43472 [2018-12-02 04:10:16,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2532 states. [2018-12-02 04:10:16,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2532 to 2522. [2018-12-02 04:10:16,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2522 states. [2018-12-02 04:10:16,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2522 states to 2522 states and 2529 transitions. [2018-12-02 04:10:16,379 INFO L78 Accepts]: Start accepts. Automaton has 2522 states and 2529 transitions. Word has length 2312 [2018-12-02 04:10:16,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:10:16,380 INFO L480 AbstractCegarLoop]: Abstraction has 2522 states and 2529 transitions. [2018-12-02 04:10:16,380 INFO L481 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-12-02 04:10:16,380 INFO L276 IsEmpty]: Start isEmpty. Operand 2522 states and 2529 transitions. [2018-12-02 04:10:16,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2318 [2018-12-02 04:10:16,400 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:10:16,400 INFO L402 BasicCegarLoop]: trace histogram [405, 404, 404, 404, 404, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:10:16,400 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:10:16,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:10:16,400 INFO L82 PathProgramCache]: Analyzing trace with hash 1696940994, now seen corresponding path program 72 times [2018-12-02 04:10:16,401 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:10:16,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:16,401 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:10:16,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:16,401 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:10:16,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:10:18,232 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52508 proven. 2029 refuted. 0 times theorem prover too weak. 367484 trivial. 0 not checked. [2018-12-02 04:10:18,233 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:18,233 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:10:18,233 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:10:18,233 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:10:18,233 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:18,233 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:10:18,239 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:10:18,239 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:10:19,109 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:10:19,110 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:10:19,136 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:10:20,768 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52377 proven. 1809 refuted. 0 times theorem prover too weak. 367835 trivial. 0 not checked. [2018-12-02 04:10:20,768 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:10:22,746 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52377 proven. 1809 refuted. 0 times theorem prover too weak. 367835 trivial. 0 not checked. [2018-12-02 04:10:22,768 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:10:22,768 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 29, 29] total 89 [2018-12-02 04:10:22,769 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:10:22,769 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-02 04:10:22,769 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-02 04:10:22,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1071, Invalid=6939, Unknown=0, NotChecked=0, Total=8010 [2018-12-02 04:10:22,770 INFO L87 Difference]: Start difference. First operand 2522 states and 2529 transitions. Second operand 62 states. [2018-12-02 04:10:25,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:10:25,046 INFO L93 Difference]: Finished difference Result 2851 states and 2864 transitions. [2018-12-02 04:10:25,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-12-02 04:10:25,046 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2317 [2018-12-02 04:10:25,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:10:25,050 INFO L225 Difference]: With dead ends: 2851 [2018-12-02 04:10:25,050 INFO L226 Difference]: Without dead ends: 2851 [2018-12-02 04:10:25,050 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4698 GetRequests, 4578 SyntacticMatches, 0 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3508 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1901, Invalid=12861, Unknown=0, NotChecked=0, Total=14762 [2018-12-02 04:10:25,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2851 states. [2018-12-02 04:10:25,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2851 to 2822. [2018-12-02 04:10:25,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2822 states. [2018-12-02 04:10:25,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2822 states to 2822 states and 2834 transitions. [2018-12-02 04:10:25,062 INFO L78 Accepts]: Start accepts. Automaton has 2822 states and 2834 transitions. Word has length 2317 [2018-12-02 04:10:25,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:10:25,063 INFO L480 AbstractCegarLoop]: Abstraction has 2822 states and 2834 transitions. [2018-12-02 04:10:25,063 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-02 04:10:25,063 INFO L276 IsEmpty]: Start isEmpty. Operand 2822 states and 2834 transitions. [2018-12-02 04:10:25,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2464 [2018-12-02 04:10:25,084 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:10:25,084 INFO L402 BasicCegarLoop]: trace histogram [432, 431, 431, 431, 431, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:10:25,084 INFO L423 AbstractCegarLoop]: === Iteration 88 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:10:25,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:10:25,085 INFO L82 PathProgramCache]: Analyzing trace with hash -1831952213, now seen corresponding path program 73 times [2018-12-02 04:10:25,085 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:10:25,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:25,085 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:10:25,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:25,085 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:10:25,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:10:27,828 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 103136 proven. 8974 refuted. 0 times theorem prover too weak. 367683 trivial. 0 not checked. [2018-12-02 04:10:27,829 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:27,829 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:10:27,829 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:10:27,829 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:10:27,829 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:27,829 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:10:27,835 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:10:27,835 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:10:28,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:10:28,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:10:31,150 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 154894 proven. 1651 refuted. 0 times theorem prover too weak. 323248 trivial. 0 not checked. [2018-12-02 04:10:31,150 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:10:34,798 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 106790 proven. 5218 refuted. 0 times theorem prover too weak. 367785 trivial. 0 not checked. [2018-12-02 04:10:34,815 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:10:34,816 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 56, 56] total 144 [2018-12-02 04:10:34,816 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:10:34,816 INFO L459 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-12-02 04:10:34,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-12-02 04:10:34,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3260, Invalid=17332, Unknown=0, NotChecked=0, Total=20592 [2018-12-02 04:10:34,817 INFO L87 Difference]: Start difference. First operand 2822 states and 2834 transitions. Second operand 117 states. [2018-12-02 04:10:38,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:10:38,385 INFO L93 Difference]: Finished difference Result 2542 states and 2547 transitions. [2018-12-02 04:10:38,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 141 states. [2018-12-02 04:10:38,385 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2463 [2018-12-02 04:10:38,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:10:38,388 INFO L225 Difference]: With dead ends: 2542 [2018-12-02 04:10:38,388 INFO L226 Difference]: Without dead ends: 2533 [2018-12-02 04:10:38,391 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5097 GetRequests, 4819 SyntacticMatches, 28 SemanticMatches, 250 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25500 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=9900, Invalid=53352, Unknown=0, NotChecked=0, Total=63252 [2018-12-02 04:10:38,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2533 states. [2018-12-02 04:10:38,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2533 to 2526. [2018-12-02 04:10:38,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2526 states. [2018-12-02 04:10:38,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2526 states to 2526 states and 2531 transitions. [2018-12-02 04:10:38,401 INFO L78 Accepts]: Start accepts. Automaton has 2526 states and 2531 transitions. Word has length 2463 [2018-12-02 04:10:38,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:10:38,402 INFO L480 AbstractCegarLoop]: Abstraction has 2526 states and 2531 transitions. [2018-12-02 04:10:38,402 INFO L481 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-12-02 04:10:38,402 INFO L276 IsEmpty]: Start isEmpty. Operand 2526 states and 2531 transitions. [2018-12-02 04:10:38,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2469 [2018-12-02 04:10:38,424 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:10:38,424 INFO L402 BasicCegarLoop]: trace histogram [433, 432, 432, 432, 432, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:10:38,424 INFO L423 AbstractCegarLoop]: === Iteration 89 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:10:38,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:10:38,425 INFO L82 PathProgramCache]: Analyzing trace with hash 154747760, now seen corresponding path program 74 times [2018-12-02 04:10:38,425 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:10:38,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:38,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:10:38,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:38,425 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:10:38,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:10:41,142 INFO L134 CoverageAnalysis]: Checked inductivity of 481977 backedges. 108469 proven. 5673 refuted. 0 times theorem prover too weak. 367835 trivial. 0 not checked. [2018-12-02 04:10:41,142 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:41,142 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:10:41,142 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:10:41,142 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:10:41,142 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:41,143 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:10:41,148 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:10:41,148 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:10:43,139 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-12-02 04:10:43,139 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:10:43,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:10:45,374 INFO L134 CoverageAnalysis]: Checked inductivity of 481977 backedges. 106660 proven. 5673 refuted. 0 times theorem prover too weak. 369644 trivial. 0 not checked. [2018-12-02 04:10:45,374 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:10:48,327 INFO L134 CoverageAnalysis]: Checked inductivity of 481977 backedges. 106551 proven. 5782 refuted. 0 times theorem prover too weak. 369644 trivial. 0 not checked. [2018-12-02 04:10:48,344 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:10:48,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 37, 37] total 131 [2018-12-02 04:10:48,345 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:10:48,346 INFO L459 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-12-02 04:10:48,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-12-02 04:10:48,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3365, Invalid=13665, Unknown=0, NotChecked=0, Total=17030 [2018-12-02 04:10:48,347 INFO L87 Difference]: Start difference. First operand 2526 states and 2531 transitions. Second operand 95 states. [2018-12-02 04:10:53,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:10:53,746 INFO L93 Difference]: Finished difference Result 2693 states and 2700 transitions. [2018-12-02 04:10:53,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-12-02 04:10:53,747 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 2468 [2018-12-02 04:10:53,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:10:53,757 INFO L225 Difference]: With dead ends: 2693 [2018-12-02 04:10:53,757 INFO L226 Difference]: Without dead ends: 2693 [2018-12-02 04:10:53,762 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5084 GetRequests, 4869 SyntacticMatches, 1 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14527 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=11852, Invalid=34588, Unknown=0, NotChecked=0, Total=46440 [2018-12-02 04:10:53,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2693 states. [2018-12-02 04:10:53,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2693 to 2683. [2018-12-02 04:10:53,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2683 states. [2018-12-02 04:10:53,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2683 states to 2683 states and 2690 transitions. [2018-12-02 04:10:53,785 INFO L78 Accepts]: Start accepts. Automaton has 2683 states and 2690 transitions. Word has length 2468 [2018-12-02 04:10:53,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:10:53,786 INFO L480 AbstractCegarLoop]: Abstraction has 2683 states and 2690 transitions. [2018-12-02 04:10:53,786 INFO L481 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-12-02 04:10:53,786 INFO L276 IsEmpty]: Start isEmpty. Operand 2683 states and 2690 transitions. [2018-12-02 04:10:53,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2474 [2018-12-02 04:10:53,811 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:10:53,811 INFO L402 BasicCegarLoop]: trace histogram [434, 433, 433, 433, 433, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:10:53,811 INFO L423 AbstractCegarLoop]: === Iteration 90 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:10:53,811 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:10:53,812 INFO L82 PathProgramCache]: Analyzing trace with hash -169898907, now seen corresponding path program 75 times [2018-12-02 04:10:53,812 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:10:53,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:53,812 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:10:53,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:10:53,812 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:10:54,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:10:55,942 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58810 proven. 2188 refuted. 0 times theorem prover too weak. 423168 trivial. 0 not checked. [2018-12-02 04:10:55,942 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:55,942 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:10:55,942 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:10:55,942 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:10:55,942 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:10:55,942 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:10:55,948 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:10:55,948 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:10:58,729 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:10:58,729 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:10:58,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:11:00,607 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58293 proven. 1946 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2018-12-02 04:11:00,607 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:11:02,839 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58293 proven. 1946 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2018-12-02 04:11:02,863 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:11:02,864 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 30, 30] total 95 [2018-12-02 04:11:02,864 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:11:02,864 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-12-02 04:11:02,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-12-02 04:11:02,865 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1127, Invalid=7993, Unknown=0, NotChecked=0, Total=9120 [2018-12-02 04:11:02,865 INFO L87 Difference]: Start difference. First operand 2683 states and 2690 transitions. Second operand 67 states. [2018-12-02 04:11:05,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:11:05,584 INFO L93 Difference]: Finished difference Result 3022 states and 3035 transitions. [2018-12-02 04:11:05,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-12-02 04:11:05,584 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 2473 [2018-12-02 04:11:05,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:11:05,588 INFO L225 Difference]: With dead ends: 3022 [2018-12-02 04:11:05,588 INFO L226 Difference]: Without dead ends: 3022 [2018-12-02 04:11:05,588 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5015 GetRequests, 4888 SyntacticMatches, 0 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3960 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=2053, Invalid=14459, Unknown=0, NotChecked=0, Total=16512 [2018-12-02 04:11:05,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3022 states. [2018-12-02 04:11:05,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3022 to 2993. [2018-12-02 04:11:05,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2993 states. [2018-12-02 04:11:05,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2993 states to 2993 states and 3005 transitions. [2018-12-02 04:11:05,601 INFO L78 Accepts]: Start accepts. Automaton has 2993 states and 3005 transitions. Word has length 2473 [2018-12-02 04:11:05,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:11:05,601 INFO L480 AbstractCegarLoop]: Abstraction has 2993 states and 3005 transitions. [2018-12-02 04:11:05,601 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-12-02 04:11:05,601 INFO L276 IsEmpty]: Start isEmpty. Operand 2993 states and 3005 transitions. [2018-12-02 04:11:05,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2625 [2018-12-02 04:11:05,625 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:11:05,626 INFO L402 BasicCegarLoop]: trace histogram [462, 461, 461, 461, 461, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:11:05,626 INFO L423 AbstractCegarLoop]: === Iteration 91 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:11:05,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:11:05,626 INFO L82 PathProgramCache]: Analyzing trace with hash -603003347, now seen corresponding path program 76 times [2018-12-02 04:11:05,626 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:11:05,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:05,626 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:11:05,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:05,627 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:11:05,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:11:08,676 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 114825 proven. 9656 refuted. 0 times theorem prover too weak. 423769 trivial. 0 not checked. [2018-12-02 04:11:08,677 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:08,677 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:11:08,677 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:11:08,677 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:11:08,677 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:08,677 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:11:08,683 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:11:08,683 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:11:09,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:11:09,104 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:11:12,334 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 172476 proven. 1782 refuted. 0 times theorem prover too weak. 373992 trivial. 0 not checked. [2018-12-02 04:11:12,335 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:11:15,969 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 118768 proven. 5621 refuted. 0 times theorem prover too weak. 423861 trivial. 0 not checked. [2018-12-02 04:11:15,986 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:11:15,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 58, 58] total 149 [2018-12-02 04:11:15,987 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:11:15,987 INFO L459 AbstractCegarLoop]: Interpolant automaton has 121 states [2018-12-02 04:11:15,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 121 interpolants. [2018-12-02 04:11:15,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3492, Invalid=18560, Unknown=0, NotChecked=0, Total=22052 [2018-12-02 04:11:15,988 INFO L87 Difference]: Start difference. First operand 2993 states and 3005 transitions. Second operand 121 states. [2018-12-02 04:11:19,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:11:19,599 INFO L93 Difference]: Finished difference Result 2703 states and 2708 transitions. [2018-12-02 04:11:19,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2018-12-02 04:11:19,600 INFO L78 Accepts]: Start accepts. Automaton has 121 states. Word has length 2624 [2018-12-02 04:11:19,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:11:19,602 INFO L225 Difference]: With dead ends: 2703 [2018-12-02 04:11:19,602 INFO L226 Difference]: Without dead ends: 2694 [2018-12-02 04:11:19,605 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5425 GetRequests, 5137 SyntacticMatches, 29 SemanticMatches, 259 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27425 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=10615, Invalid=57245, Unknown=0, NotChecked=0, Total=67860 [2018-12-02 04:11:19,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2694 states. [2018-12-02 04:11:19,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2694 to 2687. [2018-12-02 04:11:19,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2687 states. [2018-12-02 04:11:19,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2687 states to 2687 states and 2692 transitions. [2018-12-02 04:11:19,616 INFO L78 Accepts]: Start accepts. Automaton has 2687 states and 2692 transitions. Word has length 2624 [2018-12-02 04:11:19,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:11:19,617 INFO L480 AbstractCegarLoop]: Abstraction has 2687 states and 2692 transitions. [2018-12-02 04:11:19,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 121 states. [2018-12-02 04:11:19,617 INFO L276 IsEmpty]: Start isEmpty. Operand 2687 states and 2692 transitions. [2018-12-02 04:11:19,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2630 [2018-12-02 04:11:19,641 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:11:19,641 INFO L402 BasicCegarLoop]: trace histogram [463, 462, 462, 462, 462, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:11:19,642 INFO L423 AbstractCegarLoop]: === Iteration 92 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:11:19,642 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:11:19,642 INFO L82 PathProgramCache]: Analyzing trace with hash 1430424994, now seen corresponding path program 77 times [2018-12-02 04:11:19,642 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:11:19,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:19,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:11:19,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:19,643 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:11:19,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:11:22,665 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 120565 proven. 6093 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2018-12-02 04:11:22,665 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:22,665 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:11:22,665 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:11:22,666 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:11:22,666 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:22,666 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:11:22,671 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:11:22,671 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:11:24,590 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-12-02 04:11:24,590 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:11:24,607 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:11:27,069 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 118619 proven. 6093 refuted. 0 times theorem prover too weak. 425873 trivial. 0 not checked. [2018-12-02 04:11:27,069 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:11:30,266 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 118506 proven. 6206 refuted. 0 times theorem prover too weak. 425873 trivial. 0 not checked. [2018-12-02 04:11:30,284 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:11:30,285 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 38, 38] total 135 [2018-12-02 04:11:30,285 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:11:30,285 INFO L459 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-12-02 04:11:30,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-12-02 04:11:30,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3535, Invalid=14555, Unknown=0, NotChecked=0, Total=18090 [2018-12-02 04:11:30,286 INFO L87 Difference]: Start difference. First operand 2687 states and 2692 transitions. Second operand 98 states. [2018-12-02 04:11:32,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:11:32,854 INFO L93 Difference]: Finished difference Result 2859 states and 2866 transitions. [2018-12-02 04:11:32,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-12-02 04:11:32,855 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 2629 [2018-12-02 04:11:32,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:11:32,859 INFO L225 Difference]: With dead ends: 2859 [2018-12-02 04:11:32,859 INFO L226 Difference]: Without dead ends: 2859 [2018-12-02 04:11:32,862 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5411 GetRequests, 5189 SyntacticMatches, 1 SemanticMatches, 221 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15573 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=12575, Invalid=36931, Unknown=0, NotChecked=0, Total=49506 [2018-12-02 04:11:32,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2859 states. [2018-12-02 04:11:32,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2859 to 2849. [2018-12-02 04:11:32,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2849 states. [2018-12-02 04:11:32,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2849 states to 2849 states and 2856 transitions. [2018-12-02 04:11:32,875 INFO L78 Accepts]: Start accepts. Automaton has 2849 states and 2856 transitions. Word has length 2629 [2018-12-02 04:11:32,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:11:32,877 INFO L480 AbstractCegarLoop]: Abstraction has 2849 states and 2856 transitions. [2018-12-02 04:11:32,877 INFO L481 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-12-02 04:11:32,877 INFO L276 IsEmpty]: Start isEmpty. Operand 2849 states and 2856 transitions. [2018-12-02 04:11:32,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2635 [2018-12-02 04:11:32,903 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:11:32,903 INFO L402 BasicCegarLoop]: trace histogram [464, 463, 463, 463, 463, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:11:32,903 INFO L423 AbstractCegarLoop]: === Iteration 93 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:11:32,903 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:11:32,904 INFO L82 PathProgramCache]: Analyzing trace with hash 2134165351, now seen corresponding path program 78 times [2018-12-02 04:11:32,904 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:11:32,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:32,904 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:11:32,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:32,904 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:11:33,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:11:35,192 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64779 proven. 2353 refuted. 0 times theorem prover too weak. 485793 trivial. 0 not checked. [2018-12-02 04:11:35,193 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:35,193 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:11:35,193 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:11:35,193 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:11:35,193 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:35,193 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:11:35,214 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:11:35,214 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:11:36,344 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:11:36,344 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:11:36,375 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:11:38,412 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64638 proven. 2088 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-02 04:11:38,412 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:11:40,837 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64638 proven. 2088 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-02 04:11:40,862 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:11:40,863 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 31, 31] total 95 [2018-12-02 04:11:40,863 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:11:40,863 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-12-02 04:11:40,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-12-02 04:11:40,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1152, Invalid=7968, Unknown=0, NotChecked=0, Total=9120 [2018-12-02 04:11:40,864 INFO L87 Difference]: Start difference. First operand 2849 states and 2856 transitions. Second operand 66 states. [2018-12-02 04:11:44,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:11:44,076 INFO L93 Difference]: Finished difference Result 3198 states and 3211 transitions. [2018-12-02 04:11:44,076 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-12-02 04:11:44,076 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 2634 [2018-12-02 04:11:44,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:11:44,080 INFO L225 Difference]: With dead ends: 3198 [2018-12-02 04:11:44,080 INFO L226 Difference]: Without dead ends: 3198 [2018-12-02 04:11:44,081 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5336 GetRequests, 5208 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3949 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=2010, Invalid=14760, Unknown=0, NotChecked=0, Total=16770 [2018-12-02 04:11:44,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3198 states. [2018-12-02 04:11:44,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3198 to 3169. [2018-12-02 04:11:44,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3169 states. [2018-12-02 04:11:44,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3169 states to 3169 states and 3181 transitions. [2018-12-02 04:11:44,096 INFO L78 Accepts]: Start accepts. Automaton has 3169 states and 3181 transitions. Word has length 2634 [2018-12-02 04:11:44,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:11:44,098 INFO L480 AbstractCegarLoop]: Abstraction has 3169 states and 3181 transitions. [2018-12-02 04:11:44,098 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-12-02 04:11:44,098 INFO L276 IsEmpty]: Start isEmpty. Operand 3169 states and 3181 transitions. [2018-12-02 04:11:44,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2791 [2018-12-02 04:11:44,129 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:11:44,130 INFO L402 BasicCegarLoop]: trace histogram [493, 492, 492, 492, 492, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:11:44,130 INFO L423 AbstractCegarLoop]: === Iteration 94 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:11:44,130 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:11:44,130 INFO L82 PathProgramCache]: Analyzing trace with hash -356784400, now seen corresponding path program 79 times [2018-12-02 04:11:44,130 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:11:44,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:44,130 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:11:44,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:11:44,131 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:11:44,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:11:47,483 INFO L134 CoverageAnalysis]: Checked inductivity of 623764 backedges. 127366 proven. 10363 refuted. 0 times theorem prover too weak. 486035 trivial. 0 not checked. [2018-12-02 04:11:47,483 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:47,483 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:11:47,483 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:11:47,483 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:11:47,483 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:11:47,484 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:11:47,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:11:47,490 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:11:47,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:11:47,904 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:11:51,393 INFO L134 CoverageAnalysis]: Checked inductivity of 623764 backedges. 191339 proven. 1918 refuted. 0 times theorem prover too weak. 430507 trivial. 0 not checked. [2018-12-02 04:11:51,393 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:11:55,369 INFO L134 CoverageAnalysis]: Checked inductivity of 623764 backedges. 131609 proven. 6039 refuted. 0 times theorem prover too weak. 486116 trivial. 0 not checked. [2018-12-02 04:11:55,386 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:11:55,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 60, 60] total 154 [2018-12-02 04:11:55,387 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:11:55,388 INFO L459 AbstractCegarLoop]: Interpolant automaton has 125 states [2018-12-02 04:11:55,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2018-12-02 04:11:55,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3732, Invalid=19830, Unknown=0, NotChecked=0, Total=23562 [2018-12-02 04:11:55,389 INFO L87 Difference]: Start difference. First operand 3169 states and 3181 transitions. Second operand 125 states. [2018-12-02 04:12:05,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:12:05,124 INFO L93 Difference]: Finished difference Result 2869 states and 2874 transitions. [2018-12-02 04:12:05,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-12-02 04:12:05,125 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 2790 [2018-12-02 04:12:05,126 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:12:05,128 INFO L225 Difference]: With dead ends: 2869 [2018-12-02 04:12:05,128 INFO L226 Difference]: Without dead ends: 2860 [2018-12-02 04:12:05,130 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5763 GetRequests, 5465 SyntacticMatches, 30 SemanticMatches, 268 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29420 ImplicationChecksByTransitivity, 8.0s TimeCoverageRelationStatistics Valid=11355, Invalid=61275, Unknown=0, NotChecked=0, Total=72630 [2018-12-02 04:12:05,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2860 states. [2018-12-02 04:12:05,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2860 to 2853. [2018-12-02 04:12:05,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2853 states. [2018-12-02 04:12:05,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2853 states to 2853 states and 2858 transitions. [2018-12-02 04:12:05,142 INFO L78 Accepts]: Start accepts. Automaton has 2853 states and 2858 transitions. Word has length 2790 [2018-12-02 04:12:05,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:12:05,143 INFO L480 AbstractCegarLoop]: Abstraction has 2853 states and 2858 transitions. [2018-12-02 04:12:05,143 INFO L481 AbstractCegarLoop]: Interpolant automaton has 125 states. [2018-12-02 04:12:05,143 INFO L276 IsEmpty]: Start isEmpty. Operand 2853 states and 2858 transitions. [2018-12-02 04:12:05,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2796 [2018-12-02 04:12:05,170 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:12:05,171 INFO L402 BasicCegarLoop]: trace histogram [494, 493, 493, 493, 493, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:12:05,171 INFO L423 AbstractCegarLoop]: === Iteration 95 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:12:05,171 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:12:05,171 INFO L82 PathProgramCache]: Analyzing trace with hash 945686987, now seen corresponding path program 80 times [2018-12-02 04:12:05,171 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:12:05,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:05,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:12:05,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:05,172 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:12:05,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:12:08,534 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 133528 proven. 6528 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-02 04:12:08,534 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:12:08,534 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:12:08,534 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:12:08,534 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:12:08,535 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:12:08,535 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:12:08,540 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:12:08,541 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:12:13,274 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-12-02 04:12:13,274 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:12:13,294 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:12:15,968 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 131440 proven. 6528 refuted. 0 times theorem prover too weak. 488287 trivial. 0 not checked. [2018-12-02 04:12:15,968 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:12:19,400 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 131323 proven. 6645 refuted. 0 times theorem prover too weak. 488287 trivial. 0 not checked. [2018-12-02 04:12:19,418 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:12:19,419 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 39, 39] total 139 [2018-12-02 04:12:19,419 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:12:19,419 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-12-02 04:12:19,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-12-02 04:12:19,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3706, Invalid=15476, Unknown=0, NotChecked=0, Total=19182 [2018-12-02 04:12:19,420 INFO L87 Difference]: Start difference. First operand 2853 states and 2858 transitions. Second operand 101 states. [2018-12-02 04:12:22,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:12:22,097 INFO L93 Difference]: Finished difference Result 3030 states and 3037 transitions. [2018-12-02 04:12:22,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-12-02 04:12:22,097 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2795 [2018-12-02 04:12:22,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:12:22,100 INFO L225 Difference]: With dead ends: 3030 [2018-12-02 04:12:22,100 INFO L226 Difference]: Without dead ends: 3030 [2018-12-02 04:12:22,102 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5748 GetRequests, 5519 SyntacticMatches, 1 SemanticMatches, 228 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16657 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=13315, Invalid=39355, Unknown=0, NotChecked=0, Total=52670 [2018-12-02 04:12:22,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3030 states. [2018-12-02 04:12:22,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3030 to 3020. [2018-12-02 04:12:22,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3020 states. [2018-12-02 04:12:22,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3020 states to 3020 states and 3027 transitions. [2018-12-02 04:12:22,123 INFO L78 Accepts]: Start accepts. Automaton has 3020 states and 3027 transitions. Word has length 2795 [2018-12-02 04:12:22,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:12:22,124 INFO L480 AbstractCegarLoop]: Abstraction has 3020 states and 3027 transitions. [2018-12-02 04:12:22,124 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-12-02 04:12:22,124 INFO L276 IsEmpty]: Start isEmpty. Operand 3020 states and 3027 transitions. [2018-12-02 04:12:22,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2801 [2018-12-02 04:12:22,151 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:12:22,151 INFO L402 BasicCegarLoop]: trace histogram [495, 494, 494, 494, 494, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:12:22,151 INFO L423 AbstractCegarLoop]: === Iteration 96 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:12:22,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:12:22,151 INFO L82 PathProgramCache]: Analyzing trace with hash 601825130, now seen corresponding path program 81 times [2018-12-02 04:12:22,151 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:12:22,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:22,152 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:12:22,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:22,152 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:12:22,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:12:24,715 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71715 proven. 2524 refuted. 0 times theorem prover too weak. 554512 trivial. 0 not checked. [2018-12-02 04:12:24,715 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:12:24,716 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:12:24,716 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:12:24,716 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:12:24,716 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:12:24,716 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:12:24,721 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:12:24,722 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:12:32,006 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:12:32,006 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:12:32,042 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:12:34,285 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71427 proven. 2235 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-02 04:12:34,285 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:12:37,025 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71427 proven. 2235 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-02 04:12:37,054 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:12:37,055 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 32, 32] total 99 [2018-12-02 04:12:37,055 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:12:37,055 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-02 04:12:37,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-02 04:12:37,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1195, Invalid=8705, Unknown=0, NotChecked=0, Total=9900 [2018-12-02 04:12:37,056 INFO L87 Difference]: Start difference. First operand 3020 states and 3027 transitions. Second operand 69 states. [2018-12-02 04:12:40,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:12:40,114 INFO L93 Difference]: Finished difference Result 3379 states and 3392 transitions. [2018-12-02 04:12:40,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-12-02 04:12:40,114 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 2800 [2018-12-02 04:12:40,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:12:40,118 INFO L225 Difference]: With dead ends: 3379 [2018-12-02 04:12:40,118 INFO L226 Difference]: Without dead ends: 3379 [2018-12-02 04:12:40,119 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5671 GetRequests, 5538 SyntacticMatches, 0 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4264 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2094, Invalid=15996, Unknown=0, NotChecked=0, Total=18090 [2018-12-02 04:12:40,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3379 states. [2018-12-02 04:12:40,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3379 to 3350. [2018-12-02 04:12:40,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3350 states. [2018-12-02 04:12:40,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3350 states to 3350 states and 3362 transitions. [2018-12-02 04:12:40,134 INFO L78 Accepts]: Start accepts. Automaton has 3350 states and 3362 transitions. Word has length 2800 [2018-12-02 04:12:40,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:12:40,135 INFO L480 AbstractCegarLoop]: Abstraction has 3350 states and 3362 transitions. [2018-12-02 04:12:40,135 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-02 04:12:40,135 INFO L276 IsEmpty]: Start isEmpty. Operand 3350 states and 3362 transitions. [2018-12-02 04:12:40,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2962 [2018-12-02 04:12:40,165 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:12:40,166 INFO L402 BasicCegarLoop]: trace histogram [525, 524, 524, 524, 524, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:12:40,166 INFO L423 AbstractCegarLoop]: === Iteration 97 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:12:40,166 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:12:40,166 INFO L82 PathProgramCache]: Analyzing trace with hash -1148647064, now seen corresponding path program 82 times [2018-12-02 04:12:40,166 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:12:40,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:40,167 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:12:40,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:40,167 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:12:40,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:12:43,843 INFO L134 CoverageAnalysis]: Checked inductivity of 706803 backedges. 140789 proven. 11095 refuted. 0 times theorem prover too weak. 554919 trivial. 0 not checked. [2018-12-02 04:12:43,844 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:12:43,844 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:12:43,844 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:12:43,844 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:12:43,844 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:12:43,844 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:12:43,852 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:12:43,852 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:12:44,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:12:44,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:12:48,206 INFO L134 CoverageAnalysis]: Checked inductivity of 706803 backedges. 211528 proven. 2059 refuted. 0 times theorem prover too weak. 493216 trivial. 0 not checked. [2018-12-02 04:12:48,207 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:12:52,604 INFO L134 CoverageAnalysis]: Checked inductivity of 706803 backedges. 145343 proven. 6472 refuted. 0 times theorem prover too weak. 554988 trivial. 0 not checked. [2018-12-02 04:12:52,622 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:12:52,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 62, 62] total 159 [2018-12-02 04:12:52,623 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:12:52,623 INFO L459 AbstractCegarLoop]: Interpolant automaton has 129 states [2018-12-02 04:12:52,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 129 interpolants. [2018-12-02 04:12:52,624 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3980, Invalid=21142, Unknown=0, NotChecked=0, Total=25122 [2018-12-02 04:12:52,624 INFO L87 Difference]: Start difference. First operand 3350 states and 3362 transitions. Second operand 129 states. [2018-12-02 04:12:57,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:12:57,618 INFO L93 Difference]: Finished difference Result 3040 states and 3045 transitions. [2018-12-02 04:12:57,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 156 states. [2018-12-02 04:12:57,618 INFO L78 Accepts]: Start accepts. Automaton has 129 states. Word has length 2961 [2018-12-02 04:12:57,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:12:57,621 INFO L225 Difference]: With dead ends: 3040 [2018-12-02 04:12:57,621 INFO L226 Difference]: Without dead ends: 3031 [2018-12-02 04:12:57,623 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6111 GetRequests, 5803 SyntacticMatches, 31 SemanticMatches, 277 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31485 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=12120, Invalid=65442, Unknown=0, NotChecked=0, Total=77562 [2018-12-02 04:12:57,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3031 states. [2018-12-02 04:12:57,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3031 to 3024. [2018-12-02 04:12:57,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3024 states. [2018-12-02 04:12:57,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3024 states to 3024 states and 3029 transitions. [2018-12-02 04:12:57,634 INFO L78 Accepts]: Start accepts. Automaton has 3024 states and 3029 transitions. Word has length 2961 [2018-12-02 04:12:57,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:12:57,635 INFO L480 AbstractCegarLoop]: Abstraction has 3024 states and 3029 transitions. [2018-12-02 04:12:57,635 INFO L481 AbstractCegarLoop]: Interpolant automaton has 129 states. [2018-12-02 04:12:57,635 INFO L276 IsEmpty]: Start isEmpty. Operand 3024 states and 3029 transitions. [2018-12-02 04:12:57,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2967 [2018-12-02 04:12:57,666 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:12:57,666 INFO L402 BasicCegarLoop]: trace histogram [526, 525, 525, 525, 525, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:12:57,666 INFO L423 AbstractCegarLoop]: === Iteration 98 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:12:57,666 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:12:57,667 INFO L82 PathProgramCache]: Analyzing trace with hash -643366969, now seen corresponding path program 83 times [2018-12-02 04:12:57,667 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:12:57,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:57,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:12:57,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:12:57,667 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:12:57,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:13:01,377 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 147388 proven. 6978 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-02 04:13:01,377 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:01,377 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:13:01,377 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:13:01,377 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:13:01,377 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:01,378 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:13:01,385 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:13:01,385 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:13:05,178 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 32 check-sat command(s) [2018-12-02 04:13:05,178 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:13:05,197 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:13:08,067 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 78518 proven. 2387 refuted. 0 times theorem prover too weak. 628550 trivial. 0 not checked. [2018-12-02 04:13:08,067 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:13:10,910 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 78518 proven. 2387 refuted. 0 times theorem prover too weak. 628550 trivial. 0 not checked. [2018-12-02 04:13:10,929 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:13:10,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 34, 34] total 105 [2018-12-02 04:13:10,930 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:13:10,931 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-12-02 04:13:10,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-12-02 04:13:10,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1674, Invalid=9246, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 04:13:10,931 INFO L87 Difference]: Start difference. First operand 3024 states and 3029 transitions. Second operand 103 states. [2018-12-02 04:13:15,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:13:15,702 INFO L93 Difference]: Finished difference Result 3214 states and 3222 transitions. [2018-12-02 04:13:15,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2018-12-02 04:13:15,702 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 2966 [2018-12-02 04:13:15,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:13:15,706 INFO L225 Difference]: With dead ends: 3214 [2018-12-02 04:13:15,706 INFO L226 Difference]: Without dead ends: 3214 [2018-12-02 04:13:15,707 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6096 GetRequests, 5867 SyntacticMatches, 31 SemanticMatches, 198 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12218 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=9168, Invalid=30632, Unknown=0, NotChecked=0, Total=39800 [2018-12-02 04:13:15,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3214 states. [2018-12-02 04:13:15,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3214 to 3201. [2018-12-02 04:13:15,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3201 states. [2018-12-02 04:13:15,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3201 states to 3201 states and 3209 transitions. [2018-12-02 04:13:15,721 INFO L78 Accepts]: Start accepts. Automaton has 3201 states and 3209 transitions. Word has length 2966 [2018-12-02 04:13:15,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:13:15,722 INFO L480 AbstractCegarLoop]: Abstraction has 3201 states and 3209 transitions. [2018-12-02 04:13:15,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-12-02 04:13:15,722 INFO L276 IsEmpty]: Start isEmpty. Operand 3201 states and 3209 transitions. [2018-12-02 04:13:15,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2977 [2018-12-02 04:13:15,752 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:13:15,752 INFO L402 BasicCegarLoop]: trace histogram [528, 527, 527, 527, 527, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:13:15,752 INFO L423 AbstractCegarLoop]: === Iteration 99 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:13:15,753 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:13:15,753 INFO L82 PathProgramCache]: Analyzing trace with hash -310569395, now seen corresponding path program 84 times [2018-12-02 04:13:15,753 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:13:15,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:13:15,753 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:13:15,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:13:15,753 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:13:16,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:13:19,252 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83691 proven. 2733 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2018-12-02 04:13:19,252 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:19,252 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:13:19,252 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:13:19,252 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:13:19,252 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:19,252 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:13:19,261 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 04:13:19,261 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-02 04:13:19,644 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 04:13:19,644 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:13:19,670 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:13:23,150 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83459 proven. 8569 refuted. 0 times theorem prover too weak. 622746 trivial. 0 not checked. [2018-12-02 04:13:23,150 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:13:26,329 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83459 proven. 8569 refuted. 0 times theorem prover too weak. 622746 trivial. 0 not checked. [2018-12-02 04:13:26,346 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:13:26,347 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 71, 71] total 109 [2018-12-02 04:13:26,347 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:13:26,348 INFO L459 AbstractCegarLoop]: Interpolant automaton has 106 states [2018-12-02 04:13:26,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 106 interpolants. [2018-12-02 04:13:26,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2377, Invalid=9395, Unknown=0, NotChecked=0, Total=11772 [2018-12-02 04:13:26,349 INFO L87 Difference]: Start difference. First operand 3201 states and 3209 transitions. Second operand 106 states. [2018-12-02 04:13:29,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:13:29,018 INFO L93 Difference]: Finished difference Result 3555 states and 3567 transitions. [2018-12-02 04:13:29,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2018-12-02 04:13:29,019 INFO L78 Accepts]: Start accepts. Automaton has 106 states. Word has length 2976 [2018-12-02 04:13:29,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:13:29,025 INFO L225 Difference]: With dead ends: 3555 [2018-12-02 04:13:29,025 INFO L226 Difference]: Without dead ends: 3555 [2018-12-02 04:13:29,027 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6084 GetRequests, 5845 SyntacticMatches, 67 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9841 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=6678, Invalid=23424, Unknown=0, NotChecked=0, Total=30102 [2018-12-02 04:13:29,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states. [2018-12-02 04:13:29,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3541. [2018-12-02 04:13:29,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3541 states. [2018-12-02 04:13:29,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3541 states to 3541 states and 3553 transitions. [2018-12-02 04:13:29,052 INFO L78 Accepts]: Start accepts. Automaton has 3541 states and 3553 transitions. Word has length 2976 [2018-12-02 04:13:29,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:13:29,053 INFO L480 AbstractCegarLoop]: Abstraction has 3541 states and 3553 transitions. [2018-12-02 04:13:29,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 106 states. [2018-12-02 04:13:29,053 INFO L276 IsEmpty]: Start isEmpty. Operand 3541 states and 3553 transitions. [2018-12-02 04:13:29,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3138 [2018-12-02 04:13:29,088 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:13:29,089 INFO L402 BasicCegarLoop]: trace histogram [558, 557, 557, 557, 557, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:13:29,089 INFO L423 AbstractCegarLoop]: === Iteration 100 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:13:29,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:13:29,089 INFO L82 PathProgramCache]: Analyzing trace with hash -182742773, now seen corresponding path program 85 times [2018-12-02 04:13:29,089 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:13:29,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:13:29,090 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:13:29,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:13:29,090 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:13:29,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:13:33,178 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 155124 proven. 11852 refuted. 0 times theorem prover too weak. 630874 trivial. 0 not checked. [2018-12-02 04:13:33,178 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:33,178 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:13:33,178 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:13:33,178 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:13:33,178 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:33,178 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:13:33,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:13:33,184 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:13:33,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:13:33,661 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:13:38,015 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 233088 proven. 2205 refuted. 0 times theorem prover too weak. 562557 trivial. 0 not checked. [2018-12-02 04:13:38,015 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:13:42,787 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 160000 proven. 6920 refuted. 0 times theorem prover too weak. 630930 trivial. 0 not checked. [2018-12-02 04:13:42,805 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:13:42,806 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 64, 64] total 164 [2018-12-02 04:13:42,806 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:13:42,806 INFO L459 AbstractCegarLoop]: Interpolant automaton has 133 states [2018-12-02 04:13:42,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 133 interpolants. [2018-12-02 04:13:42,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4236, Invalid=22496, Unknown=0, NotChecked=0, Total=26732 [2018-12-02 04:13:42,808 INFO L87 Difference]: Start difference. First operand 3541 states and 3553 transitions. Second operand 133 states. [2018-12-02 04:13:47,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:13:47,746 INFO L93 Difference]: Finished difference Result 3216 states and 3221 transitions. [2018-12-02 04:13:47,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2018-12-02 04:13:47,746 INFO L78 Accepts]: Start accepts. Automaton has 133 states. Word has length 3137 [2018-12-02 04:13:47,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:13:47,749 INFO L225 Difference]: With dead ends: 3216 [2018-12-02 04:13:47,750 INFO L226 Difference]: Without dead ends: 3207 [2018-12-02 04:13:47,753 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6469 GetRequests, 6151 SyntacticMatches, 32 SemanticMatches, 286 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33620 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=12910, Invalid=69746, Unknown=0, NotChecked=0, Total=82656 [2018-12-02 04:13:47,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3207 states. [2018-12-02 04:13:47,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3207 to 3200. [2018-12-02 04:13:47,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3200 states. [2018-12-02 04:13:47,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3200 states to 3200 states and 3205 transitions. [2018-12-02 04:13:47,765 INFO L78 Accepts]: Start accepts. Automaton has 3200 states and 3205 transitions. Word has length 3137 [2018-12-02 04:13:47,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:13:47,766 INFO L480 AbstractCegarLoop]: Abstraction has 3200 states and 3205 transitions. [2018-12-02 04:13:47,766 INFO L481 AbstractCegarLoop]: Interpolant automaton has 133 states. [2018-12-02 04:13:47,766 INFO L276 IsEmpty]: Start isEmpty. Operand 3200 states and 3205 transitions. [2018-12-02 04:13:47,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3143 [2018-12-02 04:13:47,800 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:13:47,800 INFO L402 BasicCegarLoop]: trace histogram [559, 558, 558, 558, 558, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:13:47,800 INFO L423 AbstractCegarLoop]: === Iteration 101 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:13:47,801 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:13:47,801 INFO L82 PathProgramCache]: Analyzing trace with hash -1867759088, now seen corresponding path program 86 times [2018-12-02 04:13:47,801 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:13:47,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:13:47,802 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:13:47,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:13:47,802 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:13:48,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:13:51,927 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 162175 proven. 7443 refuted. 0 times theorem prover too weak. 631050 trivial. 0 not checked. [2018-12-02 04:13:51,927 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:51,927 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:13:51,927 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-02 04:13:51,927 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-02 04:13:51,927 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:13:51,927 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:13:51,933 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 04:13:51,933 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-02 04:13:56,226 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-12-02 04:13:56,226 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 04:13:56,250 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:13:59,564 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 159788 proven. 7443 refuted. 0 times theorem prover too weak. 633437 trivial. 0 not checked. [2018-12-02 04:13:59,564 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:14:03,707 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 159663 proven. 7568 refuted. 0 times theorem prover too weak. 633437 trivial. 0 not checked. [2018-12-02 04:14:03,727 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-02 04:14:03,728 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 41, 41] total 142 [2018-12-02 04:14:03,728 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-02 04:14:03,728 INFO L459 AbstractCegarLoop]: Interpolant automaton has 107 states [2018-12-02 04:14:03,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2018-12-02 04:14:03,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3964, Invalid=16058, Unknown=0, NotChecked=0, Total=20022 [2018-12-02 04:14:03,729 INFO L87 Difference]: Start difference. First operand 3200 states and 3205 transitions. Second operand 107 states. [2018-12-02 04:14:07,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:14:07,217 INFO L93 Difference]: Finished difference Result 3387 states and 3394 transitions. [2018-12-02 04:14:07,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2018-12-02 04:14:07,217 INFO L78 Accepts]: Start accepts. Automaton has 107 states. Word has length 3142 [2018-12-02 04:14:07,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:14:07,221 INFO L225 Difference]: With dead ends: 3387 [2018-12-02 04:14:07,221 INFO L226 Difference]: Without dead ends: 3387 [2018-12-02 04:14:07,224 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6452 GetRequests, 6209 SyntacticMatches, 6 SemanticMatches, 237 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18963 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=14033, Invalid=42849, Unknown=0, NotChecked=0, Total=56882 [2018-12-02 04:14:07,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3387 states. [2018-12-02 04:14:07,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3387 to 3377. [2018-12-02 04:14:07,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3377 states. [2018-12-02 04:14:07,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3377 states to 3377 states and 3384 transitions. [2018-12-02 04:14:07,240 INFO L78 Accepts]: Start accepts. Automaton has 3377 states and 3384 transitions. Word has length 3142 [2018-12-02 04:14:07,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:14:07,241 INFO L480 AbstractCegarLoop]: Abstraction has 3377 states and 3384 transitions. [2018-12-02 04:14:07,241 INFO L481 AbstractCegarLoop]: Interpolant automaton has 107 states. [2018-12-02 04:14:07,241 INFO L276 IsEmpty]: Start isEmpty. Operand 3377 states and 3384 transitions. [2018-12-02 04:14:07,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3148 [2018-12-02 04:14:07,275 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:14:07,275 INFO L402 BasicCegarLoop]: trace histogram [560, 559, 559, 559, 559, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:14:07,275 INFO L423 AbstractCegarLoop]: === Iteration 102 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION]=== [2018-12-02 04:14:07,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:14:07,276 INFO L82 PathProgramCache]: Analyzing trace with hash -486718779, now seen corresponding path program 87 times [2018-12-02 04:14:07,276 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:14:07,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:14:07,276 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 04:14:07,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:14:07,276 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:14:08,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 04:14:08,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 04:14:09,306 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 04:14:09,580 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 04:14:09 BoogieIcfgContainer [2018-12-02 04:14:09,580 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 04:14:09,580 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 04:14:09,580 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 04:14:09,580 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 04:14:09,581 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:05:07" (3/4) ... [2018-12-02 04:14:09,582 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-02 04:14:09,846 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_fbdcc59c-4908-4e5a-9607-13face5cf8cd/bin-2019/utaipan/witness.graphml [2018-12-02 04:14:09,846 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 04:14:09,847 INFO L168 Benchmark]: Toolchain (without parser) took 543001.46 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 950.8 MB in the beginning and 3.3 GB in the end (delta: -2.4 GB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2018-12-02 04:14:09,848 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:14:09,848 INFO L168 Benchmark]: CACSL2BoogieTranslator took 126.56 ms. Allocated memory is still 1.0 GB. Free memory was 950.8 MB in the beginning and 939.0 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 11.5 GB. [2018-12-02 04:14:09,848 INFO L168 Benchmark]: Boogie Procedure Inliner took 13.69 ms. Allocated memory is still 1.0 GB. Free memory is still 939.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:14:09,848 INFO L168 Benchmark]: Boogie Preprocessor took 49.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 939.0 MB in the beginning and 1.1 GB in the end (delta: -194.8 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. [2018-12-02 04:14:09,848 INFO L168 Benchmark]: RCFGBuilder took 147.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 18.4 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. [2018-12-02 04:14:09,849 INFO L168 Benchmark]: TraceAbstraction took 542395.62 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.4 GB in the end (delta: -2.3 GB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2018-12-02 04:14:09,849 INFO L168 Benchmark]: Witness Printer took 266.21 ms. Allocated memory is still 5.0 GB. Free memory was 3.4 GB in the beginning and 3.3 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. [2018-12-02 04:14:09,850 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 126.56 ms. Allocated memory is still 1.0 GB. Free memory was 950.8 MB in the beginning and 939.0 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 13.69 ms. Allocated memory is still 1.0 GB. Free memory is still 939.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 49.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 939.0 MB in the beginning and 1.1 GB in the end (delta: -194.8 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 147.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 18.4 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 542395.62 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.4 GB in the end (delta: -2.3 GB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. * Witness Printer took 266.21 ms. Allocated memory is still 5.0 GB. Free memory was 3.4 GB in the beginning and 3.3 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] char mask[32]; [L26] i = 0 VAL [b={157:0}, i=0, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=0, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=148, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=162, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L20] return i; VAL [\old(size)=1, \result=2, b={140:0}, b={140:0}, i=2, size=1] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=2, i=0, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=2, i=0, mask={140:0}] [L26] i++ VAL [b={157:0}, i=1, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=1, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=148, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=162, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=143, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L20] return i; VAL [\old(size)=2, \result=3, b={140:0}, b={140:0}, i=3, size=2] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=3, i=1, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=3, i=1, mask={140:0}] [L26] i++ VAL [b={157:0}, i=2, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=2, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=148, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=162, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=143, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=131, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L20] return i; VAL [\old(size)=3, \result=4, b={140:0}, b={140:0}, i=4, size=3] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=4, i=2, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=4, i=2, mask={140:0}] [L26] i++ VAL [b={157:0}, i=3, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=3, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=148, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=162, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=143, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=131, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=130, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L20] return i; VAL [\old(size)=4, \result=5, b={140:0}, b={140:0}, i=5, size=4] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=5, i=3, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=5, i=3, mask={140:0}] [L26] i++ VAL [b={157:0}, i=4, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=4, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=148, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=162, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=143, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=131, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=130, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=139, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L20] return i; VAL [\old(size)=5, \result=6, b={140:0}, b={140:0}, i=6, size=5] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=6, i=4, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=6, i=4, mask={140:0}] [L26] i++ VAL [b={157:0}, i=5, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=5, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=148, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=162, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=143, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=131, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=130, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=139, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=129, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L20] return i; VAL [\old(size)=6, \result=7, b={140:0}, b={140:0}, i=7, size=6] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=7, i=5, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=7, i=5, mask={140:0}] [L26] i++ VAL [b={157:0}, i=6, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=6, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=148, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=162, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=143, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=131, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=130, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=139, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=129, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=149, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L20] return i; VAL [\old(size)=7, \result=8, b={140:0}, b={140:0}, i=8, size=7] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=8, i=6, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=8, i=6, mask={140:0}] [L26] i++ VAL [b={157:0}, i=7, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=7, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=148, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=162, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=143, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=131, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=130, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=139, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=129, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=149, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=155, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L20] return i; VAL [\old(size)=8, \result=9, b={140:0}, b={140:0}, i=9, size=8] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=9, i=7, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=9, i=7, mask={140:0}] [L26] i++ VAL [b={157:0}, i=8, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=8, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=148, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=162, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=143, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=131, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=130, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=139, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=129, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=149, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=155, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=135, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L20] return i; VAL [\old(size)=9, \result=10, b={140:0}, b={140:0}, i=10, size=9] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=10, i=8, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=10, i=8, mask={140:0}] [L26] i++ VAL [b={157:0}, i=9, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=9, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=148, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=162, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=143, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=131, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=130, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=139, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=129, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=149, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=155, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=135, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L20] return i; VAL [\old(size)=10, \result=11, b={140:0}, b={140:0}, i=11, size=10] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=11, i=9, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=11, i=9, mask={140:0}] [L26] i++ VAL [b={157:0}, i=10, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=10, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=148, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=162, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=143, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=131, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=130, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=139, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=129, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=149, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=155, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=135, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=146, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L20] return i; VAL [\old(size)=11, \result=12, b={140:0}, b={140:0}, i=12, size=11] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=12, i=10, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=12, i=10, mask={140:0}] [L26] i++ VAL [b={157:0}, i=11, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=11, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=148, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=162, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=143, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=131, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=130, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=139, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=129, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=149, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=155, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=135, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=146, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=151, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L20] return i; VAL [\old(size)=12, \result=13, b={140:0}, b={140:0}, i=13, size=12] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=13, i=11, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=13, i=11, mask={140:0}] [L26] i++ VAL [b={157:0}, i=12, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=12, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=148, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=162, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=143, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=131, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=130, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=139, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=129, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=149, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=155, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=135, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=146, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=151, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=158, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L20] return i; VAL [\old(size)=13, \result=14, b={140:0}, b={140:0}, i=14, size=13] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=14, i=12, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=14, i=12, mask={140:0}] [L26] i++ VAL [b={157:0}, i=13, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=13, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=148, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=162, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=143, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=131, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=130, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=139, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=129, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=149, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=155, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=135, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=146, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=151, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=158, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=154, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L20] return i; VAL [\old(size)=14, \result=15, b={140:0}, b={140:0}, i=15, size=14] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=15, i=13, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=15, i=13, mask={140:0}] [L26] i++ VAL [b={157:0}, i=14, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=14, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=148, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=162, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=143, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=131, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=130, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=139, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=129, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=149, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=155, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=135, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=146, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=151, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=158, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=154, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=136, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L20] return i; VAL [\old(size)=15, \result=16, b={140:0}, b={140:0}, i=16, size=15] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=16, i=14, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=16, i=14, mask={140:0}] [L26] i++ VAL [b={157:0}, i=15, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=15, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=148, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=162, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=143, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=131, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=130, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=139, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=129, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=149, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=155, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=135, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=146, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=151, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=158, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=154, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=136, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=138, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L20] return i; VAL [\old(size)=16, \result=17, b={140:0}, b={140:0}, i=17, size=16] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=17, i=15, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=17, i=15, mask={140:0}] [L26] i++ VAL [b={157:0}, i=16, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=16, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=148, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=162, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=143, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=131, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=130, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=139, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=129, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=149, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=155, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=135, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=146, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=151, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=158, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=154, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=136, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=138, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=152, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L20] return i; VAL [\old(size)=17, \result=18, b={140:0}, b={140:0}, i=18, size=17] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=18, i=16, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=18, i=16, mask={140:0}] [L26] i++ VAL [b={157:0}, i=17, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=17, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=148, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=162, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=143, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=131, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=130, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=139, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=129, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=149, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=155, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=135, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=146, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=151, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=158, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=154, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=136, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=138, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=152, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=141, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L20] return i; VAL [\old(size)=18, \result=19, b={140:0}, b={140:0}, i=19, size=18] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=19, i=17, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=19, i=17, mask={140:0}] [L26] i++ VAL [b={157:0}, i=18, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=18, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=148, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=162, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=143, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=131, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=130, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=139, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=129, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=149, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=155, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=135, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=146, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=151, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=158, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=154, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=136, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=138, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=152, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=141, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=132, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L20] return i; VAL [\old(size)=19, \result=20, b={140:0}, b={140:0}, i=20, size=19] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=20, i=18, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=20, i=18, mask={140:0}] [L26] i++ VAL [b={157:0}, i=19, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=19, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=148, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=162, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=143, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=131, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=130, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=139, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=129, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=149, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=155, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=135, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=146, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=151, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=158, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=154, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=136, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=138, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=152, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=141, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=132, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=133, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L20] return i; VAL [\old(size)=20, \result=21, b={140:0}, b={140:0}, i=21, size=20] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=21, i=19, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=21, i=19, mask={140:0}] [L26] i++ VAL [b={157:0}, i=20, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=20, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=148, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=162, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=143, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=131, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=130, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=139, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=129, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=149, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=155, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=135, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=146, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=151, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=158, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=154, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=136, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=138, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=152, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=141, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=132, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=133, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=137, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L20] return i; VAL [\old(size)=21, \result=22, b={140:0}, b={140:0}, i=22, size=21] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=22, i=20, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=22, i=20, mask={140:0}] [L26] i++ VAL [b={157:0}, i=21, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=21, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=148, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=162, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=143, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=131, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=130, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=139, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=129, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=149, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=155, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=135, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=146, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=151, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=158, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=154, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=136, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=138, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=152, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=141, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=132, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=133, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=137, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=159, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L20] return i; VAL [\old(size)=22, \result=23, b={140:0}, b={140:0}, i=23, size=22] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=23, i=21, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=23, i=21, mask={140:0}] [L26] i++ VAL [b={157:0}, i=22, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=22, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=148, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=162, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=143, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=131, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=130, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=139, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=129, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=149, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=155, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=135, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=146, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=151, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=158, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=154, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=136, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=138, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=152, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=141, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=132, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=133, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=137, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=159, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=163, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L20] return i; VAL [\old(size)=23, \result=24, b={140:0}, b={140:0}, i=24, size=23] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=24, i=22, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=24, i=22, mask={140:0}] [L26] i++ VAL [b={157:0}, i=23, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=23, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=148, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=162, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=143, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=131, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=130, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=139, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=129, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=149, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=155, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=135, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=146, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=151, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=158, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=154, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=136, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=138, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=152, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=141, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=132, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=133, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=137, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=159, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=163, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=144, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L20] return i; VAL [\old(size)=24, \result=25, b={140:0}, b={140:0}, i=25, size=24] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=25, i=23, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=25, i=23, mask={140:0}] [L26] i++ VAL [b={157:0}, i=24, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=24, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=148, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=162, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=143, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=131, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=130, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=139, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=129, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=149, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=155, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=135, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=146, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=151, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=158, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=154, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=136, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=138, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=152, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=141, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=132, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=133, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=137, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=159, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=163, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=144, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=153, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L20] return i; VAL [\old(size)=25, \result=26, b={140:0}, b={140:0}, i=26, size=25] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=26, i=24, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=26, i=24, mask={140:0}] [L26] i++ VAL [b={157:0}, i=25, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=25, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=148, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=162, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=143, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=131, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=130, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=139, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=129, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=149, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=155, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=135, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=146, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=151, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=158, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=154, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=136, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=138, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=152, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=141, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=132, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=133, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=137, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=159, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=163, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=144, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=153, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=145, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L20] return i; VAL [\old(size)=26, \result=27, b={140:0}, b={140:0}, i=27, size=26] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=27, i=25, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=27, i=25, mask={140:0}] [L26] i++ VAL [b={157:0}, i=26, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=26, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=148, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=162, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=143, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=131, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=130, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=139, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=129, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=149, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=155, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=135, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=146, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=151, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=158, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=154, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=136, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=138, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=152, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=141, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=132, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=133, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=137, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=159, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=163, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=144, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=153, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=145, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=164, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L20] return i; VAL [\old(size)=27, \result=28, b={140:0}, b={140:0}, i=28, size=27] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=28, i=26, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=28, i=26, mask={140:0}] [L26] i++ VAL [b={157:0}, i=27, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=27, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=148, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=162, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=143, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=131, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=130, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=139, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=129, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=149, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=155, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=135, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=146, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=151, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=158, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=154, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=136, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=138, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=152, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=141, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=132, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=133, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=137, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=159, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=163, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=144, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=153, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=145, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=164, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=160, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L20] return i; VAL [\old(size)=28, \result=29, b={140:0}, b={140:0}, i=29, size=28] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=29, i=27, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=29, i=27, mask={140:0}] [L26] i++ VAL [b={157:0}, i=28, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=28, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=148, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=162, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=143, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=131, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=130, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=139, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=129, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=149, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=155, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=135, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=146, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=151, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=158, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=154, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=136, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=138, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=152, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=141, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=132, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=133, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=137, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=159, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=163, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=144, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=153, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=145, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=164, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=160, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=142, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L20] return i; VAL [\old(size)=29, \result=30, b={140:0}, b={140:0}, i=30, size=29] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=30, i=28, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=30, i=28, mask={140:0}] [L26] i++ VAL [b={157:0}, i=29, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=29, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=148, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=162, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=143, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=131, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=130, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=139, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=129, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=149, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=155, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=135, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=146, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=151, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=158, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=154, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=136, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=138, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=152, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=141, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=132, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=133, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=137, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=159, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=163, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=144, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=153, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=145, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=164, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=160, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=142, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=161, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L20] return i; VAL [\old(size)=30, \result=31, b={140:0}, b={140:0}, i=31, size=30] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=31, i=29, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=31, i=29, mask={140:0}] [L26] i++ VAL [b={157:0}, i=30, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=30, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=148, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=162, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=143, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=131, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=130, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=139, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=129, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=149, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=155, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=135, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=146, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=151, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=158, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=154, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=136, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=138, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=152, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=141, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=132, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=133, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=137, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=159, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=163, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=144, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=153, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=145, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=164, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=160, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=142, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=161, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=134, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L20] return i; VAL [\old(size)=31, \result=32, b={140:0}, b={140:0}, i=32, size=31] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=32, i=30, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=32, i=30, mask={140:0}] [L26] i++ VAL [b={157:0}, i=31, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=31, mask={140:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=148, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=162, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=143, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=131, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=130, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=139, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=129, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=149, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=155, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=135, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=150, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=146, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=151, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=158, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=154, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=136, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=138, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=152, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=141, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=132, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=133, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=137, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=159, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=163, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=144, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=153, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=145, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=164, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=160, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=142, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=161, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=134, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 40 locations, 8 error locations. UNSAFE Result, 542.3s OverallTime, 102 OverallIterations, 560 TraceHistogramMax, 171.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3148 SDtfs, 77223 SDslu, 52128 SDs, 0 SdLazy, 243961 SolverSat, 13353 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 69.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 229303 GetRequests, 216982 SyntacticMatches, 1066 SemanticMatches, 11255 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 634503 ImplicationChecksByTransitivity, 204.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3541occurred in iteration=99, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.5s AbstIntTime, 5 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.8s AutomataMinimizationTime, 101 MinimizatonAttempts, 1444 StatesRemovedByMinimization, 98 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 4.0s SsaConstructionTime, 53.9s SatisfiabilityAnalysisTime, 251.0s InterpolantComputationTime, 224889 NumberOfCodeBlocks, 201360 NumberOfCodeBlocksAsserted, 734 NumberOfCheckSat, 332235 ConstructedInterpolants, 45 QuantifiedInterpolants, 938387608 SizeOfPredicates, 271 NumberOfNonLiveVariables, 221457 ConjunctsInSsa, 2975 ConjunctsInUnsatCore, 287 InterpolantComputations, 8 PerfectInterpolantSequences, 49038250/49603719 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...