./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i -s /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i -s /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN: Overapproximated counterexample --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-03 03:58:14,001 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-03 03:58:14,002 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-03 03:58:14,008 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-03 03:58:14,008 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-03 03:58:14,009 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-03 03:58:14,009 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-03 03:58:14,011 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-03 03:58:14,012 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-03 03:58:14,013 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-03 03:58:14,013 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-03 03:58:14,014 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-03 03:58:14,014 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-03 03:58:14,015 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-03 03:58:14,016 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-03 03:58:14,016 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-03 03:58:14,017 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-03 03:58:14,018 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-03 03:58:14,020 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-03 03:58:14,021 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-03 03:58:14,021 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-03 03:58:14,022 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-03 03:58:14,024 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-03 03:58:14,024 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-03 03:58:14,024 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-03 03:58:14,025 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-03 03:58:14,025 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-03 03:58:14,026 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-03 03:58:14,026 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-03 03:58:14,027 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-03 03:58:14,027 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-03 03:58:14,028 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-03 03:58:14,028 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-03 03:58:14,028 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-03 03:58:14,029 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-03 03:58:14,029 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-03 03:58:14,029 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default.epf [2018-12-03 03:58:14,038 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-03 03:58:14,038 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-03 03:58:14,039 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-03 03:58:14,039 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-03 03:58:14,039 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-03 03:58:14,040 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-03 03:58:14,040 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-03 03:58:14,040 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-03 03:58:14,040 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-03 03:58:14,040 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-03 03:58:14,040 INFO L133 SettingsManager]: * Log string format=TERM [2018-12-03 03:58:14,041 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-03 03:58:14,041 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-03 03:58:14,041 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-03 03:58:14,041 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-03 03:58:14,042 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-03 03:58:14,042 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-03 03:58:14,042 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-03 03:58:14,042 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-03 03:58:14,042 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-03 03:58:14,042 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-03 03:58:14,043 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-03 03:58:14,043 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-03 03:58:14,043 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-03 03:58:14,043 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-03 03:58:14,043 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-03 03:58:14,043 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-03 03:58:14,043 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-12-03 03:58:14,044 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a [2018-12-03 03:58:14,063 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-03 03:58:14,071 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-03 03:58:14,073 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-03 03:58:14,074 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-03 03:58:14,074 INFO L276 PluginConnector]: CDTParser initialized [2018-12-03 03:58:14,074 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-03 03:58:14,112 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/ccdbc7399/3a2839fe68fa4cba813236412025f901/FLAGb5dad133f [2018-12-03 03:58:14,608 INFO L307 CDTParser]: Found 1 translation units. [2018-12-03 03:58:14,608 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-03 03:58:14,618 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/ccdbc7399/3a2839fe68fa4cba813236412025f901/FLAGb5dad133f [2018-12-03 03:58:14,627 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/ccdbc7399/3a2839fe68fa4cba813236412025f901 [2018-12-03 03:58:14,628 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-03 03:58:14,629 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-03 03:58:14,630 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-03 03:58:14,630 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-03 03:58:14,632 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-03 03:58:14,632 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.12 03:58:14" (1/1) ... [2018-12-03 03:58:14,634 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6e67ed33 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:14, skipping insertion in model container [2018-12-03 03:58:14,634 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.12 03:58:14" (1/1) ... [2018-12-03 03:58:14,638 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-03 03:58:14,670 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-03 03:58:15,085 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-03 03:58:15,099 INFO L191 MainTranslator]: Completed pre-run [2018-12-03 03:58:15,197 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-03 03:58:15,242 INFO L195 MainTranslator]: Completed translation [2018-12-03 03:58:15,242 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15 WrapperNode [2018-12-03 03:58:15,243 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-03 03:58:15,243 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-03 03:58:15,243 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-03 03:58:15,243 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-03 03:58:15,248 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,266 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,272 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-03 03:58:15,273 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-03 03:58:15,273 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-03 03:58:15,273 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-03 03:58:15,279 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,279 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,284 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,284 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,303 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,308 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,313 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... [2018-12-03 03:58:15,317 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-03 03:58:15,318 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-03 03:58:15,318 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-03 03:58:15,318 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-03 03:58:15,319 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-03 03:58:15,358 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-12-03 03:58:15,358 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-12-03 03:58:15,359 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-12-03 03:58:15,359 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2018-12-03 03:58:15,359 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-12-03 03:58:15,359 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_unregister [2018-12-03 03:58:15,359 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-03 03:58:15,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-12-03 03:58:15,359 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-12-03 03:58:15,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-12-03 03:58:15,359 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-12-03 03:58:15,359 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-12-03 03:58:15,360 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize [2018-12-03 03:58:15,360 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-03 03:58:15,360 INFO L130 BoogieDeclarations]: Found specification of procedure external_alloc [2018-12-03 03:58:15,360 INFO L138 BoogieDeclarations]: Found implementation of procedure external_alloc [2018-12-03 03:58:15,360 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-12-03 03:58:15,360 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-12-03 03:58:15,360 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-12-03 03:58:15,360 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2018-12-03 03:58:15,360 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-12-03 03:58:15,361 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-12-03 03:58:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-12-03 03:58:15,361 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-12-03 03:58:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-12-03 03:58:15,361 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2018-12-03 03:58:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-12-03 03:58:15,361 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-12-03 03:58:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-12-03 03:58:15,361 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-12-03 03:58:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-12-03 03:58:15,361 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-12-03 03:58:15,362 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-12-03 03:58:15,362 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2018-12-03 03:58:15,362 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_external_alloc [2018-12-03 03:58:15,362 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-12-03 03:58:15,362 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2018-12-03 03:58:15,362 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-12-03 03:58:15,362 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2018-12-03 03:58:15,362 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-12-03 03:58:15,362 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2018-12-03 03:58:15,362 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-12-03 03:58:15,363 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-12-03 03:58:15,363 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-03 03:58:15,363 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-12-03 03:58:15,363 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-12-03 03:58:15,363 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-12-03 03:58:15,363 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_release_3 [2018-12-03 03:58:15,363 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-12-03 03:58:15,363 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-12-03 03:58:15,363 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-12-03 03:58:15,363 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-12-03 03:58:15,364 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-12-03 03:58:15,364 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-12-03 03:58:15,364 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-12-03 03:58:15,364 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-12-03 03:58:15,364 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-12-03 03:58:15,364 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-12-03 03:58:15,364 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-12-03 03:58:15,364 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2018-12-03 03:58:15,364 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-12-03 03:58:15,364 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_probe [2018-12-03 03:58:15,365 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-12-03 03:58:15,365 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_valid_tm [2018-12-03 03:58:15,365 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-12-03 03:58:15,365 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-12-03 03:58:15,365 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-03 03:58:15,365 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-03 03:58:15,365 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-12-03 03:58:15,365 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-12-03 03:58:15,365 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-12-03 03:58:15,365 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-12-03 03:58:15,366 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-12-03 03:58:15,366 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-12-03 03:58:15,366 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-12-03 03:58:15,366 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_update_irq [2018-12-03 03:58:15,366 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-12-03 03:58:15,366 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2018-12-03 03:58:15,366 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-03 03:58:15,366 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-03 03:58:15,366 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-12-03 03:58:15,367 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2018-12-03 03:58:15,367 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-12-03 03:58:15,367 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-12-03 03:58:15,367 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-12-03 03:58:15,367 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-12-03 03:58:15,367 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-12-03 03:58:15,367 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_unlock_irqrestore [2018-12-03 03:58:15,367 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-12-03 03:58:15,367 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-12-03 03:58:15,367 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-12-03 03:58:15,368 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-12-03 03:58:15,368 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-12-03 03:58:15,368 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-12-03 03:58:15,368 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-12-03 03:58:15,368 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-12-03 03:58:15,368 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-12-03 03:58:15,368 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-12-03 03:58:15,368 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2018-12-03 03:58:15,368 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-03 03:58:15,368 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-12-03 03:58:15,369 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_set_drvdata [2018-12-03 03:58:15,369 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-12-03 03:58:15,369 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-12-03 03:58:15,369 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-12-03 03:58:15,369 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-12-03 03:58:15,369 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-12-03 03:58:15,369 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-12-03 03:58:15,369 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-12-03 03:58:15,369 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-12-03 03:58:15,369 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-12-03 03:58:15,370 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-12-03 03:58:15,370 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-12-03 03:58:15,370 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-12-03 03:58:15,370 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-12-03 03:58:15,370 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-12-03 03:58:15,370 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-12-03 03:58:15,370 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-12-03 03:58:15,370 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-12-03 03:58:15,370 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-12-03 03:58:15,370 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-12-03 03:58:15,370 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-12-03 03:58:15,371 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-12-03 03:58:15,371 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-12-03 03:58:15,371 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-12-03 03:58:15,371 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_3 [2018-12-03 03:58:15,371 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-12-03 03:58:15,371 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_2 [2018-12-03 03:58:15,371 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-12-03 03:58:15,371 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-12-03 03:58:15,371 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-12-03 03:58:15,372 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2018-12-03 03:58:15,372 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-12-03 03:58:15,372 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-12-03 03:58:15,372 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-12-03 03:58:15,372 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-12-03 03:58:15,372 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-03 03:58:15,372 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-03 03:58:16,064 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-03 03:58:16,064 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-12-03 03:58:16,065 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 03:58:16 BoogieIcfgContainer [2018-12-03 03:58:16,065 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-03 03:58:16,065 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-03 03:58:16,065 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-03 03:58:16,067 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-03 03:58:16,067 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.12 03:58:14" (1/3) ... [2018-12-03 03:58:16,068 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3751a983 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.12 03:58:16, skipping insertion in model container [2018-12-03 03:58:16,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 03:58:15" (2/3) ... [2018-12-03 03:58:16,068 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3751a983 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.12 03:58:16, skipping insertion in model container [2018-12-03 03:58:16,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 03:58:16" (3/3) ... [2018-12-03 03:58:16,069 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-03 03:58:16,075 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-03 03:58:16,080 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-03 03:58:16,090 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-03 03:58:16,111 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-03 03:58:16,111 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-03 03:58:16,111 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-03 03:58:16,111 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-03 03:58:16,111 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-03 03:58:16,111 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-03 03:58:16,111 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-03 03:58:16,111 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-03 03:58:16,128 INFO L276 IsEmpty]: Start isEmpty. Operand 487 states. [2018-12-03 03:58:16,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-03 03:58:16,135 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:16,135 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:16,137 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:16,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:16,140 INFO L82 PathProgramCache]: Analyzing trace with hash -458857320, now seen corresponding path program 1 times [2018-12-03 03:58:16,142 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:16,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,180 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:16,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,180 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:16,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:16,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 03:58:16,314 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 03:58:16,314 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 03:58:16,314 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:16,318 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 03:58:16,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 03:58:16,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 03:58:16,327 INFO L87 Difference]: Start difference. First operand 487 states. Second operand 3 states. [2018-12-03 03:58:16,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:16,384 INFO L93 Difference]: Finished difference Result 824 states and 1044 transitions. [2018-12-03 03:58:16,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 03:58:16,385 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-03 03:58:16,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:16,394 INFO L225 Difference]: With dead ends: 824 [2018-12-03 03:58:16,394 INFO L226 Difference]: Without dead ends: 332 [2018-12-03 03:58:16,398 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 03:58:16,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 332 states. [2018-12-03 03:58:16,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 332 to 332. [2018-12-03 03:58:16,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 332 states. [2018-12-03 03:58:16,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 332 states to 332 states and 403 transitions. [2018-12-03 03:58:16,442 INFO L78 Accepts]: Start accepts. Automaton has 332 states and 403 transitions. Word has length 47 [2018-12-03 03:58:16,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:16,443 INFO L480 AbstractCegarLoop]: Abstraction has 332 states and 403 transitions. [2018-12-03 03:58:16,443 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 03:58:16,443 INFO L276 IsEmpty]: Start isEmpty. Operand 332 states and 403 transitions. [2018-12-03 03:58:16,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-03 03:58:16,446 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:16,446 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:16,446 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:16,446 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:16,446 INFO L82 PathProgramCache]: Analyzing trace with hash -717010078, now seen corresponding path program 1 times [2018-12-03 03:58:16,447 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:16,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,449 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:16,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,449 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:16,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:16,502 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 03:58:16,502 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 03:58:16,502 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 03:58:16,502 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:16,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 03:58:16,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 03:58:16,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 03:58:16,504 INFO L87 Difference]: Start difference. First operand 332 states and 403 transitions. Second operand 3 states. [2018-12-03 03:58:16,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:16,565 INFO L93 Difference]: Finished difference Result 777 states and 946 transitions. [2018-12-03 03:58:16,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 03:58:16,565 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-12-03 03:58:16,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:16,567 INFO L225 Difference]: With dead ends: 777 [2018-12-03 03:58:16,568 INFO L226 Difference]: Without dead ends: 462 [2018-12-03 03:58:16,569 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 03:58:16,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-12-03 03:58:16,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 459. [2018-12-03 03:58:16,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-12-03 03:58:16,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 559 transitions. [2018-12-03 03:58:16,588 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 559 transitions. Word has length 68 [2018-12-03 03:58:16,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:16,588 INFO L480 AbstractCegarLoop]: Abstraction has 459 states and 559 transitions. [2018-12-03 03:58:16,588 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 03:58:16,588 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 559 transitions. [2018-12-03 03:58:16,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-12-03 03:58:16,589 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:16,590 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:16,590 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:16,590 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:16,590 INFO L82 PathProgramCache]: Analyzing trace with hash 1417324652, now seen corresponding path program 1 times [2018-12-03 03:58:16,590 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:16,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,592 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:16,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,592 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:16,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:16,662 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 03:58:16,663 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 03:58:16,663 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 03:58:16,663 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:16,663 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 03:58:16,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 03:58:16,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 03:58:16,664 INFO L87 Difference]: Start difference. First operand 459 states and 559 transitions. Second operand 5 states. [2018-12-03 03:58:16,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:16,756 INFO L93 Difference]: Finished difference Result 1345 states and 1665 transitions. [2018-12-03 03:58:16,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-03 03:58:16,757 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-12-03 03:58:16,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:16,762 INFO L225 Difference]: With dead ends: 1345 [2018-12-03 03:58:16,762 INFO L226 Difference]: Without dead ends: 913 [2018-12-03 03:58:16,764 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 03:58:16,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 913 states. [2018-12-03 03:58:16,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 913 to 890. [2018-12-03 03:58:16,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 890 states. [2018-12-03 03:58:16,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 890 states to 890 states and 1092 transitions. [2018-12-03 03:58:16,809 INFO L78 Accepts]: Start accepts. Automaton has 890 states and 1092 transitions. Word has length 70 [2018-12-03 03:58:16,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:16,810 INFO L480 AbstractCegarLoop]: Abstraction has 890 states and 1092 transitions. [2018-12-03 03:58:16,810 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 03:58:16,810 INFO L276 IsEmpty]: Start isEmpty. Operand 890 states and 1092 transitions. [2018-12-03 03:58:16,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-12-03 03:58:16,811 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:16,811 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:16,812 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:16,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:16,812 INFO L82 PathProgramCache]: Analyzing trace with hash -837085032, now seen corresponding path program 1 times [2018-12-03 03:58:16,812 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:16,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:16,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:16,814 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:16,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:16,914 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 03:58:16,914 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 03:58:16,914 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 03:58:16,914 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:16,914 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 03:58:16,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 03:58:16,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 03:58:16,915 INFO L87 Difference]: Start difference. First operand 890 states and 1092 transitions. Second operand 5 states. [2018-12-03 03:58:16,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:16,979 INFO L93 Difference]: Finished difference Result 1785 states and 2210 transitions. [2018-12-03 03:58:16,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 03:58:16,980 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2018-12-03 03:58:16,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:16,982 INFO L225 Difference]: With dead ends: 1785 [2018-12-03 03:58:16,982 INFO L226 Difference]: Without dead ends: 922 [2018-12-03 03:58:16,984 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 03:58:16,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 922 states. [2018-12-03 03:58:17,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 922 to 898. [2018-12-03 03:58:17,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 898 states. [2018-12-03 03:58:17,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 898 states to 898 states and 1094 transitions. [2018-12-03 03:58:17,009 INFO L78 Accepts]: Start accepts. Automaton has 898 states and 1094 transitions. Word has length 71 [2018-12-03 03:58:17,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:17,009 INFO L480 AbstractCegarLoop]: Abstraction has 898 states and 1094 transitions. [2018-12-03 03:58:17,009 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 03:58:17,009 INFO L276 IsEmpty]: Start isEmpty. Operand 898 states and 1094 transitions. [2018-12-03 03:58:17,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-03 03:58:17,010 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:17,010 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:17,010 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:17,010 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:17,011 INFO L82 PathProgramCache]: Analyzing trace with hash 564763209, now seen corresponding path program 1 times [2018-12-03 03:58:17,011 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:17,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:17,012 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:17,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:17,012 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:17,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:17,065 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 03:58:17,065 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 03:58:17,065 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 03:58:17,066 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:17,066 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 03:58:17,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 03:58:17,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 03:58:17,066 INFO L87 Difference]: Start difference. First operand 898 states and 1094 transitions. Second operand 5 states. [2018-12-03 03:58:17,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:17,142 INFO L93 Difference]: Finished difference Result 1801 states and 2210 transitions. [2018-12-03 03:58:17,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 03:58:17,142 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2018-12-03 03:58:17,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:17,146 INFO L225 Difference]: With dead ends: 1801 [2018-12-03 03:58:17,146 INFO L226 Difference]: Without dead ends: 930 [2018-12-03 03:58:17,149 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 03:58:17,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 930 states. [2018-12-03 03:58:17,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 930 to 906. [2018-12-03 03:58:17,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 906 states. [2018-12-03 03:58:17,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 906 states to 906 states and 1096 transitions. [2018-12-03 03:58:17,188 INFO L78 Accepts]: Start accepts. Automaton has 906 states and 1096 transitions. Word has length 72 [2018-12-03 03:58:17,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:17,188 INFO L480 AbstractCegarLoop]: Abstraction has 906 states and 1096 transitions. [2018-12-03 03:58:17,188 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 03:58:17,188 INFO L276 IsEmpty]: Start isEmpty. Operand 906 states and 1096 transitions. [2018-12-03 03:58:17,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-03 03:58:17,189 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:17,189 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:17,190 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:17,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:17,190 INFO L82 PathProgramCache]: Analyzing trace with hash -653509867, now seen corresponding path program 1 times [2018-12-03 03:58:17,190 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:17,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:17,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:17,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:17,192 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:17,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:17,259 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 03:58:17,259 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 03:58:17,259 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 03:58:17,259 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:17,259 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 03:58:17,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 03:58:17,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 03:58:17,260 INFO L87 Difference]: Start difference. First operand 906 states and 1096 transitions. Second operand 5 states. [2018-12-03 03:58:17,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:17,318 INFO L93 Difference]: Finished difference Result 1712 states and 2088 transitions. [2018-12-03 03:58:17,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 03:58:17,318 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2018-12-03 03:58:17,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:17,320 INFO L225 Difference]: With dead ends: 1712 [2018-12-03 03:58:17,320 INFO L226 Difference]: Without dead ends: 833 [2018-12-03 03:58:17,322 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 03:58:17,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 833 states. [2018-12-03 03:58:17,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 833 to 815. [2018-12-03 03:58:17,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 815 states. [2018-12-03 03:58:17,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 815 states to 815 states and 980 transitions. [2018-12-03 03:58:17,344 INFO L78 Accepts]: Start accepts. Automaton has 815 states and 980 transitions. Word has length 73 [2018-12-03 03:58:17,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:17,344 INFO L480 AbstractCegarLoop]: Abstraction has 815 states and 980 transitions. [2018-12-03 03:58:17,344 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 03:58:17,344 INFO L276 IsEmpty]: Start isEmpty. Operand 815 states and 980 transitions. [2018-12-03 03:58:17,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-12-03 03:58:17,345 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:17,345 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:17,346 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:17,346 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:17,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1428324143, now seen corresponding path program 1 times [2018-12-03 03:58:17,346 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:17,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:17,347 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:17,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:17,347 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:17,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:17,428 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-03 03:58:17,428 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:58:17,428 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:58:17,429 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 86 with the following transitions: [2018-12-03 03:58:17,430 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 03:58:17,461 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:58:17,462 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:58:17,698 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:58:17,699 INFO L272 AbstractInterpreter]: Visited 18 different actions 18 times. Never merged. Never widened. Performed 1017 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1017 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 177 variables. [2018-12-03 03:58:17,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:17,710 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:58:17,834 INFO L227 lantSequenceWeakener]: Weakened 16 states. On average, predicates are now at 94.21% of their original sizes. [2018-12-03 03:58:17,835 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:58:17,888 INFO L418 sIntCurrentIteration]: We unified 84 AI predicates to 84 [2018-12-03 03:58:17,888 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:58:17,889 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:58:17,889 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 16 [2018-12-03 03:58:17,889 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:17,889 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-03 03:58:17,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-03 03:58:17,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-03 03:58:17,890 INFO L87 Difference]: Start difference. First operand 815 states and 980 transitions. Second operand 9 states. [2018-12-03 03:58:19,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:19,685 INFO L93 Difference]: Finished difference Result 1950 states and 2346 transitions. [2018-12-03 03:58:19,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-03 03:58:19,685 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 85 [2018-12-03 03:58:19,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:19,690 INFO L225 Difference]: With dead ends: 1950 [2018-12-03 03:58:19,690 INFO L226 Difference]: Without dead ends: 1159 [2018-12-03 03:58:19,693 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 85 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-12-03 03:58:19,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1159 states. [2018-12-03 03:58:19,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1159 to 1095. [2018-12-03 03:58:19,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1095 states. [2018-12-03 03:58:19,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1095 states to 1095 states and 1324 transitions. [2018-12-03 03:58:19,757 INFO L78 Accepts]: Start accepts. Automaton has 1095 states and 1324 transitions. Word has length 85 [2018-12-03 03:58:19,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:19,758 INFO L480 AbstractCegarLoop]: Abstraction has 1095 states and 1324 transitions. [2018-12-03 03:58:19,758 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-03 03:58:19,758 INFO L276 IsEmpty]: Start isEmpty. Operand 1095 states and 1324 transitions. [2018-12-03 03:58:19,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-03 03:58:19,759 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:19,759 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:19,760 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:19,760 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:19,760 INFO L82 PathProgramCache]: Analyzing trace with hash 1160945827, now seen corresponding path program 1 times [2018-12-03 03:58:19,760 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:19,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:19,762 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:19,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:19,762 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:19,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:19,851 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-03 03:58:19,851 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:58:19,852 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:58:19,852 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 87 with the following transitions: [2018-12-03 03:58:19,852 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 03:58:19,854 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:58:19,854 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:58:19,969 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:58:19,969 INFO L272 AbstractInterpreter]: Visited 38 different actions 46 times. Merged at 3 different actions 5 times. Never widened. Performed 1463 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1463 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 03:58:19,971 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:19,971 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:58:20,133 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 03:58:20,133 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:58:21,226 INFO L418 sIntCurrentIteration]: We unified 85 AI predicates to 85 [2018-12-03 03:58:21,227 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:58:21,227 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:58:21,227 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [9] total 33 [2018-12-03 03:58:21,227 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:21,227 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-03 03:58:21,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-03 03:58:21,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=533, Unknown=0, NotChecked=0, Total=650 [2018-12-03 03:58:21,227 INFO L87 Difference]: Start difference. First operand 1095 states and 1324 transitions. Second operand 26 states. [2018-12-03 03:58:37,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:37,027 INFO L93 Difference]: Finished difference Result 2630 states and 3199 transitions. [2018-12-03 03:58:37,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-03 03:58:37,027 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 86 [2018-12-03 03:58:37,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:37,032 INFO L225 Difference]: With dead ends: 2630 [2018-12-03 03:58:37,032 INFO L226 Difference]: Without dead ends: 1563 [2018-12-03 03:58:37,034 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 87 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 287 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=132, Invalid=624, Unknown=0, NotChecked=0, Total=756 [2018-12-03 03:58:37,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1563 states. [2018-12-03 03:58:37,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1563 to 1135. [2018-12-03 03:58:37,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1135 states. [2018-12-03 03:58:37,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1135 states to 1135 states and 1377 transitions. [2018-12-03 03:58:37,093 INFO L78 Accepts]: Start accepts. Automaton has 1135 states and 1377 transitions. Word has length 86 [2018-12-03 03:58:37,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:37,093 INFO L480 AbstractCegarLoop]: Abstraction has 1135 states and 1377 transitions. [2018-12-03 03:58:37,093 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-03 03:58:37,093 INFO L276 IsEmpty]: Start isEmpty. Operand 1135 states and 1377 transitions. [2018-12-03 03:58:37,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-12-03 03:58:37,094 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:37,095 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:37,095 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:37,095 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:37,095 INFO L82 PathProgramCache]: Analyzing trace with hash 1794890282, now seen corresponding path program 1 times [2018-12-03 03:58:37,095 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:37,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:37,097 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:37,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:37,097 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:37,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:37,170 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-03 03:58:37,170 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:58:37,170 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:58:37,170 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 88 with the following transitions: [2018-12-03 03:58:37,170 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 03:58:37,172 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:58:37,172 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:58:37,263 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:58:37,263 INFO L272 AbstractInterpreter]: Visited 41 different actions 54 times. Merged at 3 different actions 5 times. Never widened. Performed 1649 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1649 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 03:58:37,265 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:37,265 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:58:37,392 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 03:58:37,392 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:58:38,530 INFO L418 sIntCurrentIteration]: We unified 86 AI predicates to 86 [2018-12-03 03:58:38,530 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:58:38,530 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:58:38,530 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-03 03:58:38,530 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:38,531 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-03 03:58:38,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-03 03:58:38,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=581, Unknown=0, NotChecked=0, Total=702 [2018-12-03 03:58:38,531 INFO L87 Difference]: Start difference. First operand 1135 states and 1377 transitions. Second operand 27 states. [2018-12-03 03:58:49,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:58:49,900 INFO L93 Difference]: Finished difference Result 2665 states and 3243 transitions. [2018-12-03 03:58:49,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-12-03 03:58:49,900 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 87 [2018-12-03 03:58:49,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:58:49,904 INFO L225 Difference]: With dead ends: 2665 [2018-12-03 03:58:49,904 INFO L226 Difference]: Without dead ends: 1877 [2018-12-03 03:58:49,905 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 88 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 307 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=136, Invalid=676, Unknown=0, NotChecked=0, Total=812 [2018-12-03 03:58:49,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1877 states. [2018-12-03 03:58:49,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1877 to 1196. [2018-12-03 03:58:49,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1196 states. [2018-12-03 03:58:49,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1196 states to 1196 states and 1462 transitions. [2018-12-03 03:58:49,963 INFO L78 Accepts]: Start accepts. Automaton has 1196 states and 1462 transitions. Word has length 87 [2018-12-03 03:58:49,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:58:49,963 INFO L480 AbstractCegarLoop]: Abstraction has 1196 states and 1462 transitions. [2018-12-03 03:58:49,963 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-03 03:58:49,963 INFO L276 IsEmpty]: Start isEmpty. Operand 1196 states and 1462 transitions. [2018-12-03 03:58:49,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-03 03:58:49,964 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:58:49,964 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:58:49,964 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:58:49,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:49,964 INFO L82 PathProgramCache]: Analyzing trace with hash -1236221092, now seen corresponding path program 1 times [2018-12-03 03:58:49,965 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:58:49,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:49,966 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:58:49,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:58:49,966 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:58:49,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:58:50,033 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-03 03:58:50,034 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:58:50,034 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:58:50,034 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 89 with the following transitions: [2018-12-03 03:58:50,034 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 03:58:50,035 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:58:50,035 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:58:50,130 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:58:50,130 INFO L272 AbstractInterpreter]: Visited 42 different actions 59 times. Merged at 3 different actions 8 times. Widened at 1 different actions 1 times. Performed 1705 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1705 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 03:58:50,134 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:58:50,134 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:58:50,277 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 03:58:50,278 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:58:51,443 INFO L418 sIntCurrentIteration]: We unified 87 AI predicates to 87 [2018-12-03 03:58:51,443 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:58:51,443 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:58:51,443 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-12-03 03:58:51,443 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:58:51,443 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-03 03:58:51,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-03 03:58:51,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=631, Unknown=0, NotChecked=0, Total=756 [2018-12-03 03:58:51,444 INFO L87 Difference]: Start difference. First operand 1196 states and 1462 transitions. Second operand 28 states. [2018-12-03 03:59:02,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:59:02,743 INFO L93 Difference]: Finished difference Result 2707 states and 3297 transitions. [2018-12-03 03:59:02,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-03 03:59:02,743 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 88 [2018-12-03 03:59:02,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:59:02,746 INFO L225 Difference]: With dead ends: 2707 [2018-12-03 03:59:02,746 INFO L226 Difference]: Without dead ends: 1919 [2018-12-03 03:59:02,748 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 89 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 327 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-12-03 03:59:02,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1919 states. [2018-12-03 03:59:02,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1919 to 1231. [2018-12-03 03:59:02,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1231 states. [2018-12-03 03:59:02,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1231 states to 1231 states and 1509 transitions. [2018-12-03 03:59:02,810 INFO L78 Accepts]: Start accepts. Automaton has 1231 states and 1509 transitions. Word has length 88 [2018-12-03 03:59:02,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:59:02,811 INFO L480 AbstractCegarLoop]: Abstraction has 1231 states and 1509 transitions. [2018-12-03 03:59:02,811 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-03 03:59:02,811 INFO L276 IsEmpty]: Start isEmpty. Operand 1231 states and 1509 transitions. [2018-12-03 03:59:02,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-12-03 03:59:02,812 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:59:02,812 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:59:02,812 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:59:02,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:02,812 INFO L82 PathProgramCache]: Analyzing trace with hash -1919946173, now seen corresponding path program 1 times [2018-12-03 03:59:02,813 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:59:02,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:02,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:59:02,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:02,814 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:59:02,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:59:02,878 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-03 03:59:02,878 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:59:02,879 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:59:02,879 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 90 with the following transitions: [2018-12-03 03:59:02,879 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 03:59:02,880 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:59:02,880 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:59:02,970 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:59:02,970 INFO L272 AbstractInterpreter]: Visited 43 different actions 56 times. Merged at 3 different actions 5 times. Never widened. Performed 1689 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1689 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 03:59:02,979 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:02,979 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:59:03,103 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 03:59:03,104 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:59:04,361 INFO L418 sIntCurrentIteration]: We unified 88 AI predicates to 88 [2018-12-03 03:59:04,361 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:59:04,361 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:59:04,361 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-12-03 03:59:04,361 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:59:04,362 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-03 03:59:04,362 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-03 03:59:04,362 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=683, Unknown=0, NotChecked=0, Total=812 [2018-12-03 03:59:04,362 INFO L87 Difference]: Start difference. First operand 1231 states and 1509 transitions. Second operand 29 states. [2018-12-03 03:59:22,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:59:22,968 INFO L93 Difference]: Finished difference Result 2749 states and 3350 transitions. [2018-12-03 03:59:22,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-03 03:59:22,968 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 89 [2018-12-03 03:59:22,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:59:22,971 INFO L225 Difference]: With dead ends: 2749 [2018-12-03 03:59:22,971 INFO L226 Difference]: Without dead ends: 1961 [2018-12-03 03:59:22,973 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 90 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 347 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=144, Invalid=786, Unknown=0, NotChecked=0, Total=930 [2018-12-03 03:59:22,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1961 states. [2018-12-03 03:59:23,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1961 to 1266. [2018-12-03 03:59:23,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1266 states. [2018-12-03 03:59:23,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1266 states to 1266 states and 1555 transitions. [2018-12-03 03:59:23,042 INFO L78 Accepts]: Start accepts. Automaton has 1266 states and 1555 transitions. Word has length 89 [2018-12-03 03:59:23,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:59:23,042 INFO L480 AbstractCegarLoop]: Abstraction has 1266 states and 1555 transitions. [2018-12-03 03:59:23,042 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-03 03:59:23,042 INFO L276 IsEmpty]: Start isEmpty. Operand 1266 states and 1555 transitions. [2018-12-03 03:59:23,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-12-03 03:59:23,044 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:59:23,044 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:59:23,044 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:59:23,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:23,044 INFO L82 PathProgramCache]: Analyzing trace with hash 1725251545, now seen corresponding path program 1 times [2018-12-03 03:59:23,044 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:59:23,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:23,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:59:23,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:23,045 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:59:23,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:59:23,125 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-03 03:59:23,125 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:59:23,125 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:59:23,125 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 93 with the following transitions: [2018-12-03 03:59:23,125 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 03:59:23,126 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:59:23,127 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:59:23,212 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:59:23,212 INFO L272 AbstractInterpreter]: Visited 44 different actions 52 times. Merged at 3 different actions 5 times. Never widened. Performed 1637 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1637 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 03:59:23,214 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:23,214 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:59:23,344 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 03:59:23,344 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:59:24,394 INFO L418 sIntCurrentIteration]: We unified 91 AI predicates to 91 [2018-12-03 03:59:24,394 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:59:24,394 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:59:24,394 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [9] total 34 [2018-12-03 03:59:24,395 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:59:24,395 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-03 03:59:24,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-03 03:59:24,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=579, Unknown=0, NotChecked=0, Total=702 [2018-12-03 03:59:24,395 INFO L87 Difference]: Start difference. First operand 1266 states and 1555 transitions. Second operand 27 states. [2018-12-03 03:59:37,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:59:37,202 INFO L93 Difference]: Finished difference Result 3103 states and 3795 transitions. [2018-12-03 03:59:37,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-12-03 03:59:37,203 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 92 [2018-12-03 03:59:37,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:59:37,206 INFO L225 Difference]: With dead ends: 3103 [2018-12-03 03:59:37,206 INFO L226 Difference]: Without dead ends: 2036 [2018-12-03 03:59:37,207 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 93 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 308 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=138, Invalid=674, Unknown=0, NotChecked=0, Total=812 [2018-12-03 03:59:37,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2036 states. [2018-12-03 03:59:37,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2036 to 1301. [2018-12-03 03:59:37,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1301 states. [2018-12-03 03:59:37,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1301 states to 1301 states and 1601 transitions. [2018-12-03 03:59:37,297 INFO L78 Accepts]: Start accepts. Automaton has 1301 states and 1601 transitions. Word has length 92 [2018-12-03 03:59:37,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:59:37,297 INFO L480 AbstractCegarLoop]: Abstraction has 1301 states and 1601 transitions. [2018-12-03 03:59:37,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-03 03:59:37,297 INFO L276 IsEmpty]: Start isEmpty. Operand 1301 states and 1601 transitions. [2018-12-03 03:59:37,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-12-03 03:59:37,298 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:59:37,298 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:59:37,298 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:59:37,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:37,299 INFO L82 PathProgramCache]: Analyzing trace with hash 2108498356, now seen corresponding path program 1 times [2018-12-03 03:59:37,299 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:59:37,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:37,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:59:37,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:37,300 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:59:37,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:59:37,372 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-03 03:59:37,372 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:59:37,372 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:59:37,372 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 94 with the following transitions: [2018-12-03 03:59:37,372 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 03:59:37,373 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:59:37,373 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:59:37,472 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:59:37,472 INFO L272 AbstractInterpreter]: Visited 47 different actions 64 times. Merged at 3 different actions 8 times. Widened at 1 different actions 1 times. Performed 1853 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1853 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 03:59:37,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:37,475 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:59:37,603 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 03:59:37,604 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:59:38,683 INFO L418 sIntCurrentIteration]: We unified 92 AI predicates to 92 [2018-12-03 03:59:38,684 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:59:38,684 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:59:38,684 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-12-03 03:59:38,684 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:59:38,684 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-03 03:59:38,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-03 03:59:38,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-12-03 03:59:38,685 INFO L87 Difference]: Start difference. First operand 1301 states and 1601 transitions. Second operand 28 states. [2018-12-03 03:59:52,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 03:59:52,207 INFO L93 Difference]: Finished difference Result 2863 states and 3500 transitions. [2018-12-03 03:59:52,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-03 03:59:52,207 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 93 [2018-12-03 03:59:52,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 03:59:52,210 INFO L225 Difference]: With dead ends: 2863 [2018-12-03 03:59:52,210 INFO L226 Difference]: Without dead ends: 2075 [2018-12-03 03:59:52,211 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 94 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 329 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=142, Invalid=728, Unknown=0, NotChecked=0, Total=870 [2018-12-03 03:59:52,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2075 states. [2018-12-03 03:59:52,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2075 to 1362. [2018-12-03 03:59:52,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1362 states. [2018-12-03 03:59:52,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1362 states to 1362 states and 1686 transitions. [2018-12-03 03:59:52,296 INFO L78 Accepts]: Start accepts. Automaton has 1362 states and 1686 transitions. Word has length 93 [2018-12-03 03:59:52,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 03:59:52,296 INFO L480 AbstractCegarLoop]: Abstraction has 1362 states and 1686 transitions. [2018-12-03 03:59:52,296 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-03 03:59:52,296 INFO L276 IsEmpty]: Start isEmpty. Operand 1362 states and 1686 transitions. [2018-12-03 03:59:52,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-12-03 03:59:52,297 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 03:59:52,297 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 03:59:52,297 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 03:59:52,297 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:52,298 INFO L82 PathProgramCache]: Analyzing trace with hash -104305390, now seen corresponding path program 1 times [2018-12-03 03:59:52,298 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 03:59:52,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:52,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 03:59:52,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 03:59:52,299 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 03:59:52,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 03:59:52,368 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-03 03:59:52,368 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 03:59:52,368 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 03:59:52,368 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 95 with the following transitions: [2018-12-03 03:59:52,368 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 03:59:52,369 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 03:59:52,369 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 03:59:52,464 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 03:59:52,464 INFO L272 AbstractInterpreter]: Visited 48 different actions 61 times. Merged at 3 different actions 5 times. Never widened. Performed 1849 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1849 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 03:59:52,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 03:59:52,465 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 03:59:52,614 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 03:59:52,614 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 03:59:53,808 INFO L418 sIntCurrentIteration]: We unified 93 AI predicates to 93 [2018-12-03 03:59:53,808 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 03:59:53,808 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 03:59:53,808 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-12-03 03:59:53,809 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 03:59:53,809 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-03 03:59:53,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-03 03:59:53,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=681, Unknown=0, NotChecked=0, Total=812 [2018-12-03 03:59:53,809 INFO L87 Difference]: Start difference. First operand 1362 states and 1686 transitions. Second operand 29 states. [2018-12-03 04:00:04,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:00:04,943 INFO L93 Difference]: Finished difference Result 2905 states and 3554 transitions. [2018-12-03 04:00:04,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-03 04:00:04,943 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 94 [2018-12-03 04:00:04,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:00:04,946 INFO L225 Difference]: With dead ends: 2905 [2018-12-03 04:00:04,946 INFO L226 Difference]: Without dead ends: 2117 [2018-12-03 04:00:04,948 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 95 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 350 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=146, Invalid=784, Unknown=0, NotChecked=0, Total=930 [2018-12-03 04:00:04,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2117 states. [2018-12-03 04:00:05,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2117 to 1397. [2018-12-03 04:00:05,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1397 states. [2018-12-03 04:00:05,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1397 states to 1397 states and 1733 transitions. [2018-12-03 04:00:05,041 INFO L78 Accepts]: Start accepts. Automaton has 1397 states and 1733 transitions. Word has length 94 [2018-12-03 04:00:05,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:00:05,041 INFO L480 AbstractCegarLoop]: Abstraction has 1397 states and 1733 transitions. [2018-12-03 04:00:05,041 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-03 04:00:05,041 INFO L276 IsEmpty]: Start isEmpty. Operand 1397 states and 1733 transitions. [2018-12-03 04:00:05,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-12-03 04:00:05,042 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:00:05,043 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:00:05,043 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:00:05,043 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:05,043 INFO L82 PathProgramCache]: Analyzing trace with hash -1190297779, now seen corresponding path program 1 times [2018-12-03 04:00:05,043 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:00:05,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:05,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:00:05,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:05,045 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:00:05,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:00:05,107 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-03 04:00:05,107 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:00:05,107 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:00:05,107 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 96 with the following transitions: [2018-12-03 04:00:05,107 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 04:00:05,108 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:00:05,108 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:00:05,203 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:00:05,203 INFO L272 AbstractInterpreter]: Visited 49 different actions 62 times. Merged at 3 different actions 5 times. Never widened. Performed 1863 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1863 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:00:05,206 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:05,206 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:00:05,340 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:00:05,340 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:00:06,668 INFO L418 sIntCurrentIteration]: We unified 94 AI predicates to 94 [2018-12-03 04:00:06,668 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:00:06,668 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:00:06,668 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-12-03 04:00:06,668 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:00:06,668 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-03 04:00:06,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-03 04:00:06,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-12-03 04:00:06,669 INFO L87 Difference]: Start difference. First operand 1397 states and 1733 transitions. Second operand 30 states. [2018-12-03 04:00:20,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:00:20,635 INFO L93 Difference]: Finished difference Result 2947 states and 3607 transitions. [2018-12-03 04:00:20,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-03 04:00:20,635 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 95 [2018-12-03 04:00:20,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:00:20,639 INFO L225 Difference]: With dead ends: 2947 [2018-12-03 04:00:20,639 INFO L226 Difference]: Without dead ends: 2159 [2018-12-03 04:00:20,640 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 96 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 371 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-12-03 04:00:20,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2159 states. [2018-12-03 04:00:20,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2159 to 1432. [2018-12-03 04:00:20,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1432 states. [2018-12-03 04:00:20,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1432 states to 1432 states and 1779 transitions. [2018-12-03 04:00:20,762 INFO L78 Accepts]: Start accepts. Automaton has 1432 states and 1779 transitions. Word has length 95 [2018-12-03 04:00:20,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:00:20,762 INFO L480 AbstractCegarLoop]: Abstraction has 1432 states and 1779 transitions. [2018-12-03 04:00:20,762 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-03 04:00:20,762 INFO L276 IsEmpty]: Start isEmpty. Operand 1432 states and 1779 transitions. [2018-12-03 04:00:20,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-12-03 04:00:20,763 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:00:20,763 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:00:20,763 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:00:20,764 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:20,764 INFO L82 PathProgramCache]: Analyzing trace with hash 825686790, now seen corresponding path program 1 times [2018-12-03 04:00:20,764 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:00:20,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:20,765 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:00:20,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:20,765 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:00:20,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:00:20,793 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-03 04:00:20,793 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:00:20,793 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 04:00:20,793 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:00:20,793 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 04:00:20,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 04:00:20,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:00:20,793 INFO L87 Difference]: Start difference. First operand 1432 states and 1779 transitions. Second operand 3 states. [2018-12-03 04:00:20,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:00:20,941 INFO L93 Difference]: Finished difference Result 2763 states and 3432 transitions. [2018-12-03 04:00:20,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 04:00:20,941 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2018-12-03 04:00:20,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:00:20,944 INFO L225 Difference]: With dead ends: 2763 [2018-12-03 04:00:20,944 INFO L226 Difference]: Without dead ends: 1696 [2018-12-03 04:00:20,946 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:00:20,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1696 states. [2018-12-03 04:00:21,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1696 to 1693. [2018-12-03 04:00:21,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1693 states. [2018-12-03 04:00:21,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1693 states to 1693 states and 2110 transitions. [2018-12-03 04:00:21,052 INFO L78 Accepts]: Start accepts. Automaton has 1693 states and 2110 transitions. Word has length 98 [2018-12-03 04:00:21,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:00:21,053 INFO L480 AbstractCegarLoop]: Abstraction has 1693 states and 2110 transitions. [2018-12-03 04:00:21,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 04:00:21,053 INFO L276 IsEmpty]: Start isEmpty. Operand 1693 states and 2110 transitions. [2018-12-03 04:00:21,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-12-03 04:00:21,054 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:00:21,054 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:00:21,054 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:00:21,054 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:21,054 INFO L82 PathProgramCache]: Analyzing trace with hash -1703097165, now seen corresponding path program 1 times [2018-12-03 04:00:21,054 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:00:21,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:21,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:00:21,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:21,055 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:00:21,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:00:21,080 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-03 04:00:21,080 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:00:21,080 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 04:00:21,080 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:00:21,081 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 04:00:21,081 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 04:00:21,081 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:00:21,081 INFO L87 Difference]: Start difference. First operand 1693 states and 2110 transitions. Second operand 3 states. [2018-12-03 04:00:21,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:00:21,187 INFO L93 Difference]: Finished difference Result 3024 states and 3737 transitions. [2018-12-03 04:00:21,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 04:00:21,187 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 106 [2018-12-03 04:00:21,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:00:21,190 INFO L225 Difference]: With dead ends: 3024 [2018-12-03 04:00:21,190 INFO L226 Difference]: Without dead ends: 1687 [2018-12-03 04:00:21,192 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:00:21,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1687 states. [2018-12-03 04:00:21,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1687 to 1621. [2018-12-03 04:00:21,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1621 states. [2018-12-03 04:00:21,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1621 states to 1621 states and 2029 transitions. [2018-12-03 04:00:21,294 INFO L78 Accepts]: Start accepts. Automaton has 1621 states and 2029 transitions. Word has length 106 [2018-12-03 04:00:21,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:00:21,294 INFO L480 AbstractCegarLoop]: Abstraction has 1621 states and 2029 transitions. [2018-12-03 04:00:21,294 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 04:00:21,294 INFO L276 IsEmpty]: Start isEmpty. Operand 1621 states and 2029 transitions. [2018-12-03 04:00:21,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-03 04:00:21,295 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:00:21,295 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:00:21,295 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:00:21,295 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:21,295 INFO L82 PathProgramCache]: Analyzing trace with hash -149649163, now seen corresponding path program 1 times [2018-12-03 04:00:21,295 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:00:21,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:21,296 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:00:21,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:21,296 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:00:21,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:00:21,360 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-03 04:00:21,360 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:00:21,360 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:00:21,360 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 106 with the following transitions: [2018-12-03 04:00:21,361 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [672], [674], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:00:21,362 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:00:21,362 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:00:21,486 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:00:21,486 INFO L272 AbstractInterpreter]: Visited 47 different actions 67 times. Merged at 5 different actions 7 times. Never widened. Performed 1859 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1859 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:00:21,487 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:21,488 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:00:21,649 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:00:21,649 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:00:23,295 INFO L418 sIntCurrentIteration]: We unified 104 AI predicates to 104 [2018-12-03 04:00:23,295 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:00:23,295 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:00:23,295 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-03 04:00:23,295 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:00:23,296 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-03 04:00:23,296 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-03 04:00:23,296 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=844, Unknown=0, NotChecked=0, Total=992 [2018-12-03 04:00:23,296 INFO L87 Difference]: Start difference. First operand 1621 states and 2029 transitions. Second operand 32 states. [2018-12-03 04:00:40,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:00:40,125 INFO L93 Difference]: Finished difference Result 3424 states and 4238 transitions. [2018-12-03 04:00:40,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-03 04:00:40,125 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 105 [2018-12-03 04:00:40,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:00:40,131 INFO L225 Difference]: With dead ends: 3424 [2018-12-03 04:00:40,131 INFO L226 Difference]: Without dead ends: 2477 [2018-12-03 04:00:40,133 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 106 GetRequests, 73 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 424 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=163, Invalid=959, Unknown=0, NotChecked=0, Total=1122 [2018-12-03 04:00:40,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2477 states. [2018-12-03 04:00:40,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2477 to 1665. [2018-12-03 04:00:40,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1665 states. [2018-12-03 04:00:40,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1665 states to 1665 states and 2086 transitions. [2018-12-03 04:00:40,260 INFO L78 Accepts]: Start accepts. Automaton has 1665 states and 2086 transitions. Word has length 105 [2018-12-03 04:00:40,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:00:40,261 INFO L480 AbstractCegarLoop]: Abstraction has 1665 states and 2086 transitions. [2018-12-03 04:00:40,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-03 04:00:40,261 INFO L276 IsEmpty]: Start isEmpty. Operand 1665 states and 2086 transitions. [2018-12-03 04:00:40,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-12-03 04:00:40,262 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:00:40,262 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:00:40,262 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:00:40,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:40,262 INFO L82 PathProgramCache]: Analyzing trace with hash -548505771, now seen corresponding path program 1 times [2018-12-03 04:00:40,262 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:00:40,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:40,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:00:40,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:40,263 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:00:40,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:00:40,340 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-03 04:00:40,340 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:00:40,340 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:00:40,340 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 103 with the following transitions: [2018-12-03 04:00:40,340 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:00:40,341 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:00:40,341 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:00:40,429 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:00:40,430 INFO L272 AbstractInterpreter]: Visited 43 different actions 58 times. Merged at 5 different actions 7 times. Never widened. Performed 1657 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1657 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:00:40,431 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:40,431 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:00:40,596 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:00:40,596 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:00:41,839 INFO L418 sIntCurrentIteration]: We unified 101 AI predicates to 101 [2018-12-03 04:00:41,839 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:00:41,839 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:00:41,839 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-12-03 04:00:41,839 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:00:41,839 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-03 04:00:41,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-03 04:00:41,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-12-03 04:00:41,840 INFO L87 Difference]: Start difference. First operand 1665 states and 2086 transitions. Second operand 30 states. [2018-12-03 04:00:57,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:00:57,032 INFO L93 Difference]: Finished difference Result 3475 states and 4302 transitions. [2018-12-03 04:00:57,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-03 04:00:57,032 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 102 [2018-12-03 04:00:57,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:00:57,035 INFO L225 Difference]: With dead ends: 3475 [2018-12-03 04:00:57,036 INFO L226 Difference]: Without dead ends: 2528 [2018-12-03 04:00:57,037 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 103 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 389 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=155, Invalid=837, Unknown=0, NotChecked=0, Total=992 [2018-12-03 04:00:57,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2528 states. [2018-12-03 04:00:57,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2528 to 1709. [2018-12-03 04:00:57,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1709 states. [2018-12-03 04:00:57,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1709 states to 1709 states and 2143 transitions. [2018-12-03 04:00:57,167 INFO L78 Accepts]: Start accepts. Automaton has 1709 states and 2143 transitions. Word has length 102 [2018-12-03 04:00:57,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:00:57,168 INFO L480 AbstractCegarLoop]: Abstraction has 1709 states and 2143 transitions. [2018-12-03 04:00:57,168 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-03 04:00:57,168 INFO L276 IsEmpty]: Start isEmpty. Operand 1709 states and 2143 transitions. [2018-12-03 04:00:57,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-12-03 04:00:57,169 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:00:57,169 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:00:57,169 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:00:57,169 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:57,169 INFO L82 PathProgramCache]: Analyzing trace with hash -1387401743, now seen corresponding path program 1 times [2018-12-03 04:00:57,169 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:00:57,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:57,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:00:57,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:00:57,170 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:00:57,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:00:57,236 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-12-03 04:00:57,236 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:00:57,236 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:00:57,236 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 107 with the following transitions: [2018-12-03 04:00:57,236 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [676], [679], [681], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:00:57,237 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:00:57,237 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:00:57,357 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:00:57,357 INFO L272 AbstractInterpreter]: Visited 47 different actions 71 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1889 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1889 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:00:57,358 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:00:57,359 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:00:57,541 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:00:57,542 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:00:59,084 INFO L418 sIntCurrentIteration]: We unified 105 AI predicates to 105 [2018-12-03 04:00:59,085 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:00:59,085 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:00:59,085 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-03 04:00:59,085 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:00:59,085 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-03 04:00:59,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-03 04:00:59,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=844, Unknown=0, NotChecked=0, Total=992 [2018-12-03 04:00:59,085 INFO L87 Difference]: Start difference. First operand 1709 states and 2143 transitions. Second operand 32 states. [2018-12-03 04:01:17,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:01:17,734 INFO L93 Difference]: Finished difference Result 3519 states and 4359 transitions. [2018-12-03 04:01:17,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-03 04:01:17,734 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 106 [2018-12-03 04:01:17,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:01:17,738 INFO L225 Difference]: With dead ends: 3519 [2018-12-03 04:01:17,738 INFO L226 Difference]: Without dead ends: 2572 [2018-12-03 04:01:17,739 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 107 GetRequests, 74 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 424 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=163, Invalid=959, Unknown=0, NotChecked=0, Total=1122 [2018-12-03 04:01:17,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2572 states. [2018-12-03 04:01:17,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2572 to 1753. [2018-12-03 04:01:17,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1753 states. [2018-12-03 04:01:17,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1753 states to 1753 states and 2200 transitions. [2018-12-03 04:01:17,882 INFO L78 Accepts]: Start accepts. Automaton has 1753 states and 2200 transitions. Word has length 106 [2018-12-03 04:01:17,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:01:17,882 INFO L480 AbstractCegarLoop]: Abstraction has 1753 states and 2200 transitions. [2018-12-03 04:01:17,882 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-03 04:01:17,882 INFO L276 IsEmpty]: Start isEmpty. Operand 1753 states and 2200 transitions. [2018-12-03 04:01:17,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-12-03 04:01:17,883 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:01:17,883 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:01:17,883 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:01:17,883 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:01:17,883 INFO L82 PathProgramCache]: Analyzing trace with hash -867054703, now seen corresponding path program 1 times [2018-12-03 04:01:17,884 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:01:17,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:01:17,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:01:17,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:01:17,885 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:01:17,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:01:17,968 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-03 04:01:17,968 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:01:17,968 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:01:17,968 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 104 with the following transitions: [2018-12-03 04:01:17,968 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:01:17,969 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:01:17,969 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:01:18,061 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:01:18,062 INFO L272 AbstractInterpreter]: Visited 44 different actions 63 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1713 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1713 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:01:18,063 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:01:18,063 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:01:18,217 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:01:18,217 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:01:19,574 INFO L418 sIntCurrentIteration]: We unified 102 AI predicates to 102 [2018-12-03 04:01:19,575 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:01:19,575 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:01:19,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-12-03 04:01:19,575 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:01:19,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-03 04:01:19,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-03 04:01:19,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=786, Unknown=0, NotChecked=0, Total=930 [2018-12-03 04:01:19,576 INFO L87 Difference]: Start difference. First operand 1753 states and 2200 transitions. Second operand 31 states. [2018-12-03 04:01:34,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:01:34,299 INFO L93 Difference]: Finished difference Result 3570 states and 4423 transitions. [2018-12-03 04:01:34,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-03 04:01:34,299 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 103 [2018-12-03 04:01:34,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:01:34,303 INFO L225 Difference]: With dead ends: 3570 [2018-12-03 04:01:34,303 INFO L226 Difference]: Without dead ends: 2623 [2018-12-03 04:01:34,305 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 104 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 414 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=159, Invalid=897, Unknown=0, NotChecked=0, Total=1056 [2018-12-03 04:01:34,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2623 states. [2018-12-03 04:01:34,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2623 to 1797. [2018-12-03 04:01:34,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1797 states. [2018-12-03 04:01:34,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1797 states to 1797 states and 2257 transitions. [2018-12-03 04:01:34,462 INFO L78 Accepts]: Start accepts. Automaton has 1797 states and 2257 transitions. Word has length 103 [2018-12-03 04:01:34,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:01:34,462 INFO L480 AbstractCegarLoop]: Abstraction has 1797 states and 2257 transitions. [2018-12-03 04:01:34,462 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-03 04:01:34,462 INFO L276 IsEmpty]: Start isEmpty. Operand 1797 states and 2257 transitions. [2018-12-03 04:01:34,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-12-03 04:01:34,464 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:01:34,464 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:01:34,464 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:01:34,464 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:01:34,464 INFO L82 PathProgramCache]: Analyzing trace with hash 934277294, now seen corresponding path program 1 times [2018-12-03 04:01:34,464 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:01:34,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:01:34,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:01:34,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:01:34,465 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:01:34,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:01:34,541 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-03 04:01:34,541 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:01:34,542 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:01:34,542 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 105 with the following transitions: [2018-12-03 04:01:34,542 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:01:34,543 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:01:34,543 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:01:34,648 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:01:34,648 INFO L272 AbstractInterpreter]: Visited 45 different actions 64 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1727 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1727 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:01:34,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:01:34,650 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:01:34,807 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:01:34,807 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:01:36,350 INFO L418 sIntCurrentIteration]: We unified 103 AI predicates to 103 [2018-12-03 04:01:36,350 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:01:36,351 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:01:36,351 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-03 04:01:36,351 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:01:36,351 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-03 04:01:36,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-03 04:01:36,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=844, Unknown=0, NotChecked=0, Total=992 [2018-12-03 04:01:36,351 INFO L87 Difference]: Start difference. First operand 1797 states and 2257 transitions. Second operand 32 states. [2018-12-03 04:01:49,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:01:49,781 INFO L93 Difference]: Finished difference Result 3628 states and 4492 transitions. [2018-12-03 04:01:49,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-03 04:01:49,781 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 104 [2018-12-03 04:01:49,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:01:49,785 INFO L225 Difference]: With dead ends: 3628 [2018-12-03 04:01:49,785 INFO L226 Difference]: Without dead ends: 2681 [2018-12-03 04:01:49,786 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 105 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 439 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=163, Invalid=959, Unknown=0, NotChecked=0, Total=1122 [2018-12-03 04:01:49,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2681 states. [2018-12-03 04:01:49,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2681 to 1841. [2018-12-03 04:01:49,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1841 states. [2018-12-03 04:01:49,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1841 states to 1841 states and 2312 transitions. [2018-12-03 04:01:49,956 INFO L78 Accepts]: Start accepts. Automaton has 1841 states and 2312 transitions. Word has length 104 [2018-12-03 04:01:49,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:01:49,956 INFO L480 AbstractCegarLoop]: Abstraction has 1841 states and 2312 transitions. [2018-12-03 04:01:49,956 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-03 04:01:49,956 INFO L276 IsEmpty]: Start isEmpty. Operand 1841 states and 2312 transitions. [2018-12-03 04:01:49,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-12-03 04:01:49,957 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:01:49,957 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:01:49,957 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:01:49,957 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:01:49,957 INFO L82 PathProgramCache]: Analyzing trace with hash -168824598, now seen corresponding path program 1 times [2018-12-03 04:01:49,958 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:01:49,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:01:49,958 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:01:49,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:01:49,959 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:01:49,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:01:50,027 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-03 04:01:50,027 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:01:50,027 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:01:50,027 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 105 with the following transitions: [2018-12-03 04:01:50,027 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [672], [674], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:01:50,028 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:01:50,028 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:01:50,124 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:01:50,124 INFO L272 AbstractInterpreter]: Visited 46 different actions 66 times. Merged at 5 different actions 7 times. Never widened. Performed 1845 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1845 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:01:50,125 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:01:50,125 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:01:50,283 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:01:50,283 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:01:51,792 INFO L418 sIntCurrentIteration]: We unified 103 AI predicates to 103 [2018-12-03 04:01:51,792 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:01:51,793 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:01:51,793 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-12-03 04:01:51,793 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:01:51,793 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-03 04:01:51,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-03 04:01:51,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=786, Unknown=0, NotChecked=0, Total=930 [2018-12-03 04:01:51,794 INFO L87 Difference]: Start difference. First operand 1841 states and 2312 transitions. Second operand 31 states. [2018-12-03 04:02:05,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:02:05,758 INFO L93 Difference]: Finished difference Result 3666 states and 4541 transitions. [2018-12-03 04:02:05,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-03 04:02:05,758 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 104 [2018-12-03 04:02:05,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:02:05,762 INFO L225 Difference]: With dead ends: 3666 [2018-12-03 04:02:05,762 INFO L226 Difference]: Without dead ends: 2719 [2018-12-03 04:02:05,763 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 105 GetRequests, 73 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 409 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=159, Invalid=897, Unknown=0, NotChecked=0, Total=1056 [2018-12-03 04:02:05,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2719 states. [2018-12-03 04:02:05,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2719 to 1885. [2018-12-03 04:02:05,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1885 states. [2018-12-03 04:02:05,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1885 states to 1885 states and 2367 transitions. [2018-12-03 04:02:05,972 INFO L78 Accepts]: Start accepts. Automaton has 1885 states and 2367 transitions. Word has length 104 [2018-12-03 04:02:05,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:02:05,973 INFO L480 AbstractCegarLoop]: Abstraction has 1885 states and 2367 transitions. [2018-12-03 04:02:05,973 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-03 04:02:05,973 INFO L276 IsEmpty]: Start isEmpty. Operand 1885 states and 2367 transitions. [2018-12-03 04:02:05,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-03 04:02:05,974 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:02:05,974 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:02:05,974 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:02:05,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:02:05,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1048232447, now seen corresponding path program 1 times [2018-12-03 04:02:05,974 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:02:05,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:02:05,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:02:05,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:02:05,975 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:02:05,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:02:06,030 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-03 04:02:06,030 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:02:06,030 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:02:06,030 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 112 with the following transitions: [2018-12-03 04:02:06,030 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [672], [674], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 04:02:06,031 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:02:06,031 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:02:06,138 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:02:06,138 INFO L272 AbstractInterpreter]: Visited 53 different actions 77 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 2063 root evaluator evaluations with a maximum evaluation depth of 10. Performed 2063 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:02:06,139 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:02:06,139 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:02:06,327 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:02:06,327 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:02:08,130 INFO L418 sIntCurrentIteration]: We unified 110 AI predicates to 110 [2018-12-03 04:02:08,130 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:02:08,131 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:02:08,131 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [10] total 41 [2018-12-03 04:02:08,131 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:02:08,132 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-03 04:02:08,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-03 04:02:08,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-12-03 04:02:08,132 INFO L87 Difference]: Start difference. First operand 1885 states and 2367 transitions. Second operand 33 states. [2018-12-03 04:02:22,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:02:22,453 INFO L93 Difference]: Finished difference Result 3708 states and 4597 transitions. [2018-12-03 04:02:22,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-03 04:02:22,453 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 111 [2018-12-03 04:02:22,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:02:22,458 INFO L225 Difference]: With dead ends: 3708 [2018-12-03 04:02:22,458 INFO L226 Difference]: Without dead ends: 2761 [2018-12-03 04:02:22,460 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 112 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 451 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-12-03 04:02:22,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2761 states. [2018-12-03 04:02:22,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2761 to 1929. [2018-12-03 04:02:22,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1929 states. [2018-12-03 04:02:22,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1929 states to 1929 states and 2424 transitions. [2018-12-03 04:02:22,674 INFO L78 Accepts]: Start accepts. Automaton has 1929 states and 2424 transitions. Word has length 111 [2018-12-03 04:02:22,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:02:22,674 INFO L480 AbstractCegarLoop]: Abstraction has 1929 states and 2424 transitions. [2018-12-03 04:02:22,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-03 04:02:22,674 INFO L276 IsEmpty]: Start isEmpty. Operand 1929 states and 2424 transitions. [2018-12-03 04:02:22,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-12-03 04:02:22,675 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:02:22,675 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:02:22,675 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:02:22,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:02:22,676 INFO L82 PathProgramCache]: Analyzing trace with hash 27781771, now seen corresponding path program 1 times [2018-12-03 04:02:22,676 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:02:22,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:02:22,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:02:22,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:02:22,677 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:02:22,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:02:22,742 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-03 04:02:22,742 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:02:22,742 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:02:22,742 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 109 with the following transitions: [2018-12-03 04:02:22,742 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 04:02:22,743 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:02:22,743 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:02:22,835 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:02:22,835 INFO L272 AbstractInterpreter]: Visited 49 different actions 64 times. Merged at 5 different actions 7 times. Never widened. Performed 1831 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1831 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:02:22,838 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:02:22,838 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:02:23,001 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:02:23,001 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:02:24,459 INFO L418 sIntCurrentIteration]: We unified 107 AI predicates to 107 [2018-12-03 04:02:24,459 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:02:24,459 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:02:24,459 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-12-03 04:02:24,459 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:02:24,460 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-03 04:02:24,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-03 04:02:24,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=784, Unknown=0, NotChecked=0, Total=930 [2018-12-03 04:02:24,460 INFO L87 Difference]: Start difference. First operand 1929 states and 2424 transitions. Second operand 31 states. [2018-12-03 04:02:51,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:02:51,082 INFO L93 Difference]: Finished difference Result 3761 states and 4663 transitions. [2018-12-03 04:02:51,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-03 04:02:51,082 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 108 [2018-12-03 04:02:51,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:02:51,085 INFO L225 Difference]: With dead ends: 3761 [2018-12-03 04:02:51,085 INFO L226 Difference]: Without dead ends: 2814 [2018-12-03 04:02:51,086 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 109 GetRequests, 77 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 414 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=161, Invalid=895, Unknown=0, NotChecked=0, Total=1056 [2018-12-03 04:02:51,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2814 states. [2018-12-03 04:02:51,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2814 to 1975. [2018-12-03 04:02:51,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1975 states. [2018-12-03 04:02:51,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1975 states to 1975 states and 2483 transitions. [2018-12-03 04:02:51,297 INFO L78 Accepts]: Start accepts. Automaton has 1975 states and 2483 transitions. Word has length 108 [2018-12-03 04:02:51,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:02:51,297 INFO L480 AbstractCegarLoop]: Abstraction has 1975 states and 2483 transitions. [2018-12-03 04:02:51,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-03 04:02:51,297 INFO L276 IsEmpty]: Start isEmpty. Operand 1975 states and 2483 transitions. [2018-12-03 04:02:51,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-12-03 04:02:51,299 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:02:51,299 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:02:51,299 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:02:51,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:02:51,299 INFO L82 PathProgramCache]: Analyzing trace with hash 1387189799, now seen corresponding path program 1 times [2018-12-03 04:02:51,299 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:02:51,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:02:51,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:02:51,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:02:51,300 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:02:51,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:02:51,362 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-12-03 04:02:51,362 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:02:51,362 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:02:51,362 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 113 with the following transitions: [2018-12-03 04:02:51,363 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [676], [679], [681], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 04:02:51,363 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:02:51,364 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:02:51,471 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:02:51,471 INFO L272 AbstractInterpreter]: Visited 53 different actions 77 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 2063 root evaluator evaluations with a maximum evaluation depth of 10. Performed 2063 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:02:51,472 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:02:51,472 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:02:51,664 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:02:51,664 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:02:53,299 INFO L418 sIntCurrentIteration]: We unified 111 AI predicates to 111 [2018-12-03 04:02:53,299 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:02:53,299 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:02:53,299 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [10] total 41 [2018-12-03 04:02:53,299 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:02:53,299 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-03 04:02:53,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-03 04:02:53,300 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-12-03 04:02:53,300 INFO L87 Difference]: Start difference. First operand 1975 states and 2483 transitions. Second operand 33 states. [2018-12-03 04:03:16,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:03:16,061 INFO L93 Difference]: Finished difference Result 3805 states and 4720 transitions. [2018-12-03 04:03:16,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-03 04:03:16,061 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 112 [2018-12-03 04:03:16,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:03:16,064 INFO L225 Difference]: With dead ends: 3805 [2018-12-03 04:03:16,064 INFO L226 Difference]: Without dead ends: 2858 [2018-12-03 04:03:16,065 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 113 GetRequests, 79 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 451 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-12-03 04:03:16,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2858 states. [2018-12-03 04:03:16,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2858 to 2019. [2018-12-03 04:03:16,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2019 states. [2018-12-03 04:03:16,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2019 states to 2019 states and 2540 transitions. [2018-12-03 04:03:16,292 INFO L78 Accepts]: Start accepts. Automaton has 2019 states and 2540 transitions. Word has length 112 [2018-12-03 04:03:16,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:03:16,292 INFO L480 AbstractCegarLoop]: Abstraction has 2019 states and 2540 transitions. [2018-12-03 04:03:16,292 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-03 04:03:16,292 INFO L276 IsEmpty]: Start isEmpty. Operand 2019 states and 2540 transitions. [2018-12-03 04:03:16,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-12-03 04:03:16,293 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:03:16,293 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:03:16,293 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:03:16,293 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:03:16,294 INFO L82 PathProgramCache]: Analyzing trace with hash -407277920, now seen corresponding path program 1 times [2018-12-03 04:03:16,294 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:03:16,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:03:16,295 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:03:16,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:03:16,295 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:03:16,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:03:16,347 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-03 04:03:16,348 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:03:16,348 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:03:16,348 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 111 with the following transitions: [2018-12-03 04:03:16,348 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [672], [674], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 04:03:16,349 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:03:16,349 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:03:16,454 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:03:16,454 INFO L272 AbstractInterpreter]: Visited 52 different actions 76 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 2049 root evaluator evaluations with a maximum evaluation depth of 10. Performed 2049 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:03:16,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:03:16,458 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:03:16,628 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:03:16,628 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:03:18,185 INFO L418 sIntCurrentIteration]: We unified 109 AI predicates to 109 [2018-12-03 04:03:18,185 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:03:18,185 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:03:18,185 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-03 04:03:18,185 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:03:18,185 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-03 04:03:18,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-03 04:03:18,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-12-03 04:03:18,186 INFO L87 Difference]: Start difference. First operand 2019 states and 2540 transitions. Second operand 32 states. [2018-12-03 04:03:30,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:03:30,807 INFO L93 Difference]: Finished difference Result 3863 states and 4790 transitions. [2018-12-03 04:03:30,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-03 04:03:30,807 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 110 [2018-12-03 04:03:30,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:03:30,810 INFO L225 Difference]: With dead ends: 3863 [2018-12-03 04:03:30,810 INFO L226 Difference]: Without dead ends: 2916 [2018-12-03 04:03:30,811 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 111 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 435 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=165, Invalid=957, Unknown=0, NotChecked=0, Total=1122 [2018-12-03 04:03:30,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2916 states. [2018-12-03 04:03:31,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2916 to 2063. [2018-12-03 04:03:31,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2063 states. [2018-12-03 04:03:31,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2063 states to 2063 states and 2596 transitions. [2018-12-03 04:03:31,071 INFO L78 Accepts]: Start accepts. Automaton has 2063 states and 2596 transitions. Word has length 110 [2018-12-03 04:03:31,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:03:31,071 INFO L480 AbstractCegarLoop]: Abstraction has 2063 states and 2596 transitions. [2018-12-03 04:03:31,071 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-03 04:03:31,071 INFO L276 IsEmpty]: Start isEmpty. Operand 2063 states and 2596 transitions. [2018-12-03 04:03:31,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-12-03 04:03:31,072 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:03:31,072 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:03:31,072 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:03:31,072 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:03:31,073 INFO L82 PathProgramCache]: Analyzing trace with hash -182010085, now seen corresponding path program 1 times [2018-12-03 04:03:31,073 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:03:31,073 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:03:31,073 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:03:31,073 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:03:31,074 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:03:31,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:03:31,144 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-03 04:03:31,144 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:03:31,144 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:03:31,144 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 110 with the following transitions: [2018-12-03 04:03:31,144 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 04:03:31,145 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:03:31,145 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:03:31,244 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:03:31,244 INFO L272 AbstractInterpreter]: Visited 50 different actions 69 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1887 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1887 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:03:31,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:03:31,245 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:03:31,411 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:03:31,411 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:03:32,911 INFO L418 sIntCurrentIteration]: We unified 108 AI predicates to 108 [2018-12-03 04:03:32,911 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:03:32,912 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:03:32,912 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-03 04:03:32,912 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:03:32,912 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-03 04:03:32,912 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-03 04:03:32,912 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-12-03 04:03:32,912 INFO L87 Difference]: Start difference. First operand 2063 states and 2596 transitions. Second operand 32 states. [2018-12-03 04:03:51,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:03:51,472 INFO L93 Difference]: Finished difference Result 3907 states and 4846 transitions. [2018-12-03 04:03:51,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-03 04:03:51,472 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 109 [2018-12-03 04:03:51,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:03:51,475 INFO L225 Difference]: With dead ends: 3907 [2018-12-03 04:03:51,475 INFO L226 Difference]: Without dead ends: 2960 [2018-12-03 04:03:51,477 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 110 GetRequests, 77 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 440 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=165, Invalid=957, Unknown=0, NotChecked=0, Total=1122 [2018-12-03 04:03:51,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2960 states. [2018-12-03 04:03:51,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2960 to 2107. [2018-12-03 04:03:51,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2107 states. [2018-12-03 04:03:51,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2107 states to 2107 states and 2652 transitions. [2018-12-03 04:03:51,735 INFO L78 Accepts]: Start accepts. Automaton has 2107 states and 2652 transitions. Word has length 109 [2018-12-03 04:03:51,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:03:51,736 INFO L480 AbstractCegarLoop]: Abstraction has 2107 states and 2652 transitions. [2018-12-03 04:03:51,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-03 04:03:51,736 INFO L276 IsEmpty]: Start isEmpty. Operand 2107 states and 2652 transitions. [2018-12-03 04:03:51,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-12-03 04:03:51,737 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:03:51,737 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:03:51,737 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:03:51,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:03:51,738 INFO L82 PathProgramCache]: Analyzing trace with hash 695823972, now seen corresponding path program 1 times [2018-12-03 04:03:51,738 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:03:51,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:03:51,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:03:51,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:03:51,739 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:03:51,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:03:51,792 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-03 04:03:51,792 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:03:51,793 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:03:51,793 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 111 with the following transitions: [2018-12-03 04:03:51,793 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-03 04:03:51,794 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:03:51,794 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:03:51,913 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:03:51,913 INFO L272 AbstractInterpreter]: Visited 51 different actions 70 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1901 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1901 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-03 04:03:51,915 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:03:51,915 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:03:52,083 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-03 04:03:52,083 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:03:53,781 INFO L418 sIntCurrentIteration]: We unified 109 AI predicates to 109 [2018-12-03 04:03:53,781 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:03:53,781 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:03:53,781 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [10] total 41 [2018-12-03 04:03:53,781 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:03:53,781 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-03 04:03:53,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-03 04:03:53,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-12-03 04:03:53,782 INFO L87 Difference]: Start difference. First operand 2107 states and 2652 transitions. Second operand 33 states. [2018-12-03 04:04:14,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:04:14,066 INFO L93 Difference]: Finished difference Result 3958 states and 4908 transitions. [2018-12-03 04:04:14,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-03 04:04:14,066 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 110 [2018-12-03 04:04:14,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:04:14,070 INFO L225 Difference]: With dead ends: 3958 [2018-12-03 04:04:14,070 INFO L226 Difference]: Without dead ends: 3011 [2018-12-03 04:04:14,071 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 111 GetRequests, 77 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 466 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-12-03 04:04:14,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3011 states. [2018-12-03 04:04:14,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3011 to 1715. [2018-12-03 04:04:14,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1715 states. [2018-12-03 04:04:14,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2137 transitions. [2018-12-03 04:04:14,300 INFO L78 Accepts]: Start accepts. Automaton has 1715 states and 2137 transitions. Word has length 110 [2018-12-03 04:04:14,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:04:14,301 INFO L480 AbstractCegarLoop]: Abstraction has 1715 states and 2137 transitions. [2018-12-03 04:04:14,301 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-03 04:04:14,301 INFO L276 IsEmpty]: Start isEmpty. Operand 1715 states and 2137 transitions. [2018-12-03 04:04:14,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-03 04:04:14,302 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:04:14,302 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:04:14,302 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:04:14,302 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:04:14,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1533572085, now seen corresponding path program 1 times [2018-12-03 04:04:14,302 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:04:14,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:04:14,303 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:04:14,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:04:14,303 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:04:14,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:04:14,372 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-03 04:04:14,372 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:04:14,372 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:04:14,372 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 116 with the following transitions: [2018-12-03 04:04:14,372 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:04:14,373 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:04:14,373 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:04:14,653 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:04:14,653 INFO L272 AbstractInterpreter]: Visited 63 different actions 141 times. Merged at 18 different actions 28 times. Widened at 1 different actions 1 times. Performed 5832 root evaluator evaluations with a maximum evaluation depth of 4. Performed 5832 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 7 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-03 04:04:14,655 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:04:14,655 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:04:14,794 INFO L227 lantSequenceWeakener]: Weakened 73 states. On average, predicates are now at 94.04% of their original sizes. [2018-12-03 04:04:14,794 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:04:14,945 INFO L418 sIntCurrentIteration]: We unified 114 AI predicates to 114 [2018-12-03 04:04:14,945 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:04:14,945 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:04:14,945 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [9] total 33 [2018-12-03 04:04:14,945 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:04:14,946 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-03 04:04:14,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-03 04:04:14,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=558, Unknown=0, NotChecked=0, Total=650 [2018-12-03 04:04:14,946 INFO L87 Difference]: Start difference. First operand 1715 states and 2137 transitions. Second operand 26 states. [2018-12-03 04:04:23,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:04:23,959 INFO L93 Difference]: Finished difference Result 3756 states and 4649 transitions. [2018-12-03 04:04:23,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-03 04:04:23,959 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 115 [2018-12-03 04:04:23,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:04:23,963 INFO L225 Difference]: With dead ends: 3756 [2018-12-03 04:04:23,963 INFO L226 Difference]: Without dead ends: 2500 [2018-12-03 04:04:23,966 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 136 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 486 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=338, Invalid=1918, Unknown=0, NotChecked=0, Total=2256 [2018-12-03 04:04:23,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2500 states. [2018-12-03 04:04:24,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2500 to 2043. [2018-12-03 04:04:24,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2043 states. [2018-12-03 04:04:24,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2043 states to 2043 states and 2540 transitions. [2018-12-03 04:04:24,241 INFO L78 Accepts]: Start accepts. Automaton has 2043 states and 2540 transitions. Word has length 115 [2018-12-03 04:04:24,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:04:24,241 INFO L480 AbstractCegarLoop]: Abstraction has 2043 states and 2540 transitions. [2018-12-03 04:04:24,241 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-03 04:04:24,241 INFO L276 IsEmpty]: Start isEmpty. Operand 2043 states and 2540 transitions. [2018-12-03 04:04:24,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-03 04:04:24,242 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:04:24,242 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:04:24,243 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:04:24,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:04:24,243 INFO L82 PathProgramCache]: Analyzing trace with hash -130786366, now seen corresponding path program 1 times [2018-12-03 04:04:24,243 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:04:24,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:04:24,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:04:24,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:04:24,244 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:04:24,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:04:24,321 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-03 04:04:24,321 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:04:24,321 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:04:24,321 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 117 with the following transitions: [2018-12-03 04:04:24,322 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:04:24,322 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:04:24,322 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:04:24,690 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:04:24,690 INFO L272 AbstractInterpreter]: Visited 66 different actions 165 times. Merged at 18 different actions 28 times. Widened at 1 different actions 1 times. Performed 7322 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7322 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 7 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-03 04:04:24,692 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:04:24,692 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:04:24,832 INFO L227 lantSequenceWeakener]: Weakened 74 states. On average, predicates are now at 92.13% of their original sizes. [2018-12-03 04:04:24,832 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:04:25,038 INFO L418 sIntCurrentIteration]: We unified 115 AI predicates to 115 [2018-12-03 04:04:25,038 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:04:25,038 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:04:25,038 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-03 04:04:25,038 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:04:25,038 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-03 04:04:25,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-03 04:04:25,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=624, Unknown=0, NotChecked=0, Total=702 [2018-12-03 04:04:25,039 INFO L87 Difference]: Start difference. First operand 2043 states and 2540 transitions. Second operand 27 states. [2018-12-03 04:04:41,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:04:41,511 INFO L93 Difference]: Finished difference Result 4662 states and 5817 transitions. [2018-12-03 04:04:41,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-03 04:04:41,512 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 116 [2018-12-03 04:04:41,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:04:41,515 INFO L225 Difference]: With dead ends: 4662 [2018-12-03 04:04:41,515 INFO L226 Difference]: Without dead ends: 3406 [2018-12-03 04:04:41,517 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 163 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1384 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=704, Invalid=4846, Unknown=0, NotChecked=0, Total=5550 [2018-12-03 04:04:41,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3406 states. [2018-12-03 04:04:41,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3406 to 2371. [2018-12-03 04:04:41,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2371 states. [2018-12-03 04:04:41,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2371 states to 2371 states and 2957 transitions. [2018-12-03 04:04:41,850 INFO L78 Accepts]: Start accepts. Automaton has 2371 states and 2957 transitions. Word has length 116 [2018-12-03 04:04:41,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:04:41,850 INFO L480 AbstractCegarLoop]: Abstraction has 2371 states and 2957 transitions. [2018-12-03 04:04:41,850 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-03 04:04:41,850 INFO L276 IsEmpty]: Start isEmpty. Operand 2371 states and 2957 transitions. [2018-12-03 04:04:41,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-12-03 04:04:41,852 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:04:41,852 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:04:41,852 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:04:41,852 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:04:41,852 INFO L82 PathProgramCache]: Analyzing trace with hash -802655036, now seen corresponding path program 1 times [2018-12-03 04:04:41,852 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:04:41,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:04:41,853 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:04:41,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:04:41,853 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:04:41,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:04:41,911 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-03 04:04:41,912 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:04:41,912 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:04:41,912 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 118 with the following transitions: [2018-12-03 04:04:41,912 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:04:41,913 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:04:41,913 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:04:42,285 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:04:42,285 INFO L272 AbstractInterpreter]: Visited 67 different actions 164 times. Merged at 18 different actions 25 times. Never widened. Performed 7386 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7386 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 6 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-03 04:04:42,287 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:04:42,287 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:04:42,430 INFO L227 lantSequenceWeakener]: Weakened 75 states. On average, predicates are now at 92.14% of their original sizes. [2018-12-03 04:04:42,431 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:04:42,614 INFO L418 sIntCurrentIteration]: We unified 116 AI predicates to 116 [2018-12-03 04:04:42,614 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:04:42,615 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:04:42,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-03 04:04:42,615 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:04:42,615 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-03 04:04:42,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-03 04:04:42,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=624, Unknown=0, NotChecked=0, Total=702 [2018-12-03 04:04:42,615 INFO L87 Difference]: Start difference. First operand 2371 states and 2957 transitions. Second operand 27 states. [2018-12-03 04:04:59,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:04:59,775 INFO L93 Difference]: Finished difference Result 5015 states and 6225 transitions. [2018-12-03 04:04:59,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-03 04:04:59,775 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 117 [2018-12-03 04:04:59,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:04:59,779 INFO L225 Difference]: With dead ends: 5015 [2018-12-03 04:04:59,779 INFO L226 Difference]: Without dead ends: 3737 [2018-12-03 04:04:59,781 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 164 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1384 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=704, Invalid=4846, Unknown=0, NotChecked=0, Total=5550 [2018-12-03 04:04:59,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3737 states. [2018-12-03 04:05:00,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3737 to 2398. [2018-12-03 04:05:00,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2398 states. [2018-12-03 04:05:00,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2398 states to 2398 states and 3001 transitions. [2018-12-03 04:05:00,170 INFO L78 Accepts]: Start accepts. Automaton has 2398 states and 3001 transitions. Word has length 117 [2018-12-03 04:05:00,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:00,171 INFO L480 AbstractCegarLoop]: Abstraction has 2398 states and 3001 transitions. [2018-12-03 04:05:00,171 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-03 04:05:00,171 INFO L276 IsEmpty]: Start isEmpty. Operand 2398 states and 3001 transitions. [2018-12-03 04:05:00,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-03 04:05:00,172 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:00,172 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:00,172 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:00,173 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:00,173 INFO L82 PathProgramCache]: Analyzing trace with hash 748857671, now seen corresponding path program 1 times [2018-12-03 04:05:00,173 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:05:00,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:00,174 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:00,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:00,174 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:05:00,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:00,199 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-03 04:05:00,199 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:00,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 04:05:00,200 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:05:00,200 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 04:05:00,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 04:05:00,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:00,200 INFO L87 Difference]: Start difference. First operand 2398 states and 3001 transitions. Second operand 3 states. [2018-12-03 04:05:00,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:00,686 INFO L93 Difference]: Finished difference Result 5079 states and 6260 transitions. [2018-12-03 04:05:00,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 04:05:00,687 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 115 [2018-12-03 04:05:00,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:00,690 INFO L225 Difference]: With dead ends: 5079 [2018-12-03 04:05:00,691 INFO L226 Difference]: Without dead ends: 3303 [2018-12-03 04:05:00,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:00,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3303 states. [2018-12-03 04:05:01,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3303 to 3240. [2018-12-03 04:05:01,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3240 states. [2018-12-03 04:05:01,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3240 states to 3240 states and 3962 transitions. [2018-12-03 04:05:01,141 INFO L78 Accepts]: Start accepts. Automaton has 3240 states and 3962 transitions. Word has length 115 [2018-12-03 04:05:01,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:01,142 INFO L480 AbstractCegarLoop]: Abstraction has 3240 states and 3962 transitions. [2018-12-03 04:05:01,142 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 04:05:01,142 INFO L276 IsEmpty]: Start isEmpty. Operand 3240 states and 3962 transitions. [2018-12-03 04:05:01,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-12-03 04:05:01,143 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:01,143 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:01,143 INFO L423 AbstractCegarLoop]: === Iteration 34 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:01,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:01,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1364300325, now seen corresponding path program 1 times [2018-12-03 04:05:01,144 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:05:01,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:01,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:01,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:01,145 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:05:01,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:01,208 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-03 04:05:01,208 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:01,208 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:05:01,208 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 119 with the following transitions: [2018-12-03 04:05:01,208 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-03 04:05:01,209 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:05:01,209 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:05:01,592 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-03 04:05:01,592 INFO L272 AbstractInterpreter]: Visited 68 different actions 167 times. Merged at 18 different actions 25 times. Never widened. Performed 7452 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7452 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 6 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-03 04:05:01,593 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:01,593 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-03 04:05:01,738 INFO L227 lantSequenceWeakener]: Weakened 76 states. On average, predicates are now at 92.15% of their original sizes. [2018-12-03 04:05:01,738 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-03 04:05:01,951 INFO L418 sIntCurrentIteration]: We unified 117 AI predicates to 117 [2018-12-03 04:05:01,951 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-03 04:05:01,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:05:01,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-03 04:05:01,951 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-03 04:05:01,951 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-03 04:05:01,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-03 04:05:01,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=624, Unknown=0, NotChecked=0, Total=702 [2018-12-03 04:05:01,952 INFO L87 Difference]: Start difference. First operand 3240 states and 3962 transitions. Second operand 27 states. [2018-12-03 04:05:17,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:17,958 INFO L93 Difference]: Finished difference Result 6946 states and 8456 transitions. [2018-12-03 04:05:17,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-03 04:05:17,958 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 118 [2018-12-03 04:05:17,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:17,963 INFO L225 Difference]: With dead ends: 6946 [2018-12-03 04:05:17,963 INFO L226 Difference]: Without dead ends: 5118 [2018-12-03 04:05:17,966 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 165 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1384 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=704, Invalid=4846, Unknown=0, NotChecked=0, Total=5550 [2018-12-03 04:05:17,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5118 states. [2018-12-03 04:05:18,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5118 to 3267. [2018-12-03 04:05:18,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3267 states. [2018-12-03 04:05:18,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3267 states to 3267 states and 4003 transitions. [2018-12-03 04:05:18,464 INFO L78 Accepts]: Start accepts. Automaton has 3267 states and 4003 transitions. Word has length 118 [2018-12-03 04:05:18,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:18,464 INFO L480 AbstractCegarLoop]: Abstraction has 3267 states and 4003 transitions. [2018-12-03 04:05:18,464 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-03 04:05:18,464 INFO L276 IsEmpty]: Start isEmpty. Operand 3267 states and 4003 transitions. [2018-12-03 04:05:18,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-03 04:05:18,465 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:18,465 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:18,465 INFO L423 AbstractCegarLoop]: === Iteration 35 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:18,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:18,465 INFO L82 PathProgramCache]: Analyzing trace with hash -415603186, now seen corresponding path program 1 times [2018-12-03 04:05:18,465 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:05:18,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:18,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:18,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:18,466 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:05:18,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:18,506 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:18,507 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:18,507 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:05:18,507 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 117 with the following transitions: [2018-12-03 04:05:18,507 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [44], [47], [50], [62], [65], [68], [70], [73], [82], [101], [265], [268], [271], [274], [281], [285], [292], [311], [340], [359], [362], [365], [367], [462], [464], [465], [469], [472], [473], [561], [591], [593], [594], [637], [705], [711], [713], [724], [729], [731], [740], [742], [744], [758], [762], [764], [765], [768], [769], [789], [790], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [857], [858], [859], [860], [893], [905], [906], [927], [928], [961], [973], [974], [1009], [1011], [1012], [1015], [1016], [1019], [1020], [1021], [1022], [1023], [1049], [1050], [1051] [2018-12-03 04:05:18,508 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-03 04:05:18,508 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-03 04:05:18,977 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-03 04:05:18,977 INFO L272 AbstractInterpreter]: Visited 98 different actions 247 times. Merged at 29 different actions 85 times. Widened at 1 different actions 1 times. Performed 7293 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7293 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 10 fixpoints after 6 different actions. Largest state had 185 variables. [2018-12-03 04:05:18,982 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:18,983 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-03 04:05:18,983 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:18,983 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 04:05:18,993 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:18,993 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-03 04:05:19,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:19,091 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:19,134 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-03 04:05:19,134 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:19,209 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:19,227 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-03 04:05:19,227 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 11 [2018-12-03 04:05:19,227 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-03 04:05:19,227 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-03 04:05:19,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-03 04:05:19,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-12-03 04:05:19,228 INFO L87 Difference]: Start difference. First operand 3267 states and 4003 transitions. Second operand 8 states. [2018-12-03 04:05:19,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:19,759 INFO L93 Difference]: Finished difference Result 6510 states and 7980 transitions. [2018-12-03 04:05:19,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-03 04:05:19,760 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 116 [2018-12-03 04:05:19,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:19,763 INFO L225 Difference]: With dead ends: 6510 [2018-12-03 04:05:19,763 INFO L226 Difference]: Without dead ends: 3268 [2018-12-03 04:05:19,766 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 226 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=81, Unknown=0, NotChecked=0, Total=132 [2018-12-03 04:05:19,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3268 states. [2018-12-03 04:05:20,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3268 to 3268. [2018-12-03 04:05:20,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3268 states. [2018-12-03 04:05:20,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3268 states to 3268 states and 4004 transitions. [2018-12-03 04:05:20,268 INFO L78 Accepts]: Start accepts. Automaton has 3268 states and 4004 transitions. Word has length 116 [2018-12-03 04:05:20,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:20,268 INFO L480 AbstractCegarLoop]: Abstraction has 3268 states and 4004 transitions. [2018-12-03 04:05:20,268 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-03 04:05:20,268 INFO L276 IsEmpty]: Start isEmpty. Operand 3268 states and 4004 transitions. [2018-12-03 04:05:20,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-12-03 04:05:20,269 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:20,269 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:20,269 INFO L423 AbstractCegarLoop]: === Iteration 36 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:20,270 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:20,270 INFO L82 PathProgramCache]: Analyzing trace with hash -482142694, now seen corresponding path program 2 times [2018-12-03 04:05:20,270 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:05:20,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:20,271 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:20,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:20,271 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:05:20,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:20,323 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:20,323 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:20,323 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:05:20,323 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-03 04:05:20,324 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-03 04:05:20,324 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:20,324 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 04:05:20,331 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-03 04:05:20,332 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-03 04:05:20,421 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-12-03 04:05:20,421 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-03 04:05:20,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:20,454 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-03 04:05:20,454 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:20,537 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:20,554 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-03 04:05:20,554 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 14 [2018-12-03 04:05:20,554 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-03 04:05:20,554 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-03 04:05:20,554 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-03 04:05:20,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2018-12-03 04:05:20,555 INFO L87 Difference]: Start difference. First operand 3268 states and 4004 transitions. Second operand 10 states. [2018-12-03 04:05:21,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:21,083 INFO L93 Difference]: Finished difference Result 6511 states and 7981 transitions. [2018-12-03 04:05:21,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 04:05:21,083 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 117 [2018-12-03 04:05:21,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:21,087 INFO L225 Difference]: With dead ends: 6511 [2018-12-03 04:05:21,087 INFO L226 Difference]: Without dead ends: 3269 [2018-12-03 04:05:21,089 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 226 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=82, Invalid=128, Unknown=0, NotChecked=0, Total=210 [2018-12-03 04:05:21,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3269 states. [2018-12-03 04:05:21,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3269 to 3269. [2018-12-03 04:05:21,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3269 states. [2018-12-03 04:05:21,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3269 states to 3269 states and 4005 transitions. [2018-12-03 04:05:21,593 INFO L78 Accepts]: Start accepts. Automaton has 3269 states and 4005 transitions. Word has length 117 [2018-12-03 04:05:21,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:21,593 INFO L480 AbstractCegarLoop]: Abstraction has 3269 states and 4005 transitions. [2018-12-03 04:05:21,593 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-03 04:05:21,593 INFO L276 IsEmpty]: Start isEmpty. Operand 3269 states and 4005 transitions. [2018-12-03 04:05:21,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-12-03 04:05:21,594 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:21,594 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:21,594 INFO L423 AbstractCegarLoop]: === Iteration 37 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:21,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:21,595 INFO L82 PathProgramCache]: Analyzing trace with hash 1750099854, now seen corresponding path program 3 times [2018-12-03 04:05:21,595 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:05:21,595 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:21,596 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-03 04:05:21,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:21,596 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:05:21,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:21,650 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:21,651 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:21,651 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-03 04:05:21,651 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-03 04:05:21,651 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-03 04:05:21,651 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:21,651 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 04:05:21,661 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-03 04:05:21,661 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-03 04:05:21,729 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-03 04:05:21,729 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-03 04:05:21,733 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:21,762 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-03 04:05:21,762 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:21,848 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:21,863 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-03 04:05:21,864 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 16 [2018-12-03 04:05:21,864 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-03 04:05:21,864 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-03 04:05:21,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-03 04:05:21,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-12-03 04:05:21,864 INFO L87 Difference]: Start difference. First operand 3269 states and 4005 transitions. Second operand 12 states. [2018-12-03 04:05:22,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:22,366 INFO L93 Difference]: Finished difference Result 6512 states and 7982 transitions. [2018-12-03 04:05:22,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-03 04:05:22,366 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 118 [2018-12-03 04:05:22,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:22,369 INFO L225 Difference]: With dead ends: 6512 [2018-12-03 04:05:22,370 INFO L226 Difference]: Without dead ends: 3270 [2018-12-03 04:05:22,373 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 226 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=106, Invalid=166, Unknown=0, NotChecked=0, Total=272 [2018-12-03 04:05:22,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3270 states. [2018-12-03 04:05:22,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3270 to 3270. [2018-12-03 04:05:22,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3270 states. [2018-12-03 04:05:22,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3270 states to 3270 states and 4006 transitions. [2018-12-03 04:05:22,892 INFO L78 Accepts]: Start accepts. Automaton has 3270 states and 4006 transitions. Word has length 118 [2018-12-03 04:05:22,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:22,892 INFO L480 AbstractCegarLoop]: Abstraction has 3270 states and 4006 transitions. [2018-12-03 04:05:22,893 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-03 04:05:22,893 INFO L276 IsEmpty]: Start isEmpty. Operand 3270 states and 4006 transitions. [2018-12-03 04:05:22,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-12-03 04:05:22,894 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:22,895 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:22,895 INFO L423 AbstractCegarLoop]: === Iteration 38 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:22,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:22,895 INFO L82 PathProgramCache]: Analyzing trace with hash -2064825190, now seen corresponding path program 4 times [2018-12-03 04:05:22,895 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-03 04:05:22,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:22,896 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-03 04:05:22,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 04:05:22,896 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-03 04:05:22,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-03 04:05:22,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-03 04:05:23,004 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-03 04:05:23,028 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-12-03 04:05:23,069 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 194 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-03 04:05:23,070 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 234 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-03 04:05:23,070 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 226 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-03 04:05:23,071 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 192 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-03 04:05:23,083 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,084 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,085 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,086 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,086 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,093 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,093 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,094 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,094 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,099 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,100 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,101 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,101 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,102 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,102 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,103 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,104 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,104 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,105 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,105 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,105 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,107 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,107 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,107 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,108 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,108 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,109 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,109 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,110 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,110 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,111 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,111 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,111 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,112 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,112 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,112 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,113 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,113 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,113 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:23,141 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.12 04:05:23 BoogieIcfgContainer [2018-12-03 04:05:23,141 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-03 04:05:23,141 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-03 04:05:23,141 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-03 04:05:23,142 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-03 04:05:23,142 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 03:58:16" (3/4) ... [2018-12-03 04:05:23,144 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-12-03 04:05:23,144 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-03 04:05:23,145 INFO L168 Benchmark]: Toolchain (without parser) took 428516.16 ms. Allocated memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 954.9 MB in the beginning and 1.7 GB in the end (delta: -779.9 MB). Peak memory consumption was 646.7 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:23,146 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 982.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-03 04:05:23,146 INFO L168 Benchmark]: CACSL2BoogieTranslator took 613.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.4 MB). Free memory was 954.9 MB in the beginning and 1.1 GB in the end (delta: -143.5 MB). Peak memory consumption was 51.8 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:23,146 INFO L168 Benchmark]: Boogie Procedure Inliner took 29.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:23,147 INFO L168 Benchmark]: Boogie Preprocessor took 44.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:23,147 INFO L168 Benchmark]: RCFGBuilder took 746.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 952.8 MB in the end (delta: 131.8 MB). Peak memory consumption was 131.8 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:23,147 INFO L168 Benchmark]: TraceAbstraction took 427075.94 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.3 GB). Free memory was 952.8 MB in the beginning and 1.7 GB in the end (delta: -782.0 MB). Peak memory consumption was 496.2 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:23,147 INFO L168 Benchmark]: Witness Printer took 2.98 ms. Allocated memory is still 2.5 GB. Free memory is still 1.7 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-03 04:05:23,149 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 982.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 613.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.4 MB). Free memory was 954.9 MB in the beginning and 1.1 GB in the end (delta: -143.5 MB). Peak memory consumption was 51.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 29.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 746.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 952.8 MB in the end (delta: 131.8 MB). Peak memory consumption was 131.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 427075.94 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.3 GB). Free memory was 952.8 MB in the beginning and 1.7 GB in the end (delta: -782.0 MB). Peak memory consumption was 496.2 MB. Max. memory is 11.5 GB. * Witness Printer took 2.98 ms. Allocated memory is still 2.5 GB. Free memory is still 1.7 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 194 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 234 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 226 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 192 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1664]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2219, overapproximation of bitwiseAnd at line 1830. Possible FailurePath: [L1687] int ldv_irq_1_2 = 0; [L1688] int LDV_IN_INTERRUPT = 1; [L1689] int ldv_irq_1_3 = 0; [L1690] struct platform_device *tegra_rtc_driver_group0 ; [L1691] void *ldv_irq_data_1_1 ; [L1692] int ldv_irq_1_1 = 0; [L1693] int ldv_irq_1_0 = 0; [L1694] int ldv_irq_line_1_3 ; [L1695] void *ldv_irq_data_1_0 ; [L1696] int ldv_state_variable_0 ; [L1697] struct device *tegra_rtc_ops_group1 ; [L1698] int ldv_state_variable_3 ; [L1699] int ldv_irq_line_1_0 ; [L1700] int ldv_state_variable_2 ; [L1701] void *ldv_irq_data_1_3 ; [L1702] int ref_cnt ; [L1703] int ldv_irq_line_1_1 ; [L1704] struct rtc_time *tegra_rtc_ops_group0 ; [L1705] void *ldv_irq_data_1_2 ; [L1706] int ldv_state_variable_1 ; [L1707] int ldv_irq_line_1_2 ; [L1708] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2050-L2052] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2218-L2219] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2235] int ldv_retval_2 ; [L2236] int ldv_retval_0 ; [L2238] int ldv_retval_1 ; [L2761] int ldv_init = 0; VAL [\old(LDV_IN_INTERRUPT)=172, \old(ldv_init)=198, \old(ldv_irq_1_0)=205, \old(ldv_irq_1_1)=197, \old(ldv_irq_1_2)=208, \old(ldv_irq_1_3)=196, \old(ldv_irq_data_1_0)=199, \old(ldv_irq_data_1_0)=161, \old(ldv_irq_data_1_1)=215, \old(ldv_irq_data_1_1)=187, \old(ldv_irq_data_1_2)=177, \old(ldv_irq_data_1_2)=191, \old(ldv_irq_data_1_3)=154, \old(ldv_irq_data_1_3)=203, \old(ldv_irq_line_1_0)=206, \old(ldv_irq_line_1_1)=233, \old(ldv_irq_line_1_2)=229, \old(ldv_irq_line_1_3)=167, \old(ldv_retval_0)=171, \old(ldv_retval_1)=164, \old(ldv_retval_2)=190, \old(ldv_state_variable_0)=186, \old(ldv_state_variable_1)=217, \old(ldv_state_variable_2)=209, \old(ldv_state_variable_3)=236, \old(ref_cnt)=204, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=200, \old(tegra_rtc_driver_group0)=224, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=180, \old(tegra_rtc_ops_group0)=202, \old(tegra_rtc_ops_group1)=195, \old(tegra_rtc_ops_group1)=221, \old(tegra_rtc_ops_group2)=174, \old(tegra_rtc_ops_group2)=157, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2390] struct seq_file *ldvarg1 ; [L2391] void *tmp ; [L2392] unsigned int ldvarg0 ; [L2393] unsigned int tmp___0 ; [L2394] pm_message_t ldvarg2 ; [L2395] int tmp___1 ; [L2396] int tmp___2 ; [L2397] int tmp___3 ; [L2398] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2400] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] tmp = ldv_zalloc(136U) [L2401] ldvarg1 = (struct seq_file *)tmp [L2402] tmp___0 = __VERIFIER_nondet_uint() [L2403] ldvarg0 = tmp___0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2404] FCALL ldv_initialize() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2405] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, memset((void *)(& ldvarg2), 0, 4U)={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2406] ldv_state_variable_1 = 1 [L2407] ref_cnt = 0 [L2408] ldv_state_variable_0 = 1 [L2409] ldv_state_variable_3 = 0 [L2410] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1] [L2421] COND TRUE ldv_state_variable_0 != 0 [L2422] tmp___2 = __VERIFIER_nondet_int() [L2424] case 0: [L2432] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2433] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2434] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2222] int tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] CALL, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={211:0}, arg1={-1:11}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2842] return __VERIFIER_nondet_int(); [L2224] RET, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe)=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2225] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2434] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2434] ldv_retval_0 = tegra_rtc_init() [L2435] COND TRUE ldv_retval_0 == 0 [L2436] ldv_state_variable_0 = 3 [L2437] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2438] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2355] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2357] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] tmp = ldv_zalloc(624U) [L2358] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2438] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2441] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: [L2566] case 1: [L2576] case 2: [L2596] case 3: [L2606] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2607] COND TRUE ldv_state_variable_2 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2608] CALL ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2830] return __VERIFIER_nondet_int(); [L2608] RET ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_probe_2()=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2609] ldv_state_variable_2 = 2 [L2610] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=0] [L2555] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=0] [L2560] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=0] [L2561] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2214] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1952] struct tegra_rtc_info *info ; [L1953] void *tmp ; [L1954] unsigned int status ; [L1955] unsigned long sl_irq_flags ; [L1956] u32 __v ; [L1957] u32 __v___0 ; VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, arg0={0:12}, external_alloc()={182:228}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1959] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={182:228}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] tmp = dev_get_drvdata((struct device const *)dev) [L1960] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, enabled=0, info={182:228}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={182:228}] [L1961] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1835] struct tegra_rtc_info *info ; [L1836] void *tmp ; [L1837] int retries ; [L1838] int tmp___0 ; [L1839] u32 tmp___1 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, arg0={0:12}, external_alloc()={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1841] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] tmp = dev_get_drvdata((struct device const *)dev) [L1842] info = (struct tegra_rtc_info *)tmp [L1843] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={165:0}] [L1854] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1825] u32 __v ; [L1826] u32 __v___0 ; [L1828] EXPR info->rtc_base [L1828] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1828] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1829] __v = __v___0 [L1830] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, __v=156, __v___0=156, info={165:0}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1854] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={165:0}] [L1854] tmp___1 = tegra_rtc_check_busy(info) [L1855] COND FALSE !(tmp___1 != 0U) [L1859] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={162:201}, dev={0:12}, dev={0:12}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={165:0}, tmp___1=0] [L1961] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, enabled=0, info={182:228}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={182:228}] [L1962] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2775] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2777] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1664] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 65 procedures, 489 locations, 1 error locations. UNSAFE Result, 427.0s OverallTime, 38 OverallIterations, 4 TraceHistogramMax, 379.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 15782 SDtfs, 14578 SDslu, 57267 SDs, 0 SdLazy, 11707 SolverSat, 3582 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 183.5s Time, PredicateUnifierStatistics: 50 DeclaredPredicates, 3513 GetRequests, 2543 SyntacticMatches, 24 SemanticMatches, 946 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12564 ImplicationChecksByTransitivity, 31.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3270occurred in iteration=37, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 4.2s AbstIntTime, 26 AbstIntIterations, 25 AbstIntStrong, 0.9927433883928556 AbsIntWeakeningRatio, 2.387924230465667 AbsIntAvgWeakeningVarsNumRemoved, 51.701262825572215 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 6.8s AutomataMinimizationTime, 37 MinimizatonAttempts, 20819 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.2s InterpolantComputationTime, 4100 NumberOfCodeBlocks, 4100 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 4289 ConstructedInterpolants, 0 QuantifiedInterpolants, 647626 SizeOfPredicates, 3 NumberOfNonLiveVariables, 3102 ConjunctsInSsa, 15 ConjunctsInUnsatCore, 43 InterpolantComputations, 9 PerfectInterpolantSequences, 879/1084 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-635dfa2 [2018-12-03 04:05:24,635 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-03 04:05:24,636 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-03 04:05:24,645 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-03 04:05:24,645 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-03 04:05:24,646 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-03 04:05:24,647 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-03 04:05:24,648 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-03 04:05:24,649 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-03 04:05:24,650 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-03 04:05:24,650 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-03 04:05:24,651 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-03 04:05:24,651 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-03 04:05:24,652 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-03 04:05:24,653 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-03 04:05:24,653 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-03 04:05:24,654 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-03 04:05:24,655 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-03 04:05:24,656 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-03 04:05:24,657 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-03 04:05:24,658 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-03 04:05:24,659 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-03 04:05:24,660 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-03 04:05:24,661 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-03 04:05:24,661 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-03 04:05:24,661 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-03 04:05:24,662 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-03 04:05:24,662 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-03 04:05:24,663 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-03 04:05:24,664 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-03 04:05:24,664 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-03 04:05:24,664 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-03 04:05:24,665 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-03 04:05:24,665 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-03 04:05:24,665 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-03 04:05:24,666 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-03 04:05:24,666 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2018-12-03 04:05:24,675 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-03 04:05:24,676 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-03 04:05:24,676 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-03 04:05:24,676 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-03 04:05:24,676 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-03 04:05:24,676 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-03 04:05:24,677 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-03 04:05:24,677 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-03 04:05:24,677 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-03 04:05:24,677 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-03 04:05:24,677 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-03 04:05:24,677 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-03 04:05:24,677 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-03 04:05:24,677 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-03 04:05:24,678 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-03 04:05:24,678 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-03 04:05:24,679 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * Command for external solver=cvc4 --incremental --rewrite-divk --print-success --lang smt [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-12-03 04:05:24,679 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a [2018-12-03 04:05:24,697 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-03 04:05:24,706 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-03 04:05:24,709 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-03 04:05:24,710 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-03 04:05:24,711 INFO L276 PluginConnector]: CDTParser initialized [2018-12-03 04:05:24,711 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-03 04:05:24,753 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/ee33a1e2e/ed5bb040e471415683448b606cad5fc6/FLAGc650aabe9 [2018-12-03 04:05:25,254 INFO L307 CDTParser]: Found 1 translation units. [2018-12-03 04:05:25,255 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-03 04:05:25,266 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/ee33a1e2e/ed5bb040e471415683448b606cad5fc6/FLAGc650aabe9 [2018-12-03 04:05:25,732 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/data/ee33a1e2e/ed5bb040e471415683448b606cad5fc6 [2018-12-03 04:05:25,734 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-03 04:05:25,735 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-03 04:05:25,735 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-03 04:05:25,735 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-03 04:05:25,738 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-03 04:05:25,739 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.12 04:05:25" (1/1) ... [2018-12-03 04:05:25,741 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@47abe2bb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:25, skipping insertion in model container [2018-12-03 04:05:25,741 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.12 04:05:25" (1/1) ... [2018-12-03 04:05:25,747 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-03 04:05:25,788 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-03 04:05:26,191 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-03 04:05:26,284 INFO L191 MainTranslator]: Completed pre-run [2018-12-03 04:05:26,358 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-03 04:05:26,395 INFO L195 MainTranslator]: Completed translation [2018-12-03 04:05:26,395 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26 WrapperNode [2018-12-03 04:05:26,395 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-03 04:05:26,396 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-03 04:05:26,396 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-03 04:05:26,396 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-03 04:05:26,401 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,419 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,425 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-03 04:05:26,426 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-03 04:05:26,426 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-03 04:05:26,426 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-03 04:05:26,432 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,432 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,437 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,437 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,457 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,462 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,466 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... [2018-12-03 04:05:26,471 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-03 04:05:26,471 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-03 04:05:26,471 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-03 04:05:26,471 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-03 04:05:26,472 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-03 04:05:26,516 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-12-03 04:05:26,516 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-12-03 04:05:26,516 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-12-03 04:05:26,516 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2018-12-03 04:05:26,516 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1 [2018-12-03 04:05:26,516 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-12-03 04:05:26,517 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_unregister [2018-12-03 04:05:26,517 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE8 [2018-12-03 04:05:26,517 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-03 04:05:26,517 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-12-03 04:05:26,517 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-12-03 04:05:26,517 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-12-03 04:05:26,517 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-12-03 04:05:26,518 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-12-03 04:05:26,518 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-12-03 04:05:26,518 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize [2018-12-03 04:05:26,518 INFO L130 BoogieDeclarations]: Found specification of procedure external_alloc [2018-12-03 04:05:26,518 INFO L138 BoogieDeclarations]: Found implementation of procedure external_alloc [2018-12-03 04:05:26,518 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-12-03 04:05:26,518 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-12-03 04:05:26,518 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-12-03 04:05:26,519 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2018-12-03 04:05:26,519 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-12-03 04:05:26,519 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-12-03 04:05:26,519 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-12-03 04:05:26,519 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-12-03 04:05:26,519 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-12-03 04:05:26,519 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2018-12-03 04:05:26,519 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-12-03 04:05:26,520 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-12-03 04:05:26,520 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-12-03 04:05:26,520 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-12-03 04:05:26,520 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-12-03 04:05:26,520 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-12-03 04:05:26,520 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-12-03 04:05:26,520 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2018-12-03 04:05:26,520 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_external_alloc [2018-12-03 04:05:26,520 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-12-03 04:05:26,521 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2018-12-03 04:05:26,521 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-12-03 04:05:26,521 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2018-12-03 04:05:26,521 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-12-03 04:05:26,521 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2018-12-03 04:05:26,521 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-12-03 04:05:26,521 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-12-03 04:05:26,521 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-12-03 04:05:26,522 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-12-03 04:05:26,522 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-12-03 04:05:26,522 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_release_3 [2018-12-03 04:05:26,522 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-12-03 04:05:26,522 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-12-03 04:05:26,522 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-12-03 04:05:26,522 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-12-03 04:05:26,522 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-12-03 04:05:26,523 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-12-03 04:05:26,523 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-12-03 04:05:26,523 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-12-03 04:05:26,523 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-12-03 04:05:26,523 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-12-03 04:05:26,523 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-12-03 04:05:26,523 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2018-12-03 04:05:26,523 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-12-03 04:05:26,523 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_probe [2018-12-03 04:05:26,524 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-12-03 04:05:26,524 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_valid_tm [2018-12-03 04:05:26,524 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-12-03 04:05:26,524 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-12-03 04:05:26,524 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-03 04:05:26,524 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-03 04:05:26,524 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-12-03 04:05:26,524 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-12-03 04:05:26,524 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-12-03 04:05:26,525 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-12-03 04:05:26,525 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-12-03 04:05:26,525 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-12-03 04:05:26,525 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-12-03 04:05:26,525 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_update_irq [2018-12-03 04:05:26,525 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-12-03 04:05:26,525 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2018-12-03 04:05:26,525 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-03 04:05:26,525 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-03 04:05:26,526 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-12-03 04:05:26,526 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2018-12-03 04:05:26,526 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-12-03 04:05:26,526 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-12-03 04:05:26,526 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-12-03 04:05:26,526 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-12-03 04:05:26,526 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-12-03 04:05:26,526 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_unlock_irqrestore [2018-12-03 04:05:26,526 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-12-03 04:05:26,526 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-12-03 04:05:26,527 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-12-03 04:05:26,527 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-12-03 04:05:26,527 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-12-03 04:05:26,527 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-12-03 04:05:26,527 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-12-03 04:05:26,527 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-12-03 04:05:26,527 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-12-03 04:05:26,527 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-12-03 04:05:26,527 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2018-12-03 04:05:26,527 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE8 [2018-12-03 04:05:26,528 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1 [2018-12-03 04:05:26,528 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-12-03 04:05:26,528 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-03 04:05:26,528 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-12-03 04:05:26,528 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_set_drvdata [2018-12-03 04:05:26,528 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-12-03 04:05:26,528 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-12-03 04:05:26,528 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-12-03 04:05:26,528 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-12-03 04:05:26,528 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-12-03 04:05:26,529 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-12-03 04:05:26,529 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-12-03 04:05:26,529 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1 [2018-12-03 04:05:26,529 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-12-03 04:05:26,529 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-12-03 04:05:26,529 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-12-03 04:05:26,529 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-12-03 04:05:26,529 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-12-03 04:05:26,529 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-12-03 04:05:26,530 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-12-03 04:05:26,530 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-12-03 04:05:26,530 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-12-03 04:05:26,530 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-12-03 04:05:26,530 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-12-03 04:05:26,530 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-12-03 04:05:26,530 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-12-03 04:05:26,530 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-12-03 04:05:26,530 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-12-03 04:05:26,531 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_3 [2018-12-03 04:05:26,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-12-03 04:05:26,531 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_2 [2018-12-03 04:05:26,531 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-12-03 04:05:26,531 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-12-03 04:05:26,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-12-03 04:05:26,531 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2018-12-03 04:05:26,531 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-12-03 04:05:26,531 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-12-03 04:05:26,531 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-12-03 04:05:26,532 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-12-03 04:05:26,532 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-03 04:05:26,532 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-03 04:05:29,368 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-03 04:05:29,368 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-12-03 04:05:29,368 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 04:05:29 BoogieIcfgContainer [2018-12-03 04:05:29,369 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-03 04:05:29,369 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-03 04:05:29,369 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-03 04:05:29,371 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-03 04:05:29,371 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.12 04:05:25" (1/3) ... [2018-12-03 04:05:29,372 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@22cb6dd0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.12 04:05:29, skipping insertion in model container [2018-12-03 04:05:29,372 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 04:05:26" (2/3) ... [2018-12-03 04:05:29,372 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@22cb6dd0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.12 04:05:29, skipping insertion in model container [2018-12-03 04:05:29,372 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 04:05:29" (3/3) ... [2018-12-03 04:05:29,373 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-03 04:05:29,379 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-03 04:05:29,385 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-03 04:05:29,394 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-03 04:05:29,414 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-03 04:05:29,415 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-03 04:05:29,415 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-03 04:05:29,415 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-03 04:05:29,415 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-03 04:05:29,415 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-03 04:05:29,415 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-03 04:05:29,415 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-03 04:05:29,415 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-03 04:05:29,431 INFO L276 IsEmpty]: Start isEmpty. Operand 486 states. [2018-12-03 04:05:29,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-03 04:05:29,438 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:29,439 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:29,440 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:29,444 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:29,444 INFO L82 PathProgramCache]: Analyzing trace with hash 1646624460, now seen corresponding path program 1 times [2018-12-03 04:05:29,447 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:29,447 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:29,467 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:29,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:29,616 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:29,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 04:05:29,641 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:29,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:29,645 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 04:05:29,647 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 04:05:29,654 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 04:05:29,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:29,656 INFO L87 Difference]: Start difference. First operand 486 states. Second operand 3 states. [2018-12-03 04:05:29,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:29,729 INFO L93 Difference]: Finished difference Result 822 states and 1040 transitions. [2018-12-03 04:05:29,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 04:05:29,730 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-03 04:05:29,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:29,740 INFO L225 Difference]: With dead ends: 822 [2018-12-03 04:05:29,740 INFO L226 Difference]: Without dead ends: 331 [2018-12-03 04:05:29,744 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:29,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2018-12-03 04:05:29,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 331. [2018-12-03 04:05:29,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 331 states. [2018-12-03 04:05:29,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 331 states to 331 states and 401 transitions. [2018-12-03 04:05:29,788 INFO L78 Accepts]: Start accepts. Automaton has 331 states and 401 transitions. Word has length 47 [2018-12-03 04:05:29,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:29,789 INFO L480 AbstractCegarLoop]: Abstraction has 331 states and 401 transitions. [2018-12-03 04:05:29,789 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 04:05:29,789 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 401 transitions. [2018-12-03 04:05:29,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-12-03 04:05:29,792 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:29,792 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:29,792 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:29,792 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:29,792 INFO L82 PathProgramCache]: Analyzing trace with hash -884307126, now seen corresponding path program 1 times [2018-12-03 04:05:29,793 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:29,793 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:29,815 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:29,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:29,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:29,965 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:29,965 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:29,967 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:29,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 04:05:29,968 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 04:05:29,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 04:05:29,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 04:05:29,968 INFO L87 Difference]: Start difference. First operand 331 states and 401 transitions. Second operand 5 states. [2018-12-03 04:05:30,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:30,070 INFO L93 Difference]: Finished difference Result 970 states and 1194 transitions. [2018-12-03 04:05:30,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-03 04:05:30,071 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-12-03 04:05:30,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:30,076 INFO L225 Difference]: With dead ends: 970 [2018-12-03 04:05:30,076 INFO L226 Difference]: Without dead ends: 656 [2018-12-03 04:05:30,077 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 04:05:30,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 656 states. [2018-12-03 04:05:30,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 656 to 643. [2018-12-03 04:05:30,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 643 states. [2018-12-03 04:05:30,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 786 transitions. [2018-12-03 04:05:30,126 INFO L78 Accepts]: Start accepts. Automaton has 643 states and 786 transitions. Word has length 70 [2018-12-03 04:05:30,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:30,126 INFO L480 AbstractCegarLoop]: Abstraction has 643 states and 786 transitions. [2018-12-03 04:05:30,126 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 04:05:30,126 INFO L276 IsEmpty]: Start isEmpty. Operand 643 states and 786 transitions. [2018-12-03 04:05:30,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-12-03 04:05:30,129 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:30,130 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:30,130 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:30,130 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:30,130 INFO L82 PathProgramCache]: Analyzing trace with hash -1663745524, now seen corresponding path program 1 times [2018-12-03 04:05:30,131 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:30,131 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:30,154 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:30,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:30,281 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:30,297 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:30,297 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:30,299 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:30,299 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 04:05:30,299 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 04:05:30,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 04:05:30,300 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 04:05:30,300 INFO L87 Difference]: Start difference. First operand 643 states and 786 transitions. Second operand 5 states. [2018-12-03 04:05:30,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:30,387 INFO L93 Difference]: Finished difference Result 1285 states and 1586 transitions. [2018-12-03 04:05:30,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 04:05:30,387 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2018-12-03 04:05:30,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:30,391 INFO L225 Difference]: With dead ends: 1285 [2018-12-03 04:05:30,391 INFO L226 Difference]: Without dead ends: 659 [2018-12-03 04:05:30,393 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 04:05:30,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2018-12-03 04:05:30,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 647. [2018-12-03 04:05:30,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 647 states. [2018-12-03 04:05:30,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 647 states to 647 states and 786 transitions. [2018-12-03 04:05:30,430 INFO L78 Accepts]: Start accepts. Automaton has 647 states and 786 transitions. Word has length 71 [2018-12-03 04:05:30,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:30,430 INFO L480 AbstractCegarLoop]: Abstraction has 647 states and 786 transitions. [2018-12-03 04:05:30,430 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 04:05:30,430 INFO L276 IsEmpty]: Start isEmpty. Operand 647 states and 786 transitions. [2018-12-03 04:05:30,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-03 04:05:30,432 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:30,432 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:30,433 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:30,433 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:30,433 INFO L82 PathProgramCache]: Analyzing trace with hash -1544904286, now seen corresponding path program 1 times [2018-12-03 04:05:30,433 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:30,433 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:30,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:30,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:30,555 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:30,563 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:30,563 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:30,565 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:30,565 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 04:05:30,566 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 04:05:30,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 04:05:30,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:30,566 INFO L87 Difference]: Start difference. First operand 647 states and 786 transitions. Second operand 3 states. [2018-12-03 04:05:30,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:30,657 INFO L93 Difference]: Finished difference Result 1528 states and 1859 transitions. [2018-12-03 04:05:30,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 04:05:30,658 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-12-03 04:05:30,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:30,661 INFO L225 Difference]: With dead ends: 1528 [2018-12-03 04:05:30,662 INFO L226 Difference]: Without dead ends: 898 [2018-12-03 04:05:30,664 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:30,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 898 states. [2018-12-03 04:05:30,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 898 to 895. [2018-12-03 04:05:30,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 895 states. [2018-12-03 04:05:30,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 1088 transitions. [2018-12-03 04:05:30,708 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 1088 transitions. Word has length 68 [2018-12-03 04:05:30,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:30,708 INFO L480 AbstractCegarLoop]: Abstraction has 895 states and 1088 transitions. [2018-12-03 04:05:30,709 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 04:05:30,709 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 1088 transitions. [2018-12-03 04:05:30,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-03 04:05:30,710 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:30,710 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:30,710 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:30,711 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:30,711 INFO L82 PathProgramCache]: Analyzing trace with hash -1782427673, now seen corresponding path program 1 times [2018-12-03 04:05:30,711 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:30,711 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:30,730 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:30,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:30,865 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:30,895 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:30,896 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:30,898 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:30,898 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 04:05:30,899 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 04:05:30,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 04:05:30,899 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 04:05:30,899 INFO L87 Difference]: Start difference. First operand 895 states and 1088 transitions. Second operand 5 states. [2018-12-03 04:05:30,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:30,992 INFO L93 Difference]: Finished difference Result 1796 states and 2200 transitions. [2018-12-03 04:05:30,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 04:05:30,992 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2018-12-03 04:05:30,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:30,995 INFO L225 Difference]: With dead ends: 1796 [2018-12-03 04:05:30,996 INFO L226 Difference]: Without dead ends: 927 [2018-12-03 04:05:30,998 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 04:05:30,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states. [2018-12-03 04:05:31,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 903. [2018-12-03 04:05:31,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 903 states. [2018-12-03 04:05:31,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 903 states to 903 states and 1090 transitions. [2018-12-03 04:05:31,032 INFO L78 Accepts]: Start accepts. Automaton has 903 states and 1090 transitions. Word has length 72 [2018-12-03 04:05:31,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:31,033 INFO L480 AbstractCegarLoop]: Abstraction has 903 states and 1090 transitions. [2018-12-03 04:05:31,033 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 04:05:31,033 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 1090 transitions. [2018-12-03 04:05:31,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-03 04:05:31,034 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:31,034 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:31,035 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:31,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:31,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1402464713, now seen corresponding path program 1 times [2018-12-03 04:05:31,035 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:31,035 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:31,053 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:31,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:31,175 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:31,202 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:31,202 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:31,204 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:31,204 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 04:05:31,204 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 04:05:31,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 04:05:31,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 04:05:31,205 INFO L87 Difference]: Start difference. First operand 903 states and 1090 transitions. Second operand 5 states. [2018-12-03 04:05:31,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:31,307 INFO L93 Difference]: Finished difference Result 1707 states and 2078 transitions. [2018-12-03 04:05:31,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 04:05:31,307 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2018-12-03 04:05:31,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:31,311 INFO L225 Difference]: With dead ends: 1707 [2018-12-03 04:05:31,311 INFO L226 Difference]: Without dead ends: 830 [2018-12-03 04:05:31,313 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 04:05:31,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states. [2018-12-03 04:05:31,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 812. [2018-12-03 04:05:31,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-12-03 04:05:31,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 974 transitions. [2018-12-03 04:05:31,343 INFO L78 Accepts]: Start accepts. Automaton has 812 states and 974 transitions. Word has length 73 [2018-12-03 04:05:31,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:31,344 INFO L480 AbstractCegarLoop]: Abstraction has 812 states and 974 transitions. [2018-12-03 04:05:31,344 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 04:05:31,344 INFO L276 IsEmpty]: Start isEmpty. Operand 812 states and 974 transitions. [2018-12-03 04:05:31,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-12-03 04:05:31,345 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:31,345 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:31,345 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:31,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:31,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1316738903, now seen corresponding path program 1 times [2018-12-03 04:05:31,346 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:31,346 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:31,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:31,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:31,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:31,542 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-03 04:05:31,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:31,722 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-03 04:05:31,724 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 04:05:31,724 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 13 [2018-12-03 04:05:31,725 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-12-03 04:05:31,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-12-03 04:05:31,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-12-03 04:05:31,725 INFO L87 Difference]: Start difference. First operand 812 states and 974 transitions. Second operand 13 states. [2018-12-03 04:05:34,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:34,210 INFO L93 Difference]: Finished difference Result 2154 states and 2671 transitions. [2018-12-03 04:05:34,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-03 04:05:34,211 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 85 [2018-12-03 04:05:34,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:34,215 INFO L225 Difference]: With dead ends: 2154 [2018-12-03 04:05:34,215 INFO L226 Difference]: Without dead ends: 1368 [2018-12-03 04:05:34,216 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 158 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=152, Invalid=498, Unknown=0, NotChecked=0, Total=650 [2018-12-03 04:05:34,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1368 states. [2018-12-03 04:05:34,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1368 to 1155. [2018-12-03 04:05:34,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1155 states. [2018-12-03 04:05:34,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1155 states to 1155 states and 1392 transitions. [2018-12-03 04:05:34,255 INFO L78 Accepts]: Start accepts. Automaton has 1155 states and 1392 transitions. Word has length 85 [2018-12-03 04:05:34,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:34,255 INFO L480 AbstractCegarLoop]: Abstraction has 1155 states and 1392 transitions. [2018-12-03 04:05:34,255 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-12-03 04:05:34,255 INFO L276 IsEmpty]: Start isEmpty. Operand 1155 states and 1392 transitions. [2018-12-03 04:05:34,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-03 04:05:34,256 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:34,256 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:34,256 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:34,257 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:34,257 INFO L82 PathProgramCache]: Analyzing trace with hash 1516400962, now seen corresponding path program 1 times [2018-12-03 04:05:34,257 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:34,257 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:34,282 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:34,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:34,409 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:34,482 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:34,482 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:34,630 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:34,632 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:34,632 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 04:05:34,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:34,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:34,714 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:34,733 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:34,733 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:34,827 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:34,843 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-03 04:05:34,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-12-03 04:05:34,843 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-03 04:05:34,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-03 04:05:34,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-03 04:05:34,844 INFO L87 Difference]: Start difference. First operand 1155 states and 1392 transitions. Second operand 14 states. [2018-12-03 04:05:36,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:36,223 INFO L93 Difference]: Finished difference Result 2670 states and 3229 transitions. [2018-12-03 04:05:36,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-12-03 04:05:36,224 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 86 [2018-12-03 04:05:36,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:36,228 INFO L225 Difference]: With dead ends: 2670 [2018-12-03 04:05:36,228 INFO L226 Difference]: Without dead ends: 1541 [2018-12-03 04:05:36,230 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 329 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-12-03 04:05:36,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1541 states. [2018-12-03 04:05:36,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1541 to 1472. [2018-12-03 04:05:36,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1472 states. [2018-12-03 04:05:36,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1472 states to 1472 states and 1785 transitions. [2018-12-03 04:05:36,273 INFO L78 Accepts]: Start accepts. Automaton has 1472 states and 1785 transitions. Word has length 86 [2018-12-03 04:05:36,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:36,273 INFO L480 AbstractCegarLoop]: Abstraction has 1472 states and 1785 transitions. [2018-12-03 04:05:36,273 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-03 04:05:36,273 INFO L276 IsEmpty]: Start isEmpty. Operand 1472 states and 1785 transitions. [2018-12-03 04:05:36,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-12-03 04:05:36,275 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:36,275 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:36,275 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:36,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:36,275 INFO L82 PathProgramCache]: Analyzing trace with hash -2059129438, now seen corresponding path program 1 times [2018-12-03 04:05:36,276 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:36,276 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:36,301 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:36,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:36,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:36,479 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:36,479 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:36,613 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:36,616 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:36,616 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 04:05:36,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:36,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:36,691 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:36,696 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:36,696 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:36,792 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:36,807 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-03 04:05:36,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-12-03 04:05:36,808 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-03 04:05:36,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-03 04:05:36,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-03 04:05:36,808 INFO L87 Difference]: Start difference. First operand 1472 states and 1785 transitions. Second operand 14 states. [2018-12-03 04:05:38,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:38,112 INFO L93 Difference]: Finished difference Result 3304 states and 4019 transitions. [2018-12-03 04:05:38,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-12-03 04:05:38,114 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 87 [2018-12-03 04:05:38,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:38,118 INFO L225 Difference]: With dead ends: 3304 [2018-12-03 04:05:38,118 INFO L226 Difference]: Without dead ends: 1858 [2018-12-03 04:05:38,121 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 333 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-12-03 04:05:38,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1858 states. [2018-12-03 04:05:38,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1858 to 1472. [2018-12-03 04:05:38,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1472 states. [2018-12-03 04:05:38,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1472 states to 1472 states and 1785 transitions. [2018-12-03 04:05:38,169 INFO L78 Accepts]: Start accepts. Automaton has 1472 states and 1785 transitions. Word has length 87 [2018-12-03 04:05:38,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:38,169 INFO L480 AbstractCegarLoop]: Abstraction has 1472 states and 1785 transitions. [2018-12-03 04:05:38,169 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-03 04:05:38,169 INFO L276 IsEmpty]: Start isEmpty. Operand 1472 states and 1785 transitions. [2018-12-03 04:05:38,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-03 04:05:38,170 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:38,170 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:38,171 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:38,171 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:38,171 INFO L82 PathProgramCache]: Analyzing trace with hash 1854992155, now seen corresponding path program 1 times [2018-12-03 04:05:38,171 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:38,171 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:38,197 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:38,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:38,306 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:38,376 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:38,377 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:38,506 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:38,508 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:38,508 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 04:05:38,515 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:38,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:38,571 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:38,576 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:38,576 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:38,665 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:38,681 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-03 04:05:38,681 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-12-03 04:05:38,682 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-03 04:05:38,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-03 04:05:38,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-03 04:05:38,682 INFO L87 Difference]: Start difference. First operand 1472 states and 1785 transitions. Second operand 14 states. [2018-12-03 04:05:40,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:40,066 INFO L93 Difference]: Finished difference Result 2860 states and 3465 transitions. [2018-12-03 04:05:40,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-03 04:05:40,066 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 88 [2018-12-03 04:05:40,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:40,069 INFO L225 Difference]: With dead ends: 2860 [2018-12-03 04:05:40,069 INFO L226 Difference]: Without dead ends: 1414 [2018-12-03 04:05:40,070 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 337 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2018-12-03 04:05:40,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states. [2018-12-03 04:05:40,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 398. [2018-12-03 04:05:40,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 398 states. [2018-12-03 04:05:40,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 398 states to 398 states and 465 transitions. [2018-12-03 04:05:40,096 INFO L78 Accepts]: Start accepts. Automaton has 398 states and 465 transitions. Word has length 88 [2018-12-03 04:05:40,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:40,096 INFO L480 AbstractCegarLoop]: Abstraction has 398 states and 465 transitions. [2018-12-03 04:05:40,096 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-03 04:05:40,096 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states and 465 transitions. [2018-12-03 04:05:40,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-12-03 04:05:40,097 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:40,097 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:40,097 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:40,097 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:40,097 INFO L82 PathProgramCache]: Analyzing trace with hash -1289094802, now seen corresponding path program 1 times [2018-12-03 04:05:40,098 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:40,098 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:40,115 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:40,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:40,219 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:40,226 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-03 04:05:40,227 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:40,228 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:40,228 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 04:05:40,228 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 04:05:40,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 04:05:40,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:40,229 INFO L87 Difference]: Start difference. First operand 398 states and 465 transitions. Second operand 3 states. [2018-12-03 04:05:40,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:40,311 INFO L93 Difference]: Finished difference Result 852 states and 1012 transitions. [2018-12-03 04:05:40,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 04:05:40,311 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 97 [2018-12-03 04:05:40,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:40,312 INFO L225 Difference]: With dead ends: 852 [2018-12-03 04:05:40,312 INFO L226 Difference]: Without dead ends: 480 [2018-12-03 04:05:40,313 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:40,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states. [2018-12-03 04:05:40,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2018-12-03 04:05:40,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2018-12-03 04:05:40,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 566 transitions. [2018-12-03 04:05:40,350 INFO L78 Accepts]: Start accepts. Automaton has 480 states and 566 transitions. Word has length 97 [2018-12-03 04:05:40,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:40,350 INFO L480 AbstractCegarLoop]: Abstraction has 480 states and 566 transitions. [2018-12-03 04:05:40,350 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 04:05:40,350 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 566 transitions. [2018-12-03 04:05:40,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-12-03 04:05:40,351 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:40,351 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:40,351 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:40,352 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:40,352 INFO L82 PathProgramCache]: Analyzing trace with hash -94289413, now seen corresponding path program 1 times [2018-12-03 04:05:40,352 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:40,352 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:40,377 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:40,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:40,525 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:40,536 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-03 04:05:40,537 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:40,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:40,539 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-03 04:05:40,539 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 04:05:40,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 04:05:40,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:40,539 INFO L87 Difference]: Start difference. First operand 480 states and 566 transitions. Second operand 3 states. [2018-12-03 04:05:40,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:40,676 INFO L93 Difference]: Finished difference Result 1169 states and 1373 transitions. [2018-12-03 04:05:40,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 04:05:40,677 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-12-03 04:05:40,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:40,679 INFO L225 Difference]: With dead ends: 1169 [2018-12-03 04:05:40,679 INFO L226 Difference]: Without dead ends: 715 [2018-12-03 04:05:40,680 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 04:05:40,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2018-12-03 04:05:40,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 712. [2018-12-03 04:05:40,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 712 states. [2018-12-03 04:05:40,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 712 states to 712 states and 824 transitions. [2018-12-03 04:05:40,736 INFO L78 Accepts]: Start accepts. Automaton has 712 states and 824 transitions. Word has length 114 [2018-12-03 04:05:40,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:40,736 INFO L480 AbstractCegarLoop]: Abstraction has 712 states and 824 transitions. [2018-12-03 04:05:40,737 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 04:05:40,737 INFO L276 IsEmpty]: Start isEmpty. Operand 712 states and 824 transitions. [2018-12-03 04:05:40,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-03 04:05:40,737 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:40,737 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:40,738 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:40,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:40,738 INFO L82 PathProgramCache]: Analyzing trace with hash -1420932234, now seen corresponding path program 1 times [2018-12-03 04:05:40,738 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:40,738 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:40,755 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:41,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:41,069 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:41,080 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-03 04:05:41,080 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-03 04:05:41,084 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 04:05:41,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-03 04:05:41,084 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-03 04:05:41,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-03 04:05:41,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 04:05:41,085 INFO L87 Difference]: Start difference. First operand 712 states and 824 transitions. Second operand 4 states. [2018-12-03 04:05:41,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:41,149 INFO L93 Difference]: Finished difference Result 1402 states and 1625 transitions. [2018-12-03 04:05:41,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-03 04:05:41,150 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 115 [2018-12-03 04:05:41,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:41,151 INFO L225 Difference]: With dead ends: 1402 [2018-12-03 04:05:41,151 INFO L226 Difference]: Without dead ends: 713 [2018-12-03 04:05:41,152 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-03 04:05:41,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states. [2018-12-03 04:05:41,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 713. [2018-12-03 04:05:41,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 713 states. [2018-12-03 04:05:41,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 713 states to 713 states and 825 transitions. [2018-12-03 04:05:41,189 INFO L78 Accepts]: Start accepts. Automaton has 713 states and 825 transitions. Word has length 115 [2018-12-03 04:05:41,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:41,189 INFO L480 AbstractCegarLoop]: Abstraction has 713 states and 825 transitions. [2018-12-03 04:05:41,189 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-03 04:05:41,189 INFO L276 IsEmpty]: Start isEmpty. Operand 713 states and 825 transitions. [2018-12-03 04:05:41,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-03 04:05:41,190 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:41,190 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:41,191 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:41,191 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:41,191 INFO L82 PathProgramCache]: Analyzing trace with hash 732072980, now seen corresponding path program 1 times [2018-12-03 04:05:41,191 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:41,191 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:41,217 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:41,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:41,552 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:41,571 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-03 04:05:41,572 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:41,651 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:41,654 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 04:05:41,654 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 04:05:41,662 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 04:05:41,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 04:05:41,743 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 04:05:41,747 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-03 04:05:41,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-03 04:05:41,791 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-03 04:05:41,807 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-03 04:05:41,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5] total 8 [2018-12-03 04:05:41,808 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-03 04:05:41,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-03 04:05:41,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-03 04:05:41,808 INFO L87 Difference]: Start difference. First operand 713 states and 825 transitions. Second operand 8 states. [2018-12-03 04:05:41,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 04:05:41,938 INFO L93 Difference]: Finished difference Result 1407 states and 1632 transitions. [2018-12-03 04:05:41,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-03 04:05:41,939 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 116 [2018-12-03 04:05:41,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 04:05:41,940 INFO L225 Difference]: With dead ends: 1407 [2018-12-03 04:05:41,940 INFO L226 Difference]: Without dead ends: 716 [2018-12-03 04:05:41,941 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 464 GetRequests, 454 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-12-03 04:05:41,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2018-12-03 04:05:41,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 716. [2018-12-03 04:05:41,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 716 states. [2018-12-03 04:05:41,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 828 transitions. [2018-12-03 04:05:41,974 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 828 transitions. Word has length 116 [2018-12-03 04:05:41,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 04:05:41,974 INFO L480 AbstractCegarLoop]: Abstraction has 716 states and 828 transitions. [2018-12-03 04:05:41,974 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-03 04:05:41,974 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 828 transitions. [2018-12-03 04:05:41,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-12-03 04:05:41,975 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 04:05:41,975 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 04:05:41,975 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 04:05:41,976 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 04:05:41,976 INFO L82 PathProgramCache]: Analyzing trace with hash 1051230966, now seen corresponding path program 2 times [2018-12-03 04:05:41,976 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-03 04:05:41,976 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/cvc4 Starting monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-03 04:05:41,997 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-12-03 04:05:42,732 ERROR L235 seRefinementStrategy]: Caught known exception: Array theory solver does not yet support write-chains connecting two different constant arrays [2018-12-03 04:05:42,732 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-12-03 04:05:42,732 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_25bfceff-1ab8-4c3c-9620-8b90c3a350fd/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-12-03 04:05:42,742 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-03 04:05:44,987 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-03 04:05:44,987 INFO L250 tOrderPrioritization]: Conjunction of SSA is sat [2018-12-03 04:05:47,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-03 04:05:47,940 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-03 04:05:47,996 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-12-03 04:05:48,033 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-12-03 04:05:48,034 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,034 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-12-03 04:05:48,034 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,035 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,035 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,035 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-12-03 04:05:48,035 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-03 04:05:48,035 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-12-03 04:05:48,036 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,036 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-03 04:05:48,036 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-12-03 04:05:48,036 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,036 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,036 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-12-03 04:05:48,037 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-03 04:05:48,037 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,037 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,037 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-03 04:05:48,037 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-03 04:05:48,039 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,039 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,040 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,040 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,041 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,041 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,042 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,043 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,043 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,044 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,045 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,045 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,046 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,046 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,047 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,047 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,049 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,049 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,049 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,050 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,050 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,051 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,051 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,052 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,052 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,052 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,052 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,053 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,053 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,054 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,054 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,055 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,055 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,056 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,056 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,057 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,057 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,058 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,058 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,058 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,058 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,059 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,059 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,059 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,060 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,060 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,061 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,061 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,061 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,062 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,062 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,063 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,063 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,064 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,064 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,064 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,065 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,065 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,065 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,065 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,066 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,066 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,066 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,067 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,067 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,067 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,068 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,068 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,068 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,069 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,069 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,069 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,069 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,069 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,070 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,070 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,070 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,070 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,071 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,071 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,071 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,072 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,072 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,072 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,073 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,073 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,073 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,074 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,074 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,074 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,074 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,075 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,075 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,075 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,075 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,075 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,076 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,076 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,076 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,076 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,076 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,077 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,077 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,077 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,077 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,078 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,078 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,078 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,079 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,079 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-03 04:05:48,079 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,079 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,080 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,080 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,080 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,081 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,081 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,082 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,082 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,083 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,083 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,083 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,084 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,084 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,084 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,085 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,085 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,086 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,086 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,086 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,087 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,087 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,087 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,088 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,088 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,089 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,089 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,089 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,089 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,090 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,090 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,091 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,091 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,092 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,092 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,092 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,092 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,093 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,093 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,094 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,094 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,095 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,095 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,096 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,096 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,096 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,097 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,097 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,097 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-03 04:05:48,111 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.12 04:05:48 BoogieIcfgContainer [2018-12-03 04:05:48,111 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-03 04:05:48,112 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-03 04:05:48,112 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-03 04:05:48,112 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-03 04:05:48,112 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 04:05:29" (3/4) ... [2018-12-03 04:05:48,115 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-12-03 04:05:48,115 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-03 04:05:48,115 INFO L168 Benchmark]: Toolchain (without parser) took 22381.23 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 490.7 MB). Free memory was 938.0 MB in the beginning and 1.2 GB in the end (delta: -285.3 MB). Peak memory consumption was 205.4 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:48,116 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-03 04:05:48,116 INFO L168 Benchmark]: CACSL2BoogieTranslator took 660.50 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.6 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -162.5 MB). Peak memory consumption was 67.1 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:48,117 INFO L168 Benchmark]: Boogie Procedure Inliner took 29.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:48,117 INFO L168 Benchmark]: Boogie Preprocessor took 45.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:48,117 INFO L168 Benchmark]: RCFGBuilder took 2897.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 956.0 MB in the end (delta: 130.6 MB). Peak memory consumption was 130.6 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:48,118 INFO L168 Benchmark]: TraceAbstraction took 18742.19 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 338.2 MB). Free memory was 956.0 MB in the beginning and 1.2 GB in the end (delta: -267.3 MB). Peak memory consumption was 70.8 MB. Max. memory is 11.5 GB. [2018-12-03 04:05:48,118 INFO L168 Benchmark]: Witness Printer took 3.12 ms. Allocated memory is still 1.5 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-03 04:05:48,119 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 660.50 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.6 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -162.5 MB). Peak memory consumption was 67.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 29.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 45.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 2897.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 956.0 MB in the end (delta: 130.6 MB). Peak memory consumption was 130.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 18742.19 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 338.2 MB). Free memory was 956.0 MB in the beginning and 1.2 GB in the end (delta: -267.3 MB). Peak memory consumption was 70.8 MB. Max. memory is 11.5 GB. * Witness Printer took 3.12 ms. Allocated memory is still 1.5 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1664]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2219. Possible FailurePath: [L1687] int ldv_irq_1_2 = 0; [L1688] int LDV_IN_INTERRUPT = 1; [L1689] int ldv_irq_1_3 = 0; [L1690] struct platform_device *tegra_rtc_driver_group0 ; [L1691] void *ldv_irq_data_1_1 ; [L1692] int ldv_irq_1_1 = 0; [L1693] int ldv_irq_1_0 = 0; [L1694] int ldv_irq_line_1_3 ; [L1695] void *ldv_irq_data_1_0 ; [L1696] int ldv_state_variable_0 ; [L1697] struct device *tegra_rtc_ops_group1 ; [L1698] int ldv_state_variable_3 ; [L1699] int ldv_irq_line_1_0 ; [L1700] int ldv_state_variable_2 ; [L1701] void *ldv_irq_data_1_3 ; [L1702] int ref_cnt ; [L1703] int ldv_irq_line_1_1 ; [L1704] struct rtc_time *tegra_rtc_ops_group0 ; [L1705] void *ldv_irq_data_1_2 ; [L1706] int ldv_state_variable_1 ; [L1707] int ldv_irq_line_1_2 ; [L1708] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2050-L2052] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2218-L2219] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2235] int ldv_retval_2 ; [L2236] int ldv_retval_0 ; [L2238] int ldv_retval_1 ; [L2761] int ldv_init = 0; VAL [\old(LDV_IN_INTERRUPT)=0, \old(ldv_init)=0, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_line_1_0)=0, \old(ldv_irq_line_1_1)=0, \old(ldv_irq_line_1_2)=0, \old(ldv_irq_line_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group2)=null, \old(tegra_rtc_ops_group2)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2390] struct seq_file *ldvarg1 ; [L2391] void *tmp ; [L2392] unsigned int ldvarg0 ; [L2393] unsigned int tmp___0 ; [L2394] pm_message_t ldvarg2 ; [L2395] int tmp___1 ; [L2396] int tmp___2 ; [L2397] int tmp___3 ; [L2398] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=268435456] [L2400] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] tmp = ldv_zalloc(136U) [L2401] ldvarg1 = (struct seq_file *)tmp [L2402] tmp___0 = __VERIFIER_nondet_uint() [L2403] ldvarg0 = tmp___0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2404] FCALL ldv_initialize() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2405] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, memset((void *)(& ldvarg2), 0, 4U)={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2406] ldv_state_variable_1 = 1 [L2407] ref_cnt = 0 [L2408] ldv_state_variable_0 = 1 [L2409] ldv_state_variable_3 = 0 [L2410] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1] [L2421] COND TRUE ldv_state_variable_0 != 0 [L2422] tmp___2 = __VERIFIER_nondet_int() [L2424] case 0: [L2432] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2433] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2434] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2222] int tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] CALL, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={8192:0}, arg1={-1:11}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2842] return __VERIFIER_nondet_int(); [L2224] RET, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe)=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2225] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2434] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2434] ldv_retval_0 = tegra_rtc_init() [L2435] COND TRUE ldv_retval_0 == 0 [L2436] ldv_state_variable_0 = 3 [L2437] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2438] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2355] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=8388608] [L2357] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] tmp = ldv_zalloc(624U) [L2358] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2438] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2441] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: [L2566] case 1: [L2576] case 2: [L2596] case 3: [L2606] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2607] COND TRUE ldv_state_variable_2 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2608] CALL ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2830] return __VERIFIER_nondet_int(); [L2608] RET ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_probe_2()=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2609] ldv_state_variable_2 = 2 [L2610] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2555] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2560] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2561] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2214] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1952] struct tegra_rtc_info *info ; [L1953] void *tmp ; [L1954] unsigned int status ; [L1955] unsigned long sl_irq_flags ; [L1956] u32 __v ; [L1957] u32 __v___0 ; VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, arg0={0:12}, external_alloc()={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1959] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={0:0}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] tmp = dev_get_drvdata((struct device const *)dev) [L1960] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1961] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1835] struct tegra_rtc_info *info ; [L1836] void *tmp ; [L1837] int retries ; [L1838] int tmp___0 ; [L1839] u32 tmp___1 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, arg0={0:12}, external_alloc()={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1841] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] tmp = dev_get_drvdata((struct device const *)dev) [L1842] info = (struct tegra_rtc_info *)tmp [L1843] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1854] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1825] u32 __v ; [L1826] u32 __v___0 ; [L1828] EXPR info->rtc_base [L1828] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1828] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1829] __v = __v___0 [L1830] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, __v=0, __v___0=0, info={0:0}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1854] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1854] tmp___1 = tegra_rtc_check_busy(info) [L1855] COND FALSE !(tmp___1 != 0U) [L1859] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___1=0] [L1961] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={0:0}] [L1962] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2775] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2777] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1664] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 65 procedures, 488 locations, 1 error locations. UNSAFE Result, 18.6s OverallTime, 15 OverallIterations, 4 TraceHistogramMax, 7.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5824 SDtfs, 5662 SDslu, 13308 SDs, 0 SdLazy, 5083 SolverSat, 540 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2447 GetRequests, 2311 SyntacticMatches, 9 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1472occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 14 MinimizatonAttempts, 1757 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.6s SsaConstructionTime, 3.8s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 1685 NumberOfCodeBlocks, 1685 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 2378 ConstructedInterpolants, 0 QuantifiedInterpolants, 389916 SizeOfPredicates, 60 NumberOfNonLiveVariables, 9318 ConjunctsInSsa, 138 ConjunctsInUnsatCore, 27 InterpolantComputations, 10 PerfectInterpolantSequences, 355/435 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...