./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c244c639ec9718adcbacffa967b748c52a23cd0 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 01:04:29,287 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 01:04:29,288 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 01:04:29,294 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 01:04:29,294 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 01:04:29,294 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 01:04:29,295 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 01:04:29,296 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 01:04:29,296 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 01:04:29,297 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 01:04:29,297 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 01:04:29,297 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 01:04:29,298 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 01:04:29,298 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 01:04:29,299 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 01:04:29,299 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 01:04:29,300 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 01:04:29,301 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 01:04:29,301 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 01:04:29,302 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 01:04:29,303 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 01:04:29,303 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 01:04:29,304 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 01:04:29,305 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 01:04:29,305 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 01:04:29,305 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 01:04:29,306 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 01:04:29,306 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 01:04:29,306 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 01:04:29,307 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 01:04:29,307 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 01:04:29,307 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 01:04:29,307 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 01:04:29,308 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 01:04:29,308 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 01:04:29,308 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 01:04:29,309 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-12-02 01:04:29,315 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 01:04:29,316 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 01:04:29,316 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 01:04:29,316 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 01:04:29,316 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-02 01:04:29,316 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-02 01:04:29,316 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-02 01:04:29,316 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-02 01:04:29,317 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 01:04:29,317 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-02 01:04:29,318 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 01:04:29,318 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 01:04:29,319 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 01:04:29,319 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 01:04:29,319 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-02 01:04:29,319 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-02 01:04:29,319 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 01:04:29,319 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 01:04:29,319 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-02 01:04:29,319 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c244c639ec9718adcbacffa967b748c52a23cd0 [2018-12-02 01:04:29,337 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 01:04:29,346 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 01:04:29,348 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 01:04:29,350 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 01:04:29,350 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 01:04:29,350 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-12-02 01:04:29,389 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/data/49d3f963c/42cfb9bc79184e00b9d03fcc48901ad7/FLAGde5fa334d [2018-12-02 01:04:29,849 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 01:04:29,849 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-12-02 01:04:29,854 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/data/49d3f963c/42cfb9bc79184e00b9d03fcc48901ad7/FLAGde5fa334d [2018-12-02 01:04:29,862 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/data/49d3f963c/42cfb9bc79184e00b9d03fcc48901ad7 [2018-12-02 01:04:29,864 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 01:04:29,865 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 01:04:29,866 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 01:04:29,866 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 01:04:29,868 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 01:04:29,869 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 01:04:29" (1/1) ... [2018-12-02 01:04:29,870 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4040b4f8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:29, skipping insertion in model container [2018-12-02 01:04:29,870 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 01:04:29" (1/1) ... [2018-12-02 01:04:29,875 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 01:04:29,895 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 01:04:30,024 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 01:04:30,029 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 01:04:30,051 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 01:04:30,061 INFO L195 MainTranslator]: Completed translation [2018-12-02 01:04:30,062 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30 WrapperNode [2018-12-02 01:04:30,062 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 01:04:30,062 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 01:04:30,062 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 01:04:30,062 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 01:04:30,067 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,071 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,104 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 01:04:30,104 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 01:04:30,104 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 01:04:30,104 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 01:04:30,110 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,111 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,113 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,113 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,120 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,128 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,130 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... [2018-12-02 01:04:30,132 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 01:04:30,133 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 01:04:30,133 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 01:04:30,133 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 01:04:30,134 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 01:04:30,164 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-12-02 01:04:30,164 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-12-02 01:04:30,164 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-12-02 01:04:30,164 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-12-02 01:04:30,164 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 01:04:30,164 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 01:04:30,164 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-02 01:04:30,165 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-02 01:04:30,165 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-02 01:04:30,165 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-02 01:04:30,165 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-12-02 01:04:30,165 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-12-02 01:04:30,165 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-02 01:04:30,165 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-02 01:04:30,165 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-12-02 01:04:30,165 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-12-02 01:04:30,165 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-02 01:04:30,165 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-02 01:04:30,165 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-02 01:04:30,165 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-02 01:04:30,165 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 01:04:30,166 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 01:04:30,166 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-02 01:04:30,167 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-02 01:04:30,167 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-02 01:04:30,167 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-02 01:04:30,167 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-02 01:04:30,167 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-02 01:04:30,167 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 01:04:30,167 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 01:04:30,167 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-02 01:04:30,167 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-02 01:04:30,402 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 01:04:30,402 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-12-02 01:04:30,402 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 01:04:30 BoogieIcfgContainer [2018-12-02 01:04:30,402 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 01:04:30,403 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 01:04:30,403 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 01:04:30,404 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 01:04:30,405 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 01:04:29" (1/3) ... [2018-12-02 01:04:30,405 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2986bf56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 01:04:30, skipping insertion in model container [2018-12-02 01:04:30,405 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 01:04:30" (2/3) ... [2018-12-02 01:04:30,405 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2986bf56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 01:04:30, skipping insertion in model container [2018-12-02 01:04:30,405 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 01:04:30" (3/3) ... [2018-12-02 01:04:30,406 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.02_false-unreach-call_false-termination.cil.c [2018-12-02 01:04:30,412 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 01:04:30,417 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-02 01:04:30,426 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-02 01:04:30,445 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 01:04:30,445 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-02 01:04:30,445 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 01:04:30,445 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 01:04:30,445 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 01:04:30,445 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 01:04:30,446 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 01:04:30,446 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 01:04:30,458 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states. [2018-12-02 01:04:30,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:30,463 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:30,464 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:30,465 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:30,468 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:30,468 INFO L82 PathProgramCache]: Analyzing trace with hash -1029162199, now seen corresponding path program 1 times [2018-12-02 01:04:30,470 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:30,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:30,497 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:30,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:30,497 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:30,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:30,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:30,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:30,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 01:04:30,606 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:30,611 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 01:04:30,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 01:04:30,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 01:04:30,624 INFO L87 Difference]: Start difference. First operand 169 states. Second operand 4 states. [2018-12-02 01:04:30,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:30,734 INFO L93 Difference]: Finished difference Result 320 states and 454 transitions. [2018-12-02 01:04:30,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 01:04:30,735 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 90 [2018-12-02 01:04:30,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:30,743 INFO L225 Difference]: With dead ends: 320 [2018-12-02 01:04:30,743 INFO L226 Difference]: Without dead ends: 160 [2018-12-02 01:04:30,745 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 01:04:30,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-12-02 01:04:30,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 160. [2018-12-02 01:04:30,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 01:04:30,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 212 transitions. [2018-12-02 01:04:30,779 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 212 transitions. Word has length 90 [2018-12-02 01:04:30,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:30,780 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 212 transitions. [2018-12-02 01:04:30,780 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 01:04:30,780 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 212 transitions. [2018-12-02 01:04:30,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:30,782 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:30,782 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:30,782 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:30,782 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:30,782 INFO L82 PathProgramCache]: Analyzing trace with hash 881880359, now seen corresponding path program 1 times [2018-12-02 01:04:30,782 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:30,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:30,783 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:30,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:30,783 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:30,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:30,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:30,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:30,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:30,846 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:30,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:30,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:30,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:30,847 INFO L87 Difference]: Start difference. First operand 160 states and 212 transitions. Second operand 5 states. [2018-12-02 01:04:31,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:31,074 INFO L93 Difference]: Finished difference Result 328 states and 450 transitions. [2018-12-02 01:04:31,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 01:04:31,075 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:31,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:31,076 INFO L225 Difference]: With dead ends: 328 [2018-12-02 01:04:31,076 INFO L226 Difference]: Without dead ends: 188 [2018-12-02 01:04:31,077 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:31,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-12-02 01:04:31,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 160. [2018-12-02 01:04:31,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 01:04:31,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 211 transitions. [2018-12-02 01:04:31,090 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 211 transitions. Word has length 90 [2018-12-02 01:04:31,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:31,090 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 211 transitions. [2018-12-02 01:04:31,090 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:31,090 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 211 transitions. [2018-12-02 01:04:31,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:31,091 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:31,091 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:31,092 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:31,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:31,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1835820517, now seen corresponding path program 1 times [2018-12-02 01:04:31,092 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:31,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:31,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,093 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:31,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:31,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:31,146 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:31,146 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:31,146 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:31,146 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:31,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:31,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:31,147 INFO L87 Difference]: Start difference. First operand 160 states and 211 transitions. Second operand 5 states. [2018-12-02 01:04:31,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:31,353 INFO L93 Difference]: Finished difference Result 328 states and 449 transitions. [2018-12-02 01:04:31,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 01:04:31,354 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:31,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:31,355 INFO L225 Difference]: With dead ends: 328 [2018-12-02 01:04:31,356 INFO L226 Difference]: Without dead ends: 188 [2018-12-02 01:04:31,357 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:31,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-12-02 01:04:31,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 160. [2018-12-02 01:04:31,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 01:04:31,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 210 transitions. [2018-12-02 01:04:31,372 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 210 transitions. Word has length 90 [2018-12-02 01:04:31,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:31,373 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 210 transitions. [2018-12-02 01:04:31,373 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:31,373 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 210 transitions. [2018-12-02 01:04:31,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:31,374 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:31,374 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:31,374 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:31,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:31,375 INFO L82 PathProgramCache]: Analyzing trace with hash 619666791, now seen corresponding path program 1 times [2018-12-02 01:04:31,375 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:31,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,376 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:31,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,376 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:31,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:31,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:31,449 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:31,449 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:31,449 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:31,450 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:31,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:31,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:31,450 INFO L87 Difference]: Start difference. First operand 160 states and 210 transitions. Second operand 5 states. [2018-12-02 01:04:31,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:31,690 INFO L93 Difference]: Finished difference Result 326 states and 443 transitions. [2018-12-02 01:04:31,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 01:04:31,691 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:31,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:31,692 INFO L225 Difference]: With dead ends: 326 [2018-12-02 01:04:31,692 INFO L226 Difference]: Without dead ends: 186 [2018-12-02 01:04:31,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:31,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-12-02 01:04:31,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 160. [2018-12-02 01:04:31,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 01:04:31,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 209 transitions. [2018-12-02 01:04:31,708 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 209 transitions. Word has length 90 [2018-12-02 01:04:31,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:31,709 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 209 transitions. [2018-12-02 01:04:31,709 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:31,709 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 209 transitions. [2018-12-02 01:04:31,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:31,710 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:31,710 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:31,710 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:31,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:31,711 INFO L82 PathProgramCache]: Analyzing trace with hash -112300635, now seen corresponding path program 1 times [2018-12-02 01:04:31,711 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:31,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:31,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,712 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:31,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:31,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:31,778 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:31,778 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:31,778 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:31,778 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:31,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:31,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:31,778 INFO L87 Difference]: Start difference. First operand 160 states and 209 transitions. Second operand 5 states. [2018-12-02 01:04:31,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:31,956 INFO L93 Difference]: Finished difference Result 343 states and 469 transitions. [2018-12-02 01:04:31,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 01:04:31,956 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:31,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:31,958 INFO L225 Difference]: With dead ends: 343 [2018-12-02 01:04:31,958 INFO L226 Difference]: Without dead ends: 203 [2018-12-02 01:04:31,958 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:31,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states. [2018-12-02 01:04:31,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 160. [2018-12-02 01:04:31,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 01:04:31,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 208 transitions. [2018-12-02 01:04:31,973 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 208 transitions. Word has length 90 [2018-12-02 01:04:31,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:31,973 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 208 transitions. [2018-12-02 01:04:31,973 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:31,973 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 208 transitions. [2018-12-02 01:04:31,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:31,975 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:31,975 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:31,975 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:31,975 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:31,975 INFO L82 PathProgramCache]: Analyzing trace with hash -1798480473, now seen corresponding path program 1 times [2018-12-02 01:04:31,975 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:31,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,976 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:31,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:31,977 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:31,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:32,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:32,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:32,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:32,034 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:32,035 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:32,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:32,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:32,035 INFO L87 Difference]: Start difference. First operand 160 states and 208 transitions. Second operand 5 states. [2018-12-02 01:04:32,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:32,244 INFO L93 Difference]: Finished difference Result 341 states and 463 transitions. [2018-12-02 01:04:32,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 01:04:32,244 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:32,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:32,246 INFO L225 Difference]: With dead ends: 341 [2018-12-02 01:04:32,246 INFO L226 Difference]: Without dead ends: 201 [2018-12-02 01:04:32,246 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:32,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-12-02 01:04:32,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 160. [2018-12-02 01:04:32,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 01:04:32,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 207 transitions. [2018-12-02 01:04:32,258 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 207 transitions. Word has length 90 [2018-12-02 01:04:32,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:32,258 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 207 transitions. [2018-12-02 01:04:32,258 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:32,258 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 207 transitions. [2018-12-02 01:04:32,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:32,259 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:32,259 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:32,260 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:32,260 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:32,260 INFO L82 PathProgramCache]: Analyzing trace with hash -1852873371, now seen corresponding path program 1 times [2018-12-02 01:04:32,260 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:32,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:32,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,261 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:32,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:32,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:32,291 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:32,292 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 01:04:32,292 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:32,292 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 01:04:32,292 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 01:04:32,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:32,293 INFO L87 Difference]: Start difference. First operand 160 states and 207 transitions. Second operand 6 states. [2018-12-02 01:04:32,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:32,323 INFO L93 Difference]: Finished difference Result 312 states and 418 transitions. [2018-12-02 01:04:32,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 01:04:32,324 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2018-12-02 01:04:32,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:32,325 INFO L225 Difference]: With dead ends: 312 [2018-12-02 01:04:32,325 INFO L226 Difference]: Without dead ends: 173 [2018-12-02 01:04:32,326 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 01:04:32,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-12-02 01:04:32,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 165. [2018-12-02 01:04:32,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-12-02 01:04:32,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 212 transitions. [2018-12-02 01:04:32,335 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 212 transitions. Word has length 90 [2018-12-02 01:04:32,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:32,335 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 212 transitions. [2018-12-02 01:04:32,335 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 01:04:32,335 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 212 transitions. [2018-12-02 01:04:32,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:32,336 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:32,336 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:32,336 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:32,336 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:32,336 INFO L82 PathProgramCache]: Analyzing trace with hash 413507815, now seen corresponding path program 1 times [2018-12-02 01:04:32,336 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:32,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,337 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:32,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,337 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:32,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:32,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:32,370 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:32,370 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 01:04:32,370 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:32,370 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 01:04:32,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 01:04:32,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:32,371 INFO L87 Difference]: Start difference. First operand 165 states and 212 transitions. Second operand 6 states. [2018-12-02 01:04:32,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:32,392 INFO L93 Difference]: Finished difference Result 319 states and 423 transitions. [2018-12-02 01:04:32,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 01:04:32,393 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2018-12-02 01:04:32,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:32,394 INFO L225 Difference]: With dead ends: 319 [2018-12-02 01:04:32,394 INFO L226 Difference]: Without dead ends: 175 [2018-12-02 01:04:32,394 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 01:04:32,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-12-02 01:04:32,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 170. [2018-12-02 01:04:32,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-12-02 01:04:32,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 217 transitions. [2018-12-02 01:04:32,403 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 217 transitions. Word has length 90 [2018-12-02 01:04:32,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:32,403 INFO L480 AbstractCegarLoop]: Abstraction has 170 states and 217 transitions. [2018-12-02 01:04:32,403 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 01:04:32,403 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 217 transitions. [2018-12-02 01:04:32,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:32,404 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:32,404 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:32,404 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:32,404 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:32,405 INFO L82 PathProgramCache]: Analyzing trace with hash 661654309, now seen corresponding path program 1 times [2018-12-02 01:04:32,405 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:32,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,405 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:32,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,405 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:32,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:32,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:32,439 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:32,439 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 01:04:32,439 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:32,440 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 01:04:32,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 01:04:32,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:32,440 INFO L87 Difference]: Start difference. First operand 170 states and 217 transitions. Second operand 6 states. [2018-12-02 01:04:32,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:32,464 INFO L93 Difference]: Finished difference Result 326 states and 428 transitions. [2018-12-02 01:04:32,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 01:04:32,464 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2018-12-02 01:04:32,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:32,466 INFO L225 Difference]: With dead ends: 326 [2018-12-02 01:04:32,466 INFO L226 Difference]: Without dead ends: 177 [2018-12-02 01:04:32,467 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 01:04:32,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-12-02 01:04:32,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 175. [2018-12-02 01:04:32,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-12-02 01:04:32,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 222 transitions. [2018-12-02 01:04:32,479 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 222 transitions. Word has length 90 [2018-12-02 01:04:32,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:32,479 INFO L480 AbstractCegarLoop]: Abstraction has 175 states and 222 transitions. [2018-12-02 01:04:32,479 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 01:04:32,479 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 222 transitions. [2018-12-02 01:04:32,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:32,480 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:32,480 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:32,480 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:32,480 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:32,480 INFO L82 PathProgramCache]: Analyzing trace with hash 589267751, now seen corresponding path program 1 times [2018-12-02 01:04:32,480 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:32,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,481 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:32,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,481 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:32,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:32,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:32,526 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:32,526 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:32,526 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:32,526 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:32,526 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:32,527 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:32,527 INFO L87 Difference]: Start difference. First operand 175 states and 222 transitions. Second operand 5 states. [2018-12-02 01:04:32,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:32,874 INFO L93 Difference]: Finished difference Result 428 states and 562 transitions. [2018-12-02 01:04:32,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 01:04:32,874 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:32,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:32,876 INFO L225 Difference]: With dead ends: 428 [2018-12-02 01:04:32,876 INFO L226 Difference]: Without dead ends: 274 [2018-12-02 01:04:32,877 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-02 01:04:32,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-12-02 01:04:32,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 226. [2018-12-02 01:04:32,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-12-02 01:04:32,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 285 transitions. [2018-12-02 01:04:32,896 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 285 transitions. Word has length 90 [2018-12-02 01:04:32,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:32,896 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 285 transitions. [2018-12-02 01:04:32,896 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:32,896 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 285 transitions. [2018-12-02 01:04:32,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:32,897 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:32,897 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:32,898 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:32,898 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:32,898 INFO L82 PathProgramCache]: Analyzing trace with hash 1975471145, now seen corresponding path program 1 times [2018-12-02 01:04:32,898 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:32,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,899 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:32,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:32,899 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:32,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:32,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:32,933 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:32,933 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:32,933 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:32,934 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:32,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:32,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:32,934 INFO L87 Difference]: Start difference. First operand 226 states and 285 transitions. Second operand 5 states. [2018-12-02 01:04:33,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:33,107 INFO L93 Difference]: Finished difference Result 430 states and 547 transitions. [2018-12-02 01:04:33,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 01:04:33,107 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:33,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:33,108 INFO L225 Difference]: With dead ends: 430 [2018-12-02 01:04:33,108 INFO L226 Difference]: Without dead ends: 226 [2018-12-02 01:04:33,108 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 01:04:33,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-12-02 01:04:33,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 226. [2018-12-02 01:04:33,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-12-02 01:04:33,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 282 transitions. [2018-12-02 01:04:33,118 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 282 transitions. Word has length 90 [2018-12-02 01:04:33,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:33,118 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 282 transitions. [2018-12-02 01:04:33,118 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:33,119 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 282 transitions. [2018-12-02 01:04:33,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:33,119 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:33,119 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:33,119 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:33,119 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:33,119 INFO L82 PathProgramCache]: Analyzing trace with hash -396268117, now seen corresponding path program 1 times [2018-12-02 01:04:33,119 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:33,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:33,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,120 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:33,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:33,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:33,160 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:33,160 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:33,160 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:33,160 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:33,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:33,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:33,160 INFO L87 Difference]: Start difference. First operand 226 states and 282 transitions. Second operand 5 states. [2018-12-02 01:04:33,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:33,412 INFO L93 Difference]: Finished difference Result 525 states and 693 transitions. [2018-12-02 01:04:33,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 01:04:33,413 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:33,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:33,414 INFO L225 Difference]: With dead ends: 525 [2018-12-02 01:04:33,414 INFO L226 Difference]: Without dead ends: 320 [2018-12-02 01:04:33,415 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 01:04:33,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states. [2018-12-02 01:04:33,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 262. [2018-12-02 01:04:33,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2018-12-02 01:04:33,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 320 transitions. [2018-12-02 01:04:33,435 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 320 transitions. Word has length 90 [2018-12-02 01:04:33,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:33,436 INFO L480 AbstractCegarLoop]: Abstraction has 262 states and 320 transitions. [2018-12-02 01:04:33,436 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:33,436 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 320 transitions. [2018-12-02 01:04:33,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:33,436 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:33,437 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:33,437 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:33,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:33,437 INFO L82 PathProgramCache]: Analyzing trace with hash -334228503, now seen corresponding path program 1 times [2018-12-02 01:04:33,437 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:33,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:33,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,438 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:33,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:33,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:33,477 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:33,477 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 01:04:33,478 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:33,478 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:33,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:33,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 01:04:33,478 INFO L87 Difference]: Start difference. First operand 262 states and 320 transitions. Second operand 5 states. [2018-12-02 01:04:33,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:33,720 INFO L93 Difference]: Finished difference Result 571 states and 739 transitions. [2018-12-02 01:04:33,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 01:04:33,720 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-02 01:04:33,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:33,721 INFO L225 Difference]: With dead ends: 571 [2018-12-02 01:04:33,721 INFO L226 Difference]: Without dead ends: 330 [2018-12-02 01:04:33,722 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 01:04:33,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-12-02 01:04:33,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 287. [2018-12-02 01:04:33,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2018-12-02 01:04:33,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 342 transitions. [2018-12-02 01:04:33,735 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 342 transitions. Word has length 90 [2018-12-02 01:04:33,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:33,736 INFO L480 AbstractCegarLoop]: Abstraction has 287 states and 342 transitions. [2018-12-02 01:04:33,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:33,736 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 342 transitions. [2018-12-02 01:04:33,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 01:04:33,736 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:33,736 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:33,736 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:33,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:33,736 INFO L82 PathProgramCache]: Analyzing trace with hash -193679893, now seen corresponding path program 1 times [2018-12-02 01:04:33,737 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:33,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,737 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:33,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,737 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:33,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:33,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:33,757 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:33,757 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 01:04:33,757 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:33,757 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 01:04:33,757 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 01:04:33,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:33,757 INFO L87 Difference]: Start difference. First operand 287 states and 342 transitions. Second operand 3 states. [2018-12-02 01:04:33,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:33,784 INFO L93 Difference]: Finished difference Result 769 states and 926 transitions. [2018-12-02 01:04:33,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 01:04:33,785 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 90 [2018-12-02 01:04:33,785 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:33,787 INFO L225 Difference]: With dead ends: 769 [2018-12-02 01:04:33,787 INFO L226 Difference]: Without dead ends: 504 [2018-12-02 01:04:33,788 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:33,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2018-12-02 01:04:33,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 499. [2018-12-02 01:04:33,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2018-12-02 01:04:33,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 600 transitions. [2018-12-02 01:04:33,826 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 600 transitions. Word has length 90 [2018-12-02 01:04:33,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:33,826 INFO L480 AbstractCegarLoop]: Abstraction has 499 states and 600 transitions. [2018-12-02 01:04:33,826 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 01:04:33,826 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 600 transitions. [2018-12-02 01:04:33,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-12-02 01:04:33,827 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:33,827 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:33,827 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:33,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:33,828 INFO L82 PathProgramCache]: Analyzing trace with hash 1567785109, now seen corresponding path program 1 times [2018-12-02 01:04:33,828 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:33,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,828 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:33,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:33,829 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:33,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:33,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 01:04:33,854 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:33,854 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 01:04:33,854 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:33,855 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 01:04:33,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 01:04:33,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:33,855 INFO L87 Difference]: Start difference. First operand 499 states and 600 transitions. Second operand 3 states. [2018-12-02 01:04:33,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:33,912 INFO L93 Difference]: Finished difference Result 1401 states and 1753 transitions. [2018-12-02 01:04:33,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 01:04:33,912 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 91 [2018-12-02 01:04:33,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:33,917 INFO L225 Difference]: With dead ends: 1401 [2018-12-02 01:04:33,917 INFO L226 Difference]: Without dead ends: 929 [2018-12-02 01:04:33,919 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:33,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 929 states. [2018-12-02 01:04:34,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 929 to 927. [2018-12-02 01:04:34,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 927 states. [2018-12-02 01:04:34,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 927 states to 927 states and 1136 transitions. [2018-12-02 01:04:34,006 INFO L78 Accepts]: Start accepts. Automaton has 927 states and 1136 transitions. Word has length 91 [2018-12-02 01:04:34,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:34,007 INFO L480 AbstractCegarLoop]: Abstraction has 927 states and 1136 transitions. [2018-12-02 01:04:34,007 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 01:04:34,007 INFO L276 IsEmpty]: Start isEmpty. Operand 927 states and 1136 transitions. [2018-12-02 01:04:34,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-02 01:04:34,008 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:34,008 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:34,009 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:34,009 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:34,009 INFO L82 PathProgramCache]: Analyzing trace with hash 1900476813, now seen corresponding path program 1 times [2018-12-02 01:04:34,009 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:34,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:34,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,010 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:34,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:34,037 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 01:04:34,037 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:34,038 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 01:04:34,038 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:34,038 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 01:04:34,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 01:04:34,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 01:04:34,038 INFO L87 Difference]: Start difference. First operand 927 states and 1136 transitions. Second operand 4 states. [2018-12-02 01:04:34,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:34,166 INFO L93 Difference]: Finished difference Result 1825 states and 2233 transitions. [2018-12-02 01:04:34,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 01:04:34,166 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 111 [2018-12-02 01:04:34,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:34,169 INFO L225 Difference]: With dead ends: 1825 [2018-12-02 01:04:34,169 INFO L226 Difference]: Without dead ends: 920 [2018-12-02 01:04:34,172 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 01:04:34,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 920 states. [2018-12-02 01:04:34,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 920 to 920. [2018-12-02 01:04:34,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2018-12-02 01:04:34,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1124 transitions. [2018-12-02 01:04:34,227 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1124 transitions. Word has length 111 [2018-12-02 01:04:34,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:34,228 INFO L480 AbstractCegarLoop]: Abstraction has 920 states and 1124 transitions. [2018-12-02 01:04:34,228 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 01:04:34,228 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1124 transitions. [2018-12-02 01:04:34,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-02 01:04:34,229 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:34,229 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:34,229 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:34,229 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:34,229 INFO L82 PathProgramCache]: Analyzing trace with hash 549091595, now seen corresponding path program 1 times [2018-12-02 01:04:34,229 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:34,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:34,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,230 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:34,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:34,248 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-02 01:04:34,248 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:34,248 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 01:04:34,248 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:34,249 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 01:04:34,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 01:04:34,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:34,249 INFO L87 Difference]: Start difference. First operand 920 states and 1124 transitions. Second operand 3 states. [2018-12-02 01:04:34,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:34,348 INFO L93 Difference]: Finished difference Result 2694 states and 3354 transitions. [2018-12-02 01:04:34,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 01:04:34,348 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 111 [2018-12-02 01:04:34,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:34,352 INFO L225 Difference]: With dead ends: 2694 [2018-12-02 01:04:34,352 INFO L226 Difference]: Without dead ends: 1359 [2018-12-02 01:04:34,355 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:34,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1359 states. [2018-12-02 01:04:34,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1359 to 1359. [2018-12-02 01:04:34,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1359 states. [2018-12-02 01:04:34,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1359 states to 1359 states and 1660 transitions. [2018-12-02 01:04:34,415 INFO L78 Accepts]: Start accepts. Automaton has 1359 states and 1660 transitions. Word has length 111 [2018-12-02 01:04:34,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:34,415 INFO L480 AbstractCegarLoop]: Abstraction has 1359 states and 1660 transitions. [2018-12-02 01:04:34,415 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 01:04:34,415 INFO L276 IsEmpty]: Start isEmpty. Operand 1359 states and 1660 transitions. [2018-12-02 01:04:34,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-12-02 01:04:34,417 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:34,417 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:34,417 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:34,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:34,418 INFO L82 PathProgramCache]: Analyzing trace with hash 263914882, now seen corresponding path program 1 times [2018-12-02 01:04:34,418 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:34,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:34,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,418 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:34,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:34,447 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-12-02 01:04:34,447 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:34,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 01:04:34,448 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:34,448 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 01:04:34,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 01:04:34,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:34,448 INFO L87 Difference]: Start difference. First operand 1359 states and 1660 transitions. Second operand 3 states. [2018-12-02 01:04:34,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:34,554 INFO L93 Difference]: Finished difference Result 3754 states and 4763 transitions. [2018-12-02 01:04:34,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 01:04:34,554 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 155 [2018-12-02 01:04:34,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:34,560 INFO L225 Difference]: With dead ends: 3754 [2018-12-02 01:04:34,560 INFO L226 Difference]: Without dead ends: 2417 [2018-12-02 01:04:34,564 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 01:04:34,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2417 states. [2018-12-02 01:04:34,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2417 to 2414. [2018-12-02 01:04:34,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2414 states. [2018-12-02 01:04:34,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2414 states to 2414 states and 3034 transitions. [2018-12-02 01:04:34,673 INFO L78 Accepts]: Start accepts. Automaton has 2414 states and 3034 transitions. Word has length 155 [2018-12-02 01:04:34,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:34,673 INFO L480 AbstractCegarLoop]: Abstraction has 2414 states and 3034 transitions. [2018-12-02 01:04:34,673 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 01:04:34,673 INFO L276 IsEmpty]: Start isEmpty. Operand 2414 states and 3034 transitions. [2018-12-02 01:04:34,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-12-02 01:04:34,675 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:34,675 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:34,676 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:34,676 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:34,676 INFO L82 PathProgramCache]: Analyzing trace with hash -2013016935, now seen corresponding path program 1 times [2018-12-02 01:04:34,676 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:34,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:34,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:34,677 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:34,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:34,730 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-12-02 01:04:34,731 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:34,731 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 01:04:34,731 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 157 with the following transitions: [2018-12-02 01:04:34,733 INFO L205 CegarAbsIntRunner]: [4], [7], [18], [20], [22], [24], [28], [29], [31], [36], [39], [44], [47], [50], [52], [54], [56], [59], [61], [64], [75], [77], [83], [84], [87], [101], [102], [107], [113], [119], [125], [131], [133], [134], [144], [146], [148], [149], [152], [158], [164], [168], [169], [174], [221], [222], [234], [243], [246], [249], [255], [261], [268], [271], [274], [281], [284], [296], [299], [302], [306], [308], [310], [311], [316], [322], [328], [334], [340], [342], [343], [357], [359], [389], [390], [400], [402], [404], [405], [440], [441], [442], [443], [444], [445], [446], [447], [448], [449], [450], [451], [452], [454], [455], [456], [462], [463], [466], [467], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [500], [501], [502] [2018-12-02 01:04:34,764 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 01:04:34,764 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 01:04:34,934 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 01:04:34,935 INFO L272 AbstractInterpreter]: Visited 99 different actions 116 times. Merged at 10 different actions 10 times. Never widened. Performed 935 root evaluator evaluations with a maximum evaluation depth of 3. Performed 935 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 36 variables. [2018-12-02 01:04:34,946 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:34,946 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 01:04:35,104 INFO L227 lantSequenceWeakener]: Weakened 110 states. On average, predicates are now at 70.02% of their original sizes. [2018-12-02 01:04:35,104 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 01:04:35,463 INFO L418 sIntCurrentIteration]: We unified 155 AI predicates to 155 [2018-12-02 01:04:35,464 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 01:04:35,464 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 01:04:35,464 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [41] imperfect sequences [6] total 45 [2018-12-02 01:04:35,464 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:35,465 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-02 01:04:35,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-02 01:04:35,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=1240, Unknown=0, NotChecked=0, Total=1640 [2018-12-02 01:04:35,465 INFO L87 Difference]: Start difference. First operand 2414 states and 3034 transitions. Second operand 41 states. [2018-12-02 01:04:39,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:39,193 INFO L93 Difference]: Finished difference Result 5777 states and 7349 transitions. [2018-12-02 01:04:39,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-12-02 01:04:39,193 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 156 [2018-12-02 01:04:39,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:39,202 INFO L225 Difference]: With dead ends: 5777 [2018-12-02 01:04:39,202 INFO L226 Difference]: Without dead ends: 3384 [2018-12-02 01:04:39,209 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 186 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1572 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1178, Invalid=3934, Unknown=0, NotChecked=0, Total=5112 [2018-12-02 01:04:39,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3384 states. [2018-12-02 01:04:39,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3384 to 3363. [2018-12-02 01:04:39,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3363 states. [2018-12-02 01:04:39,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3363 states to 3363 states and 4196 transitions. [2018-12-02 01:04:39,404 INFO L78 Accepts]: Start accepts. Automaton has 3363 states and 4196 transitions. Word has length 156 [2018-12-02 01:04:39,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:39,405 INFO L480 AbstractCegarLoop]: Abstraction has 3363 states and 4196 transitions. [2018-12-02 01:04:39,405 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-02 01:04:39,405 INFO L276 IsEmpty]: Start isEmpty. Operand 3363 states and 4196 transitions. [2018-12-02 01:04:39,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 200 [2018-12-02 01:04:39,407 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:39,407 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:39,407 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:39,407 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:39,407 INFO L82 PathProgramCache]: Analyzing trace with hash -309106171, now seen corresponding path program 1 times [2018-12-02 01:04:39,408 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:39,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:39,408 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:39,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:39,408 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:39,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:39,442 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2018-12-02 01:04:39,443 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 01:04:39,443 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 01:04:39,443 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:39,443 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 01:04:39,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 01:04:39,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 01:04:39,443 INFO L87 Difference]: Start difference. First operand 3363 states and 4196 transitions. Second operand 4 states. [2018-12-02 01:04:39,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:39,823 INFO L93 Difference]: Finished difference Result 6685 states and 8413 transitions. [2018-12-02 01:04:39,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 01:04:39,823 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 199 [2018-12-02 01:04:39,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:39,832 INFO L225 Difference]: With dead ends: 6685 [2018-12-02 01:04:39,833 INFO L226 Difference]: Without dead ends: 3510 [2018-12-02 01:04:39,842 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 01:04:39,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3510 states. [2018-12-02 01:04:40,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3510 to 3431. [2018-12-02 01:04:40,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3431 states. [2018-12-02 01:04:40,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3431 states to 3431 states and 4077 transitions. [2018-12-02 01:04:40,044 INFO L78 Accepts]: Start accepts. Automaton has 3431 states and 4077 transitions. Word has length 199 [2018-12-02 01:04:40,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:40,044 INFO L480 AbstractCegarLoop]: Abstraction has 3431 states and 4077 transitions. [2018-12-02 01:04:40,044 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 01:04:40,044 INFO L276 IsEmpty]: Start isEmpty. Operand 3431 states and 4077 transitions. [2018-12-02 01:04:40,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 200 [2018-12-02 01:04:40,046 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:40,046 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:40,047 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:40,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:40,047 INFO L82 PathProgramCache]: Analyzing trace with hash 1856200831, now seen corresponding path program 1 times [2018-12-02 01:04:40,047 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:40,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:40,047 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:40,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:40,047 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:40,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:40,116 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 81 trivial. 0 not checked. [2018-12-02 01:04:40,116 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:40,116 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 01:04:40,116 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 200 with the following transitions: [2018-12-02 01:04:40,117 INFO L205 CegarAbsIntRunner]: [4], [7], [18], [20], [22], [24], [28], [29], [31], [36], [39], [44], [47], [50], [52], [54], [56], [59], [61], [64], [75], [77], [83], [84], [87], [89], [92], [101], [102], [107], [113], [119], [125], [131], [133], [134], [144], [146], [148], [149], [152], [158], [164], [168], [169], [174], [179], [195], [197], [199], [208], [210], [218], [221], [222], [234], [243], [246], [249], [255], [258], [264], [268], [271], [274], [281], [284], [296], [299], [302], [306], [308], [310], [311], [316], [322], [328], [334], [340], [342], [343], [357], [359], [389], [390], [400], [402], [404], [405], [440], [441], [442], [443], [444], [445], [446], [447], [448], [449], [450], [451], [452], [454], [455], [456], [458], [459], [462], [463], [464], [465], [466], [467], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [500], [501], [502] [2018-12-02 01:04:40,120 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 01:04:40,120 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 01:04:40,181 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 01:04:40,181 INFO L272 AbstractInterpreter]: Visited 116 different actions 168 times. Merged at 12 different actions 12 times. Never widened. Performed 1159 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1159 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 3 fixpoints after 3 different actions. Largest state had 36 variables. [2018-12-02 01:04:40,182 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:40,182 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 01:04:40,292 INFO L227 lantSequenceWeakener]: Weakened 153 states. On average, predicates are now at 73.89% of their original sizes. [2018-12-02 01:04:40,292 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 01:04:41,023 INFO L418 sIntCurrentIteration]: We unified 198 AI predicates to 198 [2018-12-02 01:04:41,023 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 01:04:41,023 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 01:04:41,024 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [57] imperfect sequences [6] total 61 [2018-12-02 01:04:41,024 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:41,024 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-12-02 01:04:41,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-12-02 01:04:41,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=423, Invalid=2769, Unknown=0, NotChecked=0, Total=3192 [2018-12-02 01:04:41,025 INFO L87 Difference]: Start difference. First operand 3431 states and 4077 transitions. Second operand 57 states. [2018-12-02 01:04:47,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:47,962 INFO L93 Difference]: Finished difference Result 7175 states and 8619 transitions. [2018-12-02 01:04:47,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-02 01:04:47,962 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 199 [2018-12-02 01:04:47,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:47,969 INFO L225 Difference]: With dead ends: 7175 [2018-12-02 01:04:47,969 INFO L226 Difference]: Without dead ends: 3932 [2018-12-02 01:04:47,975 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 272 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5758 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1767, Invalid=15263, Unknown=0, NotChecked=0, Total=17030 [2018-12-02 01:04:47,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3932 states. [2018-12-02 01:04:48,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3932 to 3899. [2018-12-02 01:04:48,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3899 states. [2018-12-02 01:04:48,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3899 states to 3899 states and 4616 transitions. [2018-12-02 01:04:48,167 INFO L78 Accepts]: Start accepts. Automaton has 3899 states and 4616 transitions. Word has length 199 [2018-12-02 01:04:48,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:48,168 INFO L480 AbstractCegarLoop]: Abstraction has 3899 states and 4616 transitions. [2018-12-02 01:04:48,168 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-12-02 01:04:48,168 INFO L276 IsEmpty]: Start isEmpty. Operand 3899 states and 4616 transitions. [2018-12-02 01:04:48,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-12-02 01:04:48,170 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:48,170 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:48,170 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:48,170 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:48,170 INFO L82 PathProgramCache]: Analyzing trace with hash 2861300, now seen corresponding path program 1 times [2018-12-02 01:04:48,170 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:48,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:48,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:48,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:48,171 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:48,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:48,215 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2018-12-02 01:04:48,215 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:48,215 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 01:04:48,215 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 201 with the following transitions: [2018-12-02 01:04:48,215 INFO L205 CegarAbsIntRunner]: [4], [7], [18], [20], [22], [24], [28], [29], [31], [36], [39], [44], [47], [50], [52], [54], [56], [59], [61], [64], [75], [77], [83], [84], [87], [101], [102], [107], [113], [119], [125], [131], [133], [134], [144], [146], [148], [149], [152], [158], [164], [168], [169], [174], [179], [195], [197], [199], [208], [210], [218], [221], [222], [234], [243], [246], [249], [255], [258], [261], [268], [271], [274], [281], [284], [296], [299], [302], [304], [306], [308], [310], [311], [316], [322], [328], [334], [340], [342], [343], [357], [359], [389], [390], [400], [402], [404], [405], [440], [441], [442], [443], [444], [445], [446], [447], [448], [449], [450], [451], [452], [454], [455], [456], [458], [459], [462], [463], [464], [465], [466], [467], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [500], [501], [502] [2018-12-02 01:04:48,217 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 01:04:48,217 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 01:04:48,306 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 01:04:48,306 INFO L272 AbstractInterpreter]: Visited 119 different actions 338 times. Merged at 29 different actions 64 times. Never widened. Performed 3463 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3463 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 6 fixpoints after 3 different actions. Largest state had 36 variables. [2018-12-02 01:04:48,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:48,309 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 01:04:48,309 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:48,309 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 01:04:48,316 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:48,316 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 01:04:48,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:48,379 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 01:04:48,403 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 68 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-12-02 01:04:48,403 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 01:04:48,511 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-12-02 01:04:48,527 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-02 01:04:48,527 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 8 [2018-12-02 01:04:48,527 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:48,527 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 01:04:48,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 01:04:48,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-12-02 01:04:48,528 INFO L87 Difference]: Start difference. First operand 3899 states and 4616 transitions. Second operand 3 states. [2018-12-02 01:04:48,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:48,732 INFO L93 Difference]: Finished difference Result 6387 states and 7671 transitions. [2018-12-02 01:04:48,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 01:04:48,732 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 200 [2018-12-02 01:04:48,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:48,738 INFO L225 Difference]: With dead ends: 6387 [2018-12-02 01:04:48,738 INFO L226 Difference]: Without dead ends: 1560 [2018-12-02 01:04:48,746 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 400 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-12-02 01:04:48,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1560 states. [2018-12-02 01:04:48,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1560 to 1482. [2018-12-02 01:04:48,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1482 states. [2018-12-02 01:04:48,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1482 states to 1482 states and 1651 transitions. [2018-12-02 01:04:48,840 INFO L78 Accepts]: Start accepts. Automaton has 1482 states and 1651 transitions. Word has length 200 [2018-12-02 01:04:48,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:48,841 INFO L480 AbstractCegarLoop]: Abstraction has 1482 states and 1651 transitions. [2018-12-02 01:04:48,841 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 01:04:48,841 INFO L276 IsEmpty]: Start isEmpty. Operand 1482 states and 1651 transitions. [2018-12-02 01:04:48,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2018-12-02 01:04:48,842 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:48,843 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:48,843 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:48,843 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:48,843 INFO L82 PathProgramCache]: Analyzing trace with hash 1404390967, now seen corresponding path program 1 times [2018-12-02 01:04:48,843 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:48,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:48,844 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:48,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:48,844 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:48,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:48,913 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2018-12-02 01:04:48,913 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:48,913 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 01:04:48,913 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 202 with the following transitions: [2018-12-02 01:04:48,913 INFO L205 CegarAbsIntRunner]: [4], [7], [18], [20], [22], [24], [28], [29], [31], [36], [39], [44], [47], [50], [52], [54], [56], [59], [61], [64], [75], [77], [83], [84], [87], [101], [102], [107], [113], [119], [125], [131], [133], [134], [144], [146], [148], [149], [152], [158], [164], [168], [169], [174], [179], [195], [197], [199], [208], [210], [218], [221], [222], [234], [243], [246], [249], [255], [258], [261], [268], [271], [274], [281], [284], [296], [299], [302], [304], [306], [308], [310], [311], [316], [322], [328], [334], [340], [342], [343], [357], [359], [389], [390], [393], [398], [400], [402], [404], [405], [440], [441], [442], [443], [444], [445], [446], [447], [448], [449], [450], [451], [452], [454], [455], [456], [458], [459], [462], [463], [464], [465], [466], [467], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [500], [501], [502] [2018-12-02 01:04:48,915 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 01:04:48,916 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 01:04:49,016 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 01:04:49,016 INFO L272 AbstractInterpreter]: Visited 120 different actions 340 times. Merged at 29 different actions 51 times. Never widened. Performed 3039 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3039 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 6 fixpoints after 4 different actions. Largest state had 36 variables. [2018-12-02 01:04:49,017 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:49,017 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 01:04:49,018 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:49,018 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 01:04:49,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:49,025 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 01:04:49,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:49,085 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 01:04:49,128 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 66 proven. 0 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2018-12-02 01:04:49,128 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 01:04:49,229 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 81 trivial. 0 not checked. [2018-12-02 01:04:49,244 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-02 01:04:49,244 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 7 [2018-12-02 01:04:49,244 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:49,245 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 01:04:49,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 01:04:49,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-02 01:04:49,245 INFO L87 Difference]: Start difference. First operand 1482 states and 1651 transitions. Second operand 3 states. [2018-12-02 01:04:49,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:49,333 INFO L93 Difference]: Finished difference Result 3098 states and 3543 transitions. [2018-12-02 01:04:49,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 01:04:49,333 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 201 [2018-12-02 01:04:49,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:49,336 INFO L225 Difference]: With dead ends: 3098 [2018-12-02 01:04:49,336 INFO L226 Difference]: Without dead ends: 1774 [2018-12-02 01:04:49,338 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 399 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-02 01:04:49,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1774 states. [2018-12-02 01:04:49,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1774 to 1768. [2018-12-02 01:04:49,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1768 states. [2018-12-02 01:04:49,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1768 states to 1768 states and 1971 transitions. [2018-12-02 01:04:49,428 INFO L78 Accepts]: Start accepts. Automaton has 1768 states and 1971 transitions. Word has length 201 [2018-12-02 01:04:49,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:49,428 INFO L480 AbstractCegarLoop]: Abstraction has 1768 states and 1971 transitions. [2018-12-02 01:04:49,428 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 01:04:49,428 INFO L276 IsEmpty]: Start isEmpty. Operand 1768 states and 1971 transitions. [2018-12-02 01:04:49,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-12-02 01:04:49,429 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:49,430 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:49,430 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:49,430 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:49,430 INFO L82 PathProgramCache]: Analyzing trace with hash -1590584356, now seen corresponding path program 1 times [2018-12-02 01:04:49,430 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:49,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:49,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:49,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:49,431 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:49,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:49,466 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2018-12-02 01:04:49,466 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:49,466 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 01:04:49,466 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 203 with the following transitions: [2018-12-02 01:04:49,467 INFO L205 CegarAbsIntRunner]: [4], [7], [18], [20], [22], [24], [28], [29], [31], [36], [39], [44], [47], [50], [52], [54], [56], [59], [61], [64], [75], [77], [83], [84], [87], [101], [102], [107], [113], [119], [125], [131], [133], [134], [137], [142], [144], [146], [148], [149], [152], [158], [164], [168], [169], [174], [179], [195], [197], [199], [208], [210], [218], [221], [222], [234], [243], [246], [249], [255], [258], [261], [268], [271], [274], [281], [284], [296], [299], [302], [304], [306], [308], [310], [311], [316], [322], [328], [334], [340], [342], [343], [357], [359], [389], [390], [393], [398], [400], [402], [404], [405], [440], [441], [442], [443], [444], [445], [446], [447], [448], [449], [450], [451], [452], [454], [455], [456], [458], [459], [462], [463], [464], [465], [466], [467], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [500], [501], [502] [2018-12-02 01:04:49,468 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 01:04:49,468 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 01:04:49,548 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 01:04:49,548 INFO L272 AbstractInterpreter]: Visited 121 different actions 388 times. Merged at 29 different actions 52 times. Never widened. Performed 3380 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3380 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 8 fixpoints after 4 different actions. Largest state had 36 variables. [2018-12-02 01:04:49,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:49,549 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 01:04:49,550 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 01:04:49,550 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 01:04:49,558 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:49,558 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 01:04:49,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 01:04:49,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 01:04:49,668 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 4 proven. 62 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2018-12-02 01:04:49,668 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 01:04:49,783 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2018-12-02 01:04:49,807 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 01:04:49,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2018-12-02 01:04:49,807 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 01:04:49,808 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 01:04:49,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 01:04:49,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-02 01:04:49,808 INFO L87 Difference]: Start difference. First operand 1768 states and 1971 transitions. Second operand 5 states. [2018-12-02 01:04:50,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 01:04:50,116 INFO L93 Difference]: Finished difference Result 2561 states and 2867 transitions. [2018-12-02 01:04:50,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 01:04:50,117 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 202 [2018-12-02 01:04:50,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 01:04:50,120 INFO L225 Difference]: With dead ends: 2561 [2018-12-02 01:04:50,120 INFO L226 Difference]: Without dead ends: 1555 [2018-12-02 01:04:50,121 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 397 SyntacticMatches, 5 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-02 01:04:50,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1555 states. [2018-12-02 01:04:50,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1555 to 1552. [2018-12-02 01:04:50,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1552 states. [2018-12-02 01:04:50,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1552 states to 1552 states and 1729 transitions. [2018-12-02 01:04:50,220 INFO L78 Accepts]: Start accepts. Automaton has 1552 states and 1729 transitions. Word has length 202 [2018-12-02 01:04:50,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 01:04:50,220 INFO L480 AbstractCegarLoop]: Abstraction has 1552 states and 1729 transitions. [2018-12-02 01:04:50,220 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 01:04:50,220 INFO L276 IsEmpty]: Start isEmpty. Operand 1552 states and 1729 transitions. [2018-12-02 01:04:50,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 209 [2018-12-02 01:04:50,221 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 01:04:50,221 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 01:04:50,221 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 01:04:50,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 01:04:50,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1736392345, now seen corresponding path program 1 times [2018-12-02 01:04:50,222 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 01:04:50,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:50,222 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 01:04:50,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 01:04:50,222 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 01:04:50,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 01:04:50,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 01:04:50,307 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 01:04:50,383 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 01:04:50 BoogieIcfgContainer [2018-12-02 01:04:50,384 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 01:04:50,384 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 01:04:50,384 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 01:04:50,384 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 01:04:50,384 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 01:04:30" (3/4) ... [2018-12-02 01:04:50,386 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-02 01:04:50,462 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_434a7982-c03b-444d-92da-bcfb034b97ec/bin-2019/utaipan/witness.graphml [2018-12-02 01:04:50,463 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 01:04:50,463 INFO L168 Benchmark]: Toolchain (without parser) took 20598.91 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 933.8 MB). Free memory was 948.6 MB in the beginning and 938.1 MB in the end (delta: 10.5 MB). Peak memory consumption was 944.3 MB. Max. memory is 11.5 GB. [2018-12-02 01:04:50,464 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 01:04:50,464 INFO L168 Benchmark]: CACSL2BoogieTranslator took 196.29 ms. Allocated memory is still 1.0 GB. Free memory was 948.6 MB in the beginning and 932.5 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-02 01:04:50,465 INFO L168 Benchmark]: Boogie Procedure Inliner took 41.95 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 120.1 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -185.9 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. [2018-12-02 01:04:50,465 INFO L168 Benchmark]: Boogie Preprocessor took 28.19 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-12-02 01:04:50,465 INFO L168 Benchmark]: RCFGBuilder took 269.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 42.3 MB). Peak memory consumption was 42.3 MB. Max. memory is 11.5 GB. [2018-12-02 01:04:50,465 INFO L168 Benchmark]: TraceAbstraction took 19980.96 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 813.7 MB). Free memory was 1.1 GB in the beginning and 959.6 MB in the end (delta: 113.0 MB). Peak memory consumption was 926.7 MB. Max. memory is 11.5 GB. [2018-12-02 01:04:50,466 INFO L168 Benchmark]: Witness Printer took 78.74 ms. Allocated memory is still 2.0 GB. Free memory was 959.6 MB in the beginning and 938.1 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-12-02 01:04:50,467 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 196.29 ms. Allocated memory is still 1.0 GB. Free memory was 948.6 MB in the beginning and 932.5 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 41.95 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 120.1 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -185.9 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 28.19 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 269.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 42.3 MB). Peak memory consumption was 42.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19980.96 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 813.7 MB). Free memory was 1.1 GB in the beginning and 959.6 MB in the end (delta: 113.0 MB). Peak memory consumption was 926.7 MB. Max. memory is 11.5 GB. * Witness Printer took 78.74 ms. Allocated memory is still 2.0 GB. Free memory was 959.6 MB in the beginning and 938.1 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; VAL [\old(E_1)=16, \old(E_2)=5, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=11, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=15, \old(t1_pc)=8, \old(t1_st)=4, \old(T2_E)=14, \old(t2_i)=6, \old(t2_pc)=9, \old(t2_st)=10, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L563] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L567] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L477] m_i = 1 [L478] t1_i = 1 [L479] t2_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L567] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L568] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L511] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L211] COND TRUE m_i == 1 [L212] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L221] COND TRUE t2_i == 1 [L222] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L324] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L329] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L334] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L514] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L165] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L184] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L514] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L357] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L362] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L367] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L518] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L521] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L522] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L257] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L78] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L113] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L124] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L126] t2_pc = 1 [L127] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L305] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND TRUE \read(tmp_ndt_1) [L276] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L277] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L37] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L48] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L51] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND TRUE E_1 == 1 [L167] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND TRUE \read(tmp___0) [L404] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1, tmp___1=0] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L53] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L56] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L58] m_pc = 1 [L59] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L277] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L78] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L81] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L97] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L98] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L147] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND TRUE E_2 == 1 [L186] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND TRUE \read(tmp___1) [L412] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=0, tmp___0=0, tmp___1=1] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L98] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L99] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L113] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L116] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L132] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 169 locations, 1 error locations. UNSAFE Result, 19.9s OverallTime, 25 OverallIterations, 3 TraceHistogramMax, 14.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5855 SDtfs, 7472 SDslu, 10700 SDs, 0 SdLazy, 5633 SolverSat, 2222 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.1s Time, PredicateUnifierStatistics: 4 DeclaredPredicates, 1825 GetRequests, 1511 SyntacticMatches, 32 SemanticMatches, 282 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7362 ImplicationChecksByTransitivity, 2.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3899occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.5s AbstIntTime, 5 AbstIntIterations, 2 AbstIntStrong, 0.9878012681626707 AbsIntWeakeningRatio, 0.5609065155807366 AbsIntAvgWeakeningVarsNumRemoved, 11.541076487252125 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.3s AutomataMinimizationTime, 24 MinimizatonAttempts, 560 StatesRemovedByMinimization, 20 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 3696 NumberOfCodeBlocks, 3696 NumberOfCodeBlocksAsserted, 28 NumberOfCheckSat, 4061 ConstructedInterpolants, 0 QuantifiedInterpolants, 945291 SizeOfPredicates, 4 NumberOfNonLiveVariables, 2346 ConjunctsInSsa, 16 ConjunctsInUnsatCore, 30 InterpolantComputations, 24 PerfectInterpolantSequences, 1158/1319 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...