./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 14:53:39,621 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 14:53:39,622 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 14:53:39,628 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 14:53:39,628 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 14:53:39,629 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 14:53:39,629 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 14:53:39,630 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 14:53:39,631 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 14:53:39,632 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 14:53:39,632 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 14:53:39,632 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 14:53:39,633 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 14:53:39,633 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 14:53:39,634 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 14:53:39,634 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 14:53:39,635 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 14:53:39,636 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 14:53:39,637 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 14:53:39,638 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 14:53:39,638 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 14:53:39,639 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 14:53:39,640 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 14:53:39,640 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 14:53:39,640 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 14:53:39,641 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 14:53:39,641 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 14:53:39,642 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 14:53:39,642 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 14:53:39,643 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 14:53:39,643 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 14:53:39,643 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 14:53:39,644 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 14:53:39,644 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 14:53:39,644 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 14:53:39,645 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 14:53:39,645 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-12-02 14:53:39,652 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 14:53:39,652 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 14:53:39,653 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 14:53:39,653 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 14:53:39,653 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-02 14:53:39,653 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-02 14:53:39,653 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-02 14:53:39,654 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-02 14:53:39,654 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-02 14:53:39,654 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-02 14:53:39,654 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-02 14:53:39,654 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-02 14:53:39,654 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-02 14:53:39,654 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-02 14:53:39,655 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-02 14:53:39,656 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 14:53:39,656 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 14:53:39,656 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 14:53:39,657 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-02 14:53:39,657 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2018-12-02 14:53:39,674 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 14:53:39,684 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 14:53:39,686 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 14:53:39,688 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 14:53:39,688 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 14:53:39,689 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-12-02 14:53:39,728 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/data/48fb47ffe/f346745d597142d2902cc7d5251a5d3b/FLAGf66539bdf [2018-12-02 14:53:40,141 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 14:53:40,141 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-12-02 14:53:40,146 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/data/48fb47ffe/f346745d597142d2902cc7d5251a5d3b/FLAGf66539bdf [2018-12-02 14:53:40,154 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/data/48fb47ffe/f346745d597142d2902cc7d5251a5d3b [2018-12-02 14:53:40,155 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 14:53:40,156 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 14:53:40,157 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 14:53:40,157 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 14:53:40,159 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 14:53:40,159 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,161 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@643265e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40, skipping insertion in model container [2018-12-02 14:53:40,161 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,165 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 14:53:40,181 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 14:53:40,288 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 14:53:40,291 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 14:53:40,316 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 14:53:40,325 INFO L195 MainTranslator]: Completed translation [2018-12-02 14:53:40,326 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40 WrapperNode [2018-12-02 14:53:40,326 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 14:53:40,326 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 14:53:40,326 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 14:53:40,326 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 14:53:40,362 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,369 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,376 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 14:53:40,376 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 14:53:40,376 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 14:53:40,376 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 14:53:40,383 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,384 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,385 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,385 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,390 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,397 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,398 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... [2018-12-02 14:53:40,400 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 14:53:40,400 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 14:53:40,400 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 14:53:40,400 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 14:53:40,401 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 14:53:40,432 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-12-02 14:53:40,432 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-12-02 14:53:40,432 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-12-02 14:53:40,432 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-12-02 14:53:40,432 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-12-02 14:53:40,432 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-12-02 14:53:40,433 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 14:53:40,433 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 14:53:40,433 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-02 14:53:40,433 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-02 14:53:40,433 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-02 14:53:40,433 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-02 14:53:40,433 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-12-02 14:53:40,433 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-12-02 14:53:40,433 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-02 14:53:40,433 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-02 14:53:40,433 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-12-02 14:53:40,433 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-12-02 14:53:40,433 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-02 14:53:40,433 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-02 14:53:40,434 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-02 14:53:40,434 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-02 14:53:40,434 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-12-02 14:53:40,434 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-12-02 14:53:40,434 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-02 14:53:40,434 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-02 14:53:40,434 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-02 14:53:40,434 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-02 14:53:40,434 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-12-02 14:53:40,435 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-12-02 14:53:40,435 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-02 14:53:40,435 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-02 14:53:40,435 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-12-02 14:53:40,435 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-12-02 14:53:40,435 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-02 14:53:40,435 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-02 14:53:40,435 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 14:53:40,435 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 14:53:40,436 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-02 14:53:40,436 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-02 14:53:40,436 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-12-02 14:53:40,436 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-12-02 14:53:40,436 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-02 14:53:40,436 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-02 14:53:40,436 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-02 14:53:40,436 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-02 14:53:40,437 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 14:53:40,437 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 14:53:40,437 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-02 14:53:40,437 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-02 14:53:40,748 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 14:53:40,748 INFO L280 CfgBuilder]: Removed 7 assue(true) statements. [2018-12-02 14:53:40,748 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 02:53:40 BoogieIcfgContainer [2018-12-02 14:53:40,748 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 14:53:40,749 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 14:53:40,749 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 14:53:40,751 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 14:53:40,752 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 02:53:40" (1/3) ... [2018-12-02 14:53:40,752 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@76a6486b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 02:53:40, skipping insertion in model container [2018-12-02 14:53:40,752 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:53:40" (2/3) ... [2018-12-02 14:53:40,753 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@76a6486b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 02:53:40, skipping insertion in model container [2018-12-02 14:53:40,753 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 02:53:40" (3/3) ... [2018-12-02 14:53:40,754 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.03_false-unreach-call_false-termination.cil.c [2018-12-02 14:53:40,760 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 14:53:40,764 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-02 14:53:40,773 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-02 14:53:40,792 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 14:53:40,792 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-02 14:53:40,792 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 14:53:40,792 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 14:53:40,792 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 14:53:40,792 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 14:53:40,792 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 14:53:40,793 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 14:53:40,807 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states. [2018-12-02 14:53:40,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:40,812 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:40,813 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:40,814 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:40,817 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:40,817 INFO L82 PathProgramCache]: Analyzing trace with hash 1541128221, now seen corresponding path program 1 times [2018-12-02 14:53:40,819 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:40,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:40,855 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:40,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:40,855 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:40,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:41,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:41,037 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:41,037 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:41,037 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:41,042 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:41,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:41,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:41,052 INFO L87 Difference]: Start difference. First operand 199 states. Second operand 5 states. [2018-12-02 14:53:41,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:41,388 INFO L93 Difference]: Finished difference Result 412 states and 610 transitions. [2018-12-02 14:53:41,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:41,390 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:41,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:41,398 INFO L225 Difference]: With dead ends: 412 [2018-12-02 14:53:41,398 INFO L226 Difference]: Without dead ends: 222 [2018-12-02 14:53:41,400 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:41,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-12-02 14:53:41,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 190. [2018-12-02 14:53:41,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-12-02 14:53:41,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 258 transitions. [2018-12-02 14:53:41,442 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 258 transitions. Word has length 105 [2018-12-02 14:53:41,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:41,442 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 258 transitions. [2018-12-02 14:53:41,442 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:41,443 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 258 transitions. [2018-12-02 14:53:41,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:41,446 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:41,446 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:41,446 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:41,446 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:41,446 INFO L82 PathProgramCache]: Analyzing trace with hash -1187081125, now seen corresponding path program 1 times [2018-12-02 14:53:41,447 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:41,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:41,448 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:41,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:41,448 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:41,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:41,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:41,547 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:41,547 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:41,547 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:41,548 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:41,548 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:41,548 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:41,549 INFO L87 Difference]: Start difference. First operand 190 states and 258 transitions. Second operand 5 states. [2018-12-02 14:53:41,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:41,797 INFO L93 Difference]: Finished difference Result 391 states and 548 transitions. [2018-12-02 14:53:41,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:41,797 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:41,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:41,799 INFO L225 Difference]: With dead ends: 391 [2018-12-02 14:53:41,799 INFO L226 Difference]: Without dead ends: 222 [2018-12-02 14:53:41,800 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:41,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-12-02 14:53:41,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 190. [2018-12-02 14:53:41,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-12-02 14:53:41,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 257 transitions. [2018-12-02 14:53:41,811 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 257 transitions. Word has length 105 [2018-12-02 14:53:41,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:41,811 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 257 transitions. [2018-12-02 14:53:41,812 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:41,812 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 257 transitions. [2018-12-02 14:53:41,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:41,812 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:41,813 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:41,813 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:41,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:41,813 INFO L82 PathProgramCache]: Analyzing trace with hash 2050048093, now seen corresponding path program 1 times [2018-12-02 14:53:41,813 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:41,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:41,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:41,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:41,814 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:41,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:41,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:41,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:41,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:41,872 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:41,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:41,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:41,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:41,872 INFO L87 Difference]: Start difference. First operand 190 states and 257 transitions. Second operand 5 states. [2018-12-02 14:53:42,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:42,119 INFO L93 Difference]: Finished difference Result 389 states and 542 transitions. [2018-12-02 14:53:42,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:42,119 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:42,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:42,120 INFO L225 Difference]: With dead ends: 389 [2018-12-02 14:53:42,120 INFO L226 Difference]: Without dead ends: 220 [2018-12-02 14:53:42,121 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:42,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-12-02 14:53:42,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 190. [2018-12-02 14:53:42,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-12-02 14:53:42,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 256 transitions. [2018-12-02 14:53:42,132 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 256 transitions. Word has length 105 [2018-12-02 14:53:42,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:42,132 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 256 transitions. [2018-12-02 14:53:42,132 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:42,132 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 256 transitions. [2018-12-02 14:53:42,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:42,133 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:42,133 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:42,133 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:42,133 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:42,133 INFO L82 PathProgramCache]: Analyzing trace with hash 907545627, now seen corresponding path program 1 times [2018-12-02 14:53:42,133 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:42,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:42,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:42,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:42,134 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:42,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:42,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:42,181 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:42,181 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:42,181 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:42,181 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:42,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:42,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:42,182 INFO L87 Difference]: Start difference. First operand 190 states and 256 transitions. Second operand 5 states. [2018-12-02 14:53:42,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:42,414 INFO L93 Difference]: Finished difference Result 387 states and 536 transitions. [2018-12-02 14:53:42,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:42,414 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:42,414 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:42,415 INFO L225 Difference]: With dead ends: 387 [2018-12-02 14:53:42,415 INFO L226 Difference]: Without dead ends: 218 [2018-12-02 14:53:42,416 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:42,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-12-02 14:53:42,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 190. [2018-12-02 14:53:42,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-12-02 14:53:42,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 255 transitions. [2018-12-02 14:53:42,426 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 255 transitions. Word has length 105 [2018-12-02 14:53:42,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:42,427 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 255 transitions. [2018-12-02 14:53:42,427 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:42,427 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 255 transitions. [2018-12-02 14:53:42,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:42,428 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:42,428 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:42,428 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:42,428 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:42,428 INFO L82 PathProgramCache]: Analyzing trace with hash 1147785373, now seen corresponding path program 1 times [2018-12-02 14:53:42,428 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:42,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:42,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:42,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:42,429 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:42,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:42,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:42,480 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:42,480 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:42,480 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:42,480 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:42,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:42,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:42,481 INFO L87 Difference]: Start difference. First operand 190 states and 255 transitions. Second operand 5 states. [2018-12-02 14:53:42,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:42,704 INFO L93 Difference]: Finished difference Result 407 states and 568 transitions. [2018-12-02 14:53:42,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:42,704 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:42,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:42,706 INFO L225 Difference]: With dead ends: 407 [2018-12-02 14:53:42,706 INFO L226 Difference]: Without dead ends: 238 [2018-12-02 14:53:42,707 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:42,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 238 states. [2018-12-02 14:53:42,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 238 to 190. [2018-12-02 14:53:42,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-12-02 14:53:42,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 254 transitions. [2018-12-02 14:53:42,724 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 254 transitions. Word has length 105 [2018-12-02 14:53:42,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:42,724 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 254 transitions. [2018-12-02 14:53:42,724 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:42,724 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 254 transitions. [2018-12-02 14:53:42,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:42,725 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:42,726 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:42,726 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:42,726 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:42,726 INFO L82 PathProgramCache]: Analyzing trace with hash 1986819035, now seen corresponding path program 1 times [2018-12-02 14:53:42,726 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:42,727 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:42,727 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:42,727 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:42,727 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:42,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:42,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:42,784 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:42,784 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:42,784 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:42,785 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:42,785 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:42,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:42,785 INFO L87 Difference]: Start difference. First operand 190 states and 254 transitions. Second operand 5 states. [2018-12-02 14:53:43,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:43,048 INFO L93 Difference]: Finished difference Result 405 states and 562 transitions. [2018-12-02 14:53:43,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:43,049 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:43,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:43,050 INFO L225 Difference]: With dead ends: 405 [2018-12-02 14:53:43,050 INFO L226 Difference]: Without dead ends: 236 [2018-12-02 14:53:43,050 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:43,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-12-02 14:53:43,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 190. [2018-12-02 14:53:43,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-12-02 14:53:43,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 253 transitions. [2018-12-02 14:53:43,062 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 253 transitions. Word has length 105 [2018-12-02 14:53:43,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:43,063 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 253 transitions. [2018-12-02 14:53:43,063 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:43,063 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 253 transitions. [2018-12-02 14:53:43,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:43,064 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:43,064 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:43,064 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:43,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:43,064 INFO L82 PathProgramCache]: Analyzing trace with hash 2013884637, now seen corresponding path program 1 times [2018-12-02 14:53:43,064 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:43,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:43,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,065 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:43,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:43,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:43,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:43,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 14:53:43,111 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:43,111 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:53:43,112 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:53:43,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:53:43,112 INFO L87 Difference]: Start difference. First operand 190 states and 253 transitions. Second operand 4 states. [2018-12-02 14:53:43,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:43,258 INFO L93 Difference]: Finished difference Result 518 states and 714 transitions. [2018-12-02 14:53:43,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:53:43,258 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 105 [2018-12-02 14:53:43,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:43,259 INFO L225 Difference]: With dead ends: 518 [2018-12-02 14:53:43,259 INFO L226 Difference]: Without dead ends: 350 [2018-12-02 14:53:43,260 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:53:43,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states. [2018-12-02 14:53:43,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 345. [2018-12-02 14:53:43,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 345 states. [2018-12-02 14:53:43,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 345 states to 345 states and 459 transitions. [2018-12-02 14:53:43,277 INFO L78 Accepts]: Start accepts. Automaton has 345 states and 459 transitions. Word has length 105 [2018-12-02 14:53:43,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:43,278 INFO L480 AbstractCegarLoop]: Abstraction has 345 states and 459 transitions. [2018-12-02 14:53:43,278 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:53:43,278 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 459 transitions. [2018-12-02 14:53:43,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:43,279 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:43,279 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:43,279 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:43,279 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:43,279 INFO L82 PathProgramCache]: Analyzing trace with hash -1143453794, now seen corresponding path program 1 times [2018-12-02 14:53:43,279 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:43,280 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,280 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:43,280 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,280 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:43,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:43,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:43,312 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:43,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 14:53:43,313 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:43,313 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 14:53:43,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 14:53:43,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:43,313 INFO L87 Difference]: Start difference. First operand 345 states and 459 transitions. Second operand 6 states. [2018-12-02 14:53:43,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:43,356 INFO L93 Difference]: Finished difference Result 684 states and 934 transitions. [2018-12-02 14:53:43,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 14:53:43,356 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 105 [2018-12-02 14:53:43,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:43,358 INFO L225 Difference]: With dead ends: 684 [2018-12-02 14:53:43,358 INFO L226 Difference]: Without dead ends: 361 [2018-12-02 14:53:43,359 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:53:43,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 361 states. [2018-12-02 14:53:43,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 361 to 350. [2018-12-02 14:53:43,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 350 states. [2018-12-02 14:53:43,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 463 transitions. [2018-12-02 14:53:43,380 INFO L78 Accepts]: Start accepts. Automaton has 350 states and 463 transitions. Word has length 105 [2018-12-02 14:53:43,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:43,380 INFO L480 AbstractCegarLoop]: Abstraction has 350 states and 463 transitions. [2018-12-02 14:53:43,380 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 14:53:43,380 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 463 transitions. [2018-12-02 14:53:43,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:43,381 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:43,381 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:43,381 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:43,381 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:43,381 INFO L82 PathProgramCache]: Analyzing trace with hash -1560850400, now seen corresponding path program 1 times [2018-12-02 14:53:43,381 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:43,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,382 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:43,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,382 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:43,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:43,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:43,427 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:43,428 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 14:53:43,428 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:43,428 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:53:43,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:53:43,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:53:43,428 INFO L87 Difference]: Start difference. First operand 350 states and 463 transitions. Second operand 4 states. [2018-12-02 14:53:43,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:43,557 INFO L93 Difference]: Finished difference Result 993 states and 1359 transitions. [2018-12-02 14:53:43,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:53:43,557 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 105 [2018-12-02 14:53:43,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:43,560 INFO L225 Difference]: With dead ends: 993 [2018-12-02 14:53:43,560 INFO L226 Difference]: Without dead ends: 665 [2018-12-02 14:53:43,561 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:53:43,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states. [2018-12-02 14:53:43,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 658. [2018-12-02 14:53:43,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 658 states. [2018-12-02 14:53:43,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 868 transitions. [2018-12-02 14:53:43,592 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 868 transitions. Word has length 105 [2018-12-02 14:53:43,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:43,593 INFO L480 AbstractCegarLoop]: Abstraction has 658 states and 868 transitions. [2018-12-02 14:53:43,593 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:53:43,593 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 868 transitions. [2018-12-02 14:53:43,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:43,594 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:43,594 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:43,594 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:43,594 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:43,594 INFO L82 PathProgramCache]: Analyzing trace with hash 827632703, now seen corresponding path program 1 times [2018-12-02 14:53:43,594 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:43,595 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,595 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:43,595 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,595 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:43,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:43,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:43,630 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:43,630 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 14:53:43,630 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:43,630 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 14:53:43,630 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 14:53:43,631 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:43,631 INFO L87 Difference]: Start difference. First operand 658 states and 868 transitions. Second operand 6 states. [2018-12-02 14:53:43,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:43,685 INFO L93 Difference]: Finished difference Result 1320 states and 1785 transitions. [2018-12-02 14:53:43,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 14:53:43,685 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 105 [2018-12-02 14:53:43,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:43,688 INFO L225 Difference]: With dead ends: 1320 [2018-12-02 14:53:43,688 INFO L226 Difference]: Without dead ends: 684 [2018-12-02 14:53:43,690 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:53:43,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 684 states. [2018-12-02 14:53:43,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 684 to 668. [2018-12-02 14:53:43,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 668 states. [2018-12-02 14:53:43,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 668 states and 876 transitions. [2018-12-02 14:53:43,718 INFO L78 Accepts]: Start accepts. Automaton has 668 states and 876 transitions. Word has length 105 [2018-12-02 14:53:43,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:43,719 INFO L480 AbstractCegarLoop]: Abstraction has 668 states and 876 transitions. [2018-12-02 14:53:43,719 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 14:53:43,719 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 876 transitions. [2018-12-02 14:53:43,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:43,719 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:43,719 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:43,719 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:43,720 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:43,720 INFO L82 PathProgramCache]: Analyzing trace with hash 1703651709, now seen corresponding path program 1 times [2018-12-02 14:53:43,720 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:43,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:43,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,720 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:43,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:43,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:43,745 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:43,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 14:53:43,745 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:43,745 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 14:53:43,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 14:53:43,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:43,746 INFO L87 Difference]: Start difference. First operand 668 states and 876 transitions. Second operand 6 states. [2018-12-02 14:53:43,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:43,803 INFO L93 Difference]: Finished difference Result 1354 states and 1822 transitions. [2018-12-02 14:53:43,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 14:53:43,803 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 105 [2018-12-02 14:53:43,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:43,806 INFO L225 Difference]: With dead ends: 1354 [2018-12-02 14:53:43,806 INFO L226 Difference]: Without dead ends: 708 [2018-12-02 14:53:43,808 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:53:43,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 708 states. [2018-12-02 14:53:43,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 708 to 688. [2018-12-02 14:53:43,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 688 states. [2018-12-02 14:53:43,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 896 transitions. [2018-12-02 14:53:43,855 INFO L78 Accepts]: Start accepts. Automaton has 688 states and 896 transitions. Word has length 105 [2018-12-02 14:53:43,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:43,855 INFO L480 AbstractCegarLoop]: Abstraction has 688 states and 896 transitions. [2018-12-02 14:53:43,855 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 14:53:43,855 INFO L276 IsEmpty]: Start isEmpty. Operand 688 states and 896 transitions. [2018-12-02 14:53:43,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:43,856 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:43,856 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:43,856 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:43,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:43,856 INFO L82 PathProgramCache]: Analyzing trace with hash -1697829249, now seen corresponding path program 1 times [2018-12-02 14:53:43,856 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:43,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:43,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:43,857 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:43,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:43,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:43,887 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:43,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 14:53:43,887 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:43,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 14:53:43,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 14:53:43,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:43,888 INFO L87 Difference]: Start difference. First operand 688 states and 896 transitions. Second operand 6 states. [2018-12-02 14:53:43,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:43,962 INFO L93 Difference]: Finished difference Result 1382 states and 1842 transitions. [2018-12-02 14:53:43,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 14:53:43,962 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 105 [2018-12-02 14:53:43,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:43,966 INFO L225 Difference]: With dead ends: 1382 [2018-12-02 14:53:43,966 INFO L226 Difference]: Without dead ends: 716 [2018-12-02 14:53:43,968 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:53:43,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2018-12-02 14:53:43,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 708. [2018-12-02 14:53:43,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 708 states. [2018-12-02 14:53:44,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 708 states to 708 states and 916 transitions. [2018-12-02 14:53:44,000 INFO L78 Accepts]: Start accepts. Automaton has 708 states and 916 transitions. Word has length 105 [2018-12-02 14:53:44,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:44,000 INFO L480 AbstractCegarLoop]: Abstraction has 708 states and 916 transitions. [2018-12-02 14:53:44,000 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 14:53:44,001 INFO L276 IsEmpty]: Start isEmpty. Operand 708 states and 916 transitions. [2018-12-02 14:53:44,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:44,001 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:44,001 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:44,002 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:44,002 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:44,002 INFO L82 PathProgramCache]: Analyzing trace with hash -2092196035, now seen corresponding path program 1 times [2018-12-02 14:53:44,002 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:44,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:44,003 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:44,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:44,003 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:44,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:44,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:44,048 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:44,048 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:44,048 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:44,048 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:44,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:44,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:44,049 INFO L87 Difference]: Start difference. First operand 708 states and 916 transitions. Second operand 5 states. [2018-12-02 14:53:44,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:44,440 INFO L93 Difference]: Finished difference Result 1699 states and 2243 transitions. [2018-12-02 14:53:44,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 14:53:44,440 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:44,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:44,443 INFO L225 Difference]: With dead ends: 1699 [2018-12-02 14:53:44,443 INFO L226 Difference]: Without dead ends: 1014 [2018-12-02 14:53:44,445 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-02 14:53:44,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1014 states. [2018-12-02 14:53:44,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1014 to 934. [2018-12-02 14:53:44,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2018-12-02 14:53:44,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 1180 transitions. [2018-12-02 14:53:44,481 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 1180 transitions. Word has length 105 [2018-12-02 14:53:44,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:44,481 INFO L480 AbstractCegarLoop]: Abstraction has 934 states and 1180 transitions. [2018-12-02 14:53:44,481 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:44,481 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 1180 transitions. [2018-12-02 14:53:44,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:44,482 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:44,482 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:44,482 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:44,482 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:44,482 INFO L82 PathProgramCache]: Analyzing trace with hash -1817436421, now seen corresponding path program 1 times [2018-12-02 14:53:44,482 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:44,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:44,483 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:44,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:44,483 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:44,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:44,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:44,530 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:44,530 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:44,530 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:44,530 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:44,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:44,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:44,530 INFO L87 Difference]: Start difference. First operand 934 states and 1180 transitions. Second operand 5 states. [2018-12-02 14:53:44,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:44,726 INFO L93 Difference]: Finished difference Result 1845 states and 2342 transitions. [2018-12-02 14:53:44,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:44,727 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:44,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:44,729 INFO L225 Difference]: With dead ends: 1845 [2018-12-02 14:53:44,729 INFO L226 Difference]: Without dead ends: 934 [2018-12-02 14:53:44,731 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:44,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 934 states. [2018-12-02 14:53:44,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 934 to 934. [2018-12-02 14:53:44,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2018-12-02 14:53:44,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 1170 transitions. [2018-12-02 14:53:44,766 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 1170 transitions. Word has length 105 [2018-12-02 14:53:44,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:44,766 INFO L480 AbstractCegarLoop]: Abstraction has 934 states and 1170 transitions. [2018-12-02 14:53:44,766 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:44,766 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 1170 transitions. [2018-12-02 14:53:44,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:44,767 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:44,767 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:44,767 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:44,767 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:44,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1115836547, now seen corresponding path program 1 times [2018-12-02 14:53:44,767 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:44,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:44,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:44,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:44,768 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:44,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:44,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:44,813 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:44,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:44,814 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:44,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:44,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:44,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:44,814 INFO L87 Difference]: Start difference. First operand 934 states and 1170 transitions. Second operand 5 states. [2018-12-02 14:53:45,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:45,041 INFO L93 Difference]: Finished difference Result 1845 states and 2322 transitions. [2018-12-02 14:53:45,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:53:45,042 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:45,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:45,044 INFO L225 Difference]: With dead ends: 1845 [2018-12-02 14:53:45,044 INFO L226 Difference]: Without dead ends: 934 [2018-12-02 14:53:45,045 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:53:45,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 934 states. [2018-12-02 14:53:45,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 934 to 934. [2018-12-02 14:53:45,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2018-12-02 14:53:45,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 1160 transitions. [2018-12-02 14:53:45,081 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 1160 transitions. Word has length 105 [2018-12-02 14:53:45,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:45,081 INFO L480 AbstractCegarLoop]: Abstraction has 934 states and 1160 transitions. [2018-12-02 14:53:45,081 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:45,082 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 1160 transitions. [2018-12-02 14:53:45,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:45,082 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:45,082 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:45,082 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:45,082 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:45,082 INFO L82 PathProgramCache]: Analyzing trace with hash -1093204293, now seen corresponding path program 1 times [2018-12-02 14:53:45,083 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:45,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:45,083 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:45,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:45,083 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:45,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:45,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:45,133 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:45,133 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:45,133 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:45,133 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:45,133 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:45,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:45,133 INFO L87 Difference]: Start difference. First operand 934 states and 1160 transitions. Second operand 5 states. [2018-12-02 14:53:45,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:45,443 INFO L93 Difference]: Finished difference Result 1978 states and 2497 transitions. [2018-12-02 14:53:45,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 14:53:45,443 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:45,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:45,447 INFO L225 Difference]: With dead ends: 1978 [2018-12-02 14:53:45,447 INFO L226 Difference]: Without dead ends: 1067 [2018-12-02 14:53:45,449 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:53:45,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1067 states. [2018-12-02 14:53:45,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1067 to 1066. [2018-12-02 14:53:45,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1066 states. [2018-12-02 14:53:45,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1066 states to 1066 states and 1313 transitions. [2018-12-02 14:53:45,500 INFO L78 Accepts]: Start accepts. Automaton has 1066 states and 1313 transitions. Word has length 105 [2018-12-02 14:53:45,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:45,501 INFO L480 AbstractCegarLoop]: Abstraction has 1066 states and 1313 transitions. [2018-12-02 14:53:45,501 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:45,501 INFO L276 IsEmpty]: Start isEmpty. Operand 1066 states and 1313 transitions. [2018-12-02 14:53:45,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:45,502 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:45,502 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:45,502 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:45,502 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:45,502 INFO L82 PathProgramCache]: Analyzing trace with hash -1602677383, now seen corresponding path program 1 times [2018-12-02 14:53:45,502 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:45,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:45,503 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:45,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:45,503 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:45,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:45,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:45,541 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:45,541 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:45,541 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:45,541 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:45,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:45,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:45,542 INFO L87 Difference]: Start difference. First operand 1066 states and 1313 transitions. Second operand 5 states. [2018-12-02 14:53:45,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:45,851 INFO L93 Difference]: Finished difference Result 2310 states and 2964 transitions. [2018-12-02 14:53:45,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 14:53:45,851 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:45,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:45,854 INFO L225 Difference]: With dead ends: 2310 [2018-12-02 14:53:45,854 INFO L226 Difference]: Without dead ends: 1266 [2018-12-02 14:53:45,855 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:53:45,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1266 states. [2018-12-02 14:53:45,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1266 to 1135. [2018-12-02 14:53:45,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1135 states. [2018-12-02 14:53:45,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1135 states to 1135 states and 1366 transitions. [2018-12-02 14:53:45,901 INFO L78 Accepts]: Start accepts. Automaton has 1135 states and 1366 transitions. Word has length 105 [2018-12-02 14:53:45,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:45,901 INFO L480 AbstractCegarLoop]: Abstraction has 1135 states and 1366 transitions. [2018-12-02 14:53:45,902 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:45,902 INFO L276 IsEmpty]: Start isEmpty. Operand 1135 states and 1366 transitions. [2018-12-02 14:53:45,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:45,902 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:45,902 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:45,903 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:45,903 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:45,903 INFO L82 PathProgramCache]: Analyzing trace with hash 320550651, now seen corresponding path program 1 times [2018-12-02 14:53:45,903 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:45,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:45,904 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:45,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:45,904 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:45,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:45,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:45,941 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:45,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 14:53:45,941 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:45,942 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:53:45,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:53:45,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:53:45,942 INFO L87 Difference]: Start difference. First operand 1135 states and 1366 transitions. Second operand 5 states. [2018-12-02 14:53:46,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:46,281 INFO L93 Difference]: Finished difference Result 2657 states and 3411 transitions. [2018-12-02 14:53:46,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 14:53:46,282 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 105 [2018-12-02 14:53:46,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:46,287 INFO L225 Difference]: With dead ends: 2657 [2018-12-02 14:53:46,287 INFO L226 Difference]: Without dead ends: 1544 [2018-12-02 14:53:46,290 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-02 14:53:46,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1544 states. [2018-12-02 14:53:46,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1544 to 1321. [2018-12-02 14:53:46,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1321 states. [2018-12-02 14:53:46,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1321 states to 1321 states and 1563 transitions. [2018-12-02 14:53:46,380 INFO L78 Accepts]: Start accepts. Automaton has 1321 states and 1563 transitions. Word has length 105 [2018-12-02 14:53:46,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:46,380 INFO L480 AbstractCegarLoop]: Abstraction has 1321 states and 1563 transitions. [2018-12-02 14:53:46,380 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:53:46,380 INFO L276 IsEmpty]: Start isEmpty. Operand 1321 states and 1563 transitions. [2018-12-02 14:53:46,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-02 14:53:46,381 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:46,381 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:46,381 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:46,381 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:46,381 INFO L82 PathProgramCache]: Analyzing trace with hash 382590265, now seen corresponding path program 1 times [2018-12-02 14:53:46,382 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:46,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:46,382 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:46,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:46,382 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:46,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:46,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:46,407 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:46,407 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:53:46,408 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:46,408 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:53:46,408 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:53:46,408 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:46,408 INFO L87 Difference]: Start difference. First operand 1321 states and 1563 transitions. Second operand 3 states. [2018-12-02 14:53:46,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:46,535 INFO L93 Difference]: Finished difference Result 3779 states and 4530 transitions. [2018-12-02 14:53:46,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:53:46,535 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 105 [2018-12-02 14:53:46,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:46,540 INFO L225 Difference]: With dead ends: 3779 [2018-12-02 14:53:46,540 INFO L226 Difference]: Without dead ends: 2483 [2018-12-02 14:53:46,542 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:46,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2483 states. [2018-12-02 14:53:46,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2483 to 2480. [2018-12-02 14:53:46,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2480 states. [2018-12-02 14:53:46,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2480 states to 2480 states and 2957 transitions. [2018-12-02 14:53:46,641 INFO L78 Accepts]: Start accepts. Automaton has 2480 states and 2957 transitions. Word has length 105 [2018-12-02 14:53:46,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:46,641 INFO L480 AbstractCegarLoop]: Abstraction has 2480 states and 2957 transitions. [2018-12-02 14:53:46,641 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:53:46,641 INFO L276 IsEmpty]: Start isEmpty. Operand 2480 states and 2957 transitions. [2018-12-02 14:53:46,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-12-02 14:53:46,642 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:46,642 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:46,642 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:46,642 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:46,643 INFO L82 PathProgramCache]: Analyzing trace with hash -604850563, now seen corresponding path program 1 times [2018-12-02 14:53:46,643 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:46,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:46,643 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:46,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:46,643 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:46,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:46,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:53:46,664 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:46,664 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:53:46,664 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:46,664 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:53:46,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:53:46,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:46,665 INFO L87 Difference]: Start difference. First operand 2480 states and 2957 transitions. Second operand 3 states. [2018-12-02 14:53:46,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:46,901 INFO L93 Difference]: Finished difference Result 7221 states and 8975 transitions. [2018-12-02 14:53:46,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:53:46,901 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 106 [2018-12-02 14:53:46,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:46,913 INFO L225 Difference]: With dead ends: 7221 [2018-12-02 14:53:46,913 INFO L226 Difference]: Without dead ends: 4772 [2018-12-02 14:53:46,917 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:46,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4772 states. [2018-12-02 14:53:47,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4772 to 4766. [2018-12-02 14:53:47,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4766 states. [2018-12-02 14:53:47,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4766 states to 4766 states and 5802 transitions. [2018-12-02 14:53:47,129 INFO L78 Accepts]: Start accepts. Automaton has 4766 states and 5802 transitions. Word has length 106 [2018-12-02 14:53:47,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:47,130 INFO L480 AbstractCegarLoop]: Abstraction has 4766 states and 5802 transitions. [2018-12-02 14:53:47,130 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:53:47,130 INFO L276 IsEmpty]: Start isEmpty. Operand 4766 states and 5802 transitions. [2018-12-02 14:53:47,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-12-02 14:53:47,131 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:47,131 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:47,132 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:47,132 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:47,132 INFO L82 PathProgramCache]: Analyzing trace with hash 1287801291, now seen corresponding path program 1 times [2018-12-02 14:53:47,132 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:47,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:47,133 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:47,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:47,133 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:47,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:47,152 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 14:53:47,152 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:47,152 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 14:53:47,152 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:47,153 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:53:47,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:53:47,153 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:53:47,153 INFO L87 Difference]: Start difference. First operand 4766 states and 5802 transitions. Second operand 4 states. [2018-12-02 14:53:47,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:47,422 INFO L93 Difference]: Finished difference Result 8489 states and 10299 transitions. [2018-12-02 14:53:47,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:53:47,423 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 127 [2018-12-02 14:53:47,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:47,433 INFO L225 Difference]: With dead ends: 8489 [2018-12-02 14:53:47,433 INFO L226 Difference]: Without dead ends: 3748 [2018-12-02 14:53:47,439 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:53:47,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3748 states. [2018-12-02 14:53:47,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3748 to 3701. [2018-12-02 14:53:47,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3701 states. [2018-12-02 14:53:47,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3701 states to 3701 states and 4480 transitions. [2018-12-02 14:53:47,603 INFO L78 Accepts]: Start accepts. Automaton has 3701 states and 4480 transitions. Word has length 127 [2018-12-02 14:53:47,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:47,603 INFO L480 AbstractCegarLoop]: Abstraction has 3701 states and 4480 transitions. [2018-12-02 14:53:47,603 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:53:47,603 INFO L276 IsEmpty]: Start isEmpty. Operand 3701 states and 4480 transitions. [2018-12-02 14:53:47,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-12-02 14:53:47,604 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:47,604 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:47,604 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:47,605 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:47,605 INFO L82 PathProgramCache]: Analyzing trace with hash -1359803063, now seen corresponding path program 1 times [2018-12-02 14:53:47,605 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:47,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:47,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:47,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:47,605 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:47,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:47,629 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-02 14:53:47,629 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:47,629 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:53:47,629 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:47,629 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:53:47,630 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:53:47,630 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:47,630 INFO L87 Difference]: Start difference. First operand 3701 states and 4480 transitions. Second operand 3 states. [2018-12-02 14:53:48,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:48,015 INFO L93 Difference]: Finished difference Result 10969 states and 13561 transitions. [2018-12-02 14:53:48,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:53:48,016 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2018-12-02 14:53:48,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:48,028 INFO L225 Difference]: With dead ends: 10969 [2018-12-02 14:53:48,028 INFO L226 Difference]: Without dead ends: 5505 [2018-12-02 14:53:48,035 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:48,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5505 states. [2018-12-02 14:53:48,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5505 to 5505. [2018-12-02 14:53:48,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5505 states. [2018-12-02 14:53:48,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5505 states to 5505 states and 6681 transitions. [2018-12-02 14:53:48,258 INFO L78 Accepts]: Start accepts. Automaton has 5505 states and 6681 transitions. Word has length 127 [2018-12-02 14:53:48,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:48,258 INFO L480 AbstractCegarLoop]: Abstraction has 5505 states and 6681 transitions. [2018-12-02 14:53:48,258 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:53:48,258 INFO L276 IsEmpty]: Start isEmpty. Operand 5505 states and 6681 transitions. [2018-12-02 14:53:48,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-12-02 14:53:48,260 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:48,260 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:48,260 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:48,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:48,261 INFO L82 PathProgramCache]: Analyzing trace with hash 591261288, now seen corresponding path program 1 times [2018-12-02 14:53:48,261 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:48,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:48,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:48,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:48,261 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:48,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:48,289 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2018-12-02 14:53:48,289 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:48,289 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:53:48,289 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:48,289 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:53:48,289 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:53:48,290 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:48,290 INFO L87 Difference]: Start difference. First operand 5505 states and 6681 transitions. Second operand 3 states. [2018-12-02 14:53:48,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:48,721 INFO L93 Difference]: Finished difference Result 16191 states and 20284 transitions. [2018-12-02 14:53:48,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:53:48,721 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2018-12-02 14:53:48,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:48,740 INFO L225 Difference]: With dead ends: 16191 [2018-12-02 14:53:48,740 INFO L226 Difference]: Without dead ends: 10711 [2018-12-02 14:53:48,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:48,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10711 states. [2018-12-02 14:53:49,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10711 to 10708. [2018-12-02 14:53:49,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10708 states. [2018-12-02 14:53:49,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10708 states to 10708 states and 13192 transitions. [2018-12-02 14:53:49,188 INFO L78 Accepts]: Start accepts. Automaton has 10708 states and 13192 transitions. Word has length 180 [2018-12-02 14:53:49,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:49,188 INFO L480 AbstractCegarLoop]: Abstraction has 10708 states and 13192 transitions. [2018-12-02 14:53:49,189 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:53:49,189 INFO L276 IsEmpty]: Start isEmpty. Operand 10708 states and 13192 transitions. [2018-12-02 14:53:49,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-12-02 14:53:49,192 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:49,192 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:49,192 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:49,193 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:49,193 INFO L82 PathProgramCache]: Analyzing trace with hash -598185276, now seen corresponding path program 1 times [2018-12-02 14:53:49,193 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:49,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:49,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:49,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:49,193 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:49,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:49,251 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-12-02 14:53:49,251 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:53:49,251 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:53:49,252 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 182 with the following transitions: [2018-12-02 14:53:49,253 INFO L205 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [55], [60], [63], [74], [76], [78], [80], [84], [85], [90], [104], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [245], [248], [251], [253], [255], [257], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [322], [324], [325], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [433], [439], [455], [459], [462], [465], [472], [475], [487], [490], [493], [497], [499], [501], [502], [503], [517], [519], [549], [553], [554], [557], [559], [560], [561], [562], [563], [567], [568], [569], [570], [571], [572], [573], [574], [575], [576], [579], [580], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [619], [620], [621] [2018-12-02 14:53:49,285 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:53:49,285 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:53:49,446 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 14:53:49,447 INFO L272 AbstractInterpreter]: Visited 100 different actions 100 times. Never merged. Never widened. Performed 747 root evaluator evaluations with a maximum evaluation depth of 3. Performed 747 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 46 variables. [2018-12-02 14:53:49,452 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:49,452 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 14:53:49,611 INFO L227 lantSequenceWeakener]: Weakened 108 states. On average, predicates are now at 66.23% of their original sizes. [2018-12-02 14:53:49,611 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 14:53:50,092 INFO L418 sIntCurrentIteration]: We unified 180 AI predicates to 180 [2018-12-02 14:53:50,092 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 14:53:50,093 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:53:50,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [41] imperfect sequences [6] total 45 [2018-12-02 14:53:50,093 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:50,093 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-02 14:53:50,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-02 14:53:50,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=331, Invalid=1309, Unknown=0, NotChecked=0, Total=1640 [2018-12-02 14:53:50,094 INFO L87 Difference]: Start difference. First operand 10708 states and 13192 transitions. Second operand 41 states. [2018-12-02 14:53:54,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:54,764 INFO L93 Difference]: Finished difference Result 21535 states and 26583 transitions. [2018-12-02 14:53:54,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-02 14:53:54,764 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 181 [2018-12-02 14:53:54,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:54,786 INFO L225 Difference]: With dead ends: 21535 [2018-12-02 14:53:54,787 INFO L226 Difference]: Without dead ends: 10843 [2018-12-02 14:53:54,801 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 207 GetRequests, 141 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1103 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=924, Invalid=3632, Unknown=0, NotChecked=0, Total=4556 [2018-12-02 14:53:54,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10843 states. [2018-12-02 14:53:55,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10843 to 10831. [2018-12-02 14:53:55,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10831 states. [2018-12-02 14:53:55,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10831 states to 10831 states and 13338 transitions. [2018-12-02 14:53:55,252 INFO L78 Accepts]: Start accepts. Automaton has 10831 states and 13338 transitions. Word has length 181 [2018-12-02 14:53:55,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:55,252 INFO L480 AbstractCegarLoop]: Abstraction has 10831 states and 13338 transitions. [2018-12-02 14:53:55,252 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-02 14:53:55,252 INFO L276 IsEmpty]: Start isEmpty. Operand 10831 states and 13338 transitions. [2018-12-02 14:53:55,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-12-02 14:53:55,255 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:55,256 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:55,256 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:55,256 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:55,256 INFO L82 PathProgramCache]: Analyzing trace with hash -843736823, now seen corresponding path program 1 times [2018-12-02 14:53:55,256 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:55,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:55,256 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:55,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:55,257 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:55,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:55,284 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2018-12-02 14:53:55,285 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:53:55,285 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:53:55,285 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:55,285 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:53:55,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:53:55,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:55,285 INFO L87 Difference]: Start difference. First operand 10831 states and 13338 transitions. Second operand 3 states. [2018-12-02 14:53:55,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:53:55,972 INFO L93 Difference]: Finished difference Result 26224 states and 34028 transitions. [2018-12-02 14:53:55,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:53:55,972 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 182 [2018-12-02 14:53:55,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:53:56,003 INFO L225 Difference]: With dead ends: 26224 [2018-12-02 14:53:56,003 INFO L226 Difference]: Without dead ends: 15549 [2018-12-02 14:53:56,023 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:53:56,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15549 states. [2018-12-02 14:53:56,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15549 to 15540. [2018-12-02 14:53:56,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15540 states. [2018-12-02 14:53:56,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15540 states to 15540 states and 19796 transitions. [2018-12-02 14:53:56,783 INFO L78 Accepts]: Start accepts. Automaton has 15540 states and 19796 transitions. Word has length 182 [2018-12-02 14:53:56,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:53:56,783 INFO L480 AbstractCegarLoop]: Abstraction has 15540 states and 19796 transitions. [2018-12-02 14:53:56,783 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:53:56,783 INFO L276 IsEmpty]: Start isEmpty. Operand 15540 states and 19796 transitions. [2018-12-02 14:53:56,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2018-12-02 14:53:56,787 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:53:56,787 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:53:56,787 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:53:56,787 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:56,787 INFO L82 PathProgramCache]: Analyzing trace with hash 1569340676, now seen corresponding path program 1 times [2018-12-02 14:53:56,787 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:53:56,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:56,788 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:53:56,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:53:56,788 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:53:56,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:53:56,856 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-12-02 14:53:56,856 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:53:56,857 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:53:56,857 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 184 with the following transitions: [2018-12-02 14:53:56,857 INFO L205 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [55], [60], [63], [74], [76], [78], [80], [84], [85], [90], [104], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [245], [248], [251], [253], [255], [257], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [322], [324], [325], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [433], [439], [446], [452], [459], [462], [465], [472], [475], [487], [490], [493], [497], [499], [501], [502], [503], [517], [519], [549], [553], [554], [557], [559], [560], [561], [562], [563], [567], [568], [569], [570], [571], [572], [573], [574], [575], [576], [579], [580], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [619], [620], [621] [2018-12-02 14:53:56,860 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:53:56,860 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:53:56,927 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 14:53:56,927 INFO L272 AbstractInterpreter]: Visited 115 different actions 134 times. Merged at 12 different actions 12 times. Never widened. Performed 1281 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1281 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 48 variables. [2018-12-02 14:53:56,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:53:56,929 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 14:53:57,054 INFO L227 lantSequenceWeakener]: Weakened 128 states. On average, predicates are now at 69.51% of their original sizes. [2018-12-02 14:53:57,054 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 14:53:57,610 INFO L418 sIntCurrentIteration]: We unified 182 AI predicates to 182 [2018-12-02 14:53:57,610 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 14:53:57,610 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:53:57,610 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [49] imperfect sequences [6] total 53 [2018-12-02 14:53:57,610 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:53:57,611 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-02 14:53:57,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-02 14:53:57,611 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=579, Invalid=1773, Unknown=0, NotChecked=0, Total=2352 [2018-12-02 14:53:57,612 INFO L87 Difference]: Start difference. First operand 15540 states and 19796 transitions. Second operand 49 states. [2018-12-02 14:54:03,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:54:03,734 INFO L93 Difference]: Finished difference Result 34913 states and 45018 transitions. [2018-12-02 14:54:03,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-12-02 14:54:03,734 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 183 [2018-12-02 14:54:03,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:54:03,787 INFO L225 Difference]: With dead ends: 34913 [2018-12-02 14:54:03,787 INFO L226 Difference]: Without dead ends: 19529 [2018-12-02 14:54:03,823 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 219 GetRequests, 135 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2302 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1711, Invalid=5599, Unknown=0, NotChecked=0, Total=7310 [2018-12-02 14:54:03,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19529 states. [2018-12-02 14:54:04,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19529 to 19492. [2018-12-02 14:54:04,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19492 states. [2018-12-02 14:54:04,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19492 states to 19492 states and 24747 transitions. [2018-12-02 14:54:04,970 INFO L78 Accepts]: Start accepts. Automaton has 19492 states and 24747 transitions. Word has length 183 [2018-12-02 14:54:04,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:54:04,971 INFO L480 AbstractCegarLoop]: Abstraction has 19492 states and 24747 transitions. [2018-12-02 14:54:04,971 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-02 14:54:04,971 INFO L276 IsEmpty]: Start isEmpty. Operand 19492 states and 24747 transitions. [2018-12-02 14:54:04,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 190 [2018-12-02 14:54:04,978 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:54:04,978 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:54:04,979 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:54:04,979 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:04,979 INFO L82 PathProgramCache]: Analyzing trace with hash -189185009, now seen corresponding path program 1 times [2018-12-02 14:54:04,979 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:54:04,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:04,979 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:54:04,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:04,980 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:54:04,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:54:05,032 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-12-02 14:54:05,032 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:54:05,032 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:54:05,032 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 190 with the following transitions: [2018-12-02 14:54:05,033 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [55], [60], [63], [74], [76], [78], [80], [84], [85], [90], [104], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [245], [248], [251], [253], [255], [257], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [322], [324], [325], [328], [333], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [433], [439], [446], [449], [455], [459], [462], [465], [472], [475], [487], [490], [493], [497], [499], [501], [502], [503], [517], [519], [549], [553], [554], [557], [559], [560], [561], [562], [563], [567], [568], [569], [570], [571], [572], [573], [574], [575], [576], [579], [580], [583], [584], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [619], [620], [621] [2018-12-02 14:54:05,036 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:54:05,036 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:54:05,077 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 14:54:05,077 INFO L272 AbstractInterpreter]: Visited 123 different actions 142 times. Merged at 11 different actions 11 times. Never widened. Performed 1321 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1321 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 48 variables. [2018-12-02 14:54:05,078 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:05,078 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 14:54:05,158 INFO L227 lantSequenceWeakener]: Weakened 133 states. On average, predicates are now at 68.94% of their original sizes. [2018-12-02 14:54:05,158 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 14:54:05,784 INFO L418 sIntCurrentIteration]: We unified 188 AI predicates to 188 [2018-12-02 14:54:05,784 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 14:54:05,784 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:54:05,784 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [52] imperfect sequences [6] total 56 [2018-12-02 14:54:05,784 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:54:05,784 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-12-02 14:54:05,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-12-02 14:54:05,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=482, Invalid=2170, Unknown=0, NotChecked=0, Total=2652 [2018-12-02 14:54:05,785 INFO L87 Difference]: Start difference. First operand 19492 states and 24747 transitions. Second operand 52 states. [2018-12-02 14:54:12,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:54:12,084 INFO L93 Difference]: Finished difference Result 33863 states and 43013 transitions. [2018-12-02 14:54:12,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-12-02 14:54:12,084 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 189 [2018-12-02 14:54:12,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:54:12,125 INFO L225 Difference]: With dead ends: 33863 [2018-12-02 14:54:12,125 INFO L226 Difference]: Without dead ends: 19778 [2018-12-02 14:54:12,147 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 226 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2326 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1352, Invalid=6658, Unknown=0, NotChecked=0, Total=8010 [2018-12-02 14:54:12,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19778 states. [2018-12-02 14:54:13,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19778 to 19730. [2018-12-02 14:54:13,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19730 states. [2018-12-02 14:54:13,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19730 states to 19730 states and 25057 transitions. [2018-12-02 14:54:13,141 INFO L78 Accepts]: Start accepts. Automaton has 19730 states and 25057 transitions. Word has length 189 [2018-12-02 14:54:13,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:54:13,141 INFO L480 AbstractCegarLoop]: Abstraction has 19730 states and 25057 transitions. [2018-12-02 14:54:13,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-12-02 14:54:13,141 INFO L276 IsEmpty]: Start isEmpty. Operand 19730 states and 25057 transitions. [2018-12-02 14:54:13,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-12-02 14:54:13,146 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:54:13,146 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:54:13,146 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:54:13,146 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:13,146 INFO L82 PathProgramCache]: Analyzing trace with hash 1691178036, now seen corresponding path program 1 times [2018-12-02 14:54:13,146 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:54:13,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:13,147 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:54:13,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:13,147 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:54:13,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:54:13,203 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-12-02 14:54:13,204 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:54:13,204 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:54:13,204 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 191 with the following transitions: [2018-12-02 14:54:13,204 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [55], [60], [63], [74], [76], [78], [80], [84], [85], [90], [104], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [245], [248], [251], [253], [255], [257], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [322], [324], [325], [328], [333], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [433], [439], [446], [449], [452], [459], [462], [465], [472], [475], [487], [490], [493], [497], [499], [501], [502], [503], [517], [519], [549], [553], [554], [557], [559], [560], [561], [562], [563], [567], [568], [569], [570], [571], [572], [573], [574], [575], [576], [579], [580], [583], [584], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [619], [620], [621] [2018-12-02 14:54:13,205 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:54:13,206 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:54:13,279 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 14:54:13,279 INFO L272 AbstractInterpreter]: Visited 126 different actions 228 times. Merged at 16 different actions 42 times. Never widened. Performed 3056 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3056 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 2 different actions. Largest state had 48 variables. [2018-12-02 14:54:13,285 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:13,286 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 14:54:13,286 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:54:13,286 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:54:13,293 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:54:13,293 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 14:54:13,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:54:13,366 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:54:13,388 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 14:54:13,389 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 14:54:13,599 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-12-02 14:54:13,615 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:54:13,616 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 7 [2018-12-02 14:54:13,616 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:54:13,616 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:54:13,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:54:13,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:54:13,616 INFO L87 Difference]: Start difference. First operand 19730 states and 25057 transitions. Second operand 3 states. [2018-12-02 14:54:15,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:54:15,268 INFO L93 Difference]: Finished difference Result 55028 states and 76610 transitions. [2018-12-02 14:54:15,268 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:54:15,268 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 190 [2018-12-02 14:54:15,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:54:15,349 INFO L225 Difference]: With dead ends: 55028 [2018-12-02 14:54:15,349 INFO L226 Difference]: Without dead ends: 35854 [2018-12-02 14:54:15,409 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 377 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:54:15,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35854 states. [2018-12-02 14:54:17,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35854 to 35789. [2018-12-02 14:54:17,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35789 states. [2018-12-02 14:54:17,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35789 states to 35789 states and 46868 transitions. [2018-12-02 14:54:17,285 INFO L78 Accepts]: Start accepts. Automaton has 35789 states and 46868 transitions. Word has length 190 [2018-12-02 14:54:17,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:54:17,286 INFO L480 AbstractCegarLoop]: Abstraction has 35789 states and 46868 transitions. [2018-12-02 14:54:17,286 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:54:17,286 INFO L276 IsEmpty]: Start isEmpty. Operand 35789 states and 46868 transitions. [2018-12-02 14:54:17,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-12-02 14:54:17,292 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:54:17,292 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:54:17,292 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:54:17,292 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:17,292 INFO L82 PathProgramCache]: Analyzing trace with hash 1574011971, now seen corresponding path program 1 times [2018-12-02 14:54:17,292 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:54:17,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:17,293 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:54:17,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:17,293 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:54:17,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:54:17,347 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-12-02 14:54:17,347 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:54:17,347 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:54:17,347 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 192 with the following transitions: [2018-12-02 14:54:17,348 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [55], [60], [63], [74], [76], [78], [80], [84], [85], [90], [104], [107], [112], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [245], [248], [251], [253], [255], [257], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [322], [324], [325], [328], [333], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [433], [439], [446], [449], [452], [459], [462], [465], [472], [475], [487], [490], [493], [497], [499], [501], [502], [503], [517], [519], [549], [553], [554], [557], [559], [560], [561], [562], [563], [567], [568], [569], [570], [571], [572], [573], [574], [575], [576], [579], [580], [583], [584], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [619], [620], [621] [2018-12-02 14:54:17,349 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:54:17,350 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:54:17,401 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 14:54:17,401 INFO L272 AbstractInterpreter]: Visited 127 different actions 195 times. Merged at 16 different actions 30 times. Never widened. Performed 2231 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2231 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 3 different actions. Largest state had 48 variables. [2018-12-02 14:54:17,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:17,403 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 14:54:17,403 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:54:17,403 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:54:17,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:54:17,410 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 14:54:17,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:54:17,475 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:54:17,524 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 38 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 14:54:17,524 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 14:54:17,608 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-02 14:54:17,624 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:54:17,624 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2018-12-02 14:54:17,624 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:54:17,625 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:54:17,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:54:17,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-02 14:54:17,625 INFO L87 Difference]: Start difference. First operand 35789 states and 46868 transitions. Second operand 5 states. [2018-12-02 14:54:19,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:54:19,810 INFO L93 Difference]: Finished difference Result 52737 states and 70127 transitions. [2018-12-02 14:54:19,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:54:19,811 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 191 [2018-12-02 14:54:19,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:54:19,893 INFO L225 Difference]: With dead ends: 52737 [2018-12-02 14:54:19,893 INFO L226 Difference]: Without dead ends: 36012 [2018-12-02 14:54:19,934 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 387 GetRequests, 375 SyntacticMatches, 5 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-02 14:54:19,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36012 states. [2018-12-02 14:54:21,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36012 to 35861. [2018-12-02 14:54:21,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35861 states. [2018-12-02 14:54:21,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35861 states to 35861 states and 45719 transitions. [2018-12-02 14:54:21,895 INFO L78 Accepts]: Start accepts. Automaton has 35861 states and 45719 transitions. Word has length 191 [2018-12-02 14:54:21,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:54:21,896 INFO L480 AbstractCegarLoop]: Abstraction has 35861 states and 45719 transitions. [2018-12-02 14:54:21,896 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:54:21,896 INFO L276 IsEmpty]: Start isEmpty. Operand 35861 states and 45719 transitions. [2018-12-02 14:54:21,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 252 [2018-12-02 14:54:21,905 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:54:21,905 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:54:21,905 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:54:21,905 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:21,905 INFO L82 PathProgramCache]: Analyzing trace with hash -1950754852, now seen corresponding path program 1 times [2018-12-02 14:54:21,905 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:54:21,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:21,906 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:54:21,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:21,906 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:54:21,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:54:21,973 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 16 proven. 7 refuted. 0 times theorem prover too weak. 127 trivial. 0 not checked. [2018-12-02 14:54:21,973 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:54:21,973 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:54:21,973 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 252 with the following transitions: [2018-12-02 14:54:21,973 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [55], [58], [60], [63], [74], [76], [78], [80], [84], [85], [90], [104], [107], [110], [112], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [243], [245], [248], [251], [253], [255], [257], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [322], [324], [325], [328], [333], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [433], [439], [446], [449], [459], [462], [472], [475], [487], [490], [493], [495], [497], [499], [501], [502], [503], [517], [519], [549], [553], [554], [555], [556], [557], [559], [560], [561], [562], [563], [567], [568], [569], [570], [571], [572], [573], [574], [575], [576], [579], [580], [583], [584], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [619], [620], [621] [2018-12-02 14:54:21,974 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:54:21,974 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:54:22,002 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 14:54:22,002 INFO L272 AbstractInterpreter]: Visited 129 different actions 141 times. Merged at 7 different actions 7 times. Never widened. Performed 1131 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1131 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 48 variables. [2018-12-02 14:54:22,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:22,004 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 14:54:22,082 INFO L227 lantSequenceWeakener]: Weakened 150 states. On average, predicates are now at 70.15% of their original sizes. [2018-12-02 14:54:22,082 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 14:54:22,735 INFO L418 sIntCurrentIteration]: We unified 250 AI predicates to 250 [2018-12-02 14:54:22,735 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 14:54:22,735 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:54:22,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [55] imperfect sequences [4] total 57 [2018-12-02 14:54:22,736 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:54:22,736 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-12-02 14:54:22,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-12-02 14:54:22,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=511, Invalid=2459, Unknown=0, NotChecked=0, Total=2970 [2018-12-02 14:54:22,737 INFO L87 Difference]: Start difference. First operand 35861 states and 45719 transitions. Second operand 55 states. [2018-12-02 14:54:32,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:54:32,737 INFO L93 Difference]: Finished difference Result 60702 states and 77557 transitions. [2018-12-02 14:54:32,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-02 14:54:32,737 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 251 [2018-12-02 14:54:32,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:54:32,806 INFO L225 Difference]: With dead ends: 60702 [2018-12-02 14:54:32,806 INFO L226 Difference]: Without dead ends: 36083 [2018-12-02 14:54:32,845 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 286 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2392 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1310, Invalid=6880, Unknown=0, NotChecked=0, Total=8190 [2018-12-02 14:54:32,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36083 states. [2018-12-02 14:54:34,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36083 to 36010. [2018-12-02 14:54:34,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36010 states. [2018-12-02 14:54:34,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36010 states to 36010 states and 45915 transitions. [2018-12-02 14:54:34,879 INFO L78 Accepts]: Start accepts. Automaton has 36010 states and 45915 transitions. Word has length 251 [2018-12-02 14:54:34,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:54:34,879 INFO L480 AbstractCegarLoop]: Abstraction has 36010 states and 45915 transitions. [2018-12-02 14:54:34,879 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-12-02 14:54:34,879 INFO L276 IsEmpty]: Start isEmpty. Operand 36010 states and 45915 transitions. [2018-12-02 14:54:34,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 241 [2018-12-02 14:54:34,889 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:54:34,890 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:54:34,890 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:54:34,890 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:34,890 INFO L82 PathProgramCache]: Analyzing trace with hash -283785201, now seen corresponding path program 1 times [2018-12-02 14:54:34,890 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:54:34,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:34,891 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:54:34,891 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:54:34,891 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:54:34,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:54:34,941 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 20 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-12-02 14:54:34,942 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:54:34,942 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:54:34,942 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 241 with the following transitions: [2018-12-02 14:54:34,942 INFO L205 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [55], [58], [74], [76], [84], [85], [90], [93], [95], [98], [102], [103], [104], [107], [112], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [158], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [245], [248], [251], [253], [255], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [320], [322], [324], [325], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [429], [433], [439], [446], [452], [459], [462], [468], [472], [475], [486], [487], [490], [493], [497], [499], [501], [502], [503], [517], [519], [521], [523], [528], [536], [539], [544], [549], [553], [554], [557], [561], [562], [563], [565], [566], [567], [568], [569], [570], [571], [572], [573], [574], [579], [580], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [600], [601], [602], [603], [604], [605], [606], [607], [608], [609], [610], [617], [618], [619], [620], [621] [2018-12-02 14:54:34,943 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:54:34,943 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:54:34,971 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 14:54:34,971 INFO L272 AbstractInterpreter]: Visited 123 different actions 140 times. Merged at 10 different actions 10 times. Never widened. Performed 1129 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1129 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 48 variables. [2018-12-02 14:54:34,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:54:34,973 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 14:54:35,054 INFO L227 lantSequenceWeakener]: Weakened 144 states. On average, predicates are now at 65.5% of their original sizes. [2018-12-02 14:54:35,054 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 14:54:35,712 INFO L418 sIntCurrentIteration]: We unified 239 AI predicates to 239 [2018-12-02 14:54:35,712 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 14:54:35,712 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:54:35,712 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [51] imperfect sequences [8] total 57 [2018-12-02 14:54:35,712 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:54:35,712 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-12-02 14:54:35,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-12-02 14:54:35,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=398, Invalid=2152, Unknown=0, NotChecked=0, Total=2550 [2018-12-02 14:54:35,713 INFO L87 Difference]: Start difference. First operand 36010 states and 45915 transitions. Second operand 51 states. [2018-12-02 14:55:05,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:55:05,214 INFO L93 Difference]: Finished difference Result 67548 states and 87326 transitions. [2018-12-02 14:55:05,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-12-02 14:55:05,214 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 240 [2018-12-02 14:55:05,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:55:05,289 INFO L225 Difference]: With dead ends: 67548 [2018-12-02 14:55:05,289 INFO L226 Difference]: Without dead ends: 36408 [2018-12-02 14:55:05,337 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 282 GetRequests, 190 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2771 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1360, Invalid=7382, Unknown=0, NotChecked=0, Total=8742 [2018-12-02 14:55:05,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36408 states. [2018-12-02 14:55:07,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36408 to 36070. [2018-12-02 14:55:07,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36070 states. [2018-12-02 14:55:07,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36070 states to 36070 states and 46068 transitions. [2018-12-02 14:55:07,343 INFO L78 Accepts]: Start accepts. Automaton has 36070 states and 46068 transitions. Word has length 240 [2018-12-02 14:55:07,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:55:07,343 INFO L480 AbstractCegarLoop]: Abstraction has 36070 states and 46068 transitions. [2018-12-02 14:55:07,343 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-12-02 14:55:07,343 INFO L276 IsEmpty]: Start isEmpty. Operand 36070 states and 46068 transitions. [2018-12-02 14:55:07,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-12-02 14:55:07,353 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:55:07,353 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:55:07,353 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:55:07,354 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:55:07,354 INFO L82 PathProgramCache]: Analyzing trace with hash 730108723, now seen corresponding path program 1 times [2018-12-02 14:55:07,354 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:55:07,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:07,354 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:55:07,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:07,354 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:55:07,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:55:07,402 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 26 proven. 17 refuted. 0 times theorem prover too weak. 137 trivial. 0 not checked. [2018-12-02 14:55:07,402 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:55:07,402 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:55:07,403 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 267 with the following transitions: [2018-12-02 14:55:07,403 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [55], [58], [60], [63], [74], [76], [78], [80], [84], [85], [90], [104], [107], [110], [112], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [243], [245], [248], [251], [253], [255], [257], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [322], [324], [325], [328], [333], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [433], [439], [446], [449], [455], [459], [462], [465], [472], [475], [481], [487], [490], [493], [495], [497], [499], [501], [502], [503], [517], [519], [549], [553], [554], [555], [556], [557], [559], [560], [561], [562], [563], [567], [568], [569], [570], [571], [572], [573], [574], [575], [576], [579], [580], [583], [584], [585], [586], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [619], [620], [621] [2018-12-02 14:55:07,404 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:55:07,404 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:55:07,481 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 14:55:07,481 INFO L272 AbstractInterpreter]: Visited 153 different actions 380 times. Merged at 34 different actions 55 times. Never widened. Performed 3108 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3108 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 18 fixpoints after 12 different actions. Largest state had 48 variables. [2018-12-02 14:55:07,482 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:55:07,482 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 14:55:07,483 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:55:07,483 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:55:07,489 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:55:07,490 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 14:55:07,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:55:07,561 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:55:07,589 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 122 proven. 0 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-12-02 14:55:07,589 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 14:55:07,694 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 26 proven. 7 refuted. 0 times theorem prover too weak. 147 trivial. 0 not checked. [2018-12-02 14:55:07,709 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:55:07,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5, 4] total 8 [2018-12-02 14:55:07,709 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:55:07,709 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:55:07,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:55:07,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-12-02 14:55:07,710 INFO L87 Difference]: Start difference. First operand 36070 states and 46068 transitions. Second operand 4 states. [2018-12-02 14:55:09,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:55:09,488 INFO L93 Difference]: Finished difference Result 56860 states and 73769 transitions. [2018-12-02 14:55:09,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:55:09,489 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 266 [2018-12-02 14:55:09,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:55:09,549 INFO L225 Difference]: With dead ends: 56860 [2018-12-02 14:55:09,549 INFO L226 Difference]: Without dead ends: 28756 [2018-12-02 14:55:09,607 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 539 GetRequests, 532 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-12-02 14:55:09,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28756 states. [2018-12-02 14:55:11,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28756 to 28605. [2018-12-02 14:55:11,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28605 states. [2018-12-02 14:55:11,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28605 states to 28605 states and 34521 transitions. [2018-12-02 14:55:11,200 INFO L78 Accepts]: Start accepts. Automaton has 28605 states and 34521 transitions. Word has length 266 [2018-12-02 14:55:11,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:55:11,200 INFO L480 AbstractCegarLoop]: Abstraction has 28605 states and 34521 transitions. [2018-12-02 14:55:11,200 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:55:11,200 INFO L276 IsEmpty]: Start isEmpty. Operand 28605 states and 34521 transitions. [2018-12-02 14:55:11,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-12-02 14:55:11,209 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:55:11,209 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:55:11,209 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:55:11,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:55:11,209 INFO L82 PathProgramCache]: Analyzing trace with hash -2035922887, now seen corresponding path program 1 times [2018-12-02 14:55:11,209 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:55:11,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:11,210 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:55:11,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:11,210 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:55:11,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:55:11,264 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 138 trivial. 0 not checked. [2018-12-02 14:55:11,264 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:55:11,264 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 14:55:11,264 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:55:11,264 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:55:11,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:55:11,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:55:11,265 INFO L87 Difference]: Start difference. First operand 28605 states and 34521 transitions. Second operand 4 states. [2018-12-02 14:55:12,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:55:12,693 INFO L93 Difference]: Finished difference Result 30666 states and 37430 transitions. [2018-12-02 14:55:12,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 14:55:12,693 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 254 [2018-12-02 14:55:12,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:55:12,733 INFO L225 Difference]: With dead ends: 30666 [2018-12-02 14:55:12,733 INFO L226 Difference]: Without dead ends: 23268 [2018-12-02 14:55:12,748 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:55:12,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23268 states. [2018-12-02 14:55:14,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23268 to 23081. [2018-12-02 14:55:14,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23081 states. [2018-12-02 14:55:14,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23081 states to 23081 states and 27859 transitions. [2018-12-02 14:55:14,043 INFO L78 Accepts]: Start accepts. Automaton has 23081 states and 27859 transitions. Word has length 254 [2018-12-02 14:55:14,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:55:14,043 INFO L480 AbstractCegarLoop]: Abstraction has 23081 states and 27859 transitions. [2018-12-02 14:55:14,043 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:55:14,043 INFO L276 IsEmpty]: Start isEmpty. Operand 23081 states and 27859 transitions. [2018-12-02 14:55:14,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 257 [2018-12-02 14:55:14,050 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:55:14,050 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:55:14,050 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:55:14,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:55:14,051 INFO L82 PathProgramCache]: Analyzing trace with hash 2061609197, now seen corresponding path program 1 times [2018-12-02 14:55:14,051 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:55:14,051 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:14,051 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:55:14,051 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:14,051 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:55:14,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:55:14,152 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 36 proven. 25 refuted. 0 times theorem prover too weak. 122 trivial. 0 not checked. [2018-12-02 14:55:14,152 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:55:14,152 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 14:55:14,153 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 257 with the following transitions: [2018-12-02 14:55:14,153 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [55], [85], [90], [93], [95], [98], [102], [103], [104], [114], [116], [118], [119], [124], [130], [136], [142], [148], [154], [158], [160], [162], [163], [173], [175], [177], [178], [222], [224], [229], [232], [237], [240], [245], [248], [251], [253], [255], [258], [261], [280], [281], [286], [292], [298], [304], [310], [316], [320], [322], [324], [325], [328], [333], [335], [337], [339], [340], [343], [349], [355], [361], [365], [410], [411], [412], [421], [424], [427], [429], [433], [439], [446], [449], [452], [455], [459], [465], [472], [475], [481], [486], [487], [490], [493], [497], [499], [501], [502], [503], [517], [519], [521], [523], [528], [536], [539], [544], [549], [553], [554], [557], [561], [562], [563], [565], [566], [567], [568], [569], [570], [571], [572], [573], [574], [579], [580], [583], [584], [587], [588], [589], [590], [591], [592], [593], [594], [595], [596], [597], [598], [599], [600], [601], [602], [603], [604], [605], [606], [607], [608], [609], [610], [617], [618], [619], [620], [621] [2018-12-02 14:55:14,154 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 14:55:14,154 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 14:55:14,220 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 14:55:14,220 INFO L272 AbstractInterpreter]: Visited 128 different actions 233 times. Merged at 17 different actions 42 times. Never widened. Performed 2381 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2381 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 9 fixpoints after 5 different actions. Largest state had 48 variables. [2018-12-02 14:55:14,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:55:14,222 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 14:55:14,222 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:55:14,222 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:55:14,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:55:14,228 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 14:55:14,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:55:14,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:55:14,330 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 144 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2018-12-02 14:55:14,330 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 14:55:14,435 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-12-02 14:55:14,450 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:55:14,451 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8, 6] total 12 [2018-12-02 14:55:14,451 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 14:55:14,451 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 14:55:14,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 14:55:14,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-12-02 14:55:14,451 INFO L87 Difference]: Start difference. First operand 23081 states and 27859 transitions. Second operand 6 states. [2018-12-02 14:55:14,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:55:14,848 INFO L93 Difference]: Finished difference Result 26968 states and 32137 transitions. [2018-12-02 14:55:14,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 14:55:14,848 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 256 [2018-12-02 14:55:14,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:55:14,856 INFO L225 Difference]: With dead ends: 26968 [2018-12-02 14:55:14,857 INFO L226 Difference]: Without dead ends: 4438 [2018-12-02 14:55:14,878 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 524 GetRequests, 506 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2018-12-02 14:55:14,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4438 states. [2018-12-02 14:55:15,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4438 to 4319. [2018-12-02 14:55:15,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4319 states. [2018-12-02 14:55:15,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4319 states to 4319 states and 4760 transitions. [2018-12-02 14:55:15,127 INFO L78 Accepts]: Start accepts. Automaton has 4319 states and 4760 transitions. Word has length 256 [2018-12-02 14:55:15,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:55:15,128 INFO L480 AbstractCegarLoop]: Abstraction has 4319 states and 4760 transitions. [2018-12-02 14:55:15,128 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 14:55:15,128 INFO L276 IsEmpty]: Start isEmpty. Operand 4319 states and 4760 transitions. [2018-12-02 14:55:15,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 323 [2018-12-02 14:55:15,130 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:55:15,130 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:55:15,130 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 14:55:15,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:55:15,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1737144915, now seen corresponding path program 1 times [2018-12-02 14:55:15,131 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 14:55:15,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:15,131 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:55:15,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:55:15,131 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 14:55:15,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 14:55:15,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 14:55:15,213 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 14:55:15,314 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 02:55:15 BoogieIcfgContainer [2018-12-02 14:55:15,314 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 14:55:15,315 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 14:55:15,315 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 14:55:15,315 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 14:55:15,315 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 02:53:40" (3/4) ... [2018-12-02 14:55:15,317 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-02 14:55:15,410 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_f40e1a6a-775c-4de5-b374-ab76ab05f8ea/bin-2019/utaipan/witness.graphml [2018-12-02 14:55:15,410 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 14:55:15,410 INFO L168 Benchmark]: Toolchain (without parser) took 95254.68 ms. Allocated memory was 1.0 GB in the beginning and 4.6 GB in the end (delta: 3.5 GB). Free memory was 957.8 MB in the beginning and 2.9 GB in the end (delta: -1.9 GB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2018-12-02 14:55:15,411 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 14:55:15,411 INFO L168 Benchmark]: CACSL2BoogieTranslator took 169.22 ms. Allocated memory is still 1.0 GB. Free memory was 957.8 MB in the beginning and 941.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-02 14:55:15,411 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.44 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 127.9 MB). Free memory was 941.7 MB in the beginning and 1.1 GB in the end (delta: -177.7 MB). Peak memory consumption was 13.1 MB. Max. memory is 11.5 GB. [2018-12-02 14:55:15,412 INFO L168 Benchmark]: Boogie Preprocessor took 23.89 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 14:55:15,412 INFO L168 Benchmark]: RCFGBuilder took 348.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 42.6 MB). Peak memory consumption was 42.6 MB. Max. memory is 11.5 GB. [2018-12-02 14:55:15,412 INFO L168 Benchmark]: TraceAbstraction took 94565.41 ms. Allocated memory was 1.2 GB in the beginning and 4.6 GB in the end (delta: 3.4 GB). Free memory was 1.1 GB in the beginning and 2.9 GB in the end (delta: -1.9 GB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-12-02 14:55:15,412 INFO L168 Benchmark]: Witness Printer took 95.33 ms. Allocated memory is still 4.6 GB. Free memory was 2.9 GB in the beginning and 2.9 GB in the end (delta: 71.3 MB). Peak memory consumption was 71.3 MB. Max. memory is 11.5 GB. [2018-12-02 14:55:15,413 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 169.22 ms. Allocated memory is still 1.0 GB. Free memory was 957.8 MB in the beginning and 941.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 49.44 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 127.9 MB). Free memory was 941.7 MB in the beginning and 1.1 GB in the end (delta: -177.7 MB). Peak memory consumption was 13.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 23.89 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 348.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 42.6 MB). Peak memory consumption was 42.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 94565.41 ms. Allocated memory was 1.2 GB in the beginning and 4.6 GB in the end (delta: 3.4 GB). Free memory was 1.1 GB in the beginning and 2.9 GB in the end (delta: -1.9 GB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. * Witness Printer took 95.33 ms. Allocated memory is still 4.6 GB. Free memory was 2.9 GB in the beginning and 2.9 GB in the end (delta: 71.3 MB). Peak memory consumption was 71.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [\old(E_1)=18, \old(E_2)=5, \old(E_3)=21, \old(M_E)=15, \old(m_i)=7, \old(m_pc)=13, \old(m_st)=14, \old(T1_E)=3, \old(t1_i)=17, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=16, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=11, \old(T3_E)=19, \old(t3_i)=20, \old(t3_pc)=8, \old(t3_st)=12, E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L691] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L691] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L692] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L635] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L636] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L636] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L637] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L637] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L638] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L638] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L639] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L639] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L646] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L327] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L361] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L361] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND FALSE !(\read(tmp_ndt_3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0, tmp_ndt_4=1] [L389] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L389] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0, tmp_ndt_4=1] [L331] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0, tmp_ndt_4=1] [L334] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0, tmp_ndt_4=1] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0, tmp_ndt_4=1] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0, tmp_ndt_4=1] [L355] COND FALSE !(t1_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=0, tmp_ndt_4=1] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L375] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L130] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L375] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L383] COND FALSE !(t3_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L331] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L334] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L347] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L58] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L538] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1, tmp___1=0] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1, tmp___1=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L538] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L58] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L347] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L361] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L104] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L538] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=1] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=1] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L538] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L104] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L361] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L375] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L139] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L538] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=0] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L538] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L139] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L375] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L389] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L173] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 25 procedures, 199 locations, 1 error locations. UNSAFE Result, 94.5s OverallTime, 35 OverallIterations, 6 TraceHistogramMax, 71.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 10338 SDtfs, 15523 SDslu, 28895 SDs, 0 SdLazy, 19436 SolverSat, 4393 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 12.9s Time, PredicateUnifierStatistics: 10 DeclaredPredicates, 3254 GetRequests, 2666 SyntacticMatches, 50 SemanticMatches, 538 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10969 ImplicationChecksByTransitivity, 6.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=36070occurred in iteration=31, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.6s AbstIntTime, 9 AbstIntIterations, 5 AbstIntStrong, 0.9922030111710279 AbsIntWeakeningRatio, 0.5803657362848893 AbsIntAvgWeakeningVarsNumRemoved, 13.057747834456208 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 16.0s AutomataMinimizationTime, 34 MinimizatonAttempts, 1967 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 6143 NumberOfCodeBlocks, 6143 NumberOfCodeBlocksAsserted, 39 NumberOfCheckSat, 6682 ConstructedInterpolants, 0 QuantifiedInterpolants, 1665654 SizeOfPredicates, 7 NumberOfNonLiveVariables, 3924 ConjunctsInSsa, 22 ConjunctsInUnsatCore, 42 InterpolantComputations, 30 PerfectInterpolantSequences, 2030/2208 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...