./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 04:46:55,327 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 04:46:55,328 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 04:46:55,337 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 04:46:55,337 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 04:46:55,337 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 04:46:55,338 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 04:46:55,339 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 04:46:55,340 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 04:46:55,340 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 04:46:55,341 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 04:46:55,341 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 04:46:55,342 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 04:46:55,342 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 04:46:55,343 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 04:46:55,344 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 04:46:55,345 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 04:46:55,346 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 04:46:55,347 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 04:46:55,348 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 04:46:55,349 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 04:46:55,349 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 04:46:55,351 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 04:46:55,351 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 04:46:55,351 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 04:46:55,352 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 04:46:55,352 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 04:46:55,353 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 04:46:55,353 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 04:46:55,354 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 04:46:55,354 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 04:46:55,355 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 04:46:55,355 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 04:46:55,355 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 04:46:55,356 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 04:46:55,356 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 04:46:55,356 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-12-02 04:46:55,365 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 04:46:55,366 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 04:46:55,366 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 04:46:55,366 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 04:46:55,367 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-02 04:46:55,367 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-02 04:46:55,367 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-02 04:46:55,367 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-02 04:46:55,367 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-02 04:46:55,367 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-02 04:46:55,367 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-02 04:46:55,368 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-02 04:46:55,368 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-02 04:46:55,368 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 04:46:55,368 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-02 04:46:55,369 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 04:46:55,369 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-02 04:46:55,369 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 04:46:55,369 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-02 04:46:55,369 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 04:46:55,369 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-02 04:46:55,369 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-02 04:46:55,370 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-02 04:46:55,370 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-02 04:46:55,370 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 04:46:55,370 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 04:46:55,370 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 04:46:55,370 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 04:46:55,370 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:46:55,371 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 04:46:55,371 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 04:46:55,371 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-02 04:46:55,371 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-02 04:46:55,371 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 04:46:55,371 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 04:46:55,371 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-02 04:46:55,371 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2018-12-02 04:46:55,395 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 04:46:55,404 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 04:46:55,406 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 04:46:55,408 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 04:46:55,408 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 04:46:55,408 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-02 04:46:55,446 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/data/865b227e2/19625982ac0b4f48b038c7438b322127/FLAG3adfba77e [2018-12-02 04:46:55,856 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 04:46:55,857 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-02 04:46:55,862 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/data/865b227e2/19625982ac0b4f48b038c7438b322127/FLAG3adfba77e [2018-12-02 04:46:55,870 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/data/865b227e2/19625982ac0b4f48b038c7438b322127 [2018-12-02 04:46:55,871 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 04:46:55,872 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 04:46:55,873 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 04:46:55,873 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 04:46:55,876 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 04:46:55,876 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:46:55" (1/1) ... [2018-12-02 04:46:55,878 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@706fcb08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:55, skipping insertion in model container [2018-12-02 04:46:55,878 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:46:55" (1/1) ... [2018-12-02 04:46:55,884 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 04:46:55,904 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 04:46:56,026 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:46:56,030 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 04:46:56,056 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:46:56,066 INFO L195 MainTranslator]: Completed translation [2018-12-02 04:46:56,067 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56 WrapperNode [2018-12-02 04:46:56,067 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 04:46:56,067 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 04:46:56,067 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 04:46:56,067 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 04:46:56,103 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,108 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,114 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 04:46:56,115 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 04:46:56,115 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 04:46:56,115 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 04:46:56,122 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,122 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,124 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,124 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,130 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,139 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,140 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... [2018-12-02 04:46:56,142 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 04:46:56,142 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 04:46:56,142 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 04:46:56,143 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 04:46:56,143 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:46:56,174 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-12-02 04:46:56,174 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-12-02 04:46:56,174 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-12-02 04:46:56,174 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-12-02 04:46:56,174 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-12-02 04:46:56,174 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-12-02 04:46:56,174 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-12-02 04:46:56,174 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 04:46:56,175 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-02 04:46:56,175 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-02 04:46:56,175 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-12-02 04:46:56,175 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-02 04:46:56,175 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-12-02 04:46:56,175 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-02 04:46:56,175 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-02 04:46:56,175 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-12-02 04:46:56,176 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-12-02 04:46:56,176 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-02 04:46:56,177 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 04:46:56,177 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-02 04:46:56,177 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-12-02 04:46:56,177 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-02 04:46:56,177 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-02 04:46:56,177 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 04:46:56,177 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-02 04:46:56,177 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-02 04:46:56,483 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 04:46:56,483 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-12-02 04:46:56,483 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:56 BoogieIcfgContainer [2018-12-02 04:46:56,483 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 04:46:56,484 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 04:46:56,484 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 04:46:56,485 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 04:46:56,486 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 04:46:55" (1/3) ... [2018-12-02 04:46:56,486 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31995ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:46:56, skipping insertion in model container [2018-12-02 04:46:56,486 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:56" (2/3) ... [2018-12-02 04:46:56,486 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31995ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:46:56, skipping insertion in model container [2018-12-02 04:46:56,486 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:56" (3/3) ... [2018-12-02 04:46:56,487 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-02 04:46:56,493 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 04:46:56,498 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-02 04:46:56,507 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-02 04:46:56,526 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 04:46:56,526 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-02 04:46:56,526 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 04:46:56,526 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 04:46:56,526 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 04:46:56,527 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 04:46:56,527 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 04:46:56,527 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 04:46:56,540 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states. [2018-12-02 04:46:56,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:56,546 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:56,546 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:56,548 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:56,551 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:56,551 INFO L82 PathProgramCache]: Analyzing trace with hash -2019614736, now seen corresponding path program 1 times [2018-12-02 04:46:56,552 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:56,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:56,580 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:56,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:56,580 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:56,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:56,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:56,751 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:56,751 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:56,752 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:56,755 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:56,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:56,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:56,765 INFO L87 Difference]: Start difference. First operand 229 states. Second operand 5 states. [2018-12-02 04:46:57,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:57,140 INFO L93 Difference]: Finished difference Result 475 states and 713 transitions. [2018-12-02 04:46:57,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:57,141 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:57,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:57,149 INFO L225 Difference]: With dead ends: 475 [2018-12-02 04:46:57,149 INFO L226 Difference]: Without dead ends: 256 [2018-12-02 04:46:57,152 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:57,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-12-02 04:46:57,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-12-02 04:46:57,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:57,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 304 transitions. [2018-12-02 04:46:57,193 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 304 transitions. Word has length 120 [2018-12-02 04:46:57,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:57,193 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 304 transitions. [2018-12-02 04:46:57,193 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:57,193 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 304 transitions. [2018-12-02 04:46:57,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:57,195 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:57,195 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:57,195 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:57,195 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:57,196 INFO L82 PathProgramCache]: Analyzing trace with hash 1218621358, now seen corresponding path program 1 times [2018-12-02 04:46:57,196 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:57,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:57,196 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:57,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:57,197 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:57,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:57,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:57,267 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:57,267 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:57,267 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:57,268 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:57,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:57,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:57,269 INFO L87 Difference]: Start difference. First operand 220 states and 304 transitions. Second operand 5 states. [2018-12-02 04:46:57,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:57,552 INFO L93 Difference]: Finished difference Result 454 states and 646 transitions. [2018-12-02 04:46:57,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:57,552 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:57,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:57,554 INFO L225 Difference]: With dead ends: 454 [2018-12-02 04:46:57,554 INFO L226 Difference]: Without dead ends: 256 [2018-12-02 04:46:57,555 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:57,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-12-02 04:46:57,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-12-02 04:46:57,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:57,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 303 transitions. [2018-12-02 04:46:57,570 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 303 transitions. Word has length 120 [2018-12-02 04:46:57,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:57,570 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 303 transitions. [2018-12-02 04:46:57,570 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:57,570 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 303 transitions. [2018-12-02 04:46:57,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:57,571 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:57,572 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:57,572 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:57,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:57,572 INFO L82 PathProgramCache]: Analyzing trace with hash -1724960720, now seen corresponding path program 1 times [2018-12-02 04:46:57,572 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:57,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:57,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:57,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:57,573 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:57,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:57,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:57,641 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:57,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:57,641 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:57,642 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:57,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:57,642 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:57,642 INFO L87 Difference]: Start difference. First operand 220 states and 303 transitions. Second operand 5 states. [2018-12-02 04:46:57,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:57,899 INFO L93 Difference]: Finished difference Result 452 states and 640 transitions. [2018-12-02 04:46:57,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:57,899 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:57,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:57,900 INFO L225 Difference]: With dead ends: 452 [2018-12-02 04:46:57,900 INFO L226 Difference]: Without dead ends: 254 [2018-12-02 04:46:57,901 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:57,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states. [2018-12-02 04:46:57,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 220. [2018-12-02 04:46:57,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:57,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 302 transitions. [2018-12-02 04:46:57,913 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 302 transitions. Word has length 120 [2018-12-02 04:46:57,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:57,913 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 302 transitions. [2018-12-02 04:46:57,913 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:57,913 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 302 transitions. [2018-12-02 04:46:57,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:57,914 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:57,914 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:57,914 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:57,914 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:57,915 INFO L82 PathProgramCache]: Analyzing trace with hash 951031662, now seen corresponding path program 1 times [2018-12-02 04:46:57,915 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:57,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:57,915 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:57,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:57,915 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:57,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:57,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:57,962 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:57,962 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:57,963 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:57,963 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:57,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:57,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:57,963 INFO L87 Difference]: Start difference. First operand 220 states and 302 transitions. Second operand 5 states. [2018-12-02 04:46:58,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:58,240 INFO L93 Difference]: Finished difference Result 450 states and 634 transitions. [2018-12-02 04:46:58,240 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:58,241 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:58,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:58,242 INFO L225 Difference]: With dead ends: 450 [2018-12-02 04:46:58,242 INFO L226 Difference]: Without dead ends: 252 [2018-12-02 04:46:58,243 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:58,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-12-02 04:46:58,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 220. [2018-12-02 04:46:58,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:58,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 301 transitions. [2018-12-02 04:46:58,259 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 301 transitions. Word has length 120 [2018-12-02 04:46:58,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:58,260 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 301 transitions. [2018-12-02 04:46:58,260 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:58,260 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 301 transitions. [2018-12-02 04:46:58,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:58,261 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:58,261 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:58,261 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:58,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:58,261 INFO L82 PathProgramCache]: Analyzing trace with hash 67522672, now seen corresponding path program 1 times [2018-12-02 04:46:58,261 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:58,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:58,262 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:58,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:58,262 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:58,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:58,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:58,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:58,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:58,303 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:58,303 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:58,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:58,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:58,304 INFO L87 Difference]: Start difference. First operand 220 states and 301 transitions. Second operand 5 states. [2018-12-02 04:46:58,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:58,563 INFO L93 Difference]: Finished difference Result 471 states and 668 transitions. [2018-12-02 04:46:58,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:58,564 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:58,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:58,565 INFO L225 Difference]: With dead ends: 471 [2018-12-02 04:46:58,565 INFO L226 Difference]: Without dead ends: 273 [2018-12-02 04:46:58,566 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:58,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states. [2018-12-02 04:46:58,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 220. [2018-12-02 04:46:58,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:58,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 300 transitions. [2018-12-02 04:46:58,577 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 300 transitions. Word has length 120 [2018-12-02 04:46:58,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:58,577 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 300 transitions. [2018-12-02 04:46:58,577 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:58,577 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 300 transitions. [2018-12-02 04:46:58,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:58,578 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:58,578 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:58,578 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:58,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:58,578 INFO L82 PathProgramCache]: Analyzing trace with hash -1873059342, now seen corresponding path program 1 times [2018-12-02 04:46:58,578 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:58,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:58,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:58,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:58,579 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:58,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:58,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:58,625 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:58,625 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:58,625 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:58,625 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:58,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:58,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:58,626 INFO L87 Difference]: Start difference. First operand 220 states and 300 transitions. Second operand 5 states. [2018-12-02 04:46:58,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:58,881 INFO L93 Difference]: Finished difference Result 469 states and 662 transitions. [2018-12-02 04:46:58,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:58,881 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:58,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:58,882 INFO L225 Difference]: With dead ends: 469 [2018-12-02 04:46:58,882 INFO L226 Difference]: Without dead ends: 271 [2018-12-02 04:46:58,883 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:58,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-12-02 04:46:58,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 220. [2018-12-02 04:46:58,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:58,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 299 transitions. [2018-12-02 04:46:58,893 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 299 transitions. Word has length 120 [2018-12-02 04:46:58,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:58,894 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 299 transitions. [2018-12-02 04:46:58,894 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:58,894 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 299 transitions. [2018-12-02 04:46:58,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:58,894 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:58,895 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:58,895 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:58,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:58,895 INFO L82 PathProgramCache]: Analyzing trace with hash 4003888, now seen corresponding path program 1 times [2018-12-02 04:46:58,895 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:58,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:58,895 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:58,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:58,896 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:58,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:58,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:58,938 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:58,938 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:58,938 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:58,938 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:58,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:58,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:58,939 INFO L87 Difference]: Start difference. First operand 220 states and 299 transitions. Second operand 5 states. [2018-12-02 04:46:59,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:59,163 INFO L93 Difference]: Finished difference Result 467 states and 656 transitions. [2018-12-02 04:46:59,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:59,163 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:59,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:59,164 INFO L225 Difference]: With dead ends: 467 [2018-12-02 04:46:59,164 INFO L226 Difference]: Without dead ends: 269 [2018-12-02 04:46:59,164 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:59,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-12-02 04:46:59,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 220. [2018-12-02 04:46:59,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:59,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 298 transitions. [2018-12-02 04:46:59,182 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 298 transitions. Word has length 120 [2018-12-02 04:46:59,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:59,182 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 298 transitions. [2018-12-02 04:46:59,182 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:59,182 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 298 transitions. [2018-12-02 04:46:59,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:59,183 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:59,183 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:59,183 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:59,183 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:59,184 INFO L82 PathProgramCache]: Analyzing trace with hash -766729678, now seen corresponding path program 1 times [2018-12-02 04:46:59,184 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:59,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:59,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,185 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:59,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:59,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:59,230 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:59,230 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:59,230 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:59,230 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:59,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:59,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:59,231 INFO L87 Difference]: Start difference. First operand 220 states and 298 transitions. Second operand 5 states. [2018-12-02 04:46:59,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:59,479 INFO L93 Difference]: Finished difference Result 465 states and 650 transitions. [2018-12-02 04:46:59,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:46:59,479 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-02 04:46:59,480 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:59,480 INFO L225 Difference]: With dead ends: 465 [2018-12-02 04:46:59,480 INFO L226 Difference]: Without dead ends: 267 [2018-12-02 04:46:59,481 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:59,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-12-02 04:46:59,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 220. [2018-12-02 04:46:59,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-02 04:46:59,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 297 transitions. [2018-12-02 04:46:59,492 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 297 transitions. Word has length 120 [2018-12-02 04:46:59,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:59,493 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 297 transitions. [2018-12-02 04:46:59,493 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:59,493 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 297 transitions. [2018-12-02 04:46:59,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:59,494 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:59,494 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:59,494 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:59,494 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:59,494 INFO L82 PathProgramCache]: Analyzing trace with hash -1761423376, now seen corresponding path program 1 times [2018-12-02 04:46:59,494 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:59,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,495 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:59,495 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,495 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:59,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:59,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:59,524 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:59,524 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 04:46:59,525 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:59,525 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:46:59,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:46:59,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:59,525 INFO L87 Difference]: Start difference. First operand 220 states and 297 transitions. Second operand 6 states. [2018-12-02 04:46:59,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:59,561 INFO L93 Difference]: Finished difference Result 436 states and 607 transitions. [2018-12-02 04:46:59,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:59,561 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-02 04:46:59,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:59,563 INFO L225 Difference]: With dead ends: 436 [2018-12-02 04:46:59,563 INFO L226 Difference]: Without dead ends: 239 [2018-12-02 04:46:59,564 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:46:59,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-12-02 04:46:59,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 225. [2018-12-02 04:46:59,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-12-02 04:46:59,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 302 transitions. [2018-12-02 04:46:59,583 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 302 transitions. Word has length 120 [2018-12-02 04:46:59,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:59,583 INFO L480 AbstractCegarLoop]: Abstraction has 225 states and 302 transitions. [2018-12-02 04:46:59,583 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:46:59,584 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 302 transitions. [2018-12-02 04:46:59,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:59,584 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:59,584 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:59,585 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:59,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:59,585 INFO L82 PathProgramCache]: Analyzing trace with hash -27318926, now seen corresponding path program 1 times [2018-12-02 04:46:59,585 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:59,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,585 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:59,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,586 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:59,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:59,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:59,639 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:59,639 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 04:46:59,639 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:59,639 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:46:59,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:46:59,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:46:59,640 INFO L87 Difference]: Start difference. First operand 225 states and 302 transitions. Second operand 4 states. [2018-12-02 04:46:59,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:59,798 INFO L93 Difference]: Finished difference Result 622 states and 862 transitions. [2018-12-02 04:46:59,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 04:46:59,798 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-02 04:46:59,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:59,800 INFO L225 Difference]: With dead ends: 622 [2018-12-02 04:46:59,801 INFO L226 Difference]: Without dead ends: 420 [2018-12-02 04:46:59,801 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:46:59,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-12-02 04:46:59,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 415. [2018-12-02 04:46:59,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 415 states. [2018-12-02 04:46:59,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 415 states to 415 states and 556 transitions. [2018-12-02 04:46:59,844 INFO L78 Accepts]: Start accepts. Automaton has 415 states and 556 transitions. Word has length 120 [2018-12-02 04:46:59,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:59,844 INFO L480 AbstractCegarLoop]: Abstraction has 415 states and 556 transitions. [2018-12-02 04:46:59,844 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:46:59,844 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 556 transitions. [2018-12-02 04:46:59,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:59,845 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:59,845 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:59,845 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:59,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:59,846 INFO L82 PathProgramCache]: Analyzing trace with hash -512734447, now seen corresponding path program 1 times [2018-12-02 04:46:59,846 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:59,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:59,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,847 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:59,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:59,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:59,889 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:59,889 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 04:46:59,889 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:46:59,889 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:46:59,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:46:59,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:46:59,890 INFO L87 Difference]: Start difference. First operand 415 states and 556 transitions. Second operand 6 states. [2018-12-02 04:46:59,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:59,941 INFO L93 Difference]: Finished difference Result 823 states and 1130 transitions. [2018-12-02 04:46:59,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:59,941 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-02 04:46:59,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:59,943 INFO L225 Difference]: With dead ends: 823 [2018-12-02 04:46:59,943 INFO L226 Difference]: Without dead ends: 431 [2018-12-02 04:46:59,945 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:46:59,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-12-02 04:46:59,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 420. [2018-12-02 04:46:59,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 420 states. [2018-12-02 04:46:59,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 560 transitions. [2018-12-02 04:46:59,980 INFO L78 Accepts]: Start accepts. Automaton has 420 states and 560 transitions. Word has length 120 [2018-12-02 04:46:59,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:59,981 INFO L480 AbstractCegarLoop]: Abstraction has 420 states and 560 transitions. [2018-12-02 04:46:59,981 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:46:59,981 INFO L276 IsEmpty]: Start isEmpty. Operand 420 states and 560 transitions. [2018-12-02 04:46:59,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:46:59,981 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:59,982 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:59,982 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:59,982 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:59,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1244701873, now seen corresponding path program 1 times [2018-12-02 04:46:59,982 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:46:59,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:59,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:59,983 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:46:59,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:00,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:47:00,026 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:00,026 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 04:47:00,026 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:00,026 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:47:00,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:47:00,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:47:00,027 INFO L87 Difference]: Start difference. First operand 420 states and 560 transitions. Second operand 4 states. [2018-12-02 04:47:00,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:00,211 INFO L93 Difference]: Finished difference Result 1201 states and 1654 transitions. [2018-12-02 04:47:00,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 04:47:00,212 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-02 04:47:00,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:00,215 INFO L225 Difference]: With dead ends: 1201 [2018-12-02 04:47:00,215 INFO L226 Difference]: Without dead ends: 804 [2018-12-02 04:47:00,217 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:47:00,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 804 states. [2018-12-02 04:47:00,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 804 to 797. [2018-12-02 04:47:00,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 797 states. [2018-12-02 04:47:00,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 1060 transitions. [2018-12-02 04:47:00,256 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 1060 transitions. Word has length 120 [2018-12-02 04:47:00,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:00,257 INFO L480 AbstractCegarLoop]: Abstraction has 797 states and 1060 transitions. [2018-12-02 04:47:00,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:47:00,257 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 1060 transitions. [2018-12-02 04:47:00,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:47:00,258 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:00,258 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:00,258 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:00,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:00,258 INFO L82 PathProgramCache]: Analyzing trace with hash -667773232, now seen corresponding path program 1 times [2018-12-02 04:47:00,258 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:00,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:00,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,259 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:00,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:00,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:47:00,294 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:00,294 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 04:47:00,294 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:00,294 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:47:00,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:47:00,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:47:00,295 INFO L87 Difference]: Start difference. First operand 797 states and 1060 transitions. Second operand 6 states. [2018-12-02 04:47:00,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:00,351 INFO L93 Difference]: Finished difference Result 1597 states and 2175 transitions. [2018-12-02 04:47:00,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:47:00,351 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-02 04:47:00,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:00,354 INFO L225 Difference]: With dead ends: 1597 [2018-12-02 04:47:00,354 INFO L226 Difference]: Without dead ends: 823 [2018-12-02 04:47:00,357 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:47:00,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823 states. [2018-12-02 04:47:00,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823 to 807. [2018-12-02 04:47:00,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-02 04:47:00,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1068 transitions. [2018-12-02 04:47:00,419 INFO L78 Accepts]: Start accepts. Automaton has 807 states and 1068 transitions. Word has length 120 [2018-12-02 04:47:00,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:00,420 INFO L480 AbstractCegarLoop]: Abstraction has 807 states and 1068 transitions. [2018-12-02 04:47:00,420 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:47:00,420 INFO L276 IsEmpty]: Start isEmpty. Operand 807 states and 1068 transitions. [2018-12-02 04:47:00,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:47:00,420 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:00,420 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:00,421 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:00,421 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:00,421 INFO L82 PathProgramCache]: Analyzing trace with hash 593144018, now seen corresponding path program 1 times [2018-12-02 04:47:00,421 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:00,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,422 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:00,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,422 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:00,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:00,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:47:00,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:00,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 04:47:00,471 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:00,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:47:00,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:47:00,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:47:00,472 INFO L87 Difference]: Start difference. First operand 807 states and 1068 transitions. Second operand 6 states. [2018-12-02 04:47:00,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:00,551 INFO L93 Difference]: Finished difference Result 1631 states and 2212 transitions. [2018-12-02 04:47:00,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:47:00,551 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-02 04:47:00,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:00,553 INFO L225 Difference]: With dead ends: 1631 [2018-12-02 04:47:00,554 INFO L226 Difference]: Without dead ends: 847 [2018-12-02 04:47:00,555 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:47:00,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 847 states. [2018-12-02 04:47:00,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 847 to 827. [2018-12-02 04:47:00,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 827 states. [2018-12-02 04:47:00,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1088 transitions. [2018-12-02 04:47:00,607 INFO L78 Accepts]: Start accepts. Automaton has 827 states and 1088 transitions. Word has length 120 [2018-12-02 04:47:00,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:00,608 INFO L480 AbstractCegarLoop]: Abstraction has 827 states and 1088 transitions. [2018-12-02 04:47:00,608 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:47:00,608 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1088 transitions. [2018-12-02 04:47:00,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-02 04:47:00,608 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:00,608 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:00,608 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:00,608 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:00,608 INFO L82 PathProgramCache]: Analyzing trace with hash -1762661232, now seen corresponding path program 1 times [2018-12-02 04:47:00,608 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:00,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,609 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:00,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,609 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:00,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:00,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:47:00,651 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:00,651 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 04:47:00,651 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:00,651 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:47:00,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:47:00,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:47:00,651 INFO L87 Difference]: Start difference. First operand 827 states and 1088 transitions. Second operand 4 states. [2018-12-02 04:47:00,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:00,879 INFO L93 Difference]: Finished difference Result 2411 states and 3286 transitions. [2018-12-02 04:47:00,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 04:47:00,880 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-02 04:47:00,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:00,886 INFO L225 Difference]: With dead ends: 2411 [2018-12-02 04:47:00,886 INFO L226 Difference]: Without dead ends: 1607 [2018-12-02 04:47:00,889 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:47:00,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1607 states. [2018-12-02 04:47:00,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1607 to 1598. [2018-12-02 04:47:00,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1598 states. [2018-12-02 04:47:00,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1598 states to 1598 states and 2097 transitions. [2018-12-02 04:47:00,969 INFO L78 Accepts]: Start accepts. Automaton has 1598 states and 2097 transitions. Word has length 120 [2018-12-02 04:47:00,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:00,969 INFO L480 AbstractCegarLoop]: Abstraction has 1598 states and 2097 transitions. [2018-12-02 04:47:00,969 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:47:00,969 INFO L276 IsEmpty]: Start isEmpty. Operand 1598 states and 2097 transitions. [2018-12-02 04:47:00,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:00,971 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:00,971 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:00,971 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:00,971 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:00,971 INFO L82 PathProgramCache]: Analyzing trace with hash 1599710920, now seen corresponding path program 1 times [2018-12-02 04:47:00,971 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:00,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,972 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:00,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:00,972 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:00,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:01,012 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:01,012 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:01,012 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-02 04:47:01,012 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:01,013 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:47:01,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:47:01,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:47:01,013 INFO L87 Difference]: Start difference. First operand 1598 states and 2097 transitions. Second operand 6 states. [2018-12-02 04:47:01,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:01,116 INFO L93 Difference]: Finished difference Result 3201 states and 4303 transitions. [2018-12-02 04:47:01,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:47:01,116 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 141 [2018-12-02 04:47:01,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:01,122 INFO L225 Difference]: With dead ends: 3201 [2018-12-02 04:47:01,122 INFO L226 Difference]: Without dead ends: 1626 [2018-12-02 04:47:01,126 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:47:01,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states. [2018-12-02 04:47:01,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1618. [2018-12-02 04:47:01,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-02 04:47:01,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2113 transitions. [2018-12-02 04:47:01,229 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2113 transitions. Word has length 141 [2018-12-02 04:47:01,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:01,230 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2113 transitions. [2018-12-02 04:47:01,230 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:47:01,230 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2113 transitions. [2018-12-02 04:47:01,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:01,231 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:01,231 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:01,231 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:01,231 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:01,231 INFO L82 PathProgramCache]: Analyzing trace with hash 1801534854, now seen corresponding path program 1 times [2018-12-02 04:47:01,231 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:01,232 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:01,232 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:01,232 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:01,232 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:01,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:01,270 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:01,270 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:01,270 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:47:01,270 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:01,271 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:47:01,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:47:01,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:47:01,271 INFO L87 Difference]: Start difference. First operand 1618 states and 2113 transitions. Second operand 5 states. [2018-12-02 04:47:01,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:01,594 INFO L93 Difference]: Finished difference Result 3212 states and 4210 transitions. [2018-12-02 04:47:01,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:47:01,595 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-02 04:47:01,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:01,599 INFO L225 Difference]: With dead ends: 3212 [2018-12-02 04:47:01,599 INFO L226 Difference]: Without dead ends: 1618 [2018-12-02 04:47:01,601 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:47:01,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-02 04:47:01,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-02 04:47:01,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-02 04:47:01,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2097 transitions. [2018-12-02 04:47:01,674 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2097 transitions. Word has length 141 [2018-12-02 04:47:01,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:01,674 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2097 transitions. [2018-12-02 04:47:01,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:47:01,674 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2097 transitions. [2018-12-02 04:47:01,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:01,675 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:01,675 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:01,675 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:01,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:01,676 INFO L82 PathProgramCache]: Analyzing trace with hash -1106647032, now seen corresponding path program 1 times [2018-12-02 04:47:01,676 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:01,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:01,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:01,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:01,676 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:01,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:01,709 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:01,709 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:01,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:47:01,709 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:01,709 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:47:01,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:47:01,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:47:01,709 INFO L87 Difference]: Start difference. First operand 1618 states and 2097 transitions. Second operand 5 states. [2018-12-02 04:47:02,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:02,022 INFO L93 Difference]: Finished difference Result 3212 states and 4178 transitions. [2018-12-02 04:47:02,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:47:02,022 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-02 04:47:02,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:02,027 INFO L225 Difference]: With dead ends: 3212 [2018-12-02 04:47:02,027 INFO L226 Difference]: Without dead ends: 1618 [2018-12-02 04:47:02,030 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:47:02,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-02 04:47:02,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-02 04:47:02,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-02 04:47:02,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2081 transitions. [2018-12-02 04:47:02,132 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2081 transitions. Word has length 141 [2018-12-02 04:47:02,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:02,133 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2081 transitions. [2018-12-02 04:47:02,133 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:47:02,133 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2081 transitions. [2018-12-02 04:47:02,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:02,134 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:02,134 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:02,134 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:02,134 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:02,134 INFO L82 PathProgramCache]: Analyzing trace with hash -230628026, now seen corresponding path program 1 times [2018-12-02 04:47:02,134 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:02,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:02,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:02,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:02,135 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:02,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:02,173 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:02,173 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:02,173 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:47:02,173 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:02,174 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:47:02,174 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:47:02,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:47:02,174 INFO L87 Difference]: Start difference. First operand 1618 states and 2081 transitions. Second operand 5 states. [2018-12-02 04:47:02,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:02,462 INFO L93 Difference]: Finished difference Result 3212 states and 4146 transitions. [2018-12-02 04:47:02,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:47:02,462 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-02 04:47:02,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:02,466 INFO L225 Difference]: With dead ends: 3212 [2018-12-02 04:47:02,466 INFO L226 Difference]: Without dead ends: 1618 [2018-12-02 04:47:02,468 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:47:02,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-02 04:47:02,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-02 04:47:02,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-02 04:47:02,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2065 transitions. [2018-12-02 04:47:02,540 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2065 transitions. Word has length 141 [2018-12-02 04:47:02,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:02,540 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2065 transitions. [2018-12-02 04:47:02,540 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:47:02,540 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2065 transitions. [2018-12-02 04:47:02,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:02,541 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:02,541 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:02,541 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:02,541 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:02,541 INFO L82 PathProgramCache]: Analyzing trace with hash 213272648, now seen corresponding path program 1 times [2018-12-02 04:47:02,541 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:02,542 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:02,542 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:02,542 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:02,542 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:02,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:02,587 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:02,588 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:02,588 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:47:02,588 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:02,588 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:47:02,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:47:02,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:47:02,589 INFO L87 Difference]: Start difference. First operand 1618 states and 2065 transitions. Second operand 5 states. [2018-12-02 04:47:03,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:03,026 INFO L93 Difference]: Finished difference Result 4062 states and 5227 transitions. [2018-12-02 04:47:03,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:47:03,027 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-02 04:47:03,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:03,031 INFO L225 Difference]: With dead ends: 4062 [2018-12-02 04:47:03,032 INFO L226 Difference]: Without dead ends: 2468 [2018-12-02 04:47:03,034 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:47:03,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2468 states. [2018-12-02 04:47:03,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2468 to 2324. [2018-12-02 04:47:03,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2018-12-02 04:47:03,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2887 transitions. [2018-12-02 04:47:03,133 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2887 transitions. Word has length 141 [2018-12-02 04:47:03,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:03,134 INFO L480 AbstractCegarLoop]: Abstraction has 2324 states and 2887 transitions. [2018-12-02 04:47:03,134 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:47:03,134 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2887 transitions. [2018-12-02 04:47:03,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:03,135 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:03,136 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:03,136 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:03,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:03,136 INFO L82 PathProgramCache]: Analyzing trace with hash 1751612678, now seen corresponding path program 1 times [2018-12-02 04:47:03,136 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:03,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:03,137 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:03,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:03,137 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:03,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:03,175 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:03,175 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:03,175 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:47:03,175 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:03,176 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:47:03,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:47:03,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:47:03,176 INFO L87 Difference]: Start difference. First operand 2324 states and 2887 transitions. Second operand 5 states. [2018-12-02 04:47:03,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:03,771 INFO L93 Difference]: Finished difference Result 5495 states and 7170 transitions. [2018-12-02 04:47:03,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:47:03,771 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-02 04:47:03,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:03,783 INFO L225 Difference]: With dead ends: 5495 [2018-12-02 04:47:03,783 INFO L226 Difference]: Without dead ends: 3197 [2018-12-02 04:47:03,789 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:47:03,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3197 states. [2018-12-02 04:47:03,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3197 to 2836. [2018-12-02 04:47:03,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2836 states. [2018-12-02 04:47:03,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2836 states to 2836 states and 3435 transitions. [2018-12-02 04:47:03,939 INFO L78 Accepts]: Start accepts. Automaton has 2836 states and 3435 transitions. Word has length 141 [2018-12-02 04:47:03,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:03,940 INFO L480 AbstractCegarLoop]: Abstraction has 2836 states and 3435 transitions. [2018-12-02 04:47:03,940 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:47:03,940 INFO L276 IsEmpty]: Start isEmpty. Operand 2836 states and 3435 transitions. [2018-12-02 04:47:03,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:03,941 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:03,941 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:03,941 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:03,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:03,942 INFO L82 PathProgramCache]: Analyzing trace with hash -276973432, now seen corresponding path program 1 times [2018-12-02 04:47:03,942 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:03,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:03,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:03,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:03,942 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:03,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:03,996 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:03,996 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:03,996 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:47:03,996 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:03,997 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:47:03,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:47:03,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:47:03,997 INFO L87 Difference]: Start difference. First operand 2836 states and 3435 transitions. Second operand 5 states. [2018-12-02 04:47:04,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:04,588 INFO L93 Difference]: Finished difference Result 6035 states and 7539 transitions. [2018-12-02 04:47:04,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:47:04,588 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-02 04:47:04,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:04,598 INFO L225 Difference]: With dead ends: 6035 [2018-12-02 04:47:04,598 INFO L226 Difference]: Without dead ends: 3225 [2018-12-02 04:47:04,604 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:47:04,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3225 states. [2018-12-02 04:47:04,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3225 to 3060. [2018-12-02 04:47:04,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3060 states. [2018-12-02 04:47:04,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3060 states to 3060 states and 3641 transitions. [2018-12-02 04:47:04,797 INFO L78 Accepts]: Start accepts. Automaton has 3060 states and 3641 transitions. Word has length 141 [2018-12-02 04:47:04,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:04,797 INFO L480 AbstractCegarLoop]: Abstraction has 3060 states and 3641 transitions. [2018-12-02 04:47:04,797 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:47:04,797 INFO L276 IsEmpty]: Start isEmpty. Operand 3060 states and 3641 transitions. [2018-12-02 04:47:04,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:04,799 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:04,799 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:04,799 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:04,799 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:04,800 INFO L82 PathProgramCache]: Analyzing trace with hash -758053690, now seen corresponding path program 1 times [2018-12-02 04:47:04,800 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:04,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:04,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:04,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:04,800 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:04,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:04,848 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:47:04,848 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:04,848 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:47:04,848 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:04,849 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:47:04,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:47:04,849 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:47:04,849 INFO L87 Difference]: Start difference. First operand 3060 states and 3641 transitions. Second operand 5 states. [2018-12-02 04:47:05,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:05,397 INFO L93 Difference]: Finished difference Result 6473 states and 8022 transitions. [2018-12-02 04:47:05,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:47:05,397 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-02 04:47:05,397 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:05,407 INFO L225 Difference]: With dead ends: 6473 [2018-12-02 04:47:05,407 INFO L226 Difference]: Without dead ends: 3437 [2018-12-02 04:47:05,414 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:47:05,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states. [2018-12-02 04:47:05,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3206. [2018-12-02 04:47:05,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3206 states. [2018-12-02 04:47:05,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3206 states to 3206 states and 3739 transitions. [2018-12-02 04:47:05,579 INFO L78 Accepts]: Start accepts. Automaton has 3206 states and 3739 transitions. Word has length 141 [2018-12-02 04:47:05,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:05,579 INFO L480 AbstractCegarLoop]: Abstraction has 3206 states and 3739 transitions. [2018-12-02 04:47:05,579 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:47:05,579 INFO L276 IsEmpty]: Start isEmpty. Operand 3206 states and 3739 transitions. [2018-12-02 04:47:05,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-02 04:47:05,580 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:05,580 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:05,580 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:05,580 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:05,581 INFO L82 PathProgramCache]: Analyzing trace with hash -773572408, now seen corresponding path program 1 times [2018-12-02 04:47:05,581 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:05,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:05,581 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:05,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:05,581 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:05,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:05,606 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:47:05,607 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:47:05,607 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:47:05,608 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 142 with the following transitions: [2018-12-02 04:47:05,609 INFO L205 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [330], [332], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [542], [555], [568], [581], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [696], [697], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:47:05,638 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:47:05,638 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:47:05,820 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:47:05,821 INFO L272 AbstractInterpreter]: Visited 110 different actions 110 times. Never merged. Never widened. Performed 971 root evaluator evaluations with a maximum evaluation depth of 3. Performed 971 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 58 variables. [2018-12-02 04:47:05,834 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:05,834 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:47:06,023 INFO L227 lantSequenceWeakener]: Weakened 118 states. On average, predicates are now at 69.56% of their original sizes. [2018-12-02 04:47:06,023 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:47:06,527 INFO L418 sIntCurrentIteration]: We unified 140 AI predicates to 140 [2018-12-02 04:47:06,528 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:47:06,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:47:06,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [46] imperfect sequences [3] total 47 [2018-12-02 04:47:06,528 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:06,528 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-12-02 04:47:06,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-12-02 04:47:06,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=414, Invalid=1656, Unknown=0, NotChecked=0, Total=2070 [2018-12-02 04:47:06,529 INFO L87 Difference]: Start difference. First operand 3206 states and 3739 transitions. Second operand 46 states. [2018-12-02 04:47:13,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:13,083 INFO L93 Difference]: Finished difference Result 6513 states and 7626 transitions. [2018-12-02 04:47:13,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-12-02 04:47:13,083 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 141 [2018-12-02 04:47:13,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:13,093 INFO L225 Difference]: With dead ends: 6513 [2018-12-02 04:47:13,093 INFO L226 Difference]: Without dead ends: 3322 [2018-12-02 04:47:13,099 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 170 GetRequests, 96 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1530 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1227, Invalid=4473, Unknown=0, NotChecked=0, Total=5700 [2018-12-02 04:47:13,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states. [2018-12-02 04:47:13,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 3309. [2018-12-02 04:47:13,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3309 states. [2018-12-02 04:47:13,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3309 states to 3309 states and 3847 transitions. [2018-12-02 04:47:13,267 INFO L78 Accepts]: Start accepts. Automaton has 3309 states and 3847 transitions. Word has length 141 [2018-12-02 04:47:13,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:13,268 INFO L480 AbstractCegarLoop]: Abstraction has 3309 states and 3847 transitions. [2018-12-02 04:47:13,268 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-12-02 04:47:13,268 INFO L276 IsEmpty]: Start isEmpty. Operand 3309 states and 3847 transitions. [2018-12-02 04:47:13,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-12-02 04:47:13,269 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:13,269 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:13,269 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:13,269 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:13,270 INFO L82 PathProgramCache]: Analyzing trace with hash -1812010618, now seen corresponding path program 1 times [2018-12-02 04:47:13,270 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:13,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:13,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:13,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:13,270 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:13,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:13,291 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 9 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-02 04:47:13,291 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:47:13,291 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:47:13,291 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 146 with the following transitions: [2018-12-02 04:47:13,292 INFO L205 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [330], [332], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [565], [568], [572], [578], [581], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [696], [697], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:47:13,293 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:47:13,294 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:47:13,351 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:47:13,351 INFO L272 AbstractInterpreter]: Visited 130 different actions 152 times. Merged at 13 different actions 13 times. Never widened. Performed 1404 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1404 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-12-02 04:47:13,354 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:13,354 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:47:13,494 INFO L227 lantSequenceWeakener]: Weakened 140 states. On average, predicates are now at 72.97% of their original sizes. [2018-12-02 04:47:13,494 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:47:14,208 INFO L418 sIntCurrentIteration]: We unified 144 AI predicates to 144 [2018-12-02 04:47:14,208 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:47:14,208 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:47:14,208 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [55] imperfect sequences [3] total 56 [2018-12-02 04:47:14,208 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:14,209 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-12-02 04:47:14,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-12-02 04:47:14,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=751, Invalid=2219, Unknown=0, NotChecked=0, Total=2970 [2018-12-02 04:47:14,211 INFO L87 Difference]: Start difference. First operand 3309 states and 3847 transitions. Second operand 55 states. [2018-12-02 04:47:29,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:29,301 INFO L93 Difference]: Finished difference Result 24421 states and 30695 transitions. [2018-12-02 04:47:29,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-02 04:47:29,301 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 145 [2018-12-02 04:47:29,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:29,353 INFO L225 Difference]: With dead ends: 24421 [2018-12-02 04:47:29,353 INFO L226 Difference]: Without dead ends: 16699 [2018-12-02 04:47:29,377 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 195 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3582 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2359, Invalid=8771, Unknown=0, NotChecked=0, Total=11130 [2018-12-02 04:47:29,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16699 states. [2018-12-02 04:47:30,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16699 to 16217. [2018-12-02 04:47:30,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16217 states. [2018-12-02 04:47:30,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16217 states to 16217 states and 19636 transitions. [2018-12-02 04:47:30,340 INFO L78 Accepts]: Start accepts. Automaton has 16217 states and 19636 transitions. Word has length 145 [2018-12-02 04:47:30,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:30,341 INFO L480 AbstractCegarLoop]: Abstraction has 16217 states and 19636 transitions. [2018-12-02 04:47:30,341 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-12-02 04:47:30,341 INFO L276 IsEmpty]: Start isEmpty. Operand 16217 states and 19636 transitions. [2018-12-02 04:47:30,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2018-12-02 04:47:30,353 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:30,353 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:30,354 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:30,354 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:30,354 INFO L82 PathProgramCache]: Analyzing trace with hash -708564301, now seen corresponding path program 1 times [2018-12-02 04:47:30,354 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:30,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:30,354 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:30,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:30,354 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:30,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:30,393 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-12-02 04:47:30,394 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:47:30,394 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 04:47:30,394 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:30,394 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:47:30,394 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:47:30,394 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:47:30,394 INFO L87 Difference]: Start difference. First operand 16217 states and 19636 transitions. Second operand 4 states. [2018-12-02 04:47:31,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:31,365 INFO L93 Difference]: Finished difference Result 31187 states and 38714 transitions. [2018-12-02 04:47:31,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 04:47:31,365 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 207 [2018-12-02 04:47:31,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:31,393 INFO L225 Difference]: With dead ends: 31187 [2018-12-02 04:47:31,394 INFO L226 Difference]: Without dead ends: 15097 [2018-12-02 04:47:31,418 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:47:31,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15097 states. [2018-12-02 04:47:32,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15097 to 15012. [2018-12-02 04:47:32,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15012 states. [2018-12-02 04:47:32,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15012 states to 15012 states and 17698 transitions. [2018-12-02 04:47:32,288 INFO L78 Accepts]: Start accepts. Automaton has 15012 states and 17698 transitions. Word has length 207 [2018-12-02 04:47:32,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:32,288 INFO L480 AbstractCegarLoop]: Abstraction has 15012 states and 17698 transitions. [2018-12-02 04:47:32,288 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:47:32,288 INFO L276 IsEmpty]: Start isEmpty. Operand 15012 states and 17698 transitions. [2018-12-02 04:47:32,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2018-12-02 04:47:32,297 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:32,298 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:32,298 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:32,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:32,298 INFO L82 PathProgramCache]: Analyzing trace with hash -913434924, now seen corresponding path program 1 times [2018-12-02 04:47:32,298 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:32,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:32,298 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:32,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:32,299 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:32,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:32,350 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-02 04:47:32,351 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:47:32,351 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:47:32,351 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 211 with the following transitions: [2018-12-02 04:47:32,351 INFO L205 CegarAbsIntRunner]: [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [552], [559], [565], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:47:32,353 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:47:32,353 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:47:32,399 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:47:32,399 INFO L272 AbstractInterpreter]: Visited 131 different actions 152 times. Merged at 14 different actions 14 times. Never widened. Performed 1651 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1651 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-12-02 04:47:32,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:32,406 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:47:32,528 INFO L227 lantSequenceWeakener]: Weakened 146 states. On average, predicates are now at 69.13% of their original sizes. [2018-12-02 04:47:32,528 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:47:33,293 INFO L418 sIntCurrentIteration]: We unified 209 AI predicates to 209 [2018-12-02 04:47:33,294 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:47:33,294 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:47:33,294 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [57] imperfect sequences [6] total 61 [2018-12-02 04:47:33,294 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:33,294 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-12-02 04:47:33,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-12-02 04:47:33,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=791, Invalid=2401, Unknown=0, NotChecked=0, Total=3192 [2018-12-02 04:47:33,295 INFO L87 Difference]: Start difference. First operand 15012 states and 17698 transitions. Second operand 57 states. [2018-12-02 04:47:44,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:44,290 INFO L93 Difference]: Finished difference Result 30059 states and 35455 transitions. [2018-12-02 04:47:44,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-02 04:47:44,290 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 210 [2018-12-02 04:47:44,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:44,318 INFO L225 Difference]: With dead ends: 30059 [2018-12-02 04:47:44,318 INFO L226 Difference]: Without dead ends: 15174 [2018-12-02 04:47:44,338 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 252 GetRequests, 154 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3161 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2346, Invalid=7554, Unknown=0, NotChecked=0, Total=9900 [2018-12-02 04:47:44,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15174 states. [2018-12-02 04:47:45,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15174 to 15153. [2018-12-02 04:47:45,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15153 states. [2018-12-02 04:47:45,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15153 states to 15153 states and 17847 transitions. [2018-12-02 04:47:45,281 INFO L78 Accepts]: Start accepts. Automaton has 15153 states and 17847 transitions. Word has length 210 [2018-12-02 04:47:45,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:45,281 INFO L480 AbstractCegarLoop]: Abstraction has 15153 states and 17847 transitions. [2018-12-02 04:47:45,281 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-12-02 04:47:45,282 INFO L276 IsEmpty]: Start isEmpty. Operand 15153 states and 17847 transitions. [2018-12-02 04:47:45,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 214 [2018-12-02 04:47:45,291 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:45,292 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:45,292 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:45,292 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:45,292 INFO L82 PathProgramCache]: Analyzing trace with hash -1170762779, now seen corresponding path program 1 times [2018-12-02 04:47:45,292 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:45,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:45,293 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:45,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:45,293 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:45,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:45,342 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 04:47:45,342 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:47:45,342 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:47:45,342 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 214 with the following transitions: [2018-12-02 04:47:45,342 INFO L205 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [565], [568], [572], [575], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:47:45,344 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:47:45,345 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:47:45,386 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:47:45,386 INFO L272 AbstractInterpreter]: Visited 138 different actions 157 times. Merged at 11 different actions 11 times. Never widened. Performed 1442 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1442 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-12-02 04:47:45,388 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:45,388 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:47:45,487 INFO L227 lantSequenceWeakener]: Weakened 153 states. On average, predicates are now at 70% of their original sizes. [2018-12-02 04:47:45,487 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:47:46,351 INFO L418 sIntCurrentIteration]: We unified 212 AI predicates to 212 [2018-12-02 04:47:46,352 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:47:46,352 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:47:46,352 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-12-02 04:47:46,352 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:46,352 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-12-02 04:47:46,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-12-02 04:47:46,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=774, Invalid=2766, Unknown=0, NotChecked=0, Total=3540 [2018-12-02 04:47:46,353 INFO L87 Difference]: Start difference. First operand 15153 states and 17847 transitions. Second operand 60 states. [2018-12-02 04:47:54,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:47:54,337 INFO L93 Difference]: Finished difference Result 30357 states and 35873 transitions. [2018-12-02 04:47:54,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-12-02 04:47:54,337 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 213 [2018-12-02 04:47:54,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:47:54,367 INFO L225 Difference]: With dead ends: 30357 [2018-12-02 04:47:54,367 INFO L226 Difference]: Without dead ends: 15463 [2018-12-02 04:47:54,389 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 252 GetRequests, 154 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2901 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2027, Invalid=7873, Unknown=0, NotChecked=0, Total=9900 [2018-12-02 04:47:54,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15463 states. [2018-12-02 04:47:55,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15463 to 15443. [2018-12-02 04:47:55,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15443 states. [2018-12-02 04:47:55,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15443 states to 15443 states and 18195 transitions. [2018-12-02 04:47:55,331 INFO L78 Accepts]: Start accepts. Automaton has 15443 states and 18195 transitions. Word has length 213 [2018-12-02 04:47:55,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:47:55,331 INFO L480 AbstractCegarLoop]: Abstraction has 15443 states and 18195 transitions. [2018-12-02 04:47:55,331 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-12-02 04:47:55,331 INFO L276 IsEmpty]: Start isEmpty. Operand 15443 states and 18195 transitions. [2018-12-02 04:47:55,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-12-02 04:47:55,340 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:47:55,341 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:47:55,341 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:47:55,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:55,341 INFO L82 PathProgramCache]: Analyzing trace with hash -105925495, now seen corresponding path program 1 times [2018-12-02 04:47:55,341 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:47:55,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:55,341 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:47:55,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:47:55,341 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:47:55,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:47:55,373 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 04:47:55,373 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:47:55,373 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:47:55,373 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 215 with the following transitions: [2018-12-02 04:47:55,373 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [549], [555], [559], [565], [568], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:47:55,374 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:47:55,375 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:47:55,417 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:47:55,417 INFO L272 AbstractInterpreter]: Visited 141 different actions 164 times. Merged at 13 different actions 13 times. Never widened. Performed 1709 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1709 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-02 04:47:55,418 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:47:55,419 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:47:55,514 INFO L227 lantSequenceWeakener]: Weakened 149 states. On average, predicates are now at 68.55% of their original sizes. [2018-12-02 04:47:55,514 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:47:56,502 INFO L418 sIntCurrentIteration]: We unified 213 AI predicates to 213 [2018-12-02 04:47:56,502 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:47:56,502 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:47:56,502 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-12-02 04:47:56,502 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:47:56,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-12-02 04:47:56,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-12-02 04:47:56,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=635, Invalid=2905, Unknown=0, NotChecked=0, Total=3540 [2018-12-02 04:47:56,503 INFO L87 Difference]: Start difference. First operand 15443 states and 18195 transitions. Second operand 60 states. [2018-12-02 04:48:05,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:48:05,467 INFO L93 Difference]: Finished difference Result 23771 states and 27984 transitions. [2018-12-02 04:48:05,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-02 04:48:05,467 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 214 [2018-12-02 04:48:05,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:48:05,489 INFO L225 Difference]: With dead ends: 23771 [2018-12-02 04:48:05,489 INFO L226 Difference]: Without dead ends: 15742 [2018-12-02 04:48:05,501 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 258 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3201 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1794, Invalid=9126, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 04:48:05,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15742 states. [2018-12-02 04:48:06,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15742 to 15717. [2018-12-02 04:48:06,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15717 states. [2018-12-02 04:48:06,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15717 states to 15717 states and 18521 transitions. [2018-12-02 04:48:06,409 INFO L78 Accepts]: Start accepts. Automaton has 15717 states and 18521 transitions. Word has length 214 [2018-12-02 04:48:06,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:48:06,410 INFO L480 AbstractCegarLoop]: Abstraction has 15717 states and 18521 transitions. [2018-12-02 04:48:06,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-12-02 04:48:06,410 INFO L276 IsEmpty]: Start isEmpty. Operand 15717 states and 18521 transitions. [2018-12-02 04:48:06,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-12-02 04:48:06,419 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:48:06,419 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:48:06,419 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:48:06,419 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:06,419 INFO L82 PathProgramCache]: Analyzing trace with hash 1361264291, now seen corresponding path program 1 times [2018-12-02 04:48:06,419 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:48:06,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:06,420 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:48:06,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:06,420 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:48:06,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:48:06,463 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 04:48:06,463 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:48:06,463 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:48:06,463 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 215 with the following transitions: [2018-12-02 04:48:06,463 INFO L205 CegarAbsIntRunner]: [33], [36], [47], [49], [51], [53], [57], [60], [76], [78], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [562], [568], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:48:06,465 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:48:06,465 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:48:06,510 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:48:06,510 INFO L272 AbstractInterpreter]: Visited 141 different actions 164 times. Merged at 13 different actions 13 times. Never widened. Performed 1711 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1711 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-02 04:48:06,514 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:06,514 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:48:06,608 INFO L227 lantSequenceWeakener]: Weakened 149 states. On average, predicates are now at 68.56% of their original sizes. [2018-12-02 04:48:06,609 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:48:07,557 INFO L418 sIntCurrentIteration]: We unified 213 AI predicates to 213 [2018-12-02 04:48:07,557 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:48:07,557 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:48:07,557 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-12-02 04:48:07,557 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:48:07,558 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-12-02 04:48:07,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-12-02 04:48:07,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=671, Invalid=2869, Unknown=0, NotChecked=0, Total=3540 [2018-12-02 04:48:07,559 INFO L87 Difference]: Start difference. First operand 15717 states and 18521 transitions. Second operand 60 states. [2018-12-02 04:48:24,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:48:24,402 INFO L93 Difference]: Finished difference Result 23998 states and 28234 transitions. [2018-12-02 04:48:24,402 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-02 04:48:24,402 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 214 [2018-12-02 04:48:24,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:48:24,424 INFO L225 Difference]: With dead ends: 23998 [2018-12-02 04:48:24,424 INFO L226 Difference]: Without dead ends: 16168 [2018-12-02 04:48:24,435 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 258 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3264 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1907, Invalid=9013, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 04:48:24,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16168 states. [2018-12-02 04:48:25,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16168 to 16141. [2018-12-02 04:48:25,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16141 states. [2018-12-02 04:48:25,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16141 states to 16141 states and 18992 transitions. [2018-12-02 04:48:25,367 INFO L78 Accepts]: Start accepts. Automaton has 16141 states and 18992 transitions. Word has length 214 [2018-12-02 04:48:25,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:48:25,368 INFO L480 AbstractCegarLoop]: Abstraction has 16141 states and 18992 transitions. [2018-12-02 04:48:25,368 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-12-02 04:48:25,368 INFO L276 IsEmpty]: Start isEmpty. Operand 16141 states and 18992 transitions. [2018-12-02 04:48:25,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2018-12-02 04:48:25,376 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:48:25,376 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:48:25,376 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:48:25,376 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:25,377 INFO L82 PathProgramCache]: Analyzing trace with hash -1427190956, now seen corresponding path program 1 times [2018-12-02 04:48:25,377 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:48:25,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:25,377 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:48:25,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:25,377 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:48:25,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:48:25,422 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-02 04:48:25,423 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:48:25,423 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:48:25,423 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 218 with the following transitions: [2018-12-02 04:48:25,423 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:48:25,424 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:48:25,424 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:48:25,495 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:48:25,496 INFO L272 AbstractInterpreter]: Visited 142 different actions 214 times. Merged at 18 different actions 34 times. Never widened. Performed 2808 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2808 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 3 different actions. Largest state had 60 variables. [2018-12-02 04:48:25,498 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:25,500 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:48:25,500 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:48:25,500 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:48:25,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:48:25,507 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:48:25,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:48:25,596 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:48:25,639 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 51 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-02 04:48:25,639 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:48:25,808 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-02 04:48:25,824 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:48:25,824 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 7 [2018-12-02 04:48:25,824 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:48:25,825 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:48:25,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:48:25,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:48:25,825 INFO L87 Difference]: Start difference. First operand 16141 states and 18992 transitions. Second operand 3 states. [2018-12-02 04:48:27,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:48:27,318 INFO L93 Difference]: Finished difference Result 41019 states and 51056 transitions. [2018-12-02 04:48:27,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:48:27,319 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 217 [2018-12-02 04:48:27,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:48:27,366 INFO L225 Difference]: With dead ends: 41019 [2018-12-02 04:48:27,366 INFO L226 Difference]: Without dead ends: 26134 [2018-12-02 04:48:27,400 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 440 GetRequests, 431 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-02 04:48:27,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26134 states. [2018-12-02 04:48:28,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26134 to 26118. [2018-12-02 04:48:28,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26118 states. [2018-12-02 04:48:29,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26118 states to 26118 states and 31415 transitions. [2018-12-02 04:48:29,028 INFO L78 Accepts]: Start accepts. Automaton has 26118 states and 31415 transitions. Word has length 217 [2018-12-02 04:48:29,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:48:29,029 INFO L480 AbstractCegarLoop]: Abstraction has 26118 states and 31415 transitions. [2018-12-02 04:48:29,029 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:48:29,029 INFO L276 IsEmpty]: Start isEmpty. Operand 26118 states and 31415 transitions. [2018-12-02 04:48:29,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-12-02 04:48:29,044 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:48:29,044 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:48:29,045 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:48:29,045 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:29,045 INFO L82 PathProgramCache]: Analyzing trace with hash -375898583, now seen corresponding path program 1 times [2018-12-02 04:48:29,045 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:48:29,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:29,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:48:29,046 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:29,046 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:48:29,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:48:29,096 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-02 04:48:29,096 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:48:29,096 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:48:29,096 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 219 with the following transitions: [2018-12-02 04:48:29,096 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [572], [575], [578], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:48:29,097 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:48:29,097 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:48:29,165 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:48:29,165 INFO L272 AbstractInterpreter]: Visited 143 different actions 215 times. Merged at 18 different actions 34 times. Never widened. Performed 2809 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2809 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 3 different actions. Largest state had 60 variables. [2018-12-02 04:48:29,170 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:29,170 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:48:29,170 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:48:29,170 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:48:29,178 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:48:29,178 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:48:29,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:48:29,259 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:48:29,332 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 47 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-02 04:48:29,332 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:48:29,464 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2018-12-02 04:48:29,489 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:48:29,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [6, 5] total 10 [2018-12-02 04:48:29,490 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:48:29,490 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:48:29,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:48:29,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-02 04:48:29,490 INFO L87 Difference]: Start difference. First operand 26118 states and 31415 transitions. Second operand 5 states. [2018-12-02 04:48:31,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:48:31,592 INFO L93 Difference]: Finished difference Result 42632 states and 52441 transitions. [2018-12-02 04:48:31,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:48:31,592 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 218 [2018-12-02 04:48:31,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:48:31,637 INFO L225 Difference]: With dead ends: 42632 [2018-12-02 04:48:31,637 INFO L226 Difference]: Without dead ends: 27807 [2018-12-02 04:48:31,658 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 442 GetRequests, 429 SyntacticMatches, 5 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-02 04:48:31,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27807 states. [2018-12-02 04:48:33,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27807 to 27726. [2018-12-02 04:48:33,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27726 states. [2018-12-02 04:48:33,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27726 states to 27726 states and 33745 transitions. [2018-12-02 04:48:33,484 INFO L78 Accepts]: Start accepts. Automaton has 27726 states and 33745 transitions. Word has length 218 [2018-12-02 04:48:33,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:48:33,484 INFO L480 AbstractCegarLoop]: Abstraction has 27726 states and 33745 transitions. [2018-12-02 04:48:33,484 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:48:33,484 INFO L276 IsEmpty]: Start isEmpty. Operand 27726 states and 33745 transitions. [2018-12-02 04:48:33,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-12-02 04:48:33,499 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:48:33,499 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:48:33,499 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:48:33,499 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:33,499 INFO L82 PathProgramCache]: Analyzing trace with hash 438612538, now seen corresponding path program 1 times [2018-12-02 04:48:33,499 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:48:33,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:33,500 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:48:33,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:33,500 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:48:33,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:48:33,538 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 04:48:33,539 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:48:33,539 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:48:33,539 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 222 with the following transitions: [2018-12-02 04:48:33,539 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [549], [555], [559], [565], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:48:33,540 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:48:33,540 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:48:33,577 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:48:33,577 INFO L272 AbstractInterpreter]: Visited 146 different actions 164 times. Merged at 10 different actions 10 times. Never widened. Performed 1492 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1492 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-02 04:48:33,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:33,578 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:48:33,675 INFO L227 lantSequenceWeakener]: Weakened 159 states. On average, predicates are now at 68.9% of their original sizes. [2018-12-02 04:48:33,675 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:48:34,718 INFO L418 sIntCurrentIteration]: We unified 220 AI predicates to 220 [2018-12-02 04:48:34,718 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:48:34,718 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:48:34,718 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [62] imperfect sequences [4] total 64 [2018-12-02 04:48:34,718 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:48:34,719 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-02 04:48:34,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-02 04:48:34,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=603, Invalid=3179, Unknown=0, NotChecked=0, Total=3782 [2018-12-02 04:48:34,720 INFO L87 Difference]: Start difference. First operand 27726 states and 33745 transitions. Second operand 62 states. [2018-12-02 04:48:47,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:48:47,600 INFO L93 Difference]: Finished difference Result 36754 states and 44718 transitions. [2018-12-02 04:48:47,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-02 04:48:47,600 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 221 [2018-12-02 04:48:47,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:48:47,638 INFO L225 Difference]: With dead ends: 36754 [2018-12-02 04:48:47,638 INFO L226 Difference]: Without dead ends: 28003 [2018-12-02 04:48:47,651 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 262 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3060 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1621, Invalid=9091, Unknown=0, NotChecked=0, Total=10712 [2018-12-02 04:48:47,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28003 states. [2018-12-02 04:48:49,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28003 to 27986. [2018-12-02 04:48:49,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27986 states. [2018-12-02 04:48:49,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27986 states to 27986 states and 34065 transitions. [2018-12-02 04:48:49,470 INFO L78 Accepts]: Start accepts. Automaton has 27986 states and 34065 transitions. Word has length 221 [2018-12-02 04:48:49,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:48:49,470 INFO L480 AbstractCegarLoop]: Abstraction has 27986 states and 34065 transitions. [2018-12-02 04:48:49,470 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-02 04:48:49,470 INFO L276 IsEmpty]: Start isEmpty. Operand 27986 states and 34065 transitions. [2018-12-02 04:48:49,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-12-02 04:48:49,485 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:48:49,485 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:48:49,485 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:48:49,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:49,485 INFO L82 PathProgramCache]: Analyzing trace with hash 1279761248, now seen corresponding path program 1 times [2018-12-02 04:48:49,485 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:48:49,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:49,486 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:48:49,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:48:49,486 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:48:49,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:48:49,529 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 04:48:49,529 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:48:49,529 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:48:49,530 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 222 with the following transitions: [2018-12-02 04:48:49,530 INFO L205 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [60], [76], [78], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [562], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:48:49,531 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:48:49,531 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:48:49,569 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:48:49,569 INFO L272 AbstractInterpreter]: Visited 146 different actions 164 times. Merged at 10 different actions 10 times. Never widened. Performed 1494 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1494 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-02 04:48:49,570 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:48:49,570 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:48:49,665 INFO L227 lantSequenceWeakener]: Weakened 159 states. On average, predicates are now at 68.91% of their original sizes. [2018-12-02 04:48:49,666 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:48:50,665 INFO L418 sIntCurrentIteration]: We unified 220 AI predicates to 220 [2018-12-02 04:48:50,665 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:48:50,665 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:48:50,665 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [62] imperfect sequences [4] total 64 [2018-12-02 04:48:50,665 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:48:50,665 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-02 04:48:50,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-02 04:48:50,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=640, Invalid=3142, Unknown=0, NotChecked=0, Total=3782 [2018-12-02 04:48:50,666 INFO L87 Difference]: Start difference. First operand 27986 states and 34065 transitions. Second operand 62 states. [2018-12-02 04:49:09,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:49:09,476 INFO L93 Difference]: Finished difference Result 36849 states and 44839 transitions. [2018-12-02 04:49:09,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-02 04:49:09,476 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 221 [2018-12-02 04:49:09,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:49:09,516 INFO L225 Difference]: With dead ends: 36849 [2018-12-02 04:49:09,516 INFO L226 Difference]: Without dead ends: 28325 [2018-12-02 04:49:09,529 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 263 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3205 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1750, Invalid=9170, Unknown=0, NotChecked=0, Total=10920 [2018-12-02 04:49:09,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28325 states. [2018-12-02 04:49:11,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28325 to 28303. [2018-12-02 04:49:11,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28303 states. [2018-12-02 04:49:11,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28303 states to 28303 states and 34442 transitions. [2018-12-02 04:49:11,384 INFO L78 Accepts]: Start accepts. Automaton has 28303 states and 34442 transitions. Word has length 221 [2018-12-02 04:49:11,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:49:11,384 INFO L480 AbstractCegarLoop]: Abstraction has 28303 states and 34442 transitions. [2018-12-02 04:49:11,384 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-02 04:49:11,384 INFO L276 IsEmpty]: Start isEmpty. Operand 28303 states and 34442 transitions. [2018-12-02 04:49:11,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2018-12-02 04:49:11,399 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:49:11,399 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:49:11,399 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:49:11,399 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:11,399 INFO L82 PathProgramCache]: Analyzing trace with hash -287017233, now seen corresponding path program 1 times [2018-12-02 04:49:11,399 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:49:11,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:11,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:11,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:11,400 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:49:11,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:11,445 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 16 proven. 5 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 04:49:11,446 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:11,446 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:49:11,446 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 224 with the following transitions: [2018-12-02 04:49:11,446 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:49:11,447 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:49:11,447 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:49:11,532 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:49:11,532 INFO L272 AbstractInterpreter]: Visited 159 different actions 314 times. Merged at 31 different actions 55 times. Never widened. Performed 3315 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3315 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 8 fixpoints after 5 different actions. Largest state had 60 variables. [2018-12-02 04:49:11,534 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:11,534 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:49:11,534 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:11,534 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:49:11,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:11,540 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:49:11,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:11,668 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:49:11,692 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 73 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:49:11,692 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:49:11,779 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-12-02 04:49:11,795 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:49:11,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-12-02 04:49:11,795 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:49:11,795 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:49:11,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:49:11,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:49:11,795 INFO L87 Difference]: Start difference. First operand 28303 states and 34442 transitions. Second operand 4 states. [2018-12-02 04:49:13,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:49:13,612 INFO L93 Difference]: Finished difference Result 40618 states and 50723 transitions. [2018-12-02 04:49:13,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:49:13,613 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 223 [2018-12-02 04:49:13,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:49:13,658 INFO L225 Difference]: With dead ends: 40618 [2018-12-02 04:49:13,658 INFO L226 Difference]: Without dead ends: 24248 [2018-12-02 04:49:13,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 454 GetRequests, 445 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-02 04:49:13,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24248 states. [2018-12-02 04:49:15,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24248 to 23992. [2018-12-02 04:49:15,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23992 states. [2018-12-02 04:49:15,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23992 states to 23992 states and 28992 transitions. [2018-12-02 04:49:15,363 INFO L78 Accepts]: Start accepts. Automaton has 23992 states and 28992 transitions. Word has length 223 [2018-12-02 04:49:15,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:49:15,363 INFO L480 AbstractCegarLoop]: Abstraction has 23992 states and 28992 transitions. [2018-12-02 04:49:15,363 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:49:15,363 INFO L276 IsEmpty]: Start isEmpty. Operand 23992 states and 28992 transitions. [2018-12-02 04:49:15,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 414 [2018-12-02 04:49:15,382 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:49:15,382 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:49:15,383 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:49:15,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:15,383 INFO L82 PathProgramCache]: Analyzing trace with hash -643358620, now seen corresponding path program 1 times [2018-12-02 04:49:15,383 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:49:15,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:15,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:15,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:15,384 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:49:15,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:15,468 INFO L134 CoverageAnalysis]: Checked inductivity of 409 backedges. 24 proven. 20 refuted. 0 times theorem prover too weak. 365 trivial. 0 not checked. [2018-12-02 04:49:15,468 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:15,468 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:49:15,468 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 414 with the following transitions: [2018-12-02 04:49:15,469 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [542], [546], [549], [555], [559], [562], [572], [575], [585], [588], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-02 04:49:15,470 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:49:15,470 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:49:15,519 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-02 04:49:15,519 INFO L272 AbstractInterpreter]: Visited 155 different actions 171 times. Merged at 8 different actions 8 times. Never widened. Performed 1531 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1531 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-02 04:49:15,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:15,523 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-02 04:49:15,679 INFO L227 lantSequenceWeakener]: Weakened 185 states. On average, predicates are now at 65.66% of their original sizes. [2018-12-02 04:49:15,679 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-02 04:49:16,854 INFO L418 sIntCurrentIteration]: We unified 412 AI predicates to 412 [2018-12-02 04:49:16,855 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-02 04:49:16,855 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:49:16,855 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [66] imperfect sequences [8] total 72 [2018-12-02 04:49:16,855 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:49:16,855 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-12-02 04:49:16,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-12-02 04:49:16,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=492, Invalid=3798, Unknown=0, NotChecked=0, Total=4290 [2018-12-02 04:49:16,856 INFO L87 Difference]: Start difference. First operand 23992 states and 28992 transitions. Second operand 66 states. [2018-12-02 04:49:43,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:49:43,573 INFO L93 Difference]: Finished difference Result 37738 states and 45639 transitions. [2018-12-02 04:49:43,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-12-02 04:49:43,573 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 413 [2018-12-02 04:49:43,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:49:43,613 INFO L225 Difference]: With dead ends: 37738 [2018-12-02 04:49:43,613 INFO L226 Difference]: Without dead ends: 25176 [2018-12-02 04:49:43,630 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 457 GetRequests, 348 SyntacticMatches, 0 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3738 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1415, Invalid=10795, Unknown=0, NotChecked=0, Total=12210 [2018-12-02 04:49:43,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25176 states. [2018-12-02 04:49:45,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25176 to 25129. [2018-12-02 04:49:45,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25129 states. [2018-12-02 04:49:45,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25129 states to 25129 states and 30388 transitions. [2018-12-02 04:49:45,403 INFO L78 Accepts]: Start accepts. Automaton has 25129 states and 30388 transitions. Word has length 413 [2018-12-02 04:49:45,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:49:45,403 INFO L480 AbstractCegarLoop]: Abstraction has 25129 states and 30388 transitions. [2018-12-02 04:49:45,403 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-12-02 04:49:45,403 INFO L276 IsEmpty]: Start isEmpty. Operand 25129 states and 30388 transitions. [2018-12-02 04:49:45,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 451 [2018-12-02 04:49:45,425 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:49:45,425 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:49:45,425 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:49:45,425 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:45,425 INFO L82 PathProgramCache]: Analyzing trace with hash -735215562, now seen corresponding path program 1 times [2018-12-02 04:49:45,425 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:49:45,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:45,426 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:45,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:45,426 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:49:45,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:45,508 INFO L134 CoverageAnalysis]: Checked inductivity of 534 backedges. 70 proven. 2 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2018-12-02 04:49:45,508 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:45,508 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:49:45,508 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 451 with the following transitions: [2018-12-02 04:49:45,508 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [542], [546], [549], [552], [555], [559], [562], [565], [572], [575], [578], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-02 04:49:45,510 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:49:45,510 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:49:45,876 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:49:45,877 INFO L272 AbstractInterpreter]: Visited 182 different actions 1278 times. Merged at 49 different actions 243 times. Widened at 1 different actions 1 times. Performed 14853 root evaluator evaluations with a maximum evaluation depth of 3. Performed 14853 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 76 fixpoints after 19 different actions. Largest state had 60 variables. [2018-12-02 04:49:45,878 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:45,878 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:49:45,878 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:45,878 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:49:45,885 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:45,885 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:49:45,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:45,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:49:46,043 INFO L134 CoverageAnalysis]: Checked inductivity of 534 backedges. 335 proven. 0 refuted. 0 times theorem prover too weak. 199 trivial. 0 not checked. [2018-12-02 04:49:46,043 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:49:46,224 INFO L134 CoverageAnalysis]: Checked inductivity of 534 backedges. 84 proven. 15 refuted. 0 times theorem prover too weak. 435 trivial. 0 not checked. [2018-12-02 04:49:46,239 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:49:46,239 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2018-12-02 04:49:46,240 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:49:46,240 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:49:46,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:49:46,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:49:46,240 INFO L87 Difference]: Start difference. First operand 25129 states and 30388 transitions. Second operand 3 states. [2018-12-02 04:49:48,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:49:48,889 INFO L93 Difference]: Finished difference Result 63331 states and 81144 transitions. [2018-12-02 04:49:48,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:49:48,890 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 450 [2018-12-02 04:49:48,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:49:48,969 INFO L225 Difference]: With dead ends: 63331 [2018-12-02 04:49:48,969 INFO L226 Difference]: Without dead ends: 40478 [2018-12-02 04:49:49,022 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 904 GetRequests, 900 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:49:49,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40478 states. [2018-12-02 04:49:51,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40478 to 38574. [2018-12-02 04:49:51,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38574 states. [2018-12-02 04:49:51,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38574 states to 38574 states and 48792 transitions. [2018-12-02 04:49:51,798 INFO L78 Accepts]: Start accepts. Automaton has 38574 states and 48792 transitions. Word has length 450 [2018-12-02 04:49:51,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:49:51,798 INFO L480 AbstractCegarLoop]: Abstraction has 38574 states and 48792 transitions. [2018-12-02 04:49:51,798 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:49:51,798 INFO L276 IsEmpty]: Start isEmpty. Operand 38574 states and 48792 transitions. [2018-12-02 04:49:51,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2018-12-02 04:49:51,834 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:49:51,834 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:49:51,834 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:49:51,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:51,835 INFO L82 PathProgramCache]: Analyzing trace with hash 342535070, now seen corresponding path program 1 times [2018-12-02 04:49:51,835 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:49:51,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:51,835 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:51,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:51,835 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:49:51,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:51,934 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 38 proven. 26 refuted. 0 times theorem prover too weak. 584 trivial. 0 not checked. [2018-12-02 04:49:51,934 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:51,934 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:49:51,935 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 491 with the following transitions: [2018-12-02 04:49:51,935 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [207], [210], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [296], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [542], [546], [549], [555], [559], [562], [565], [572], [575], [578], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-02 04:49:51,937 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:49:51,937 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:49:52,585 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:49:52,585 INFO L272 AbstractInterpreter]: Visited 198 different actions 2252 times. Merged at 65 different actions 358 times. Widened at 2 different actions 3 times. Performed 26884 root evaluator evaluations with a maximum evaluation depth of 3. Performed 26884 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 111 fixpoints after 21 different actions. Largest state had 60 variables. [2018-12-02 04:49:52,587 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:52,587 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:49:52,587 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:52,587 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:49:52,593 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:52,593 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:49:52,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:52,695 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:49:52,785 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 469 proven. 0 refuted. 0 times theorem prover too weak. 179 trivial. 0 not checked. [2018-12-02 04:49:52,785 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:49:52,989 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 135 proven. 0 refuted. 0 times theorem prover too weak. 513 trivial. 0 not checked. [2018-12-02 04:49:53,005 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:49:53,005 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [8] total 10 [2018-12-02 04:49:53,005 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:49:53,006 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:49:53,006 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:49:53,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-12-02 04:49:53,006 INFO L87 Difference]: Start difference. First operand 38574 states and 48792 transitions. Second operand 3 states. [2018-12-02 04:49:55,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:49:55,913 INFO L93 Difference]: Finished difference Result 78903 states and 104090 transitions. [2018-12-02 04:49:55,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:49:55,913 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 490 [2018-12-02 04:49:55,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:49:55,995 INFO L225 Difference]: With dead ends: 78903 [2018-12-02 04:49:55,995 INFO L226 Difference]: Without dead ends: 41048 [2018-12-02 04:49:56,086 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 990 GetRequests, 980 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-12-02 04:49:56,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41048 states. [2018-12-02 04:49:58,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41048 to 41042. [2018-12-02 04:49:58,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41042 states. [2018-12-02 04:49:59,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41042 states to 41042 states and 49371 transitions. [2018-12-02 04:49:59,007 INFO L78 Accepts]: Start accepts. Automaton has 41042 states and 49371 transitions. Word has length 490 [2018-12-02 04:49:59,007 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:49:59,007 INFO L480 AbstractCegarLoop]: Abstraction has 41042 states and 49371 transitions. [2018-12-02 04:49:59,007 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:49:59,008 INFO L276 IsEmpty]: Start isEmpty. Operand 41042 states and 49371 transitions. [2018-12-02 04:49:59,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 448 [2018-12-02 04:49:59,037 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:49:59,037 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:49:59,038 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:49:59,038 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:59,038 INFO L82 PathProgramCache]: Analyzing trace with hash -203778320, now seen corresponding path program 1 times [2018-12-02 04:49:59,038 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:49:59,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:59,038 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:59,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:49:59,039 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:49:59,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:59,120 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 68 proven. 31 refuted. 0 times theorem prover too weak. 431 trivial. 0 not checked. [2018-12-02 04:49:59,120 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:59,120 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:49:59,121 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 448 with the following transitions: [2018-12-02 04:49:59,121 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [546], [549], [552], [555], [559], [562], [568], [572], [575], [578], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-02 04:49:59,122 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:49:59,122 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:49:59,369 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:49:59,370 INFO L272 AbstractInterpreter]: Visited 180 different actions 951 times. Merged at 46 different actions 178 times. Widened at 1 different actions 1 times. Performed 9982 root evaluator evaluations with a maximum evaluation depth of 3. Performed 9982 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 56 fixpoints after 17 different actions. Largest state had 60 variables. [2018-12-02 04:49:59,371 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:49:59,371 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:49:59,371 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:49:59,371 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:49:59,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:49:59,378 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:49:59,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:49:59,477 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:49:59,550 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 303 proven. 0 refuted. 0 times theorem prover too weak. 227 trivial. 0 not checked. [2018-12-02 04:49:59,550 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:49:59,735 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 73 proven. 12 refuted. 0 times theorem prover too weak. 445 trivial. 0 not checked. [2018-12-02 04:49:59,760 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:49:59,760 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8, 6] total 12 [2018-12-02 04:49:59,760 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:49:59,760 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 04:49:59,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 04:49:59,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-12-02 04:49:59,761 INFO L87 Difference]: Start difference. First operand 41042 states and 49371 transitions. Second operand 6 states. [2018-12-02 04:50:01,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:50:01,461 INFO L93 Difference]: Finished difference Result 61765 states and 74594 transitions. [2018-12-02 04:50:01,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 04:50:01,461 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 447 [2018-12-02 04:50:01,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:50:01,500 INFO L225 Difference]: With dead ends: 61765 [2018-12-02 04:50:01,500 INFO L226 Difference]: Without dead ends: 21032 [2018-12-02 04:50:01,551 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 906 GetRequests, 888 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2018-12-02 04:50:01,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21032 states. [2018-12-02 04:50:02,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21032 to 19794. [2018-12-02 04:50:02,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19794 states. [2018-12-02 04:50:02,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19794 states to 19794 states and 22585 transitions. [2018-12-02 04:50:02,830 INFO L78 Accepts]: Start accepts. Automaton has 19794 states and 22585 transitions. Word has length 447 [2018-12-02 04:50:02,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:50:02,830 INFO L480 AbstractCegarLoop]: Abstraction has 19794 states and 22585 transitions. [2018-12-02 04:50:02,830 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 04:50:02,830 INFO L276 IsEmpty]: Start isEmpty. Operand 19794 states and 22585 transitions. [2018-12-02 04:50:02,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 296 [2018-12-02 04:50:02,841 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:50:02,842 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:50:02,842 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:50:02,842 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:02,842 INFO L82 PathProgramCache]: Analyzing trace with hash 734138646, now seen corresponding path program 1 times [2018-12-02 04:50:02,842 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:50:02,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:02,843 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:02,843 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:02,843 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:50:02,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:02,897 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-12-02 04:50:02,897 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:02,897 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:50:02,898 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 296 with the following transitions: [2018-12-02 04:50:02,898 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [562], [572], [575], [585], [588], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-02 04:50:02,899 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:50:02,899 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:50:03,064 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:50:03,064 INFO L272 AbstractInterpreter]: Visited 175 different actions 681 times. Merged at 42 different actions 127 times. Never widened. Performed 6585 root evaluator evaluations with a maximum evaluation depth of 3. Performed 6585 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 23 fixpoints after 11 different actions. Largest state had 60 variables. [2018-12-02 04:50:03,065 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:03,065 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:50:03,065 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:03,066 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:50:03,073 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:03,073 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:50:03,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:03,147 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:50:03,176 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 127 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-02 04:50:03,177 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:50:03,310 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-12-02 04:50:03,336 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:50:03,336 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-12-02 04:50:03,336 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:50:03,336 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:50:03,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:50:03,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:50:03,337 INFO L87 Difference]: Start difference. First operand 19794 states and 22585 transitions. Second operand 4 states. [2018-12-02 04:50:05,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:50:05,069 INFO L93 Difference]: Finished difference Result 35884 states and 41952 transitions. [2018-12-02 04:50:05,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 04:50:05,069 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 295 [2018-12-02 04:50:05,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:50:05,104 INFO L225 Difference]: With dead ends: 35884 [2018-12-02 04:50:05,104 INFO L226 Difference]: Without dead ends: 21198 [2018-12-02 04:50:05,127 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 598 GetRequests, 591 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-12-02 04:50:05,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21198 states. [2018-12-02 04:50:06,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21198 to 20988. [2018-12-02 04:50:06,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20988 states. [2018-12-02 04:50:06,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20988 states to 20988 states and 24493 transitions. [2018-12-02 04:50:06,515 INFO L78 Accepts]: Start accepts. Automaton has 20988 states and 24493 transitions. Word has length 295 [2018-12-02 04:50:06,515 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:50:06,515 INFO L480 AbstractCegarLoop]: Abstraction has 20988 states and 24493 transitions. [2018-12-02 04:50:06,515 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:50:06,516 INFO L276 IsEmpty]: Start isEmpty. Operand 20988 states and 24493 transitions. [2018-12-02 04:50:06,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 518 [2018-12-02 04:50:06,530 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:50:06,530 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:50:06,530 INFO L423 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:50:06,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:06,530 INFO L82 PathProgramCache]: Analyzing trace with hash -924058014, now seen corresponding path program 1 times [2018-12-02 04:50:06,530 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:50:06,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:06,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:06,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:06,531 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:50:06,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:06,738 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 67 proven. 44 refuted. 0 times theorem prover too weak. 632 trivial. 0 not checked. [2018-12-02 04:50:06,738 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:06,738 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:50:06,738 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 518 with the following transitions: [2018-12-02 04:50:06,739 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [345], [350], [355], [360], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [542], [546], [549], [552], [559], [562], [568], [572], [575], [578], [581], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-02 04:50:06,740 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:50:06,740 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:50:07,040 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:50:07,041 INFO L272 AbstractInterpreter]: Visited 190 different actions 1198 times. Merged at 60 different actions 213 times. Widened at 1 different actions 1 times. Performed 11832 root evaluator evaluations with a maximum evaluation depth of 3. Performed 11832 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 61 fixpoints after 19 different actions. Largest state had 60 variables. [2018-12-02 04:50:07,042 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:07,043 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:50:07,043 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:07,043 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:50:07,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:07,050 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:50:07,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:07,161 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:50:07,227 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 389 proven. 0 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-12-02 04:50:07,227 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:50:07,403 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 67 proven. 2 refuted. 0 times theorem prover too weak. 674 trivial. 0 not checked. [2018-12-02 04:50:07,418 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:50:07,418 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5, 4] total 8 [2018-12-02 04:50:07,418 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:50:07,419 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:50:07,419 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:50:07,419 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:50:07,419 INFO L87 Difference]: Start difference. First operand 20988 states and 24493 transitions. Second operand 3 states. [2018-12-02 04:50:09,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:50:09,227 INFO L93 Difference]: Finished difference Result 45111 states and 53729 transitions. [2018-12-02 04:50:09,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:50:09,228 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 517 [2018-12-02 04:50:09,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:50:09,283 INFO L225 Difference]: With dead ends: 45111 [2018-12-02 04:50:09,283 INFO L226 Difference]: Without dead ends: 28341 [2018-12-02 04:50:09,316 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1041 GetRequests, 1034 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:50:09,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28341 states. [2018-12-02 04:50:11,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28341 to 28073. [2018-12-02 04:50:11,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28073 states. [2018-12-02 04:50:11,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28073 states to 28073 states and 32754 transitions. [2018-12-02 04:50:11,204 INFO L78 Accepts]: Start accepts. Automaton has 28073 states and 32754 transitions. Word has length 517 [2018-12-02 04:50:11,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:50:11,204 INFO L480 AbstractCegarLoop]: Abstraction has 28073 states and 32754 transitions. [2018-12-02 04:50:11,204 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:50:11,204 INFO L276 IsEmpty]: Start isEmpty. Operand 28073 states and 32754 transitions. [2018-12-02 04:50:11,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 584 [2018-12-02 04:50:11,219 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:50:11,219 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:50:11,219 INFO L423 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:50:11,219 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:11,220 INFO L82 PathProgramCache]: Analyzing trace with hash 225695341, now seen corresponding path program 1 times [2018-12-02 04:50:11,220 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:50:11,220 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:11,220 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:11,220 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:11,220 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:50:11,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:11,320 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 67 proven. 50 refuted. 0 times theorem prover too weak. 881 trivial. 0 not checked. [2018-12-02 04:50:11,320 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:11,320 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:50:11,320 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 584 with the following transitions: [2018-12-02 04:50:11,320 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [304], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [345], [350], [353], [355], [360], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [542], [546], [549], [555], [559], [562], [565], [568], [572], [575], [578], [581], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-02 04:50:11,321 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:50:11,321 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:50:12,197 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:50:12,198 INFO L272 AbstractInterpreter]: Visited 238 different actions 3730 times. Merged at 84 different actions 768 times. Widened at 1 different actions 1 times. Performed 31831 root evaluator evaluations with a maximum evaluation depth of 3. Performed 31831 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 222 fixpoints after 29 different actions. Largest state had 60 variables. [2018-12-02 04:50:12,199 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:12,199 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:50:12,199 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:12,200 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:50:12,206 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:12,206 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:50:12,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:12,331 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:50:12,480 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 564 proven. 0 refuted. 0 times theorem prover too weak. 434 trivial. 0 not checked. [2018-12-02 04:50:12,480 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:50:12,719 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 67 proven. 50 refuted. 0 times theorem prover too weak. 881 trivial. 0 not checked. [2018-12-02 04:50:12,734 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:50:12,734 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 3 [2018-12-02 04:50:12,734 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:50:12,735 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:50:12,735 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:50:12,735 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:50:12,735 INFO L87 Difference]: Start difference. First operand 28073 states and 32754 transitions. Second operand 3 states. [2018-12-02 04:50:13,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:50:13,913 INFO L93 Difference]: Finished difference Result 43112 states and 49994 transitions. [2018-12-02 04:50:13,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:50:13,914 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 583 [2018-12-02 04:50:13,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:50:13,942 INFO L225 Difference]: With dead ends: 43112 [2018-12-02 04:50:13,942 INFO L226 Difference]: Without dead ends: 16620 [2018-12-02 04:50:13,973 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1168 GetRequests, 1165 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:50:13,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16620 states. [2018-12-02 04:50:15,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16620 to 16269. [2018-12-02 04:50:15,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16269 states. [2018-12-02 04:50:15,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16269 states to 16269 states and 18244 transitions. [2018-12-02 04:50:15,128 INFO L78 Accepts]: Start accepts. Automaton has 16269 states and 18244 transitions. Word has length 583 [2018-12-02 04:50:15,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:50:15,128 INFO L480 AbstractCegarLoop]: Abstraction has 16269 states and 18244 transitions. [2018-12-02 04:50:15,128 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:50:15,128 INFO L276 IsEmpty]: Start isEmpty. Operand 16269 states and 18244 transitions. [2018-12-02 04:50:15,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 693 [2018-12-02 04:50:15,137 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:50:15,137 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:50:15,137 INFO L423 AbstractCegarLoop]: === Iteration 43 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:50:15,137 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:15,138 INFO L82 PathProgramCache]: Analyzing trace with hash -1162149116, now seen corresponding path program 1 times [2018-12-02 04:50:15,138 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:50:15,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:15,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:15,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:15,138 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:50:15,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:15,264 INFO L134 CoverageAnalysis]: Checked inductivity of 1566 backedges. 45 proven. 12 refuted. 0 times theorem prover too weak. 1509 trivial. 0 not checked. [2018-12-02 04:50:15,265 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:15,265 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-02 04:50:15,265 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 693 with the following transitions: [2018-12-02 04:50:15,265 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [207], [210], [214], [216], [218], [219], [224], [230], [236], [242], [248], [254], [260], [266], [272], [274], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [296], [298], [301], [304], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [345], [348], [350], [355], [360], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [508], [509], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [546], [549], [555], [559], [562], [565], [572], [575], [578], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [644], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [730], [731], [732], [733], [734], [735], [736], [737], [738], [739], [740] [2018-12-02 04:50:15,266 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-02 04:50:15,266 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-02 04:50:16,322 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-02 04:50:16,323 INFO L272 AbstractInterpreter]: Visited 234 different actions 4022 times. Merged at 91 different actions 827 times. Widened at 1 different actions 2 times. Performed 41494 root evaluator evaluations with a maximum evaluation depth of 3. Performed 41494 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 227 fixpoints after 28 different actions. Largest state had 60 variables. [2018-12-02 04:50:16,325 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:16,325 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-02 04:50:16,325 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:50:16,325 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:50:16,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:16,331 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-02 04:50:16,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:50:16,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:50:16,597 INFO L134 CoverageAnalysis]: Checked inductivity of 1566 backedges. 729 proven. 0 refuted. 0 times theorem prover too weak. 837 trivial. 0 not checked. [2018-12-02 04:50:16,597 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:50:16,899 INFO L134 CoverageAnalysis]: Checked inductivity of 1566 backedges. 86 proven. 101 refuted. 0 times theorem prover too weak. 1379 trivial. 0 not checked. [2018-12-02 04:50:16,916 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:50:16,916 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2018-12-02 04:50:16,916 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-02 04:50:16,917 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:50:16,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:50:16,917 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:50:16,917 INFO L87 Difference]: Start difference. First operand 16269 states and 18244 transitions. Second operand 3 states. [2018-12-02 04:50:17,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:50:17,831 INFO L93 Difference]: Finished difference Result 26006 states and 29286 transitions. [2018-12-02 04:50:17,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:50:17,831 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 692 [2018-12-02 04:50:17,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:50:17,842 INFO L225 Difference]: With dead ends: 26006 [2018-12-02 04:50:17,842 INFO L226 Difference]: Without dead ends: 5326 [2018-12-02 04:50:17,862 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1387 GetRequests, 1383 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 04:50:17,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5326 states. [2018-12-02 04:50:18,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5326 to 4771. [2018-12-02 04:50:18,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4771 states. [2018-12-02 04:50:18,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4771 states to 4771 states and 5232 transitions. [2018-12-02 04:50:18,218 INFO L78 Accepts]: Start accepts. Automaton has 4771 states and 5232 transitions. Word has length 692 [2018-12-02 04:50:18,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:50:18,218 INFO L480 AbstractCegarLoop]: Abstraction has 4771 states and 5232 transitions. [2018-12-02 04:50:18,218 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:50:18,218 INFO L276 IsEmpty]: Start isEmpty. Operand 4771 states and 5232 transitions. [2018-12-02 04:50:18,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 443 [2018-12-02 04:50:18,222 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:50:18,222 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:50:18,222 INFO L423 AbstractCegarLoop]: === Iteration 44 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:50:18,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:50:18,222 INFO L82 PathProgramCache]: Analyzing trace with hash 613832725, now seen corresponding path program 1 times [2018-12-02 04:50:18,222 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-02 04:50:18,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:18,223 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:50:18,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:50:18,223 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-02 04:50:18,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 04:50:18,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 04:50:18,340 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 04:50:18,495 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 04:50:18 BoogieIcfgContainer [2018-12-02 04:50:18,496 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 04:50:18,496 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 04:50:18,496 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 04:50:18,496 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 04:50:18,497 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:56" (3/4) ... [2018-12-02 04:50:18,498 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-02 04:50:18,643 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_5f89c6a9-46ab-4bd0-ad54-a43d6f7fbe68/bin-2019/utaipan/witness.graphml [2018-12-02 04:50:18,644 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 04:50:18,645 INFO L168 Benchmark]: Toolchain (without parser) took 202772.82 ms. Allocated memory was 1.0 GB in the beginning and 4.6 GB in the end (delta: 3.6 GB). Free memory was 949.7 MB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 1.8 GB. Max. memory is 11.5 GB. [2018-12-02 04:50:18,646 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:50:18,646 INFO L168 Benchmark]: CACSL2BoogieTranslator took 194.17 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 933.4 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. [2018-12-02 04:50:18,646 INFO L168 Benchmark]: Boogie Procedure Inliner took 47.58 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 96.5 MB). Free memory was 933.4 MB in the beginning and 1.1 GB in the end (delta: -160.9 MB). Peak memory consumption was 16.0 MB. Max. memory is 11.5 GB. [2018-12-02 04:50:18,646 INFO L168 Benchmark]: Boogie Preprocessor took 27.30 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-02 04:50:18,646 INFO L168 Benchmark]: RCFGBuilder took 340.85 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 47.7 MB). Peak memory consumption was 47.7 MB. Max. memory is 11.5 GB. [2018-12-02 04:50:18,646 INFO L168 Benchmark]: TraceAbstraction took 202012.20 ms. Allocated memory was 1.1 GB in the beginning and 4.6 GB in the end (delta: 3.5 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2018-12-02 04:50:18,647 INFO L168 Benchmark]: Witness Printer took 147.75 ms. Allocated memory is still 4.6 GB. Free memory was 2.8 GB in the beginning and 2.8 GB in the end (delta: 66.1 MB). Peak memory consumption was 66.1 MB. Max. memory is 11.5 GB. [2018-12-02 04:50:18,648 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 194.17 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 933.4 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 47.58 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 96.5 MB). Free memory was 933.4 MB in the beginning and 1.1 GB in the end (delta: -160.9 MB). Peak memory consumption was 16.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.30 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 340.85 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 47.7 MB). Peak memory consumption was 47.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 202012.20 ms. Allocated memory was 1.1 GB in the beginning and 4.6 GB in the end (delta: 3.5 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. * Witness Printer took 147.75 ms. Allocated memory is still 4.6 GB. Free memory was 2.8 GB in the beginning and 2.8 GB in the end (delta: 66.1 MB). Peak memory consumption was 66.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [\old(E_1)=21, \old(E_2)=5, \old(E_3)=25, \old(E_4)=11, \old(M_E)=17, \old(m_i)=7, \old(m_pc)=15, \old(m_st)=16, \old(T1_E)=3, \old(t1_i)=19, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=18, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=13, \old(T3_E)=23, \old(t3_i)=24, \old(t3_pc)=8, \old(t3_st)=14, \old(T4_E)=26, \old(t4_i)=20, \old(t4_pc)=22, \old(t4_st)=12, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L815] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L815] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L816] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L759] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L762] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L762] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L397] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L473] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L425] COND FALSE !(t1_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L439] COND FALSE !(t2_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND FALSE !(t4_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L417] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L417] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L180] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L180] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L214] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 27 procedures, 229 locations, 1 error locations. UNSAFE Result, 201.9s OverallTime, 44 OverallIterations, 8 TraceHistogramMax, 151.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 16385 SDtfs, 29247 SDslu, 65875 SDs, 0 SdLazy, 42989 SolverSat, 8202 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 28.5s Time, PredicateUnifierStatistics: 18 DeclaredPredicates, 10911 GetRequests, 9793 SyntacticMatches, 65 SemanticMatches, 1053 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27736 ImplicationChecksByTransitivity, 17.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=41042occurred in iteration=38, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 4.5s AbstIntTime, 19 AbstIntIterations, 9 AbstIntStrong, 0.9933137762598749 AbsIntWeakeningRatio, 0.600100857286939 AbsIntAvgWeakeningVarsNumRemoved, 18.019162884518405 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 29.4s AutomataMinimizationTime, 43 MinimizatonAttempts, 6973 StatesRemovedByMinimization, 40 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 1.0s SatisfiabilityAnalysisTime, 3.9s InterpolantComputationTime, 13833 NumberOfCodeBlocks, 13833 NumberOfCodeBlocksAsserted, 54 NumberOfCheckSat, 17460 ConstructedInterpolants, 0 QuantifiedInterpolants, 8197929 SizeOfPredicates, 9 NumberOfNonLiveVariables, 16624 ConjunctsInSsa, 42 ConjunctsInUnsatCore, 63 InterpolantComputations, 36 PerfectInterpolantSequences, 16777/17279 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...