./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/config/TaipanMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -s /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 19:01:49,164 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 19:01:49,165 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 19:01:49,173 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 19:01:49,173 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 19:01:49,174 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 19:01:49,175 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 19:01:49,176 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 19:01:49,177 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 19:01:49,177 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 19:01:49,178 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 19:01:49,178 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 19:01:49,179 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 19:01:49,180 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 19:01:49,180 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 19:01:49,181 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 19:01:49,182 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 19:01:49,183 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 19:01:49,184 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 19:01:49,185 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 19:01:49,186 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 19:01:49,187 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 19:01:49,188 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 19:01:49,188 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 19:01:49,188 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 19:01:49,189 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 19:01:49,190 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 19:01:49,190 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 19:01:49,191 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 19:01:49,191 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 19:01:49,192 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 19:01:49,192 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 19:01:49,192 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 19:01:49,192 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 19:01:49,193 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 19:01:49,194 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 19:01:49,194 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf [2018-12-09 19:01:49,204 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 19:01:49,204 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 19:01:49,204 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 19:01:49,205 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 19:01:49,205 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-09 19:01:49,205 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-09 19:01:49,205 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-09 19:01:49,205 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-09 19:01:49,205 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-09 19:01:49,206 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-09 19:01:49,206 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-09 19:01:49,206 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-09 19:01:49,206 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-09 19:01:49,206 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-09 19:01:49,207 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-09 19:01:49,207 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 19:01:49,207 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-09 19:01:49,207 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-12-09 19:01:49,207 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 19:01:49,207 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-09 19:01:49,208 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 19:01:49,208 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-12-09 19:01:49,208 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-12-09 19:01:49,208 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-12-09 19:01:49,208 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 19:01:49,208 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-09 19:01:49,209 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 19:01:49,209 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 19:01:49,209 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 19:01:49,209 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 19:01:49,209 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 19:01:49,209 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 19:01:49,209 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 19:01:49,209 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-09 19:01:49,210 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 19:01:49,210 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-09 19:01:49,210 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2018-12-09 19:01:49,234 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 19:01:49,243 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 19:01:49,245 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 19:01:49,246 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 19:01:49,247 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 19:01:49,247 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-09 19:01:49,291 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/data/b054fed63/b9cc1394396245d9bf1c2cc57b532cb0/FLAGf4b8b1439 [2018-12-09 19:01:49,626 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 19:01:49,626 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-09 19:01:49,630 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/data/b054fed63/b9cc1394396245d9bf1c2cc57b532cb0/FLAGf4b8b1439 [2018-12-09 19:01:50,028 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/data/b054fed63/b9cc1394396245d9bf1c2cc57b532cb0 [2018-12-09 19:01:50,030 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 19:01:50,031 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-09 19:01:50,032 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 19:01:50,032 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 19:01:50,035 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 19:01:50,036 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,038 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6fe9828 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50, skipping insertion in model container [2018-12-09 19:01:50,038 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,044 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 19:01:50,053 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 19:01:50,137 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 19:01:50,142 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 19:01:50,152 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 19:01:50,160 INFO L195 MainTranslator]: Completed translation [2018-12-09 19:01:50,161 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50 WrapperNode [2018-12-09 19:01:50,161 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 19:01:50,161 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-09 19:01:50,161 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-09 19:01:50,161 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-09 19:01:50,166 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,171 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,175 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-09 19:01:50,175 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 19:01:50,175 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 19:01:50,175 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 19:01:50,181 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,181 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,182 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,182 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,186 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,217 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,218 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... [2018-12-09 19:01:50,219 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 19:01:50,219 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 19:01:50,220 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 19:01:50,220 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 19:01:50,220 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 19:01:50,251 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-09 19:01:50,251 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 19:01:50,251 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 19:01:50,251 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-09 19:01:50,251 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-12-09 19:01:50,251 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-12-09 19:01:50,251 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 19:01:50,252 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 19:01:50,252 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-09 19:01:50,252 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 19:01:50,252 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 19:01:50,252 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-09 19:01:50,371 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 19:01:50,372 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-12-09 19:01:50,372 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 07:01:50 BoogieIcfgContainer [2018-12-09 19:01:50,372 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 19:01:50,372 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 19:01:50,373 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 19:01:50,375 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 19:01:50,375 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 07:01:50" (1/3) ... [2018-12-09 19:01:50,375 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@54d89862 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 07:01:50, skipping insertion in model container [2018-12-09 19:01:50,375 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:01:50" (2/3) ... [2018-12-09 19:01:50,376 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@54d89862 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 07:01:50, skipping insertion in model container [2018-12-09 19:01:50,376 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 07:01:50" (3/3) ... [2018-12-09 19:01:50,377 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-09 19:01:50,382 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 19:01:50,387 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-12-09 19:01:50,397 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-12-09 19:01:50,412 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 19:01:50,413 INFO L383 AbstractCegarLoop]: Hoare is false [2018-12-09 19:01:50,413 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 19:01:50,413 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 19:01:50,413 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 19:01:50,413 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 19:01:50,413 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 19:01:50,413 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 19:01:50,424 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2018-12-09 19:01:50,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-12-09 19:01:50,430 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:50,431 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:50,432 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:50,436 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:50,436 INFO L82 PathProgramCache]: Analyzing trace with hash 1909189377, now seen corresponding path program 1 times [2018-12-09 19:01:50,437 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:50,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:50,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,466 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:50,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:50,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:50,535 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:50,535 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:01:50,535 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:50,537 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:01:50,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:01:50,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:50,546 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 3 states. [2018-12-09 19:01:50,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:50,588 INFO L93 Difference]: Finished difference Result 58 states and 63 transitions. [2018-12-09 19:01:50,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:01:50,589 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 10 [2018-12-09 19:01:50,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:50,594 INFO L225 Difference]: With dead ends: 58 [2018-12-09 19:01:50,594 INFO L226 Difference]: Without dead ends: 54 [2018-12-09 19:01:50,595 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:50,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-12-09 19:01:50,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 39. [2018-12-09 19:01:50,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-09 19:01:50,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 42 transitions. [2018-12-09 19:01:50,619 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 42 transitions. Word has length 10 [2018-12-09 19:01:50,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:50,620 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 42 transitions. [2018-12-09 19:01:50,620 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:01:50,620 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 42 transitions. [2018-12-09 19:01:50,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-12-09 19:01:50,620 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:50,620 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:50,620 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:50,621 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:50,621 INFO L82 PathProgramCache]: Analyzing trace with hash -941983064, now seen corresponding path program 1 times [2018-12-09 19:01:50,621 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:50,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:50,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,621 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:50,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:50,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:50,646 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:50,646 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 19:01:50,646 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:50,647 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:01:50,647 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:01:50,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:50,647 INFO L87 Difference]: Start difference. First operand 39 states and 42 transitions. Second operand 3 states. [2018-12-09 19:01:50,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:50,669 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-12-09 19:01:50,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:01:50,669 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-12-09 19:01:50,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:50,671 INFO L225 Difference]: With dead ends: 49 [2018-12-09 19:01:50,671 INFO L226 Difference]: Without dead ends: 49 [2018-12-09 19:01:50,671 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:50,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-12-09 19:01:50,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 41. [2018-12-09 19:01:50,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-12-09 19:01:50,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2018-12-09 19:01:50,674 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 11 [2018-12-09 19:01:50,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:50,674 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2018-12-09 19:01:50,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:01:50,674 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2018-12-09 19:01:50,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-09 19:01:50,675 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:50,675 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:50,675 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:50,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:50,675 INFO L82 PathProgramCache]: Analyzing trace with hash 863296133, now seen corresponding path program 1 times [2018-12-09 19:01:50,675 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:50,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:50,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,676 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:50,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:50,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:50,717 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:50,718 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:01:50,718 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:50,718 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:01:50,718 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:01:50,718 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:01:50,719 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 5 states. [2018-12-09 19:01:50,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:50,753 INFO L93 Difference]: Finished difference Result 40 states and 44 transitions. [2018-12-09 19:01:50,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:01:50,753 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 12 [2018-12-09 19:01:50,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:50,754 INFO L225 Difference]: With dead ends: 40 [2018-12-09 19:01:50,754 INFO L226 Difference]: Without dead ends: 40 [2018-12-09 19:01:50,754 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:01:50,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-12-09 19:01:50,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-12-09 19:01:50,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-12-09 19:01:50,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2018-12-09 19:01:50,756 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 12 [2018-12-09 19:01:50,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:50,757 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2018-12-09 19:01:50,757 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:01:50,757 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2018-12-09 19:01:50,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-09 19:01:50,757 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:50,757 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:50,757 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:50,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:50,757 INFO L82 PathProgramCache]: Analyzing trace with hash 863296134, now seen corresponding path program 1 times [2018-12-09 19:01:50,757 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:50,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:50,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,758 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:50,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:50,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:50,814 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:50,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 19:01:50,814 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:50,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 19:01:50,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 19:01:50,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:01:50,815 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 6 states. [2018-12-09 19:01:50,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:50,886 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-12-09 19:01:50,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 19:01:50,887 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 12 [2018-12-09 19:01:50,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:50,887 INFO L225 Difference]: With dead ends: 42 [2018-12-09 19:01:50,887 INFO L226 Difference]: Without dead ends: 42 [2018-12-09 19:01:50,888 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-12-09 19:01:50,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-12-09 19:01:50,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 39. [2018-12-09 19:01:50,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-09 19:01:50,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 43 transitions. [2018-12-09 19:01:50,891 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 43 transitions. Word has length 12 [2018-12-09 19:01:50,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:50,891 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 43 transitions. [2018-12-09 19:01:50,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 19:01:50,892 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 43 transitions. [2018-12-09 19:01:50,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-12-09 19:01:50,892 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:50,892 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:50,892 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:50,893 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:50,893 INFO L82 PathProgramCache]: Analyzing trace with hash 143250926, now seen corresponding path program 1 times [2018-12-09 19:01:50,893 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:50,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,894 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:50,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,894 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:50,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:50,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:50,929 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:50,929 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 19:01:50,929 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:50,929 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:01:50,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:01:50,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:50,930 INFO L87 Difference]: Start difference. First operand 39 states and 43 transitions. Second operand 3 states. [2018-12-09 19:01:50,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:50,941 INFO L93 Difference]: Finished difference Result 37 states and 41 transitions. [2018-12-09 19:01:50,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:01:50,942 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-12-09 19:01:50,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:50,942 INFO L225 Difference]: With dead ends: 37 [2018-12-09 19:01:50,943 INFO L226 Difference]: Without dead ends: 37 [2018-12-09 19:01:50,943 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:50,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-12-09 19:01:50,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2018-12-09 19:01:50,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-12-09 19:01:50,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 41 transitions. [2018-12-09 19:01:50,946 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 41 transitions. Word has length 15 [2018-12-09 19:01:50,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:50,946 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 41 transitions. [2018-12-09 19:01:50,946 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:01:50,946 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 41 transitions. [2018-12-09 19:01:50,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-12-09 19:01:50,947 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:50,947 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:50,947 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:50,947 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:50,947 INFO L82 PathProgramCache]: Analyzing trace with hash 143250927, now seen corresponding path program 1 times [2018-12-09 19:01:50,947 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:50,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,948 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:50,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:50,948 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:50,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:50,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:50,985 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:50,985 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 19:01:50,985 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:50,985 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 19:01:50,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 19:01:50,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:01:50,986 INFO L87 Difference]: Start difference. First operand 37 states and 41 transitions. Second operand 6 states. [2018-12-09 19:01:51,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:51,068 INFO L93 Difference]: Finished difference Result 56 states and 61 transitions. [2018-12-09 19:01:51,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:01:51,068 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-12-09 19:01:51,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:51,068 INFO L225 Difference]: With dead ends: 56 [2018-12-09 19:01:51,069 INFO L226 Difference]: Without dead ends: 56 [2018-12-09 19:01:51,069 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 19:01:51,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-12-09 19:01:51,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 41. [2018-12-09 19:01:51,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-12-09 19:01:51,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 46 transitions. [2018-12-09 19:01:51,072 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 46 transitions. Word has length 15 [2018-12-09 19:01:51,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:51,072 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 46 transitions. [2018-12-09 19:01:51,072 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 19:01:51,072 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 46 transitions. [2018-12-09 19:01:51,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-12-09 19:01:51,072 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:51,072 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:51,072 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:51,072 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:51,073 INFO L82 PathProgramCache]: Analyzing trace with hash 1623425863, now seen corresponding path program 1 times [2018-12-09 19:01:51,073 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:51,073 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,073 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:51,073 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,073 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:51,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:51,094 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:51,094 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:51,094 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:51,094 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 17 with the following transitions: [2018-12-09 19:01:51,095 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [10], [11], [12], [13], [16], [18], [27], [35], [73], [74], [75], [77] [2018-12-09 19:01:51,115 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:01:51,115 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:01:51,221 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:01:51,222 INFO L272 AbstractInterpreter]: Visited 15 different actions 27 times. Merged at 5 different actions 10 times. Never widened. Performed 153 root evaluator evaluations with a maximum evaluation depth of 3. Performed 153 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 20 variables. [2018-12-09 19:01:51,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:51,228 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:01:51,228 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:51,228 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:51,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:51,234 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:51,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:51,248 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:51,263 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:51,263 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:51,286 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:51,300 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:51,300 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 5 [2018-12-09 19:01:51,300 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:51,301 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:01:51,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:01:51,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:01:51,301 INFO L87 Difference]: Start difference. First operand 41 states and 46 transitions. Second operand 4 states. [2018-12-09 19:01:51,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:51,324 INFO L93 Difference]: Finished difference Result 52 states and 59 transitions. [2018-12-09 19:01:51,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:01:51,324 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-12-09 19:01:51,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:51,325 INFO L225 Difference]: With dead ends: 52 [2018-12-09 19:01:51,325 INFO L226 Difference]: Without dead ends: 52 [2018-12-09 19:01:51,325 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:01:51,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-12-09 19:01:51,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 46. [2018-12-09 19:01:51,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-12-09 19:01:51,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2018-12-09 19:01:51,328 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 16 [2018-12-09 19:01:51,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:51,328 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2018-12-09 19:01:51,328 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:01:51,328 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2018-12-09 19:01:51,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-12-09 19:01:51,329 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:51,329 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:51,329 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:51,329 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:51,329 INFO L82 PathProgramCache]: Analyzing trace with hash 2121234190, now seen corresponding path program 1 times [2018-12-09 19:01:51,329 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:51,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,330 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:51,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,330 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:51,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:51,361 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:51,361 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:51,361 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:51,362 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 21 with the following transitions: [2018-12-09 19:01:51,362 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [35], [37], [40], [73], [74], [75], [77], [78] [2018-12-09 19:01:51,363 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:01:51,363 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:01:51,419 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:01:51,419 INFO L272 AbstractInterpreter]: Visited 20 different actions 43 times. Merged at 11 different actions 21 times. Never widened. Performed 219 root evaluator evaluations with a maximum evaluation depth of 4. Performed 219 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 1 fixpoints after 1 different actions. Largest state had 21 variables. [2018-12-09 19:01:51,421 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:51,421 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:01:51,421 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:51,421 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:51,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:51,427 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:51,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:51,436 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:51,475 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:51,475 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:51,530 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:51,545 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:51,545 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 11 [2018-12-09 19:01:51,545 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:51,545 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-09 19:01:51,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-09 19:01:51,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-12-09 19:01:51,546 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand 9 states. [2018-12-09 19:01:51,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:51,634 INFO L93 Difference]: Finished difference Result 64 states and 68 transitions. [2018-12-09 19:01:51,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-09 19:01:51,635 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 20 [2018-12-09 19:01:51,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:51,635 INFO L225 Difference]: With dead ends: 64 [2018-12-09 19:01:51,635 INFO L226 Difference]: Without dead ends: 58 [2018-12-09 19:01:51,635 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 32 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=104, Unknown=0, NotChecked=0, Total=156 [2018-12-09 19:01:51,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-12-09 19:01:51,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 42. [2018-12-09 19:01:51,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-12-09 19:01:51,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 45 transitions. [2018-12-09 19:01:51,637 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 45 transitions. Word has length 20 [2018-12-09 19:01:51,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:51,638 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 45 transitions. [2018-12-09 19:01:51,638 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-09 19:01:51,638 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 45 transitions. [2018-12-09 19:01:51,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-12-09 19:01:51,638 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:51,638 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:51,638 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:51,639 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:51,639 INFO L82 PathProgramCache]: Analyzing trace with hash -1483602424, now seen corresponding path program 2 times [2018-12-09 19:01:51,639 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:51,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,639 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:51,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,639 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:51,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:51,675 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:01:51,676 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:51,676 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:51,676 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:51,676 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:51,676 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:51,676 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:51,681 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:01:51,682 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:01:51,690 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-09 19:01:51,690 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:51,692 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:51,731 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-09 19:01:51,731 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:51,790 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-09 19:01:51,804 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:51,804 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 18 [2018-12-09 19:01:51,804 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:51,804 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-09 19:01:51,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-09 19:01:51,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=247, Unknown=0, NotChecked=0, Total=306 [2018-12-09 19:01:51,805 INFO L87 Difference]: Start difference. First operand 42 states and 45 transitions. Second operand 12 states. [2018-12-09 19:01:51,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:51,902 INFO L93 Difference]: Finished difference Result 70 states and 73 transitions. [2018-12-09 19:01:51,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-09 19:01:51,902 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 21 [2018-12-09 19:01:51,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:51,902 INFO L225 Difference]: With dead ends: 70 [2018-12-09 19:01:51,902 INFO L226 Difference]: Without dead ends: 70 [2018-12-09 19:01:51,903 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=113, Invalid=349, Unknown=0, NotChecked=0, Total=462 [2018-12-09 19:01:51,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-12-09 19:01:51,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 58. [2018-12-09 19:01:51,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-12-09 19:01:51,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 61 transitions. [2018-12-09 19:01:51,905 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 61 transitions. Word has length 21 [2018-12-09 19:01:51,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:51,905 INFO L480 AbstractCegarLoop]: Abstraction has 58 states and 61 transitions. [2018-12-09 19:01:51,905 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-09 19:01:51,905 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 61 transitions. [2018-12-09 19:01:51,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-09 19:01:51,906 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:51,906 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:51,906 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:51,906 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:51,906 INFO L82 PathProgramCache]: Analyzing trace with hash -523456177, now seen corresponding path program 2 times [2018-12-09 19:01:51,906 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:51,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,907 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:51,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,907 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:51,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:51,934 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 19:01:51,934 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:51,934 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 19:01:51,934 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:51,934 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:01:51,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:01:51,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:51,935 INFO L87 Difference]: Start difference. First operand 58 states and 61 transitions. Second operand 3 states. [2018-12-09 19:01:51,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:51,951 INFO L93 Difference]: Finished difference Result 62 states and 65 transitions. [2018-12-09 19:01:51,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:01:51,951 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-09 19:01:51,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:51,951 INFO L225 Difference]: With dead ends: 62 [2018-12-09 19:01:51,951 INFO L226 Difference]: Without dead ends: 62 [2018-12-09 19:01:51,952 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:01:51,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-12-09 19:01:51,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 60. [2018-12-09 19:01:51,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-12-09 19:01:51,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2018-12-09 19:01:51,954 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 63 transitions. Word has length 25 [2018-12-09 19:01:51,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:51,954 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 63 transitions. [2018-12-09 19:01:51,955 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:01:51,955 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 63 transitions. [2018-12-09 19:01:51,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-12-09 19:01:51,955 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:51,955 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:51,955 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:51,956 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:51,956 INFO L82 PathProgramCache]: Analyzing trace with hash 2020089664, now seen corresponding path program 1 times [2018-12-09 19:01:51,956 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:51,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,956 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:51,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:51,957 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:51,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:52,014 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-09 19:01:52,014 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:52,015 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:52,015 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 32 with the following transitions: [2018-12-09 19:01:52,015 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [33], [35], [37], [38], [41], [43], [47], [55], [58], [73], [74], [75], [77], [78] [2018-12-09 19:01:52,016 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:01:52,016 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:01:52,174 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:01:52,175 INFO L272 AbstractInterpreter]: Visited 26 different actions 202 times. Merged at 15 different actions 119 times. Widened at 2 different actions 4 times. Performed 1022 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1022 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 18 fixpoints after 5 different actions. Largest state had 21 variables. [2018-12-09 19:01:52,176 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:52,176 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:01:52,176 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:52,176 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:52,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:52,183 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:52,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:52,193 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:52,211 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 19:01:52,211 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:52,227 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 19:01:52,242 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:52,242 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 4, 4] total 10 [2018-12-09 19:01:52,242 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:52,242 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-09 19:01:52,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-09 19:01:52,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-12-09 19:01:52,243 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. Second operand 10 states. [2018-12-09 19:01:52,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:52,347 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2018-12-09 19:01:52,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-09 19:01:52,347 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 31 [2018-12-09 19:01:52,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:52,348 INFO L225 Difference]: With dead ends: 74 [2018-12-09 19:01:52,348 INFO L226 Difference]: Without dead ends: 74 [2018-12-09 19:01:52,348 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-12-09 19:01:52,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-12-09 19:01:52,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 49. [2018-12-09 19:01:52,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-12-09 19:01:52,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2018-12-09 19:01:52,352 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 50 transitions. Word has length 31 [2018-12-09 19:01:52,352 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:52,352 INFO L480 AbstractCegarLoop]: Abstraction has 49 states and 50 transitions. [2018-12-09 19:01:52,352 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-09 19:01:52,352 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 50 transitions. [2018-12-09 19:01:52,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-12-09 19:01:52,353 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:52,353 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:52,353 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:52,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:52,353 INFO L82 PathProgramCache]: Analyzing trace with hash -1710006518, now seen corresponding path program 1 times [2018-12-09 19:01:52,353 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:52,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:52,354 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:52,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:52,354 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:52,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:52,407 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-09 19:01:52,407 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:52,408 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:52,408 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 43 with the following transitions: [2018-12-09 19:01:52,408 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [11], [12], [13], [16], [18], [22], [23], [27], [35], [37], [38], [41], [43], [73], [74], [75], [77], [78] [2018-12-09 19:01:52,409 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:01:52,409 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:01:52,512 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:01:52,512 INFO L272 AbstractInterpreter]: Visited 23 different actions 177 times. Merged at 15 different actions 103 times. Widened at 1 different actions 3 times. Performed 891 root evaluator evaluations with a maximum evaluation depth of 4. Performed 891 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 13 fixpoints after 3 different actions. Largest state had 21 variables. [2018-12-09 19:01:52,513 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:52,514 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:01:52,514 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:52,514 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:52,522 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:52,522 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:52,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:52,537 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:52,549 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-09 19:01:52,550 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:52,578 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-09 19:01:52,602 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:52,602 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2018-12-09 19:01:52,602 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:52,602 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:01:52,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:01:52,603 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 19:01:52,603 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. Second operand 5 states. [2018-12-09 19:01:52,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:52,628 INFO L93 Difference]: Finished difference Result 60 states and 62 transitions. [2018-12-09 19:01:52,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:01:52,628 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-12-09 19:01:52,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:52,629 INFO L225 Difference]: With dead ends: 60 [2018-12-09 19:01:52,629 INFO L226 Difference]: Without dead ends: 60 [2018-12-09 19:01:52,629 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 79 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 19:01:52,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-12-09 19:01:52,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 54. [2018-12-09 19:01:52,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-12-09 19:01:52,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 56 transitions. [2018-12-09 19:01:52,631 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 56 transitions. Word has length 42 [2018-12-09 19:01:52,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:52,631 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 56 transitions. [2018-12-09 19:01:52,631 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:01:52,631 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 56 transitions. [2018-12-09 19:01:52,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:01:52,632 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:52,632 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:52,632 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:52,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:52,632 INFO L82 PathProgramCache]: Analyzing trace with hash -1860847279, now seen corresponding path program 1 times [2018-12-09 19:01:52,632 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:52,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:52,633 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:52,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:52,633 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:52,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:52,715 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 4 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-12-09 19:01:52,716 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:52,716 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:52,716 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 47 with the following transitions: [2018-12-09 19:01:52,716 INFO L205 CegarAbsIntRunner]: [0], [1], [2], [8], [10], [12], [13], [16], [18], [22], [23], [27], [35], [37], [38], [40], [41], [43], [73], [74], [75], [77], [78] [2018-12-09 19:01:52,717 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:01:52,717 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:01:52,799 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:01:52,800 INFO L272 AbstractInterpreter]: Visited 23 different actions 181 times. Merged at 15 different actions 107 times. Widened at 1 different actions 2 times. Performed 939 root evaluator evaluations with a maximum evaluation depth of 4. Performed 939 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 14 fixpoints after 3 different actions. Largest state had 21 variables. [2018-12-09 19:01:52,801 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:52,801 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:01:52,801 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:52,801 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:52,807 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:52,807 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:52,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:52,821 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:52,859 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 19:01:52,859 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:52,932 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 19:01:52,947 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:52,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 18 [2018-12-09 19:01:52,947 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:52,947 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-09 19:01:52,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-09 19:01:52,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2018-12-09 19:01:52,947 INFO L87 Difference]: Start difference. First operand 54 states and 56 transitions. Second operand 15 states. [2018-12-09 19:01:53,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:53,078 INFO L93 Difference]: Finished difference Result 62 states and 63 transitions. [2018-12-09 19:01:53,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-09 19:01:53,078 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 46 [2018-12-09 19:01:53,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:53,078 INFO L225 Difference]: With dead ends: 62 [2018-12-09 19:01:53,078 INFO L226 Difference]: Without dead ends: 59 [2018-12-09 19:01:53,079 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 84 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=125, Invalid=381, Unknown=0, NotChecked=0, Total=506 [2018-12-09 19:01:53,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-12-09 19:01:53,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 54. [2018-12-09 19:01:53,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-12-09 19:01:53,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-12-09 19:01:53,080 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 46 [2018-12-09 19:01:53,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:53,080 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-12-09 19:01:53,080 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-09 19:01:53,080 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-12-09 19:01:53,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-09 19:01:53,081 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:53,081 INFO L402 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:53,081 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:53,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:53,081 INFO L82 PathProgramCache]: Analyzing trace with hash -374076379, now seen corresponding path program 2 times [2018-12-09 19:01:53,081 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:53,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:53,082 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:53,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:53,082 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:53,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:53,120 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 55 proven. 7 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 19:01:53,121 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:53,121 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:53,121 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:53,121 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:53,121 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:53,121 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:53,127 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:01:53,127 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:01:53,137 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-09 19:01:53,137 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:53,139 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:53,192 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 48 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 19:01:53,193 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:53,253 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 39 proven. 14 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 19:01:53,268 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:53,268 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 8] total 21 [2018-12-09 19:01:53,268 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:53,269 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-09 19:01:53,269 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-09 19:01:53,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-12-09 19:01:53,269 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 14 states. [2018-12-09 19:01:53,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:53,378 INFO L93 Difference]: Finished difference Result 83 states and 84 transitions. [2018-12-09 19:01:53,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-12-09 19:01:53,378 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 47 [2018-12-09 19:01:53,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:53,379 INFO L225 Difference]: With dead ends: 83 [2018-12-09 19:01:53,379 INFO L226 Difference]: Without dead ends: 83 [2018-12-09 19:01:53,379 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 84 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 124 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=165, Invalid=537, Unknown=0, NotChecked=0, Total=702 [2018-12-09 19:01:53,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-12-09 19:01:53,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 78. [2018-12-09 19:01:53,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-12-09 19:01:53,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 79 transitions. [2018-12-09 19:01:53,383 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 79 transitions. Word has length 47 [2018-12-09 19:01:53,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:53,383 INFO L480 AbstractCegarLoop]: Abstraction has 78 states and 79 transitions. [2018-12-09 19:01:53,383 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-09 19:01:53,383 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 79 transitions. [2018-12-09 19:01:53,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-12-09 19:01:53,384 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:53,384 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:53,384 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:53,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:53,385 INFO L82 PathProgramCache]: Analyzing trace with hash -1743494932, now seen corresponding path program 2 times [2018-12-09 19:01:53,385 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:53,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:53,386 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:53,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:53,386 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:53,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:53,452 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-09 19:01:53,453 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:53,453 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:53,453 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:53,453 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:53,453 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:53,453 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:53,460 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:01:53,460 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:01:53,472 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-09 19:01:53,472 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:53,474 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:53,494 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 19:01:53,497 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 19:01:53,497 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-09 19:01:53,498 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-09 19:01:53,502 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-09 19:01:53,512 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-09 19:01:53,512 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-09 19:01:53,520 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-09 19:01:53,520 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-12-09 19:01:53,625 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-09 19:01:53,625 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:53,652 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-09 19:01:53,668 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:53,668 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 3] total 9 [2018-12-09 19:01:53,668 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:53,668 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-09 19:01:53,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-09 19:01:53,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2018-12-09 19:01:53,669 INFO L87 Difference]: Start difference. First operand 78 states and 79 transitions. Second operand 8 states. [2018-12-09 19:01:53,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:53,731 INFO L93 Difference]: Finished difference Result 82 states and 83 transitions. [2018-12-09 19:01:53,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:01:53,731 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-12-09 19:01:53,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:53,732 INFO L225 Difference]: With dead ends: 82 [2018-12-09 19:01:53,732 INFO L226 Difference]: Without dead ends: 82 [2018-12-09 19:01:53,732 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 94 SyntacticMatches, 4 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-12-09 19:01:53,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-12-09 19:01:53,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 80. [2018-12-09 19:01:53,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-12-09 19:01:53,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2018-12-09 19:01:53,734 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 81 transitions. Word has length 51 [2018-12-09 19:01:53,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:53,735 INFO L480 AbstractCegarLoop]: Abstraction has 80 states and 81 transitions. [2018-12-09 19:01:53,735 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-09 19:01:53,735 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 81 transitions. [2018-12-09 19:01:53,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-09 19:01:53,736 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:53,736 INFO L402 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:53,736 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:53,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:53,736 INFO L82 PathProgramCache]: Analyzing trace with hash 1240037378, now seen corresponding path program 3 times [2018-12-09 19:01:53,736 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:53,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:53,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:53,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:53,737 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:53,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:53,781 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 104 proven. 13 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2018-12-09 19:01:53,781 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:53,781 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:53,781 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:53,781 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:53,781 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:53,781 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:53,788 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:01:53,788 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:01:53,804 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:01:53,805 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:53,806 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:53,838 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 93 proven. 21 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-12-09 19:01:53,838 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:53,881 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 93 proven. 21 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-12-09 19:01:53,896 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:53,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 5, 5] total 17 [2018-12-09 19:01:53,896 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:53,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-09 19:01:53,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-09 19:01:53,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=244, Unknown=0, NotChecked=0, Total=306 [2018-12-09 19:01:53,896 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. Second operand 14 states. [2018-12-09 19:01:54,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:54,038 INFO L93 Difference]: Finished difference Result 132 states and 136 transitions. [2018-12-09 19:01:54,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-09 19:01:54,039 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 73 [2018-12-09 19:01:54,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:54,039 INFO L225 Difference]: With dead ends: 132 [2018-12-09 19:01:54,039 INFO L226 Difference]: Without dead ends: 132 [2018-12-09 19:01:54,040 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=144, Invalid=456, Unknown=0, NotChecked=0, Total=600 [2018-12-09 19:01:54,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-12-09 19:01:54,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 109. [2018-12-09 19:01:54,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-12-09 19:01:54,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 112 transitions. [2018-12-09 19:01:54,043 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 112 transitions. Word has length 73 [2018-12-09 19:01:54,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:54,043 INFO L480 AbstractCegarLoop]: Abstraction has 109 states and 112 transitions. [2018-12-09 19:01:54,043 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-09 19:01:54,044 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 112 transitions. [2018-12-09 19:01:54,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-12-09 19:01:54,044 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:54,044 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:54,045 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:54,045 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:54,045 INFO L82 PathProgramCache]: Analyzing trace with hash -976841143, now seen corresponding path program 3 times [2018-12-09 19:01:54,045 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:54,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:54,046 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:54,046 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:54,046 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:54,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:54,134 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 69 proven. 103 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:01:54,134 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:54,134 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:54,134 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:54,134 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:54,134 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:54,134 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:54,140 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:01:54,140 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:01:54,154 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:01:54,154 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:54,156 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:54,215 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 70 proven. 102 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:01:54,215 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:54,341 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 76 proven. 96 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:01:54,356 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:54,356 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2018-12-09 19:01:54,356 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:54,357 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-12-09 19:01:54,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-12-09 19:01:54,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=527, Unknown=0, NotChecked=0, Total=650 [2018-12-09 19:01:54,357 INFO L87 Difference]: Start difference. First operand 109 states and 112 transitions. Second operand 20 states. [2018-12-09 19:01:54,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:54,525 INFO L93 Difference]: Finished difference Result 127 states and 129 transitions. [2018-12-09 19:01:54,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-12-09 19:01:54,525 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 77 [2018-12-09 19:01:54,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:54,525 INFO L225 Difference]: With dead ends: 127 [2018-12-09 19:01:54,526 INFO L226 Difference]: Without dead ends: 121 [2018-12-09 19:01:54,526 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 137 SyntacticMatches, 7 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 265 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=249, Invalid=807, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 19:01:54,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-12-09 19:01:54,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 114. [2018-12-09 19:01:54,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-12-09 19:01:54,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 116 transitions. [2018-12-09 19:01:54,528 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 116 transitions. Word has length 77 [2018-12-09 19:01:54,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:54,528 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 116 transitions. [2018-12-09 19:01:54,528 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-12-09 19:01:54,528 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 116 transitions. [2018-12-09 19:01:54,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-12-09 19:01:54,529 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:54,529 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:54,529 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:54,529 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:54,529 INFO L82 PathProgramCache]: Analyzing trace with hash -490807564, now seen corresponding path program 4 times [2018-12-09 19:01:54,529 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:54,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:54,530 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:54,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:54,530 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:54,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:54,583 INFO L134 CoverageAnalysis]: Checked inductivity of 236 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 226 trivial. 0 not checked. [2018-12-09 19:01:54,583 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:01:54,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 19:01:54,583 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:01:54,583 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 19:01:54,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 19:01:54,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:01:54,584 INFO L87 Difference]: Start difference. First operand 114 states and 116 transitions. Second operand 6 states. [2018-12-09 19:01:54,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:54,600 INFO L93 Difference]: Finished difference Result 113 states and 115 transitions. [2018-12-09 19:01:54,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:01:54,600 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 82 [2018-12-09 19:01:54,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:54,601 INFO L225 Difference]: With dead ends: 113 [2018-12-09 19:01:54,601 INFO L226 Difference]: Without dead ends: 113 [2018-12-09 19:01:54,601 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:01:54,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-12-09 19:01:54,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-12-09 19:01:54,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-12-09 19:01:54,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 115 transitions. [2018-12-09 19:01:54,603 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 115 transitions. Word has length 82 [2018-12-09 19:01:54,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:54,603 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 115 transitions. [2018-12-09 19:01:54,603 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 19:01:54,603 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 115 transitions. [2018-12-09 19:01:54,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-12-09 19:01:54,604 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:54,604 INFO L402 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:54,604 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:54,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:54,604 INFO L82 PathProgramCache]: Analyzing trace with hash 241027877, now seen corresponding path program 4 times [2018-12-09 19:01:54,604 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:54,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:54,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:54,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:54,605 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:54,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:54,684 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 250 proven. 28 refuted. 0 times theorem prover too weak. 222 trivial. 0 not checked. [2018-12-09 19:01:54,685 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:54,685 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:54,685 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:54,685 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:54,685 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:54,685 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:54,690 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:54,691 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:54,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:54,715 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:54,769 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 213 proven. 38 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-09 19:01:54,770 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:54,853 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 213 proven. 38 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-09 19:01:54,867 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:54,868 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6] total 22 [2018-12-09 19:01:54,868 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:54,868 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-12-09 19:01:54,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-12-09 19:01:54,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=417, Unknown=0, NotChecked=0, Total=506 [2018-12-09 19:01:54,868 INFO L87 Difference]: Start difference. First operand 113 states and 115 transitions. Second operand 18 states. [2018-12-09 19:01:55,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:55,099 INFO L93 Difference]: Finished difference Result 175 states and 181 transitions. [2018-12-09 19:01:55,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-09 19:01:55,100 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 109 [2018-12-09 19:01:55,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:55,100 INFO L225 Difference]: With dead ends: 175 [2018-12-09 19:01:55,100 INFO L226 Difference]: Without dead ends: 175 [2018-12-09 19:01:55,101 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 208 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 136 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=179, Invalid=691, Unknown=0, NotChecked=0, Total=870 [2018-12-09 19:01:55,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-12-09 19:01:55,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 149. [2018-12-09 19:01:55,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-12-09 19:01:55,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 153 transitions. [2018-12-09 19:01:55,104 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 153 transitions. Word has length 109 [2018-12-09 19:01:55,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:55,104 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 153 transitions. [2018-12-09 19:01:55,104 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-12-09 19:01:55,104 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 153 transitions. [2018-12-09 19:01:55,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-12-09 19:01:55,105 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:55,105 INFO L402 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:55,106 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:55,106 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:55,106 INFO L82 PathProgramCache]: Analyzing trace with hash -937043486, now seen corresponding path program 5 times [2018-12-09 19:01:55,106 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:55,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:55,107 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:55,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:55,107 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:55,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:55,241 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 553 proven. 153 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-09 19:01:55,241 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:55,242 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:55,242 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:55,242 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:55,242 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:55,242 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:55,249 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:01:55,249 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:01:55,281 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-12-09 19:01:55,281 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:55,283 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:55,364 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 375 proven. 60 refuted. 0 times theorem prover too weak. 520 trivial. 0 not checked. [2018-12-09 19:01:55,365 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:55,477 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 375 proven. 60 refuted. 0 times theorem prover too weak. 520 trivial. 0 not checked. [2018-12-09 19:01:55,492 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:55,492 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 8, 8] total 32 [2018-12-09 19:01:55,492 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:55,493 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-12-09 19:01:55,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-12-09 19:01:55,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=162, Invalid=830, Unknown=0, NotChecked=0, Total=992 [2018-12-09 19:01:55,493 INFO L87 Difference]: Start difference. First operand 149 states and 153 transitions. Second operand 25 states. [2018-12-09 19:01:55,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:55,872 INFO L93 Difference]: Finished difference Result 267 states and 278 transitions. [2018-12-09 19:01:55,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-09 19:01:55,872 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 145 [2018-12-09 19:01:55,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:55,873 INFO L225 Difference]: With dead ends: 267 [2018-12-09 19:01:55,873 INFO L226 Difference]: Without dead ends: 267 [2018-12-09 19:01:55,874 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 324 GetRequests, 277 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 414 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=567, Invalid=1785, Unknown=0, NotChecked=0, Total=2352 [2018-12-09 19:01:55,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-12-09 19:01:55,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 245. [2018-12-09 19:01:55,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-12-09 19:01:55,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 255 transitions. [2018-12-09 19:01:55,878 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 255 transitions. Word has length 145 [2018-12-09 19:01:55,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:55,878 INFO L480 AbstractCegarLoop]: Abstraction has 245 states and 255 transitions. [2018-12-09 19:01:55,878 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-12-09 19:01:55,878 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 255 transitions. [2018-12-09 19:01:55,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-12-09 19:01:55,879 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:55,879 INFO L402 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:55,879 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:55,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:55,879 INFO L82 PathProgramCache]: Analyzing trace with hash -714413016, now seen corresponding path program 6 times [2018-12-09 19:01:55,879 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:55,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:55,880 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:55,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:55,880 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:55,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:55,972 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 556 proven. 55 refuted. 0 times theorem prover too weak. 541 trivial. 0 not checked. [2018-12-09 19:01:55,972 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:55,972 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:55,972 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:55,972 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:55,972 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:55,972 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:55,979 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:01:55,979 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:01:56,002 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:01:56,002 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:56,005 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:56,146 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 506 proven. 262 refuted. 0 times theorem prover too weak. 384 trivial. 0 not checked. [2018-12-09 19:01:56,146 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:56,279 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 506 proven. 262 refuted. 0 times theorem prover too weak. 384 trivial. 0 not checked. [2018-12-09 19:01:56,294 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:56,294 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 19] total 31 [2018-12-09 19:01:56,294 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:56,294 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-09 19:01:56,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-09 19:01:56,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=763, Unknown=0, NotChecked=0, Total=930 [2018-12-09 19:01:56,295 INFO L87 Difference]: Start difference. First operand 245 states and 255 transitions. Second operand 28 states. [2018-12-09 19:01:56,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:56,636 INFO L93 Difference]: Finished difference Result 344 states and 358 transitions. [2018-12-09 19:01:56,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-09 19:01:56,636 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 155 [2018-12-09 19:01:56,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:56,637 INFO L225 Difference]: With dead ends: 344 [2018-12-09 19:01:56,637 INFO L226 Difference]: Without dead ends: 344 [2018-12-09 19:01:56,638 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 281 SyntacticMatches, 15 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 585 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=386, Invalid=1506, Unknown=0, NotChecked=0, Total=1892 [2018-12-09 19:01:56,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states. [2018-12-09 19:01:56,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 330. [2018-12-09 19:01:56,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 330 states. [2018-12-09 19:01:56,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 330 states to 330 states and 344 transitions. [2018-12-09 19:01:56,645 INFO L78 Accepts]: Start accepts. Automaton has 330 states and 344 transitions. Word has length 155 [2018-12-09 19:01:56,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:56,645 INFO L480 AbstractCegarLoop]: Abstraction has 330 states and 344 transitions. [2018-12-09 19:01:56,645 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-09 19:01:56,645 INFO L276 IsEmpty]: Start isEmpty. Operand 330 states and 344 transitions. [2018-12-09 19:01:56,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-12-09 19:01:56,647 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:56,647 INFO L402 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:56,647 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:56,647 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:56,647 INFO L82 PathProgramCache]: Analyzing trace with hash 1015841328, now seen corresponding path program 7 times [2018-12-09 19:01:56,648 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:56,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:56,648 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:56,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:56,648 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:56,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:56,809 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 814 proven. 295 refuted. 0 times theorem prover too weak. 569 trivial. 0 not checked. [2018-12-09 19:01:56,809 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:56,809 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:56,809 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:56,809 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:56,809 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:56,809 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:56,815 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:56,815 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:56,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:56,855 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:56,991 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 1103 proven. 34 refuted. 0 times theorem prover too weak. 541 trivial. 0 not checked. [2018-12-09 19:01:56,991 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:57,134 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 893 proven. 147 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2018-12-09 19:01:57,149 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:57,149 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 12, 12] total 34 [2018-12-09 19:01:57,149 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:57,150 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-09 19:01:57,150 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-09 19:01:57,150 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=180, Invalid=942, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 19:01:57,150 INFO L87 Difference]: Start difference. First operand 330 states and 344 transitions. Second operand 29 states. [2018-12-09 19:01:57,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:57,563 INFO L93 Difference]: Finished difference Result 303 states and 311 transitions. [2018-12-09 19:01:57,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-09 19:01:57,563 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 186 [2018-12-09 19:01:57,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:57,564 INFO L225 Difference]: With dead ends: 303 [2018-12-09 19:01:57,564 INFO L226 Difference]: Without dead ends: 294 [2018-12-09 19:01:57,565 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 411 GetRequests, 353 SyntacticMatches, 6 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 860 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=495, Invalid=2367, Unknown=0, NotChecked=0, Total=2862 [2018-12-09 19:01:57,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2018-12-09 19:01:57,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 249. [2018-12-09 19:01:57,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 249 states. [2018-12-09 19:01:57,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 254 transitions. [2018-12-09 19:01:57,570 INFO L78 Accepts]: Start accepts. Automaton has 249 states and 254 transitions. Word has length 186 [2018-12-09 19:01:57,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:57,570 INFO L480 AbstractCegarLoop]: Abstraction has 249 states and 254 transitions. [2018-12-09 19:01:57,570 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-09 19:01:57,570 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 254 transitions. [2018-12-09 19:01:57,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-12-09 19:01:57,572 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:57,572 INFO L402 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:57,572 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:57,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:57,572 INFO L82 PathProgramCache]: Analyzing trace with hash 1382499467, now seen corresponding path program 8 times [2018-12-09 19:01:57,572 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:57,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:57,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:57,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:57,573 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:57,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:57,714 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 988 proven. 228 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2018-12-09 19:01:57,715 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:57,715 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:57,715 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:57,715 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:57,715 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:57,715 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:57,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:01:57,721 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:01:57,759 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-12-09 19:01:57,759 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:57,761 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:57,849 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 643 proven. 87 refuted. 0 times theorem prover too weak. 1075 trivial. 0 not checked. [2018-12-09 19:01:57,849 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:57,970 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 643 proven. 87 refuted. 0 times theorem prover too weak. 1075 trivial. 0 not checked. [2018-12-09 19:01:57,985 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:57,985 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 9, 9] total 36 [2018-12-09 19:01:57,985 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:57,986 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-09 19:01:57,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-09 19:01:57,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=206, Invalid=1054, Unknown=0, NotChecked=0, Total=1260 [2018-12-09 19:01:57,986 INFO L87 Difference]: Start difference. First operand 249 states and 254 transitions. Second operand 28 states. [2018-12-09 19:01:58,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:58,404 INFO L93 Difference]: Finished difference Result 355 states and 365 transitions. [2018-12-09 19:01:58,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-09 19:01:58,404 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 191 [2018-12-09 19:01:58,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:58,405 INFO L225 Difference]: With dead ends: 355 [2018-12-09 19:01:58,405 INFO L226 Difference]: Without dead ends: 355 [2018-12-09 19:01:58,406 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 421 GetRequests, 367 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 566 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=747, Invalid=2333, Unknown=0, NotChecked=0, Total=3080 [2018-12-09 19:01:58,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2018-12-09 19:01:58,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 301. [2018-12-09 19:01:58,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 301 states. [2018-12-09 19:01:58,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 309 transitions. [2018-12-09 19:01:58,410 INFO L78 Accepts]: Start accepts. Automaton has 301 states and 309 transitions. Word has length 191 [2018-12-09 19:01:58,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:58,410 INFO L480 AbstractCegarLoop]: Abstraction has 301 states and 309 transitions. [2018-12-09 19:01:58,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-09 19:01:58,410 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 309 transitions. [2018-12-09 19:01:58,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2018-12-09 19:01:58,411 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:58,411 INFO L402 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:58,411 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:58,411 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:58,411 INFO L82 PathProgramCache]: Analyzing trace with hash 938276997, now seen corresponding path program 9 times [2018-12-09 19:01:58,411 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:58,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:58,412 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:58,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:58,412 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:58,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:58,519 INFO L134 CoverageAnalysis]: Checked inductivity of 2074 backedges. 891 proven. 83 refuted. 0 times theorem prover too weak. 1100 trivial. 0 not checked. [2018-12-09 19:01:58,520 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:58,520 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:58,520 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:58,520 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:58,520 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:58,520 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:58,526 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:01:58,526 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:01:58,567 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:01:58,567 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:01:58,569 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:58,734 INFO L134 CoverageAnalysis]: Checked inductivity of 2074 backedges. 834 proven. 369 refuted. 0 times theorem prover too weak. 871 trivial. 0 not checked. [2018-12-09 19:01:58,734 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:58,904 INFO L134 CoverageAnalysis]: Checked inductivity of 2074 backedges. 834 proven. 369 refuted. 0 times theorem prover too weak. 871 trivial. 0 not checked. [2018-12-09 19:01:58,918 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:58,918 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 21, 21] total 34 [2018-12-09 19:01:58,918 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:58,919 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-09 19:01:58,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-09 19:01:58,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=920, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 19:01:58,919 INFO L87 Difference]: Start difference. First operand 301 states and 309 transitions. Second operand 31 states. [2018-12-09 19:01:59,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:01:59,306 INFO L93 Difference]: Finished difference Result 405 states and 417 transitions. [2018-12-09 19:01:59,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-09 19:01:59,306 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 201 [2018-12-09 19:01:59,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:01:59,307 INFO L225 Difference]: With dead ends: 405 [2018-12-09 19:01:59,307 INFO L226 Difference]: Without dead ends: 405 [2018-12-09 19:01:59,308 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 434 GetRequests, 370 SyntacticMatches, 17 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 741 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=478, Invalid=1874, Unknown=0, NotChecked=0, Total=2352 [2018-12-09 19:01:59,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states. [2018-12-09 19:01:59,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 391. [2018-12-09 19:01:59,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 391 states. [2018-12-09 19:01:59,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 391 states and 403 transitions. [2018-12-09 19:01:59,313 INFO L78 Accepts]: Start accepts. Automaton has 391 states and 403 transitions. Word has length 201 [2018-12-09 19:01:59,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:01:59,313 INFO L480 AbstractCegarLoop]: Abstraction has 391 states and 403 transitions. [2018-12-09 19:01:59,313 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-09 19:01:59,313 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 403 transitions. [2018-12-09 19:01:59,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2018-12-09 19:01:59,314 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:01:59,314 INFO L402 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:01:59,315 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:01:59,315 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:01:59,315 INFO L82 PathProgramCache]: Analyzing trace with hash -951313496, now seen corresponding path program 10 times [2018-12-09 19:01:59,315 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:01:59,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:59,315 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:01:59,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:01:59,316 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:01:59,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:59,486 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1349 proven. 427 refuted. 0 times theorem prover too weak. 1149 trivial. 0 not checked. [2018-12-09 19:01:59,486 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:59,486 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:01:59,486 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:01:59,486 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:01:59,486 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:01:59,486 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:01:59,495 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:01:59,495 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:01:59,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:01:59,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:01:59,689 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1888 proven. 55 refuted. 0 times theorem prover too weak. 982 trivial. 0 not checked. [2018-12-09 19:01:59,689 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:01:59,893 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1475 proven. 220 refuted. 0 times theorem prover too weak. 1230 trivial. 0 not checked. [2018-12-09 19:01:59,908 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:01:59,908 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 14, 14] total 39 [2018-12-09 19:01:59,908 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:01:59,909 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-09 19:01:59,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-09 19:01:59,909 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=236, Invalid=1246, Unknown=0, NotChecked=0, Total=1482 [2018-12-09 19:01:59,909 INFO L87 Difference]: Start difference. First operand 391 states and 403 transitions. Second operand 33 states. [2018-12-09 19:02:00,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:00,345 INFO L93 Difference]: Finished difference Result 368 states and 376 transitions. [2018-12-09 19:02:00,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-12-09 19:02:00,345 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 237 [2018-12-09 19:02:00,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:00,347 INFO L225 Difference]: With dead ends: 368 [2018-12-09 19:02:00,347 INFO L226 Difference]: Without dead ends: 359 [2018-12-09 19:02:00,348 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 519 GetRequests, 451 SyntacticMatches, 7 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1245 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=660, Invalid=3246, Unknown=0, NotChecked=0, Total=3906 [2018-12-09 19:02:00,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 359 states. [2018-12-09 19:02:00,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 359 to 300. [2018-12-09 19:02:00,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 300 states. [2018-12-09 19:02:00,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 305 transitions. [2018-12-09 19:02:00,352 INFO L78 Accepts]: Start accepts. Automaton has 300 states and 305 transitions. Word has length 237 [2018-12-09 19:02:00,352 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:00,352 INFO L480 AbstractCegarLoop]: Abstraction has 300 states and 305 transitions. [2018-12-09 19:02:00,352 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-09 19:02:00,352 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 305 transitions. [2018-12-09 19:02:00,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-12-09 19:02:00,353 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:00,353 INFO L402 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 33, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:00,353 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:00,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:00,353 INFO L82 PathProgramCache]: Analyzing trace with hash 1428696967, now seen corresponding path program 11 times [2018-12-09 19:02:00,353 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:00,353 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:00,354 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:00,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:00,354 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:00,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:00,531 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1600 proven. 318 refuted. 0 times theorem prover too weak. 1175 trivial. 0 not checked. [2018-12-09 19:02:00,531 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:00,531 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:00,531 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:00,531 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:00,531 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:00,531 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:00,537 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:00,538 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:00,595 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-12-09 19:02:00,595 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:00,598 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:00,714 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1513 proven. 318 refuted. 0 times theorem prover too weak. 1262 trivial. 0 not checked. [2018-12-09 19:02:00,714 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:01,014 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1488 proven. 343 refuted. 0 times theorem prover too weak. 1262 trivial. 0 not checked. [2018-12-09 19:02:01,028 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:01,029 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 16, 16] total 47 [2018-12-09 19:02:01,029 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:01,029 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 19:02:01,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 19:02:01,029 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=368, Invalid=1794, Unknown=0, NotChecked=0, Total=2162 [2018-12-09 19:02:01,030 INFO L87 Difference]: Start difference. First operand 300 states and 305 transitions. Second operand 32 states. [2018-12-09 19:02:01,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:01,419 INFO L93 Difference]: Finished difference Result 362 states and 369 transitions. [2018-12-09 19:02:01,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 19:02:01,419 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 242 [2018-12-09 19:02:01,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:01,420 INFO L225 Difference]: With dead ends: 362 [2018-12-09 19:02:01,420 INFO L226 Difference]: Without dead ends: 362 [2018-12-09 19:02:01,421 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 527 GetRequests, 459 SyntacticMatches, 1 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1244 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1109, Invalid=3583, Unknown=0, NotChecked=0, Total=4692 [2018-12-09 19:02:01,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states. [2018-12-09 19:02:01,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 352. [2018-12-09 19:02:01,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2018-12-09 19:02:01,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 359 transitions. [2018-12-09 19:02:01,424 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 359 transitions. Word has length 242 [2018-12-09 19:02:01,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:01,424 INFO L480 AbstractCegarLoop]: Abstraction has 352 states and 359 transitions. [2018-12-09 19:02:01,424 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 19:02:01,424 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 359 transitions. [2018-12-09 19:02:01,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 248 [2018-12-09 19:02:01,425 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:01,425 INFO L402 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:01,425 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:01,425 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:01,425 INFO L82 PathProgramCache]: Analyzing trace with hash -300291550, now seen corresponding path program 12 times [2018-12-09 19:02:01,426 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:01,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:01,426 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:01,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:01,426 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:01,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:01,519 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1078 proven. 109 refuted. 0 times theorem prover too weak. 2079 trivial. 0 not checked. [2018-12-09 19:02:01,519 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:01,520 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:01,520 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:01,520 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:01,520 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:01,520 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:01,526 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:01,527 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:01,576 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:01,576 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:01,579 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:01,670 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1047 proven. 119 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-09 19:02:01,671 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:01,794 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1047 proven. 119 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-09 19:02:01,809 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:01,809 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9, 9] total 29 [2018-12-09 19:02:01,810 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:01,810 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-12-09 19:02:01,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-12-09 19:02:01,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=710, Unknown=0, NotChecked=0, Total=870 [2018-12-09 19:02:01,810 INFO L87 Difference]: Start difference. First operand 352 states and 359 transitions. Second operand 22 states. [2018-12-09 19:02:02,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:02,258 INFO L93 Difference]: Finished difference Result 481 states and 494 transitions. [2018-12-09 19:02:02,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 19:02:02,259 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 247 [2018-12-09 19:02:02,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:02,260 INFO L225 Difference]: With dead ends: 481 [2018-12-09 19:02:02,260 INFO L226 Difference]: Without dead ends: 481 [2018-12-09 19:02:02,260 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 518 GetRequests, 478 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 351 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=354, Invalid=1368, Unknown=0, NotChecked=0, Total=1722 [2018-12-09 19:02:02,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-12-09 19:02:02,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 452. [2018-12-09 19:02:02,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 452 states. [2018-12-09 19:02:02,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 452 states to 452 states and 464 transitions. [2018-12-09 19:02:02,265 INFO L78 Accepts]: Start accepts. Automaton has 452 states and 464 transitions. Word has length 247 [2018-12-09 19:02:02,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:02,265 INFO L480 AbstractCegarLoop]: Abstraction has 452 states and 464 transitions. [2018-12-09 19:02:02,265 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-12-09 19:02:02,265 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 464 transitions. [2018-12-09 19:02:02,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-12-09 19:02:02,267 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:02,267 INFO L402 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 41, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:02,267 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:02,267 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:02,267 INFO L82 PathProgramCache]: Analyzing trace with hash -1077850677, now seen corresponding path program 13 times [2018-12-09 19:02:02,267 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:02,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:02,268 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:02,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:02,268 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:02,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:02,480 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2076 proven. 584 refuted. 0 times theorem prover too weak. 2068 trivial. 0 not checked. [2018-12-09 19:02:02,480 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:02,480 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:02,480 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:02,481 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:02,481 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:02,481 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:02,488 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:02,488 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:02,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:02,543 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:02,737 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2964 proven. 81 refuted. 0 times theorem prover too weak. 1683 trivial. 0 not checked. [2018-12-09 19:02:02,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:02,961 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2260 proven. 308 refuted. 0 times theorem prover too weak. 2160 trivial. 0 not checked. [2018-12-09 19:02:02,975 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:02,976 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 16, 16] total 44 [2018-12-09 19:02:02,976 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:02,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-09 19:02:02,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-09 19:02:02,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=1592, Unknown=0, NotChecked=0, Total=1892 [2018-12-09 19:02:02,977 INFO L87 Difference]: Start difference. First operand 452 states and 464 transitions. Second operand 37 states. [2018-12-09 19:02:03,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:03,567 INFO L93 Difference]: Finished difference Result 372 states and 377 transitions. [2018-12-09 19:02:03,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-12-09 19:02:03,567 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 293 [2018-12-09 19:02:03,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:03,568 INFO L225 Difference]: With dead ends: 372 [2018-12-09 19:02:03,568 INFO L226 Difference]: Without dead ends: 363 [2018-12-09 19:02:03,568 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 637 GetRequests, 559 SyntacticMatches, 8 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1700 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=850, Invalid=4262, Unknown=0, NotChecked=0, Total=5112 [2018-12-09 19:02:03,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363 states. [2018-12-09 19:02:03,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363 to 356. [2018-12-09 19:02:03,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 356 states. [2018-12-09 19:02:03,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356 states to 356 states and 361 transitions. [2018-12-09 19:02:03,572 INFO L78 Accepts]: Start accepts. Automaton has 356 states and 361 transitions. Word has length 293 [2018-12-09 19:02:03,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:03,572 INFO L480 AbstractCegarLoop]: Abstraction has 356 states and 361 transitions. [2018-12-09 19:02:03,572 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-09 19:02:03,572 INFO L276 IsEmpty]: Start isEmpty. Operand 356 states and 361 transitions. [2018-12-09 19:02:03,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2018-12-09 19:02:03,573 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:03,573 INFO L402 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 42, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:03,573 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:03,573 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:03,573 INFO L82 PathProgramCache]: Analyzing trace with hash -1652634800, now seen corresponding path program 14 times [2018-12-09 19:02:03,573 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:03,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:03,574 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:03,574 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:03,574 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:03,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:03,776 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 2419 proven. 423 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-09 19:02:03,776 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:03,776 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:03,776 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:03,776 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:03,776 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:03,776 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:03,782 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:03,782 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:03,845 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-12-09 19:02:03,845 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:03,848 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:03,977 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 1491 proven. 156 refuted. 0 times theorem prover too weak. 3295 trivial. 0 not checked. [2018-12-09 19:02:03,977 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:04,202 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 1491 proven. 156 refuted. 0 times theorem prover too weak. 3295 trivial. 0 not checked. [2018-12-09 19:02:04,217 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:04,218 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 11, 11] total 44 [2018-12-09 19:02:04,218 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:04,218 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-12-09 19:02:04,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-12-09 19:02:04,218 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=312, Invalid=1580, Unknown=0, NotChecked=0, Total=1892 [2018-12-09 19:02:04,218 INFO L87 Difference]: Start difference. First operand 356 states and 361 transitions. Second operand 34 states. [2018-12-09 19:02:04,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:04,796 INFO L93 Difference]: Finished difference Result 431 states and 439 transitions. [2018-12-09 19:02:04,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-09 19:02:04,796 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 298 [2018-12-09 19:02:04,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:04,797 INFO L225 Difference]: With dead ends: 431 [2018-12-09 19:02:04,797 INFO L226 Difference]: Without dead ends: 431 [2018-12-09 19:02:04,798 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 645 GetRequests, 577 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 939 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1185, Invalid=3645, Unknown=0, NotChecked=0, Total=4830 [2018-12-09 19:02:04,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-12-09 19:02:04,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 418. [2018-12-09 19:02:04,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 418 states. [2018-12-09 19:02:04,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 418 states to 418 states and 426 transitions. [2018-12-09 19:02:04,801 INFO L78 Accepts]: Start accepts. Automaton has 418 states and 426 transitions. Word has length 298 [2018-12-09 19:02:04,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:04,802 INFO L480 AbstractCegarLoop]: Abstraction has 418 states and 426 transitions. [2018-12-09 19:02:04,802 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-12-09 19:02:04,802 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 426 transitions. [2018-12-09 19:02:04,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2018-12-09 19:02:04,803 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:04,803 INFO L402 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 44, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:04,803 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:04,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:04,803 INFO L82 PathProgramCache]: Analyzing trace with hash 699884682, now seen corresponding path program 15 times [2018-12-09 19:02:04,803 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:04,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:04,804 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:04,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:04,804 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:04,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:04,987 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1903 proven. 157 refuted. 0 times theorem prover too weak. 3325 trivial. 0 not checked. [2018-12-09 19:02:04,987 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:04,987 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:04,987 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:04,987 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:04,987 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:04,987 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:04,993 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:04,993 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:05,036 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:05,037 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:05,040 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:05,270 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1832 proven. 634 refuted. 0 times theorem prover too weak. 2919 trivial. 0 not checked. [2018-12-09 19:02:05,271 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:05,473 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1832 proven. 634 refuted. 0 times theorem prover too weak. 2919 trivial. 0 not checked. [2018-12-09 19:02:05,488 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:05,488 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 25, 25] total 40 [2018-12-09 19:02:05,488 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:05,488 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-09 19:02:05,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-09 19:02:05,489 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=284, Invalid=1276, Unknown=0, NotChecked=0, Total=1560 [2018-12-09 19:02:05,489 INFO L87 Difference]: Start difference. First operand 418 states and 426 transitions. Second operand 37 states. [2018-12-09 19:02:06,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:06,036 INFO L93 Difference]: Finished difference Result 542 states and 554 transitions. [2018-12-09 19:02:06,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-09 19:02:06,036 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 308 [2018-12-09 19:02:06,036 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:06,038 INFO L225 Difference]: With dead ends: 542 [2018-12-09 19:02:06,038 INFO L226 Difference]: Without dead ends: 542 [2018-12-09 19:02:06,039 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 578 SyntacticMatches, 21 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1101 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=698, Invalid=2724, Unknown=0, NotChecked=0, Total=3422 [2018-12-09 19:02:06,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 542 states. [2018-12-09 19:02:06,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 542 to 528. [2018-12-09 19:02:06,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 528 states. [2018-12-09 19:02:06,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 528 states to 528 states and 540 transitions. [2018-12-09 19:02:06,044 INFO L78 Accepts]: Start accepts. Automaton has 528 states and 540 transitions. Word has length 308 [2018-12-09 19:02:06,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:06,045 INFO L480 AbstractCegarLoop]: Abstraction has 528 states and 540 transitions. [2018-12-09 19:02:06,045 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-09 19:02:06,045 INFO L276 IsEmpty]: Start isEmpty. Operand 528 states and 540 transitions. [2018-12-09 19:02:06,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2018-12-09 19:02:06,046 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:06,047 INFO L402 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 51, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:06,047 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:06,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:06,047 INFO L82 PathProgramCache]: Analyzing trace with hash 602331853, now seen corresponding path program 16 times [2018-12-09 19:02:06,047 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:06,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:06,048 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:06,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:06,048 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:06,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:06,279 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 3025 proven. 766 refuted. 0 times theorem prover too weak. 3434 trivial. 0 not checked. [2018-12-09 19:02:06,280 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:06,280 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:06,280 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:06,280 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:06,280 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:06,280 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:06,288 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:06,288 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:06,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:06,344 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:06,563 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 4376 proven. 112 refuted. 0 times theorem prover too weak. 2737 trivial. 0 not checked. [2018-12-09 19:02:06,563 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:06,859 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 3278 proven. 411 refuted. 0 times theorem prover too weak. 3536 trivial. 0 not checked. [2018-12-09 19:02:06,874 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:06,874 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 18, 18] total 49 [2018-12-09 19:02:06,874 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:06,874 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-09 19:02:06,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-09 19:02:06,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=372, Invalid=1980, Unknown=0, NotChecked=0, Total=2352 [2018-12-09 19:02:06,875 INFO L87 Difference]: Start difference. First operand 528 states and 540 transitions. Second operand 41 states. [2018-12-09 19:02:07,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:07,584 INFO L93 Difference]: Finished difference Result 433 states and 438 transitions. [2018-12-09 19:02:07,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-09 19:02:07,584 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 354 [2018-12-09 19:02:07,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:07,586 INFO L225 Difference]: With dead ends: 433 [2018-12-09 19:02:07,586 INFO L226 Difference]: Without dead ends: 424 [2018-12-09 19:02:07,587 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 765 GetRequests, 677 SyntacticMatches, 9 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2225 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1065, Invalid=5415, Unknown=0, NotChecked=0, Total=6480 [2018-12-09 19:02:07,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states. [2018-12-09 19:02:07,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 417. [2018-12-09 19:02:07,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 417 states. [2018-12-09 19:02:07,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417 states to 417 states and 422 transitions. [2018-12-09 19:02:07,592 INFO L78 Accepts]: Start accepts. Automaton has 417 states and 422 transitions. Word has length 354 [2018-12-09 19:02:07,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:07,593 INFO L480 AbstractCegarLoop]: Abstraction has 417 states and 422 transitions. [2018-12-09 19:02:07,593 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-09 19:02:07,593 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 422 transitions. [2018-12-09 19:02:07,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 360 [2018-12-09 19:02:07,595 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:07,595 INFO L402 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 52, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:07,595 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:07,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:07,596 INFO L82 PathProgramCache]: Analyzing trace with hash -1109948414, now seen corresponding path program 17 times [2018-12-09 19:02:07,596 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:07,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:07,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:07,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:07,596 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:07,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:07,835 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 3475 proven. 543 refuted. 0 times theorem prover too weak. 3472 trivial. 0 not checked. [2018-12-09 19:02:07,835 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:07,835 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:07,835 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:07,835 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:07,835 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:07,835 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:07,843 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:07,843 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:07,904 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-12-09 19:02:07,904 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:07,906 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:08,073 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 2101 proven. 198 refuted. 0 times theorem prover too weak. 5191 trivial. 0 not checked. [2018-12-09 19:02:08,073 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:08,301 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 2101 proven. 198 refuted. 0 times theorem prover too weak. 5191 trivial. 0 not checked. [2018-12-09 19:02:08,315 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:08,316 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 12, 12] total 48 [2018-12-09 19:02:08,316 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:08,316 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-09 19:02:08,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-09 19:02:08,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=374, Invalid=1882, Unknown=0, NotChecked=0, Total=2256 [2018-12-09 19:02:08,316 INFO L87 Difference]: Start difference. First operand 417 states and 422 transitions. Second operand 37 states. [2018-12-09 19:02:09,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:09,024 INFO L93 Difference]: Finished difference Result 497 states and 505 transitions. [2018-12-09 19:02:09,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-12-09 19:02:09,024 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 359 [2018-12-09 19:02:09,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:09,025 INFO L225 Difference]: With dead ends: 497 [2018-12-09 19:02:09,026 INFO L226 Difference]: Without dead ends: 497 [2018-12-09 19:02:09,026 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 772 GetRequests, 697 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1160 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1443, Invalid=4409, Unknown=0, NotChecked=0, Total=5852 [2018-12-09 19:02:09,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 497 states. [2018-12-09 19:02:09,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 497 to 484. [2018-12-09 19:02:09,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-12-09 19:02:09,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 492 transitions. [2018-12-09 19:02:09,032 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 492 transitions. Word has length 359 [2018-12-09 19:02:09,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:09,033 INFO L480 AbstractCegarLoop]: Abstraction has 484 states and 492 transitions. [2018-12-09 19:02:09,033 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-09 19:02:09,033 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 492 transitions. [2018-12-09 19:02:09,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 370 [2018-12-09 19:02:09,035 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:09,035 INFO L402 BasicCegarLoop]: trace histogram [55, 54, 54, 54, 54, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:09,035 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:09,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:09,035 INFO L82 PathProgramCache]: Analyzing trace with hash 37339976, now seen corresponding path program 18 times [2018-12-09 19:02:09,035 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:09,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:09,036 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:09,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:09,036 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:09,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:09,234 INFO L134 CoverageAnalysis]: Checked inductivity of 8035 backedges. 2610 proven. 203 refuted. 0 times theorem prover too weak. 5222 trivial. 0 not checked. [2018-12-09 19:02:09,235 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:09,235 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:09,235 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:09,235 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:09,235 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:09,235 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:09,241 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:09,241 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:09,300 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:09,301 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:09,305 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:09,549 INFO L134 CoverageAnalysis]: Checked inductivity of 8035 backedges. 2532 proven. 792 refuted. 0 times theorem prover too weak. 4711 trivial. 0 not checked. [2018-12-09 19:02:09,549 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:09,818 INFO L134 CoverageAnalysis]: Checked inductivity of 8035 backedges. 2532 proven. 792 refuted. 0 times theorem prover too weak. 4711 trivial. 0 not checked. [2018-12-09 19:02:09,833 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:09,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 27, 27] total 43 [2018-12-09 19:02:09,833 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:09,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-12-09 19:02:09,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-12-09 19:02:09,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=331, Invalid=1475, Unknown=0, NotChecked=0, Total=1806 [2018-12-09 19:02:09,834 INFO L87 Difference]: Start difference. First operand 484 states and 492 transitions. Second operand 40 states. [2018-12-09 19:02:10,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:10,442 INFO L93 Difference]: Finished difference Result 618 states and 630 transitions. [2018-12-09 19:02:10,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-12-09 19:02:10,443 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 369 [2018-12-09 19:02:10,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:10,444 INFO L225 Difference]: With dead ends: 618 [2018-12-09 19:02:10,444 INFO L226 Difference]: Without dead ends: 618 [2018-12-09 19:02:10,444 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 782 GetRequests, 697 SyntacticMatches, 23 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1305 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=826, Invalid=3206, Unknown=0, NotChecked=0, Total=4032 [2018-12-09 19:02:10,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 618 states. [2018-12-09 19:02:10,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 618 to 604. [2018-12-09 19:02:10,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 604 states. [2018-12-09 19:02:10,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 604 states to 604 states and 616 transitions. [2018-12-09 19:02:10,449 INFO L78 Accepts]: Start accepts. Automaton has 604 states and 616 transitions. Word has length 369 [2018-12-09 19:02:10,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:10,450 INFO L480 AbstractCegarLoop]: Abstraction has 604 states and 616 transitions. [2018-12-09 19:02:10,450 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-12-09 19:02:10,450 INFO L276 IsEmpty]: Start isEmpty. Operand 604 states and 616 transitions. [2018-12-09 19:02:10,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 421 [2018-12-09 19:02:10,451 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:10,451 INFO L402 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 62, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:10,451 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:10,451 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:10,451 INFO L82 PathProgramCache]: Analyzing trace with hash -392113456, now seen corresponding path program 19 times [2018-12-09 19:02:10,451 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:10,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:10,452 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:10,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:10,452 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:10,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:10,727 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4226 proven. 973 refuted. 0 times theorem prover too weak. 5370 trivial. 0 not checked. [2018-12-09 19:02:10,727 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:10,727 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:10,727 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:10,727 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:10,727 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:10,727 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:10,733 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:10,733 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:10,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:10,802 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:11,091 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 6169 proven. 148 refuted. 0 times theorem prover too weak. 4252 trivial. 0 not checked. [2018-12-09 19:02:11,091 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:11,459 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4559 proven. 529 refuted. 0 times theorem prover too weak. 5481 trivial. 0 not checked. [2018-12-09 19:02:11,473 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:11,474 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 20, 20] total 54 [2018-12-09 19:02:11,474 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:11,474 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-12-09 19:02:11,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-12-09 19:02:11,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=452, Invalid=2410, Unknown=0, NotChecked=0, Total=2862 [2018-12-09 19:02:11,475 INFO L87 Difference]: Start difference. First operand 604 states and 616 transitions. Second operand 45 states. [2018-12-09 19:02:12,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:12,269 INFO L93 Difference]: Finished difference Result 499 states and 504 transitions. [2018-12-09 19:02:12,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-09 19:02:12,269 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 420 [2018-12-09 19:02:12,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:12,270 INFO L225 Difference]: With dead ends: 499 [2018-12-09 19:02:12,270 INFO L226 Difference]: Without dead ends: 490 [2018-12-09 19:02:12,270 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 903 GetRequests, 805 SyntacticMatches, 10 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2820 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1305, Invalid=6705, Unknown=0, NotChecked=0, Total=8010 [2018-12-09 19:02:12,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2018-12-09 19:02:12,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 483. [2018-12-09 19:02:12,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 483 states. [2018-12-09 19:02:12,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 483 states to 483 states and 488 transitions. [2018-12-09 19:02:12,273 INFO L78 Accepts]: Start accepts. Automaton has 483 states and 488 transitions. Word has length 420 [2018-12-09 19:02:12,274 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:12,274 INFO L480 AbstractCegarLoop]: Abstraction has 483 states and 488 transitions. [2018-12-09 19:02:12,274 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-12-09 19:02:12,274 INFO L276 IsEmpty]: Start isEmpty. Operand 483 states and 488 transitions. [2018-12-09 19:02:12,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 426 [2018-12-09 19:02:12,275 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:12,275 INFO L402 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 63, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:12,275 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:12,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:12,275 INFO L82 PathProgramCache]: Analyzing trace with hash 321506027, now seen corresponding path program 20 times [2018-12-09 19:02:12,275 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:12,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:12,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:12,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:12,276 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:12,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:12,530 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4798 proven. 678 refuted. 0 times theorem prover too weak. 5414 trivial. 0 not checked. [2018-12-09 19:02:12,531 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:12,531 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:12,531 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:12,531 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:12,531 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:12,531 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:12,537 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:12,537 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:12,617 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-12-09 19:02:12,618 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:12,622 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:12,871 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4600 proven. 678 refuted. 0 times theorem prover too weak. 5612 trivial. 0 not checked. [2018-12-09 19:02:12,871 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:13,293 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4563 proven. 715 refuted. 0 times theorem prover too weak. 5612 trivial. 0 not checked. [2018-12-09 19:02:13,308 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:13,308 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 19, 19] total 59 [2018-12-09 19:02:13,308 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:13,309 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-09 19:02:13,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-09 19:02:13,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=632, Invalid=2790, Unknown=0, NotChecked=0, Total=3422 [2018-12-09 19:02:13,309 INFO L87 Difference]: Start difference. First operand 483 states and 488 transitions. Second operand 41 states. [2018-12-09 19:02:13,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:13,918 INFO L93 Difference]: Finished difference Result 560 states and 567 transitions. [2018-12-09 19:02:13,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-12-09 19:02:13,918 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 425 [2018-12-09 19:02:13,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:13,919 INFO L225 Difference]: With dead ends: 560 [2018-12-09 19:02:13,919 INFO L226 Difference]: Without dead ends: 560 [2018-12-09 19:02:13,920 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 908 GetRequests, 819 SyntacticMatches, 1 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2210 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1979, Invalid=6031, Unknown=0, NotChecked=0, Total=8010 [2018-12-09 19:02:13,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 560 states. [2018-12-09 19:02:13,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 560 to 550. [2018-12-09 19:02:13,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2018-12-09 19:02:13,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 557 transitions. [2018-12-09 19:02:13,923 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 557 transitions. Word has length 425 [2018-12-09 19:02:13,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:13,924 INFO L480 AbstractCegarLoop]: Abstraction has 550 states and 557 transitions. [2018-12-09 19:02:13,924 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-09 19:02:13,924 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 557 transitions. [2018-12-09 19:02:13,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2018-12-09 19:02:13,925 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:13,925 INFO L402 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 64, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:13,925 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:13,925 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:13,925 INFO L82 PathProgramCache]: Analyzing trace with hash -867500726, now seen corresponding path program 21 times [2018-12-09 19:02:13,925 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:13,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:13,926 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:13,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:13,926 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:13,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:14,092 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2995 proven. 244 refuted. 0 times theorem prover too weak. 7977 trivial. 0 not checked. [2018-12-09 19:02:14,093 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:14,093 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:14,093 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:14,093 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:14,093 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:14,093 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:14,098 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:14,099 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:14,184 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:14,184 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:14,189 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:14,330 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2907 proven. 245 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-09 19:02:14,330 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:14,523 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2907 proven. 245 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-09 19:02:14,538 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:14,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 12, 12] total 39 [2018-12-09 19:02:14,538 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:14,539 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-09 19:02:14,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-09 19:02:14,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=269, Invalid=1291, Unknown=0, NotChecked=0, Total=1560 [2018-12-09 19:02:14,539 INFO L87 Difference]: Start difference. First operand 550 states and 557 transitions. Second operand 29 states. [2018-12-09 19:02:15,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:15,106 INFO L93 Difference]: Finished difference Result 709 states and 722 transitions. [2018-12-09 19:02:15,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-12-09 19:02:15,106 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 430 [2018-12-09 19:02:15,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:15,107 INFO L225 Difference]: With dead ends: 709 [2018-12-09 19:02:15,107 INFO L226 Difference]: Without dead ends: 709 [2018-12-09 19:02:15,108 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 891 GetRequests, 838 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 651 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=569, Invalid=2401, Unknown=0, NotChecked=0, Total=2970 [2018-12-09 19:02:15,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 709 states. [2018-12-09 19:02:15,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 709 to 680. [2018-12-09 19:02:15,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 680 states. [2018-12-09 19:02:15,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 692 transitions. [2018-12-09 19:02:15,112 INFO L78 Accepts]: Start accepts. Automaton has 680 states and 692 transitions. Word has length 430 [2018-12-09 19:02:15,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:15,112 INFO L480 AbstractCegarLoop]: Abstraction has 680 states and 692 transitions. [2018-12-09 19:02:15,112 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-09 19:02:15,112 INFO L276 IsEmpty]: Start isEmpty. Operand 680 states and 692 transitions. [2018-12-09 19:02:15,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 492 [2018-12-09 19:02:15,115 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:15,115 INFO L402 BasicCegarLoop]: trace histogram [75, 74, 74, 74, 74, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:15,115 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:15,115 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:15,116 INFO L82 PathProgramCache]: Analyzing trace with hash -666277688, now seen corresponding path program 22 times [2018-12-09 19:02:15,116 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:15,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:15,116 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:15,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:15,116 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:15,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:15,462 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 5709 proven. 1205 refuted. 0 times theorem prover too weak. 8014 trivial. 0 not checked. [2018-12-09 19:02:15,463 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:15,463 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:15,463 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:15,463 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:15,463 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:15,463 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:15,468 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:15,468 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:15,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:15,541 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:15,881 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 8388 proven. 189 refuted. 0 times theorem prover too weak. 6351 trivial. 0 not checked. [2018-12-09 19:02:15,882 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:16,311 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 6133 proven. 662 refuted. 0 times theorem prover too weak. 8133 trivial. 0 not checked. [2018-12-09 19:02:16,326 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:16,326 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 22, 22] total 59 [2018-12-09 19:02:16,326 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:16,327 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-09 19:02:16,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-09 19:02:16,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=2882, Unknown=0, NotChecked=0, Total=3422 [2018-12-09 19:02:16,327 INFO L87 Difference]: Start difference. First operand 680 states and 692 transitions. Second operand 49 states. [2018-12-09 19:02:17,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:17,159 INFO L93 Difference]: Finished difference Result 570 states and 575 transitions. [2018-12-09 19:02:17,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-12-09 19:02:17,160 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 491 [2018-12-09 19:02:17,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:17,161 INFO L225 Difference]: With dead ends: 570 [2018-12-09 19:02:17,161 INFO L226 Difference]: Without dead ends: 561 [2018-12-09 19:02:17,162 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1051 GetRequests, 943 SyntacticMatches, 11 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3485 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1570, Invalid=8132, Unknown=0, NotChecked=0, Total=9702 [2018-12-09 19:02:17,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states. [2018-12-09 19:02:17,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 554. [2018-12-09 19:02:17,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 554 states. [2018-12-09 19:02:17,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 559 transitions. [2018-12-09 19:02:17,167 INFO L78 Accepts]: Start accepts. Automaton has 554 states and 559 transitions. Word has length 491 [2018-12-09 19:02:17,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:17,168 INFO L480 AbstractCegarLoop]: Abstraction has 554 states and 559 transitions. [2018-12-09 19:02:17,168 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-09 19:02:17,168 INFO L276 IsEmpty]: Start isEmpty. Operand 554 states and 559 transitions. [2018-12-09 19:02:17,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2018-12-09 19:02:17,170 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:17,170 INFO L402 BasicCegarLoop]: trace histogram [76, 75, 75, 75, 75, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:17,171 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:17,171 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:17,171 INFO L82 PathProgramCache]: Analyzing trace with hash -1675425945, now seen corresponding path program 23 times [2018-12-09 19:02:17,171 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:17,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:17,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:17,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:17,172 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:17,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:17,525 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6418 proven. 828 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-09 19:02:17,525 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:17,525 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:17,526 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:17,526 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:17,526 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:17,526 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:17,531 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:17,531 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:17,613 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-12-09 19:02:17,614 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:17,617 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:17,885 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6173 proven. 828 refuted. 0 times theorem prover too weak. 8309 trivial. 0 not checked. [2018-12-09 19:02:17,885 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:18,401 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6132 proven. 869 refuted. 0 times theorem prover too weak. 8309 trivial. 0 not checked. [2018-12-09 19:02:18,415 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:18,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 20, 20] total 63 [2018-12-09 19:02:18,415 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:18,416 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-12-09 19:02:18,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-12-09 19:02:18,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=738, Invalid=3168, Unknown=0, NotChecked=0, Total=3906 [2018-12-09 19:02:18,416 INFO L87 Difference]: Start difference. First operand 554 states and 559 transitions. Second operand 44 states. [2018-12-09 19:02:19,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:19,196 INFO L93 Difference]: Finished difference Result 636 states and 643 transitions. [2018-12-09 19:02:19,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-12-09 19:02:19,197 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 496 [2018-12-09 19:02:19,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:19,198 INFO L225 Difference]: With dead ends: 636 [2018-12-09 19:02:19,198 INFO L226 Difference]: Without dead ends: 636 [2018-12-09 19:02:19,198 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1055 GetRequests, 959 SyntacticMatches, 1 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2592 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2327, Invalid=6985, Unknown=0, NotChecked=0, Total=9312 [2018-12-09 19:02:19,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states. [2018-12-09 19:02:19,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 626. [2018-12-09 19:02:19,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 626 states. [2018-12-09 19:02:19,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 633 transitions. [2018-12-09 19:02:19,202 INFO L78 Accepts]: Start accepts. Automaton has 626 states and 633 transitions. Word has length 496 [2018-12-09 19:02:19,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:19,203 INFO L480 AbstractCegarLoop]: Abstraction has 626 states and 633 transitions. [2018-12-09 19:02:19,203 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-12-09 19:02:19,203 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 633 transitions. [2018-12-09 19:02:19,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 502 [2018-12-09 19:02:19,204 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:19,204 INFO L402 BasicCegarLoop]: trace histogram [77, 76, 76, 76, 76, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:19,204 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:19,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:19,205 INFO L82 PathProgramCache]: Analyzing trace with hash -422752958, now seen corresponding path program 24 times [2018-12-09 19:02:19,205 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:19,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:19,205 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:19,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:19,205 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:19,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:19,377 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3876 proven. 301 refuted. 0 times theorem prover too weak. 11520 trivial. 0 not checked. [2018-12-09 19:02:19,377 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:19,377 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:19,378 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:19,378 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:19,378 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:19,378 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:19,384 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:19,384 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:19,539 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:19,539 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:19,544 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:19,701 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3825 proven. 297 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2018-12-09 19:02:19,701 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:19,942 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3825 proven. 297 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2018-12-09 19:02:19,957 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:19,958 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13, 13] total 41 [2018-12-09 19:02:19,958 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:19,958 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-09 19:02:19,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-09 19:02:19,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=1416, Unknown=0, NotChecked=0, Total=1722 [2018-12-09 19:02:19,958 INFO L87 Difference]: Start difference. First operand 626 states and 633 transitions. Second operand 30 states. [2018-12-09 19:02:20,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:20,600 INFO L93 Difference]: Finished difference Result 795 states and 808 transitions. [2018-12-09 19:02:20,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-12-09 19:02:20,601 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 501 [2018-12-09 19:02:20,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:20,602 INFO L225 Difference]: With dead ends: 795 [2018-12-09 19:02:20,602 INFO L226 Difference]: Without dead ends: 795 [2018-12-09 19:02:20,602 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1034 GetRequests, 978 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 745 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=632, Invalid=2674, Unknown=0, NotChecked=0, Total=3306 [2018-12-09 19:02:20,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 795 states. [2018-12-09 19:02:20,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 795 to 766. [2018-12-09 19:02:20,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2018-12-09 19:02:20,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 778 transitions. [2018-12-09 19:02:20,607 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 778 transitions. Word has length 501 [2018-12-09 19:02:20,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:20,607 INFO L480 AbstractCegarLoop]: Abstraction has 766 states and 778 transitions. [2018-12-09 19:02:20,607 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-09 19:02:20,607 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 778 transitions. [2018-12-09 19:02:20,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 568 [2018-12-09 19:02:20,609 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:20,609 INFO L402 BasicCegarLoop]: trace histogram [88, 87, 87, 87, 87, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:20,609 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:20,609 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:20,609 INFO L82 PathProgramCache]: Analyzing trace with hash -1064351445, now seen corresponding path program 25 times [2018-12-09 19:02:20,609 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:20,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:20,610 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:20,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:20,610 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:20,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:21,007 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 7504 proven. 1462 refuted. 0 times theorem prover too weak. 11519 trivial. 0 not checked. [2018-12-09 19:02:21,007 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:21,007 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:21,008 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:21,008 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:21,008 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:21,008 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:21,016 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:21,016 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:21,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:21,112 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:21,495 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 11078 proven. 235 refuted. 0 times theorem prover too weak. 9172 trivial. 0 not checked. [2018-12-09 19:02:21,496 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:22,010 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 8030 proven. 810 refuted. 0 times theorem prover too weak. 11645 trivial. 0 not checked. [2018-12-09 19:02:22,025 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:22,025 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 24, 24] total 64 [2018-12-09 19:02:22,025 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:22,026 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-12-09 19:02:22,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-12-09 19:02:22,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=636, Invalid=3396, Unknown=0, NotChecked=0, Total=4032 [2018-12-09 19:02:22,026 INFO L87 Difference]: Start difference. First operand 766 states and 778 transitions. Second operand 53 states. [2018-12-09 19:02:23,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:23,082 INFO L93 Difference]: Finished difference Result 646 states and 651 transitions. [2018-12-09 19:02:23,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-12-09 19:02:23,082 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 567 [2018-12-09 19:02:23,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:23,083 INFO L225 Difference]: With dead ends: 646 [2018-12-09 19:02:23,083 INFO L226 Difference]: Without dead ends: 637 [2018-12-09 19:02:23,084 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1209 GetRequests, 1091 SyntacticMatches, 12 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4220 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1860, Invalid=9696, Unknown=0, NotChecked=0, Total=11556 [2018-12-09 19:02:23,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 637 states. [2018-12-09 19:02:23,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 637 to 630. [2018-12-09 19:02:23,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 630 states. [2018-12-09 19:02:23,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 630 states to 630 states and 635 transitions. [2018-12-09 19:02:23,088 INFO L78 Accepts]: Start accepts. Automaton has 630 states and 635 transitions. Word has length 567 [2018-12-09 19:02:23,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:23,088 INFO L480 AbstractCegarLoop]: Abstraction has 630 states and 635 transitions. [2018-12-09 19:02:23,088 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-12-09 19:02:23,088 INFO L276 IsEmpty]: Start isEmpty. Operand 630 states and 635 transitions. [2018-12-09 19:02:23,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 573 [2018-12-09 19:02:23,090 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:23,091 INFO L402 BasicCegarLoop]: trace histogram [89, 88, 88, 88, 88, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:23,091 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:23,091 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:23,091 INFO L82 PathProgramCache]: Analyzing trace with hash -347201808, now seen corresponding path program 26 times [2018-12-09 19:02:23,091 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:23,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:23,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:23,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:23,091 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:23,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:23,459 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8365 proven. 993 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2018-12-09 19:02:23,459 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:23,459 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:23,459 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:23,459 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:23,459 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:23,460 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:23,465 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:23,465 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:23,563 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-12-09 19:02:23,563 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:23,567 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:23,874 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8068 proven. 993 refuted. 0 times theorem prover too weak. 11872 trivial. 0 not checked. [2018-12-09 19:02:23,874 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:24,431 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8023 proven. 1038 refuted. 0 times theorem prover too weak. 11872 trivial. 0 not checked. [2018-12-09 19:02:24,446 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:24,446 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 21, 21] total 67 [2018-12-09 19:02:24,446 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:24,446 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-12-09 19:02:24,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-12-09 19:02:24,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=853, Invalid=3569, Unknown=0, NotChecked=0, Total=4422 [2018-12-09 19:02:24,447 INFO L87 Difference]: Start difference. First operand 630 states and 635 transitions. Second operand 47 states. [2018-12-09 19:02:25,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:25,235 INFO L93 Difference]: Finished difference Result 717 states and 724 transitions. [2018-12-09 19:02:25,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-12-09 19:02:25,235 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 572 [2018-12-09 19:02:25,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:25,236 INFO L225 Difference]: With dead ends: 717 [2018-12-09 19:02:25,236 INFO L226 Difference]: Without dead ends: 717 [2018-12-09 19:02:25,237 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1212 GetRequests, 1109 SyntacticMatches, 1 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3004 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2704, Invalid=8008, Unknown=0, NotChecked=0, Total=10712 [2018-12-09 19:02:25,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 717 states. [2018-12-09 19:02:25,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 717 to 707. [2018-12-09 19:02:25,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 707 states. [2018-12-09 19:02:25,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 707 states to 707 states and 714 transitions. [2018-12-09 19:02:25,241 INFO L78 Accepts]: Start accepts. Automaton has 707 states and 714 transitions. Word has length 572 [2018-12-09 19:02:25,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:25,241 INFO L480 AbstractCegarLoop]: Abstraction has 707 states and 714 transitions. [2018-12-09 19:02:25,241 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-12-09 19:02:25,241 INFO L276 IsEmpty]: Start isEmpty. Operand 707 states and 714 transitions. [2018-12-09 19:02:25,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 578 [2018-12-09 19:02:25,243 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:25,243 INFO L402 BasicCegarLoop]: trace histogram [90, 89, 89, 89, 89, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:25,243 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:25,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:25,243 INFO L82 PathProgramCache]: Analyzing trace with hash 35953893, now seen corresponding path program 27 times [2018-12-09 19:02:25,243 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:25,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:25,244 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:25,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:25,244 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:25,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:25,499 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 5114 proven. 364 refuted. 0 times theorem prover too weak. 15908 trivial. 0 not checked. [2018-12-09 19:02:25,500 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:25,500 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:25,500 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:25,500 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:25,500 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:25,500 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:25,507 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:25,507 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:25,624 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:25,625 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:25,630 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:25,881 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 4917 proven. 354 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-09 19:02:25,882 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:26,186 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 4917 proven. 354 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-09 19:02:26,201 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:26,201 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 14, 14] total 47 [2018-12-09 19:02:26,202 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:26,202 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-09 19:02:26,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-09 19:02:26,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=1891, Unknown=0, NotChecked=0, Total=2256 [2018-12-09 19:02:26,202 INFO L87 Difference]: Start difference. First operand 707 states and 714 transitions. Second operand 35 states. [2018-12-09 19:02:26,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:26,854 INFO L93 Difference]: Finished difference Result 886 states and 899 transitions. [2018-12-09 19:02:26,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-12-09 19:02:26,855 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 577 [2018-12-09 19:02:26,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:26,856 INFO L225 Difference]: With dead ends: 886 [2018-12-09 19:02:26,856 INFO L226 Difference]: Without dead ends: 886 [2018-12-09 19:02:26,856 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1191 GetRequests, 1128 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 929 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=762, Invalid=3398, Unknown=0, NotChecked=0, Total=4160 [2018-12-09 19:02:26,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states. [2018-12-09 19:02:26,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 857. [2018-12-09 19:02:26,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 857 states. [2018-12-09 19:02:26,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 857 states to 857 states and 869 transitions. [2018-12-09 19:02:26,861 INFO L78 Accepts]: Start accepts. Automaton has 857 states and 869 transitions. Word has length 577 [2018-12-09 19:02:26,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:26,862 INFO L480 AbstractCegarLoop]: Abstraction has 857 states and 869 transitions. [2018-12-09 19:02:26,862 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-09 19:02:26,862 INFO L276 IsEmpty]: Start isEmpty. Operand 857 states and 869 transitions. [2018-12-09 19:02:26,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 649 [2018-12-09 19:02:26,864 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:26,864 INFO L402 BasicCegarLoop]: trace histogram [102, 101, 101, 101, 101, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:26,864 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:26,864 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:26,864 INFO L82 PathProgramCache]: Analyzing trace with hash 687118509, now seen corresponding path program 28 times [2018-12-09 19:02:26,864 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:26,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:26,865 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:26,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:26,865 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:26,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:27,271 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 9641 proven. 1744 refuted. 0 times theorem prover too weak. 16053 trivial. 0 not checked. [2018-12-09 19:02:27,271 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:27,271 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:27,271 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:27,271 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:27,271 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:27,271 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:27,279 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:27,279 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:27,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:27,374 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:27,824 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 14284 proven. 286 refuted. 0 times theorem prover too weak. 12868 trivial. 0 not checked. [2018-12-09 19:02:27,825 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:28,424 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 10280 proven. 973 refuted. 0 times theorem prover too weak. 16185 trivial. 0 not checked. [2018-12-09 19:02:28,439 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:28,439 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 26, 26] total 69 [2018-12-09 19:02:28,439 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:28,440 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-12-09 19:02:28,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-12-09 19:02:28,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=740, Invalid=3952, Unknown=0, NotChecked=0, Total=4692 [2018-12-09 19:02:28,440 INFO L87 Difference]: Start difference. First operand 857 states and 869 transitions. Second operand 57 states. [2018-12-09 19:02:29,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:29,483 INFO L93 Difference]: Finished difference Result 727 states and 732 transitions. [2018-12-09 19:02:29,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-12-09 19:02:29,483 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 648 [2018-12-09 19:02:29,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:29,484 INFO L225 Difference]: With dead ends: 727 [2018-12-09 19:02:29,484 INFO L226 Difference]: Without dead ends: 718 [2018-12-09 19:02:29,484 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1377 GetRequests, 1249 SyntacticMatches, 13 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5025 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=2175, Invalid=11397, Unknown=0, NotChecked=0, Total=13572 [2018-12-09 19:02:29,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states. [2018-12-09 19:02:29,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 711. [2018-12-09 19:02:29,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 711 states. [2018-12-09 19:02:29,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 716 transitions. [2018-12-09 19:02:29,488 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 716 transitions. Word has length 648 [2018-12-09 19:02:29,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:29,488 INFO L480 AbstractCegarLoop]: Abstraction has 711 states and 716 transitions. [2018-12-09 19:02:29,488 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-12-09 19:02:29,489 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 716 transitions. [2018-12-09 19:02:29,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 654 [2018-12-09 19:02:29,491 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:29,491 INFO L402 BasicCegarLoop]: trace histogram [103, 102, 102, 102, 102, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:29,491 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:29,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:29,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1741773022, now seen corresponding path program 29 times [2018-12-09 19:02:29,491 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:29,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:29,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:29,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:29,492 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:29,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:29,908 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10669 proven. 1173 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-09 19:02:29,908 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:29,909 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:29,909 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:29,909 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:29,909 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:29,909 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:29,914 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:29,914 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:30,035 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-12-09 19:02:30,035 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:30,039 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:30,384 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10315 proven. 1173 refuted. 0 times theorem prover too weak. 16469 trivial. 0 not checked. [2018-12-09 19:02:30,384 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:31,014 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10266 proven. 1222 refuted. 0 times theorem prover too weak. 16469 trivial. 0 not checked. [2018-12-09 19:02:31,029 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:31,029 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 22, 22] total 71 [2018-12-09 19:02:31,029 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:31,030 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-09 19:02:31,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-09 19:02:31,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=977, Invalid=3993, Unknown=0, NotChecked=0, Total=4970 [2018-12-09 19:02:31,030 INFO L87 Difference]: Start difference. First operand 711 states and 716 transitions. Second operand 50 states. [2018-12-09 19:02:31,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:31,868 INFO L93 Difference]: Finished difference Result 803 states and 810 transitions. [2018-12-09 19:02:31,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-09 19:02:31,868 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 653 [2018-12-09 19:02:31,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:31,869 INFO L225 Difference]: With dead ends: 803 [2018-12-09 19:02:31,869 INFO L226 Difference]: Without dead ends: 803 [2018-12-09 19:02:31,870 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1379 GetRequests, 1269 SyntacticMatches, 1 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3446 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=3110, Invalid=9100, Unknown=0, NotChecked=0, Total=12210 [2018-12-09 19:02:31,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 803 states. [2018-12-09 19:02:31,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 803 to 793. [2018-12-09 19:02:31,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 793 states. [2018-12-09 19:02:31,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 793 states to 793 states and 800 transitions. [2018-12-09 19:02:31,874 INFO L78 Accepts]: Start accepts. Automaton has 793 states and 800 transitions. Word has length 653 [2018-12-09 19:02:31,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:31,875 INFO L480 AbstractCegarLoop]: Abstraction has 793 states and 800 transitions. [2018-12-09 19:02:31,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-09 19:02:31,875 INFO L276 IsEmpty]: Start isEmpty. Operand 793 states and 800 transitions. [2018-12-09 19:02:31,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 659 [2018-12-09 19:02:31,877 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:31,877 INFO L402 BasicCegarLoop]: trace histogram [104, 103, 103, 103, 103, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:31,877 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:31,877 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:31,877 INFO L82 PathProgramCache]: Analyzing trace with hash 1104503271, now seen corresponding path program 30 times [2018-12-09 19:02:31,877 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:31,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:31,878 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:31,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:31,878 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:31,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:32,166 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6259 proven. 433 refuted. 0 times theorem prover too weak. 21789 trivial. 0 not checked. [2018-12-09 19:02:32,166 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:32,166 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:32,166 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:32,166 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:32,166 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:32,166 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:32,172 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:32,172 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:32,318 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:32,318 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:32,324 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:32,560 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6198 proven. 416 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-09 19:02:32,560 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:32,879 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6198 proven. 416 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-09 19:02:32,895 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:32,895 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15, 15] total 47 [2018-12-09 19:02:32,895 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:32,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-12-09 19:02:32,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-12-09 19:02:32,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1859, Unknown=0, NotChecked=0, Total=2256 [2018-12-09 19:02:32,896 INFO L87 Difference]: Start difference. First operand 793 states and 800 transitions. Second operand 34 states. [2018-12-09 19:02:33,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:33,824 INFO L93 Difference]: Finished difference Result 982 states and 995 transitions. [2018-12-09 19:02:33,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-09 19:02:33,824 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 658 [2018-12-09 19:02:33,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:33,825 INFO L225 Difference]: With dead ends: 982 [2018-12-09 19:02:33,826 INFO L226 Difference]: Without dead ends: 982 [2018-12-09 19:02:33,826 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1352 GetRequests, 1288 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 996 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=801, Invalid=3489, Unknown=0, NotChecked=0, Total=4290 [2018-12-09 19:02:33,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982 states. [2018-12-09 19:02:33,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982 to 953. [2018-12-09 19:02:33,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 953 states. [2018-12-09 19:02:33,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 953 states to 953 states and 965 transitions. [2018-12-09 19:02:33,832 INFO L78 Accepts]: Start accepts. Automaton has 953 states and 965 transitions. Word has length 658 [2018-12-09 19:02:33,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:33,832 INFO L480 AbstractCegarLoop]: Abstraction has 953 states and 965 transitions. [2018-12-09 19:02:33,832 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-12-09 19:02:33,832 INFO L276 IsEmpty]: Start isEmpty. Operand 953 states and 965 transitions. [2018-12-09 19:02:33,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 735 [2018-12-09 19:02:33,835 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:33,835 INFO L402 BasicCegarLoop]: trace histogram [117, 116, 116, 116, 116, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:33,835 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:33,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:33,835 INFO L82 PathProgramCache]: Analyzing trace with hash -402943376, now seen corresponding path program 31 times [2018-12-09 19:02:33,835 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:33,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:33,835 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:33,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:33,836 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:33,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:34,313 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 12150 proven. 2051 refuted. 0 times theorem prover too weak. 21799 trivial. 0 not checked. [2018-12-09 19:02:34,313 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:34,313 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:34,313 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:34,313 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:34,313 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:34,313 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:34,319 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:34,319 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:34,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:34,427 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:34,990 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 18051 proven. 342 refuted. 0 times theorem prover too weak. 17607 trivial. 0 not checked. [2018-12-09 19:02:34,990 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:35,629 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 12913 proven. 1151 refuted. 0 times theorem prover too weak. 21936 trivial. 0 not checked. [2018-12-09 19:02:35,645 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:35,645 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 28, 28] total 74 [2018-12-09 19:02:35,645 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:35,645 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-12-09 19:02:35,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-12-09 19:02:35,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=852, Invalid=4550, Unknown=0, NotChecked=0, Total=5402 [2018-12-09 19:02:35,646 INFO L87 Difference]: Start difference. First operand 953 states and 965 transitions. Second operand 61 states. [2018-12-09 19:02:36,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:36,940 INFO L93 Difference]: Finished difference Result 813 states and 818 transitions. [2018-12-09 19:02:36,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-12-09 19:02:36,940 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 734 [2018-12-09 19:02:36,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:36,942 INFO L225 Difference]: With dead ends: 813 [2018-12-09 19:02:36,942 INFO L226 Difference]: Without dead ends: 804 [2018-12-09 19:02:36,943 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1555 GetRequests, 1417 SyntacticMatches, 14 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5900 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2515, Invalid=13235, Unknown=0, NotChecked=0, Total=15750 [2018-12-09 19:02:36,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 804 states. [2018-12-09 19:02:36,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 804 to 797. [2018-12-09 19:02:36,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 797 states. [2018-12-09 19:02:36,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 802 transitions. [2018-12-09 19:02:36,949 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 802 transitions. Word has length 734 [2018-12-09 19:02:36,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:36,949 INFO L480 AbstractCegarLoop]: Abstraction has 797 states and 802 transitions. [2018-12-09 19:02:36,949 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-12-09 19:02:36,949 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 802 transitions. [2018-12-09 19:02:36,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 740 [2018-12-09 19:02:36,953 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:36,953 INFO L402 BasicCegarLoop]: trace histogram [118, 117, 117, 117, 117, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:36,954 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:36,954 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:36,954 INFO L82 PathProgramCache]: Analyzing trace with hash 79086155, now seen corresponding path program 32 times [2018-12-09 19:02:36,954 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:36,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:36,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:36,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:36,955 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:36,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:37,445 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 13360 proven. 1368 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-09 19:02:37,446 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:37,446 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:37,446 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:37,446 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:37,446 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:37,446 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:37,452 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:37,452 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:37,582 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-12-09 19:02:37,582 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:37,586 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:38,005 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 12944 proven. 1368 refuted. 0 times theorem prover too weak. 22283 trivial. 0 not checked. [2018-12-09 19:02:38,005 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:38,715 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 12891 proven. 1421 refuted. 0 times theorem prover too weak. 22283 trivial. 0 not checked. [2018-12-09 19:02:38,729 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:38,730 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 23, 23] total 75 [2018-12-09 19:02:38,730 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:38,730 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-12-09 19:02:38,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-12-09 19:02:38,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1110, Invalid=4440, Unknown=0, NotChecked=0, Total=5550 [2018-12-09 19:02:38,731 INFO L87 Difference]: Start difference. First operand 797 states and 802 transitions. Second operand 53 states. [2018-12-09 19:02:39,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:39,638 INFO L93 Difference]: Finished difference Result 894 states and 901 transitions. [2018-12-09 19:02:39,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-09 19:02:39,638 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 739 [2018-12-09 19:02:39,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:39,640 INFO L225 Difference]: With dead ends: 894 [2018-12-09 19:02:39,640 INFO L226 Difference]: Without dead ends: 894 [2018-12-09 19:02:39,640 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1556 GetRequests, 1439 SyntacticMatches, 1 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3918 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3545, Invalid=10261, Unknown=0, NotChecked=0, Total=13806 [2018-12-09 19:02:39,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 894 states. [2018-12-09 19:02:39,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 894 to 884. [2018-12-09 19:02:39,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 884 states. [2018-12-09 19:02:39,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 884 states to 884 states and 891 transitions. [2018-12-09 19:02:39,645 INFO L78 Accepts]: Start accepts. Automaton has 884 states and 891 transitions. Word has length 739 [2018-12-09 19:02:39,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:39,645 INFO L480 AbstractCegarLoop]: Abstraction has 884 states and 891 transitions. [2018-12-09 19:02:39,645 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-12-09 19:02:39,645 INFO L276 IsEmpty]: Start isEmpty. Operand 884 states and 891 transitions. [2018-12-09 19:02:39,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 745 [2018-12-09 19:02:39,648 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:39,648 INFO L402 BasicCegarLoop]: trace histogram [119, 118, 118, 118, 118, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:39,648 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:39,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:39,648 INFO L82 PathProgramCache]: Analyzing trace with hash 1460105962, now seen corresponding path program 33 times [2018-12-09 19:02:39,648 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:39,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:39,649 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:39,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:39,649 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:39,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:39,958 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7811 proven. 508 refuted. 0 times theorem prover too weak. 28876 trivial. 0 not checked. [2018-12-09 19:02:39,959 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:39,959 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:39,959 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:39,959 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:39,959 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:39,959 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:39,967 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:39,967 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:40,133 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:40,134 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:40,141 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:40,421 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7683 proven. 483 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2018-12-09 19:02:40,421 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:40,830 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7683 proven. 483 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2018-12-09 19:02:40,847 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:40,847 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 16, 16] total 51 [2018-12-09 19:02:40,847 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:40,848 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-09 19:02:40,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-09 19:02:40,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=451, Invalid=2201, Unknown=0, NotChecked=0, Total=2652 [2018-12-09 19:02:40,848 INFO L87 Difference]: Start difference. First operand 884 states and 891 transitions. Second operand 37 states. [2018-12-09 19:02:41,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:41,771 INFO L93 Difference]: Finished difference Result 1083 states and 1096 transitions. [2018-12-09 19:02:41,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-09 19:02:41,772 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 744 [2018-12-09 19:02:41,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:41,773 INFO L225 Difference]: With dead ends: 1083 [2018-12-09 19:02:41,773 INFO L226 Difference]: Without dead ends: 1083 [2018-12-09 19:02:41,774 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1527 GetRequests, 1458 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1161 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=911, Invalid=4059, Unknown=0, NotChecked=0, Total=4970 [2018-12-09 19:02:41,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1083 states. [2018-12-09 19:02:41,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1083 to 1054. [2018-12-09 19:02:41,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1054 states. [2018-12-09 19:02:41,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1054 states to 1054 states and 1066 transitions. [2018-12-09 19:02:41,779 INFO L78 Accepts]: Start accepts. Automaton has 1054 states and 1066 transitions. Word has length 744 [2018-12-09 19:02:41,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:41,780 INFO L480 AbstractCegarLoop]: Abstraction has 1054 states and 1066 transitions. [2018-12-09 19:02:41,780 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-09 19:02:41,780 INFO L276 IsEmpty]: Start isEmpty. Operand 1054 states and 1066 transitions. [2018-12-09 19:02:41,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 826 [2018-12-09 19:02:41,783 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:41,783 INFO L402 BasicCegarLoop]: trace histogram [133, 132, 132, 132, 132, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:41,783 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:41,783 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:41,783 INFO L82 PathProgramCache]: Analyzing trace with hash 1258137320, now seen corresponding path program 34 times [2018-12-09 19:02:41,783 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:41,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:41,784 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:41,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:41,784 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:41,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:42,352 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 15061 proven. 2383 refuted. 0 times theorem prover too weak. 28955 trivial. 0 not checked. [2018-12-09 19:02:42,352 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:42,352 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:42,352 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:42,353 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:42,353 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:42,353 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:42,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:42,359 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:42,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:42,480 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:43,102 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 22424 proven. 403 refuted. 0 times theorem prover too weak. 23572 trivial. 0 not checked. [2018-12-09 19:02:43,103 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:43,919 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 15959 proven. 1344 refuted. 0 times theorem prover too weak. 29096 trivial. 0 not checked. [2018-12-09 19:02:43,934 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:43,935 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 30, 30] total 79 [2018-12-09 19:02:43,935 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:43,935 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-09 19:02:43,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-09 19:02:43,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=972, Invalid=5190, Unknown=0, NotChecked=0, Total=6162 [2018-12-09 19:02:43,935 INFO L87 Difference]: Start difference. First operand 1054 states and 1066 transitions. Second operand 65 states. [2018-12-09 19:02:45,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:45,227 INFO L93 Difference]: Finished difference Result 904 states and 909 transitions. [2018-12-09 19:02:45,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-12-09 19:02:45,227 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 825 [2018-12-09 19:02:45,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:45,229 INFO L225 Difference]: With dead ends: 904 [2018-12-09 19:02:45,229 INFO L226 Difference]: Without dead ends: 895 [2018-12-09 19:02:45,229 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1743 GetRequests, 1595 SyntacticMatches, 15 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6845 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2880, Invalid=15210, Unknown=0, NotChecked=0, Total=18090 [2018-12-09 19:02:45,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 895 states. [2018-12-09 19:02:45,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 895 to 888. [2018-12-09 19:02:45,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 888 states. [2018-12-09 19:02:45,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 888 states to 888 states and 893 transitions. [2018-12-09 19:02:45,234 INFO L78 Accepts]: Start accepts. Automaton has 888 states and 893 transitions. Word has length 825 [2018-12-09 19:02:45,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:45,234 INFO L480 AbstractCegarLoop]: Abstraction has 888 states and 893 transitions. [2018-12-09 19:02:45,234 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-09 19:02:45,234 INFO L276 IsEmpty]: Start isEmpty. Operand 888 states and 893 transitions. [2018-12-09 19:02:45,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 831 [2018-12-09 19:02:45,237 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:45,237 INFO L402 BasicCegarLoop]: trace histogram [134, 133, 133, 133, 133, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:45,238 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:45,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:45,238 INFO L82 PathProgramCache]: Analyzing trace with hash 51252807, now seen corresponding path program 35 times [2018-12-09 19:02:45,238 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:45,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:45,238 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:45,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:45,239 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:45,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:45,809 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 16468 proven. 1578 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2018-12-09 19:02:45,809 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:45,809 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:45,809 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:45,809 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:45,809 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:45,809 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:45,817 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:45,817 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:45,977 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-12-09 19:02:45,978 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:45,983 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:46,437 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 15985 proven. 1578 refuted. 0 times theorem prover too weak. 29512 trivial. 0 not checked. [2018-12-09 19:02:46,437 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:47,260 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 15928 proven. 1635 refuted. 0 times theorem prover too weak. 29512 trivial. 0 not checked. [2018-12-09 19:02:47,275 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:47,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 24, 24] total 79 [2018-12-09 19:02:47,275 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:47,276 INFO L459 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-12-09 19:02:47,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-12-09 19:02:47,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1252, Invalid=4910, Unknown=0, NotChecked=0, Total=6162 [2018-12-09 19:02:47,277 INFO L87 Difference]: Start difference. First operand 888 states and 893 transitions. Second operand 56 states. [2018-12-09 19:02:48,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:48,332 INFO L93 Difference]: Finished difference Result 990 states and 997 transitions. [2018-12-09 19:02:48,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-12-09 19:02:48,332 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 830 [2018-12-09 19:02:48,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:48,334 INFO L225 Difference]: With dead ends: 990 [2018-12-09 19:02:48,334 INFO L226 Difference]: Without dead ends: 990 [2018-12-09 19:02:48,334 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1743 GetRequests, 1619 SyntacticMatches, 1 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4420 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=4009, Invalid=11491, Unknown=0, NotChecked=0, Total=15500 [2018-12-09 19:02:48,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 990 states. [2018-12-09 19:02:48,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 990 to 980. [2018-12-09 19:02:48,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 980 states. [2018-12-09 19:02:48,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 980 states to 980 states and 987 transitions. [2018-12-09 19:02:48,340 INFO L78 Accepts]: Start accepts. Automaton has 980 states and 987 transitions. Word has length 830 [2018-12-09 19:02:48,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:48,340 INFO L480 AbstractCegarLoop]: Abstraction has 980 states and 987 transitions. [2018-12-09 19:02:48,340 INFO L481 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-12-09 19:02:48,340 INFO L276 IsEmpty]: Start isEmpty. Operand 980 states and 987 transitions. [2018-12-09 19:02:48,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 836 [2018-12-09 19:02:48,343 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:48,343 INFO L402 BasicCegarLoop]: trace histogram [135, 134, 134, 134, 134, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:48,344 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:48,344 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:48,344 INFO L82 PathProgramCache]: Analyzing trace with hash 1746428258, now seen corresponding path program 36 times [2018-12-09 19:02:48,344 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:48,344 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:48,344 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:48,344 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:48,345 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:48,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:48,703 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9458 proven. 589 refuted. 0 times theorem prover too weak. 37709 trivial. 0 not checked. [2018-12-09 19:02:48,703 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:48,703 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:48,703 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:48,703 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:48,703 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:48,703 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:48,709 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:48,709 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:49,084 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:49,085 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:49,093 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:49,427 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9387 proven. 555 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-09 19:02:49,427 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:49,866 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9387 proven. 555 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-09 19:02:49,883 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:49,883 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 17, 17] total 53 [2018-12-09 19:02:49,883 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:49,883 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-09 19:02:49,884 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-09 19:02:49,884 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=500, Invalid=2362, Unknown=0, NotChecked=0, Total=2862 [2018-12-09 19:02:49,884 INFO L87 Difference]: Start difference. First operand 980 states and 987 transitions. Second operand 38 states. [2018-12-09 19:02:50,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:50,965 INFO L93 Difference]: Finished difference Result 1189 states and 1202 transitions. [2018-12-09 19:02:50,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-12-09 19:02:50,966 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 835 [2018-12-09 19:02:50,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:50,968 INFO L225 Difference]: With dead ends: 1189 [2018-12-09 19:02:50,968 INFO L226 Difference]: Without dead ends: 1189 [2018-12-09 19:02:50,969 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1710 GetRequests, 1638 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1283 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=990, Invalid=4412, Unknown=0, NotChecked=0, Total=5402 [2018-12-09 19:02:50,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1189 states. [2018-12-09 19:02:50,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1189 to 1160. [2018-12-09 19:02:50,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1160 states. [2018-12-09 19:02:50,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1160 states to 1160 states and 1172 transitions. [2018-12-09 19:02:50,979 INFO L78 Accepts]: Start accepts. Automaton has 1160 states and 1172 transitions. Word has length 835 [2018-12-09 19:02:50,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:50,980 INFO L480 AbstractCegarLoop]: Abstraction has 1160 states and 1172 transitions. [2018-12-09 19:02:50,980 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-09 19:02:50,980 INFO L276 IsEmpty]: Start isEmpty. Operand 1160 states and 1172 transitions. [2018-12-09 19:02:50,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 922 [2018-12-09 19:02:50,986 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:50,987 INFO L402 BasicCegarLoop]: trace histogram [150, 149, 149, 149, 149, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:50,987 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:50,987 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:50,987 INFO L82 PathProgramCache]: Analyzing trace with hash 1328608651, now seen corresponding path program 37 times [2018-12-09 19:02:50,987 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:50,988 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:50,988 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:50,988 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:50,988 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:51,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:51,647 INFO L134 CoverageAnalysis]: Checked inductivity of 58878 backedges. 18404 proven. 2740 refuted. 0 times theorem prover too weak. 37734 trivial. 0 not checked. [2018-12-09 19:02:51,647 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:51,647 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:51,647 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:51,647 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:51,647 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:51,647 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:51,653 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:51,653 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:02:51,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:51,796 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:52,495 INFO L134 CoverageAnalysis]: Checked inductivity of 58878 backedges. 27448 proven. 469 refuted. 0 times theorem prover too weak. 30961 trivial. 0 not checked. [2018-12-09 19:02:52,495 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:53,382 INFO L134 CoverageAnalysis]: Checked inductivity of 58878 backedges. 19448 proven. 1552 refuted. 0 times theorem prover too weak. 37878 trivial. 0 not checked. [2018-12-09 19:02:53,397 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:53,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 32, 32] total 84 [2018-12-09 19:02:53,397 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:53,398 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-09 19:02:53,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-09 19:02:53,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1100, Invalid=5872, Unknown=0, NotChecked=0, Total=6972 [2018-12-09 19:02:53,399 INFO L87 Difference]: Start difference. First operand 1160 states and 1172 transitions. Second operand 69 states. [2018-12-09 19:02:54,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:54,924 INFO L93 Difference]: Finished difference Result 1000 states and 1005 transitions. [2018-12-09 19:02:54,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-12-09 19:02:54,924 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 921 [2018-12-09 19:02:54,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:54,926 INFO L225 Difference]: With dead ends: 1000 [2018-12-09 19:02:54,926 INFO L226 Difference]: Without dead ends: 991 [2018-12-09 19:02:54,926 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1941 GetRequests, 1783 SyntacticMatches, 16 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7860 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3270, Invalid=17322, Unknown=0, NotChecked=0, Total=20592 [2018-12-09 19:02:54,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states. [2018-12-09 19:02:54,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 984. [2018-12-09 19:02:54,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 984 states. [2018-12-09 19:02:54,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 984 states to 984 states and 989 transitions. [2018-12-09 19:02:54,932 INFO L78 Accepts]: Start accepts. Automaton has 984 states and 989 transitions. Word has length 921 [2018-12-09 19:02:54,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:54,933 INFO L480 AbstractCegarLoop]: Abstraction has 984 states and 989 transitions. [2018-12-09 19:02:54,933 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-09 19:02:54,933 INFO L276 IsEmpty]: Start isEmpty. Operand 984 states and 989 transitions. [2018-12-09 19:02:54,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 927 [2018-12-09 19:02:54,939 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:54,940 INFO L402 BasicCegarLoop]: trace histogram [151, 150, 150, 150, 150, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:54,940 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:54,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:54,940 INFO L82 PathProgramCache]: Analyzing trace with hash -848043632, now seen corresponding path program 38 times [2018-12-09 19:02:54,940 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:54,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:54,941 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:02:54,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:54,941 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:54,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:55,600 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 20023 proven. 1803 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-09 19:02:55,600 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:55,600 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:55,600 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:55,600 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:55,600 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:55,601 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:55,608 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:02:55,608 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:02:55,798 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-12-09 19:02:55,798 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:55,803 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:56,361 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 19468 proven. 1803 refuted. 0 times theorem prover too weak. 38369 trivial. 0 not checked. [2018-12-09 19:02:56,361 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:02:57,273 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 19407 proven. 1864 refuted. 0 times theorem prover too weak. 38369 trivial. 0 not checked. [2018-12-09 19:02:57,288 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:02:57,288 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 25, 25] total 83 [2018-12-09 19:02:57,288 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:02:57,289 INFO L459 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-12-09 19:02:57,289 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-12-09 19:02:57,289 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1403, Invalid=5403, Unknown=0, NotChecked=0, Total=6806 [2018-12-09 19:02:57,289 INFO L87 Difference]: Start difference. First operand 984 states and 989 transitions. Second operand 59 states. [2018-12-09 19:02:58,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:02:58,447 INFO L93 Difference]: Finished difference Result 1091 states and 1098 transitions. [2018-12-09 19:02:58,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-12-09 19:02:58,447 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 926 [2018-12-09 19:02:58,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:02:58,449 INFO L225 Difference]: With dead ends: 1091 [2018-12-09 19:02:58,449 INFO L226 Difference]: Without dead ends: 1091 [2018-12-09 19:02:58,449 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1940 GetRequests, 1809 SyntacticMatches, 1 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4952 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=4502, Invalid=12790, Unknown=0, NotChecked=0, Total=17292 [2018-12-09 19:02:58,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1091 states. [2018-12-09 19:02:58,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1091 to 1081. [2018-12-09 19:02:58,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1081 states. [2018-12-09 19:02:58,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1081 states to 1081 states and 1088 transitions. [2018-12-09 19:02:58,455 INFO L78 Accepts]: Start accepts. Automaton has 1081 states and 1088 transitions. Word has length 926 [2018-12-09 19:02:58,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:02:58,455 INFO L480 AbstractCegarLoop]: Abstraction has 1081 states and 1088 transitions. [2018-12-09 19:02:58,455 INFO L481 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-12-09 19:02:58,455 INFO L276 IsEmpty]: Start isEmpty. Operand 1081 states and 1088 transitions. [2018-12-09 19:02:58,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 932 [2018-12-09 19:02:58,459 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:02:58,459 INFO L402 BasicCegarLoop]: trace histogram [152, 151, 151, 151, 151, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:02:58,459 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:02:58,459 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:02:58,459 INFO L82 PathProgramCache]: Analyzing trace with hash 401870661, now seen corresponding path program 39 times [2018-12-09 19:02:58,459 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:02:58,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:58,460 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:02:58,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:02:58,460 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:02:58,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:02:59,104 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11956 proven. 676 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2018-12-09 19:02:59,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:59,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:02:59,105 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:02:59,105 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:02:59,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:02:59,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:02:59,111 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:02:59,111 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:02:59,461 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:02:59,461 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:02:59,470 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:02:59,934 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11325 proven. 632 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-09 19:02:59,934 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:00,633 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11325 proven. 632 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-09 19:03:00,650 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:00,651 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 18, 18] total 70 [2018-12-09 19:03:00,651 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:00,651 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-12-09 19:03:00,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-12-09 19:03:00,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=700, Invalid=4270, Unknown=0, NotChecked=0, Total=4970 [2018-12-09 19:03:00,652 INFO L87 Difference]: Start difference. First operand 1081 states and 1088 transitions. Second operand 54 states. [2018-12-09 19:03:01,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:01,958 INFO L93 Difference]: Finished difference Result 1296 states and 1309 transitions. [2018-12-09 19:03:01,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-12-09 19:03:01,958 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 931 [2018-12-09 19:03:01,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:01,960 INFO L225 Difference]: With dead ends: 1296 [2018-12-09 19:03:01,960 INFO L226 Difference]: Without dead ends: 1296 [2018-12-09 19:03:01,960 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1918 GetRequests, 1828 SyntacticMatches, 1 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1731 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1324, Invalid=6866, Unknown=0, NotChecked=0, Total=8190 [2018-12-09 19:03:01,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1296 states. [2018-12-09 19:03:01,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1296 to 1271. [2018-12-09 19:03:01,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1271 states. [2018-12-09 19:03:01,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1271 states to 1271 states and 1283 transitions. [2018-12-09 19:03:01,967 INFO L78 Accepts]: Start accepts. Automaton has 1271 states and 1283 transitions. Word has length 931 [2018-12-09 19:03:01,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:01,967 INFO L480 AbstractCegarLoop]: Abstraction has 1271 states and 1283 transitions. [2018-12-09 19:03:01,967 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-12-09 19:03:01,967 INFO L276 IsEmpty]: Start isEmpty. Operand 1271 states and 1283 transitions. [2018-12-09 19:03:01,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1023 [2018-12-09 19:03:01,971 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:01,972 INFO L402 BasicCegarLoop]: trace histogram [168, 167, 167, 167, 167, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:01,972 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:01,972 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:01,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1689975411, now seen corresponding path program 40 times [2018-12-09 19:03:01,972 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:01,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:01,972 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:01,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:01,972 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:02,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:02,722 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 22209 proven. 3122 refuted. 0 times theorem prover too weak. 48364 trivial. 0 not checked. [2018-12-09 19:03:02,722 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:02,722 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:02,722 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:02,722 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:02,722 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:02,722 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:02,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:02,728 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:03:02,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:02,889 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:03,709 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 33168 proven. 540 refuted. 0 times theorem prover too weak. 39987 trivial. 0 not checked. [2018-12-09 19:03:03,709 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:04,733 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 23410 proven. 1775 refuted. 0 times theorem prover too weak. 48510 trivial. 0 not checked. [2018-12-09 19:03:04,748 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:04,748 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 34, 34] total 89 [2018-12-09 19:03:04,749 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:04,749 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-12-09 19:03:04,749 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-12-09 19:03:04,749 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1236, Invalid=6596, Unknown=0, NotChecked=0, Total=7832 [2018-12-09 19:03:04,750 INFO L87 Difference]: Start difference. First operand 1271 states and 1283 transitions. Second operand 73 states. [2018-12-09 19:03:06,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:06,609 INFO L93 Difference]: Finished difference Result 1101 states and 1106 transitions. [2018-12-09 19:03:06,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-12-09 19:03:06,609 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1022 [2018-12-09 19:03:06,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:06,610 INFO L225 Difference]: With dead ends: 1101 [2018-12-09 19:03:06,611 INFO L226 Difference]: Without dead ends: 1092 [2018-12-09 19:03:06,611 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2149 GetRequests, 1981 SyntacticMatches, 17 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8945 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3685, Invalid=19571, Unknown=0, NotChecked=0, Total=23256 [2018-12-09 19:03:06,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1092 states. [2018-12-09 19:03:06,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1092 to 1085. [2018-12-09 19:03:06,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1085 states. [2018-12-09 19:03:06,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1085 states to 1085 states and 1090 transitions. [2018-12-09 19:03:06,618 INFO L78 Accepts]: Start accepts. Automaton has 1085 states and 1090 transitions. Word has length 1022 [2018-12-09 19:03:06,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:06,618 INFO L480 AbstractCegarLoop]: Abstraction has 1085 states and 1090 transitions. [2018-12-09 19:03:06,618 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-12-09 19:03:06,618 INFO L276 IsEmpty]: Start isEmpty. Operand 1085 states and 1090 transitions. [2018-12-09 19:03:06,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1028 [2018-12-09 19:03:06,623 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:06,623 INFO L402 BasicCegarLoop]: trace histogram [169, 168, 168, 168, 168, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:06,623 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:06,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:06,623 INFO L82 PathProgramCache]: Analyzing trace with hash -697239742, now seen corresponding path program 41 times [2018-12-09 19:03:06,623 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:06,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:06,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:06,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:06,624 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:06,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:07,374 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 24055 proven. 2043 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-09 19:03:07,374 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:07,374 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:07,374 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:07,374 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:07,374 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:07,374 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:07,380 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:03:07,380 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:03:07,602 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-12-09 19:03:07,602 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:07,608 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:08,203 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 23423 proven. 2043 refuted. 0 times theorem prover too weak. 49082 trivial. 0 not checked. [2018-12-09 19:03:08,203 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:09,243 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 23358 proven. 2108 refuted. 0 times theorem prover too weak. 49082 trivial. 0 not checked. [2018-12-09 19:03:09,259 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:09,259 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 26, 26] total 87 [2018-12-09 19:03:09,259 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:09,259 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-09 19:03:09,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-09 19:03:09,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1561, Invalid=5921, Unknown=0, NotChecked=0, Total=7482 [2018-12-09 19:03:09,260 INFO L87 Difference]: Start difference. First operand 1085 states and 1090 transitions. Second operand 62 states. [2018-12-09 19:03:10,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:10,527 INFO L93 Difference]: Finished difference Result 1197 states and 1204 transitions. [2018-12-09 19:03:10,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-12-09 19:03:10,527 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1027 [2018-12-09 19:03:10,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:10,528 INFO L225 Difference]: With dead ends: 1197 [2018-12-09 19:03:10,529 INFO L226 Difference]: Without dead ends: 1197 [2018-12-09 19:03:10,529 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2147 GetRequests, 2009 SyntacticMatches, 1 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5529 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=5021, Invalid=14161, Unknown=0, NotChecked=0, Total=19182 [2018-12-09 19:03:10,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1197 states. [2018-12-09 19:03:10,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1197 to 1187. [2018-12-09 19:03:10,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1187 states. [2018-12-09 19:03:10,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1187 states to 1187 states and 1194 transitions. [2018-12-09 19:03:10,535 INFO L78 Accepts]: Start accepts. Automaton has 1187 states and 1194 transitions. Word has length 1027 [2018-12-09 19:03:10,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:10,536 INFO L480 AbstractCegarLoop]: Abstraction has 1187 states and 1194 transitions. [2018-12-09 19:03:10,536 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-09 19:03:10,536 INFO L276 IsEmpty]: Start isEmpty. Operand 1187 states and 1194 transitions. [2018-12-09 19:03:10,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1033 [2018-12-09 19:03:10,540 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:10,540 INFO L402 BasicCegarLoop]: trace histogram [170, 169, 169, 169, 169, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:10,540 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:10,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:10,541 INFO L82 PathProgramCache]: Analyzing trace with hash 548287687, now seen corresponding path program 42 times [2018-12-09 19:03:10,541 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:10,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:10,541 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:10,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:10,541 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:10,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:11,010 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13593 proven. 769 refuted. 0 times theorem prover too weak. 61044 trivial. 0 not checked. [2018-12-09 19:03:11,010 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:11,010 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:11,011 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:11,011 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:11,011 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:11,011 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:11,017 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:03:11,017 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:03:11,485 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:03:11,485 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:11,495 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:11,975 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13512 proven. 714 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-09 19:03:11,975 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:12,562 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13512 proven. 714 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-09 19:03:12,579 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:12,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19, 19] total 59 [2018-12-09 19:03:12,580 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:12,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-12-09 19:03:12,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-12-09 19:03:12,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=606, Invalid=2934, Unknown=0, NotChecked=0, Total=3540 [2018-12-09 19:03:12,581 INFO L87 Difference]: Start difference. First operand 1187 states and 1194 transitions. Second operand 42 states. [2018-12-09 19:03:13,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:13,899 INFO L93 Difference]: Finished difference Result 1416 states and 1429 transitions. [2018-12-09 19:03:13,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-12-09 19:03:13,899 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1032 [2018-12-09 19:03:13,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:13,901 INFO L225 Difference]: With dead ends: 1416 [2018-12-09 19:03:13,901 INFO L226 Difference]: Without dead ends: 1416 [2018-12-09 19:03:13,901 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2108 GetRequests, 2028 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1603 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1176, Invalid=5466, Unknown=0, NotChecked=0, Total=6642 [2018-12-09 19:03:13,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1416 states. [2018-12-09 19:03:13,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1416 to 1387. [2018-12-09 19:03:13,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1387 states. [2018-12-09 19:03:13,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1387 states to 1387 states and 1399 transitions. [2018-12-09 19:03:13,909 INFO L78 Accepts]: Start accepts. Automaton has 1387 states and 1399 transitions. Word has length 1032 [2018-12-09 19:03:13,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:13,909 INFO L480 AbstractCegarLoop]: Abstraction has 1387 states and 1399 transitions. [2018-12-09 19:03:13,909 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-12-09 19:03:13,909 INFO L276 IsEmpty]: Start isEmpty. Operand 1387 states and 1399 transitions. [2018-12-09 19:03:13,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1129 [2018-12-09 19:03:13,914 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:13,915 INFO L402 BasicCegarLoop]: trace histogram [187, 186, 186, 186, 186, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:13,915 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:13,915 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:13,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1455325456, now seen corresponding path program 43 times [2018-12-09 19:03:13,915 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:13,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:13,915 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:13,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:13,916 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:13,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:14,761 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 26506 proven. 3529 refuted. 0 times theorem prover too weak. 61088 trivial. 0 not checked. [2018-12-09 19:03:14,761 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:14,761 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:14,761 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:14,761 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:14,761 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:14,761 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:14,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:14,767 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:03:14,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:14,948 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:15,902 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 39629 proven. 616 refuted. 0 times theorem prover too weak. 50878 trivial. 0 not checked. [2018-12-09 19:03:15,902 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:17,063 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 27875 proven. 2013 refuted. 0 times theorem prover too weak. 61235 trivial. 0 not checked. [2018-12-09 19:03:17,078 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:17,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 36, 36] total 94 [2018-12-09 19:03:17,079 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:17,079 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-12-09 19:03:17,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-12-09 19:03:17,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1380, Invalid=7362, Unknown=0, NotChecked=0, Total=8742 [2018-12-09 19:03:17,080 INFO L87 Difference]: Start difference. First operand 1387 states and 1399 transitions. Second operand 77 states. [2018-12-09 19:03:18,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:18,929 INFO L93 Difference]: Finished difference Result 1207 states and 1212 transitions. [2018-12-09 19:03:18,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2018-12-09 19:03:18,929 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1128 [2018-12-09 19:03:18,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:18,932 INFO L225 Difference]: With dead ends: 1207 [2018-12-09 19:03:18,932 INFO L226 Difference]: Without dead ends: 1198 [2018-12-09 19:03:18,933 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2367 GetRequests, 2189 SyntacticMatches, 18 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10100 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4125, Invalid=21957, Unknown=0, NotChecked=0, Total=26082 [2018-12-09 19:03:18,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1198 states. [2018-12-09 19:03:18,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1198 to 1191. [2018-12-09 19:03:18,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1191 states. [2018-12-09 19:03:18,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1191 states to 1191 states and 1196 transitions. [2018-12-09 19:03:18,940 INFO L78 Accepts]: Start accepts. Automaton has 1191 states and 1196 transitions. Word has length 1128 [2018-12-09 19:03:18,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:18,941 INFO L480 AbstractCegarLoop]: Abstraction has 1191 states and 1196 transitions. [2018-12-09 19:03:18,941 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-12-09 19:03:18,941 INFO L276 IsEmpty]: Start isEmpty. Operand 1191 states and 1196 transitions. [2018-12-09 19:03:18,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1134 [2018-12-09 19:03:18,950 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:18,950 INFO L402 BasicCegarLoop]: trace histogram [188, 187, 187, 187, 187, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:18,951 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:18,951 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:18,951 INFO L82 PathProgramCache]: Analyzing trace with hash -1908118869, now seen corresponding path program 44 times [2018-12-09 19:03:18,951 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:18,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:18,951 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:18,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:18,951 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:19,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:19,803 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 28594 proven. 2298 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-09 19:03:19,803 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:19,803 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:19,803 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:19,803 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:19,803 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:19,803 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:19,809 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:03:19,809 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:03:20,048 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-12-09 19:03:20,048 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:20,055 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:20,748 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 27880 proven. 2298 refuted. 0 times theorem prover too weak. 61894 trivial. 0 not checked. [2018-12-09 19:03:20,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:21,871 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 27811 proven. 2367 refuted. 0 times theorem prover too weak. 61894 trivial. 0 not checked. [2018-12-09 19:03:21,886 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:21,886 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 27, 27] total 91 [2018-12-09 19:03:21,886 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:21,887 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-09 19:03:21,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-09 19:03:21,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1720, Invalid=6470, Unknown=0, NotChecked=0, Total=8190 [2018-12-09 19:03:21,887 INFO L87 Difference]: Start difference. First operand 1191 states and 1196 transitions. Second operand 65 states. [2018-12-09 19:03:23,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:23,639 INFO L93 Difference]: Finished difference Result 1308 states and 1315 transitions. [2018-12-09 19:03:23,640 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-12-09 19:03:23,640 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1133 [2018-12-09 19:03:23,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:23,644 INFO L225 Difference]: With dead ends: 1308 [2018-12-09 19:03:23,644 INFO L226 Difference]: Without dead ends: 1308 [2018-12-09 19:03:23,645 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2364 GetRequests, 2219 SyntacticMatches, 1 SemanticMatches, 144 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6157 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=5557, Invalid=15613, Unknown=0, NotChecked=0, Total=21170 [2018-12-09 19:03:23,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1308 states. [2018-12-09 19:03:23,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1308 to 1298. [2018-12-09 19:03:23,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1298 states. [2018-12-09 19:03:23,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1298 states to 1298 states and 1305 transitions. [2018-12-09 19:03:23,656 INFO L78 Accepts]: Start accepts. Automaton has 1298 states and 1305 transitions. Word has length 1133 [2018-12-09 19:03:23,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:23,657 INFO L480 AbstractCegarLoop]: Abstraction has 1298 states and 1305 transitions. [2018-12-09 19:03:23,657 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-09 19:03:23,657 INFO L276 IsEmpty]: Start isEmpty. Operand 1298 states and 1305 transitions. [2018-12-09 19:03:23,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1139 [2018-12-09 19:03:23,666 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:23,666 INFO L402 BasicCegarLoop]: trace histogram [189, 188, 188, 188, 188, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:23,666 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:23,667 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:23,667 INFO L82 PathProgramCache]: Analyzing trace with hash -1485351030, now seen corresponding path program 45 times [2018-12-09 19:03:23,667 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:23,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:23,667 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:23,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:23,668 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:23,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:24,264 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 16131 proven. 868 refuted. 0 times theorem prover too weak. 76027 trivial. 0 not checked. [2018-12-09 19:03:24,264 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:24,264 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:24,264 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:24,264 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:24,264 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:24,264 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:24,270 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:03:24,270 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:03:24,887 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:03:24,887 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:24,899 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:25,453 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 15963 proven. 801 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-09 19:03:25,453 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:26,143 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 15963 proven. 801 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-09 19:03:26,161 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:26,161 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 20, 20] total 63 [2018-12-09 19:03:26,161 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:26,162 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-12-09 19:03:26,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-12-09 19:03:26,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=661, Invalid=3371, Unknown=0, NotChecked=0, Total=4032 [2018-12-09 19:03:26,162 INFO L87 Difference]: Start difference. First operand 1298 states and 1305 transitions. Second operand 45 states. [2018-12-09 19:03:27,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:27,540 INFO L93 Difference]: Finished difference Result 1537 states and 1550 transitions. [2018-12-09 19:03:27,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-12-09 19:03:27,540 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 1138 [2018-12-09 19:03:27,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:27,542 INFO L225 Difference]: With dead ends: 1537 [2018-12-09 19:03:27,543 INFO L226 Difference]: Without dead ends: 1537 [2018-12-09 19:03:27,543 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2323 GetRequests, 2238 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1810 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1284, Invalid=6198, Unknown=0, NotChecked=0, Total=7482 [2018-12-09 19:03:27,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1537 states. [2018-12-09 19:03:27,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1537 to 1508. [2018-12-09 19:03:27,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1508 states. [2018-12-09 19:03:27,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1508 states to 1508 states and 1520 transitions. [2018-12-09 19:03:27,551 INFO L78 Accepts]: Start accepts. Automaton has 1508 states and 1520 transitions. Word has length 1138 [2018-12-09 19:03:27,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:27,551 INFO L480 AbstractCegarLoop]: Abstraction has 1508 states and 1520 transitions. [2018-12-09 19:03:27,551 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-12-09 19:03:27,551 INFO L276 IsEmpty]: Start isEmpty. Operand 1508 states and 1520 transitions. [2018-12-09 19:03:27,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1240 [2018-12-09 19:03:27,557 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:27,557 INFO L402 BasicCegarLoop]: trace histogram [207, 206, 206, 206, 206, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:27,558 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:27,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:27,558 INFO L82 PathProgramCache]: Analyzing trace with hash 775919112, now seen corresponding path program 46 times [2018-12-09 19:03:27,558 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:27,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:27,558 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:27,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:27,558 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:27,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:28,539 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 31325 proven. 3961 refuted. 0 times theorem prover too weak. 76164 trivial. 0 not checked. [2018-12-09 19:03:28,539 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:28,539 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:28,539 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:28,539 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:28,539 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:28,540 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:28,548 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:28,548 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:03:28,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:28,738 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:29,822 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 46876 proven. 697 refuted. 0 times theorem prover too weak. 63877 trivial. 0 not checked. [2018-12-09 19:03:29,822 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:31,150 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 32873 proven. 2266 refuted. 0 times theorem prover too weak. 76311 trivial. 0 not checked. [2018-12-09 19:03:31,165 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:31,165 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 38, 38] total 99 [2018-12-09 19:03:31,165 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:31,166 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-12-09 19:03:31,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-12-09 19:03:31,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1532, Invalid=8170, Unknown=0, NotChecked=0, Total=9702 [2018-12-09 19:03:31,167 INFO L87 Difference]: Start difference. First operand 1508 states and 1520 transitions. Second operand 81 states. [2018-12-09 19:03:32,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:32,886 INFO L93 Difference]: Finished difference Result 1318 states and 1323 transitions. [2018-12-09 19:03:32,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-12-09 19:03:32,886 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1239 [2018-12-09 19:03:32,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:32,888 INFO L225 Difference]: With dead ends: 1318 [2018-12-09 19:03:32,888 INFO L226 Difference]: Without dead ends: 1309 [2018-12-09 19:03:32,889 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2595 GetRequests, 2407 SyntacticMatches, 19 SemanticMatches, 169 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11325 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=4590, Invalid=24480, Unknown=0, NotChecked=0, Total=29070 [2018-12-09 19:03:32,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1309 states. [2018-12-09 19:03:32,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1309 to 1302. [2018-12-09 19:03:32,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1302 states. [2018-12-09 19:03:32,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1302 states to 1302 states and 1307 transitions. [2018-12-09 19:03:32,895 INFO L78 Accepts]: Start accepts. Automaton has 1302 states and 1307 transitions. Word has length 1239 [2018-12-09 19:03:32,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:32,896 INFO L480 AbstractCegarLoop]: Abstraction has 1302 states and 1307 transitions. [2018-12-09 19:03:32,896 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-12-09 19:03:32,896 INFO L276 IsEmpty]: Start isEmpty. Operand 1302 states and 1307 transitions. [2018-12-09 19:03:32,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1245 [2018-12-09 19:03:32,902 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:32,902 INFO L402 BasicCegarLoop]: trace histogram [208, 207, 207, 207, 207, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:32,902 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:32,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:32,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1962245081, now seen corresponding path program 47 times [2018-12-09 19:03:32,902 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:32,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:32,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:32,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:32,903 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:32,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:33,891 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 33670 proven. 2568 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-09 19:03:33,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:33,891 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:33,891 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:33,891 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:33,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:33,892 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:33,897 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:03:33,897 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:03:34,186 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-12-09 19:03:34,186 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:34,194 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:34,936 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 18596 proven. 893 refuted. 0 times theorem prover too weak. 93011 trivial. 0 not checked. [2018-12-09 19:03:34,936 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:35,820 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 18596 proven. 893 refuted. 0 times theorem prover too weak. 93011 trivial. 0 not checked. [2018-12-09 19:03:35,836 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:35,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 22, 22] total 81 [2018-12-09 19:03:35,836 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:35,837 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-12-09 19:03:35,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-12-09 19:03:35,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1051, Invalid=5429, Unknown=0, NotChecked=0, Total=6480 [2018-12-09 19:03:35,837 INFO L87 Difference]: Start difference. First operand 1302 states and 1307 transitions. Second operand 67 states. [2018-12-09 19:03:37,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:37,531 INFO L93 Difference]: Finished difference Result 1432 states and 1440 transitions. [2018-12-09 19:03:37,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-09 19:03:37,531 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1244 [2018-12-09 19:03:37,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:37,533 INFO L225 Difference]: With dead ends: 1432 [2018-12-09 19:03:37,533 INFO L226 Difference]: Without dead ends: 1432 [2018-12-09 19:03:37,534 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2592 GetRequests, 2447 SyntacticMatches, 7 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4720 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=4767, Invalid=14693, Unknown=0, NotChecked=0, Total=19460 [2018-12-09 19:03:37,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1432 states. [2018-12-09 19:03:37,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1432 to 1419. [2018-12-09 19:03:37,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1419 states. [2018-12-09 19:03:37,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1419 states to 1419 states and 1427 transitions. [2018-12-09 19:03:37,541 INFO L78 Accepts]: Start accepts. Automaton has 1419 states and 1427 transitions. Word has length 1244 [2018-12-09 19:03:37,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:37,541 INFO L480 AbstractCegarLoop]: Abstraction has 1419 states and 1427 transitions. [2018-12-09 19:03:37,541 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-12-09 19:03:37,541 INFO L276 IsEmpty]: Start isEmpty. Operand 1419 states and 1427 transitions. [2018-12-09 19:03:37,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1255 [2018-12-09 19:03:37,548 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:37,548 INFO L402 BasicCegarLoop]: trace histogram [210, 209, 209, 209, 209, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:37,548 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:37,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:37,549 INFO L82 PathProgramCache]: Analyzing trace with hash 1445425069, now seen corresponding path program 48 times [2018-12-09 19:03:37,549 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:37,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:37,549 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:37,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:37,549 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:37,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:38,475 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20625 proven. 993 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-09 19:03:38,475 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:38,475 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:38,475 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:38,475 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:38,475 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:38,475 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:38,483 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:03:38,483 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:03:38,653 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:03:38,653 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:38,663 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:39,688 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20477 proven. 3307 refuted. 0 times theorem prover too weak. 90831 trivial. 0 not checked. [2018-12-09 19:03:39,688 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:40,593 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20477 proven. 3307 refuted. 0 times theorem prover too weak. 90831 trivial. 0 not checked. [2018-12-09 19:03:40,609 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:40,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 47, 47] total 73 [2018-12-09 19:03:40,609 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:40,610 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-12-09 19:03:40,610 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-12-09 19:03:40,610 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1021, Invalid=4235, Unknown=0, NotChecked=0, Total=5256 [2018-12-09 19:03:40,610 INFO L87 Difference]: Start difference. First operand 1419 states and 1427 transitions. Second operand 70 states. [2018-12-09 19:03:41,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:41,907 INFO L93 Difference]: Finished difference Result 1653 states and 1665 transitions. [2018-12-09 19:03:41,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-09 19:03:41,908 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1254 [2018-12-09 19:03:41,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:41,910 INFO L225 Difference]: With dead ends: 1653 [2018-12-09 19:03:41,910 INFO L226 Difference]: Without dead ends: 1653 [2018-12-09 19:03:41,911 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2592 GetRequests, 2437 SyntacticMatches, 43 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4225 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2766, Invalid=10116, Unknown=0, NotChecked=0, Total=12882 [2018-12-09 19:03:41,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1653 states. [2018-12-09 19:03:41,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1653 to 1639. [2018-12-09 19:03:41,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1639 states. [2018-12-09 19:03:41,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1639 states to 1639 states and 1651 transitions. [2018-12-09 19:03:41,920 INFO L78 Accepts]: Start accepts. Automaton has 1639 states and 1651 transitions. Word has length 1254 [2018-12-09 19:03:41,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:41,921 INFO L480 AbstractCegarLoop]: Abstraction has 1639 states and 1651 transitions. [2018-12-09 19:03:41,921 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-12-09 19:03:41,921 INFO L276 IsEmpty]: Start isEmpty. Operand 1639 states and 1651 transitions. [2018-12-09 19:03:41,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1356 [2018-12-09 19:03:41,928 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:41,928 INFO L402 BasicCegarLoop]: trace histogram [228, 227, 227, 227, 227, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:41,928 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:41,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:41,929 INFO L82 PathProgramCache]: Analyzing trace with hash -862088469, now seen corresponding path program 49 times [2018-12-09 19:03:41,929 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:41,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:41,929 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:41,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:41,929 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:41,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:43,030 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 36696 proven. 4418 refuted. 0 times theorem prover too weak. 93865 trivial. 0 not checked. [2018-12-09 19:03:43,030 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:43,030 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:43,030 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:43,030 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:43,030 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:43,030 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:43,039 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:43,039 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:03:43,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:43,239 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:44,479 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 54954 proven. 783 refuted. 0 times theorem prover too weak. 79242 trivial. 0 not checked. [2018-12-09 19:03:44,480 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:45,936 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 38434 proven. 2534 refuted. 0 times theorem prover too weak. 94011 trivial. 0 not checked. [2018-12-09 19:03:45,952 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:45,952 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 40, 40] total 104 [2018-12-09 19:03:45,952 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:45,953 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-12-09 19:03:45,953 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-12-09 19:03:45,953 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1692, Invalid=9020, Unknown=0, NotChecked=0, Total=10712 [2018-12-09 19:03:45,953 INFO L87 Difference]: Start difference. First operand 1639 states and 1651 transitions. Second operand 85 states. [2018-12-09 19:03:48,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:48,043 INFO L93 Difference]: Finished difference Result 1434 states and 1439 transitions. [2018-12-09 19:03:48,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-12-09 19:03:48,044 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1355 [2018-12-09 19:03:48,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:48,046 INFO L225 Difference]: With dead ends: 1434 [2018-12-09 19:03:48,046 INFO L226 Difference]: Without dead ends: 1425 [2018-12-09 19:03:48,047 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2833 GetRequests, 2635 SyntacticMatches, 20 SemanticMatches, 178 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12620 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=5080, Invalid=27140, Unknown=0, NotChecked=0, Total=32220 [2018-12-09 19:03:48,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1425 states. [2018-12-09 19:03:48,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1425 to 1418. [2018-12-09 19:03:48,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1418 states. [2018-12-09 19:03:48,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1418 states to 1418 states and 1423 transitions. [2018-12-09 19:03:48,053 INFO L78 Accepts]: Start accepts. Automaton has 1418 states and 1423 transitions. Word has length 1355 [2018-12-09 19:03:48,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:48,054 INFO L480 AbstractCegarLoop]: Abstraction has 1418 states and 1423 transitions. [2018-12-09 19:03:48,054 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-12-09 19:03:48,054 INFO L276 IsEmpty]: Start isEmpty. Operand 1418 states and 1423 transitions. [2018-12-09 19:03:48,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1361 [2018-12-09 19:03:48,061 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:48,061 INFO L402 BasicCegarLoop]: trace histogram [229, 228, 228, 228, 228, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:48,061 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:48,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:48,061 INFO L82 PathProgramCache]: Analyzing trace with hash -1077882064, now seen corresponding path program 50 times [2018-12-09 19:03:48,061 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:48,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:48,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:03:48,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:48,062 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:48,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:49,166 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 39313 proven. 2853 refuted. 0 times theorem prover too weak. 93969 trivial. 0 not checked. [2018-12-09 19:03:49,166 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:49,166 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:49,167 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:49,167 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:49,167 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:49,167 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:49,175 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:03:49,175 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:03:49,548 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-12-09 19:03:49,548 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:49,557 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:50,446 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 38420 proven. 2853 refuted. 0 times theorem prover too weak. 94862 trivial. 0 not checked. [2018-12-09 19:03:50,446 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:51,821 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 38343 proven. 2930 refuted. 0 times theorem prover too weak. 94862 trivial. 0 not checked. [2018-12-09 19:03:51,836 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:51,837 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 29, 29] total 99 [2018-12-09 19:03:51,837 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:51,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-12-09 19:03:51,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-12-09 19:03:51,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2041, Invalid=7661, Unknown=0, NotChecked=0, Total=9702 [2018-12-09 19:03:51,839 INFO L87 Difference]: Start difference. First operand 1418 states and 1423 transitions. Second operand 71 states. [2018-12-09 19:03:54,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:54,107 INFO L93 Difference]: Finished difference Result 1545 states and 1552 transitions. [2018-12-09 19:03:54,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-12-09 19:03:54,108 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1360 [2018-12-09 19:03:54,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:54,112 INFO L225 Difference]: With dead ends: 1545 [2018-12-09 19:03:54,112 INFO L226 Difference]: Without dead ends: 1545 [2018-12-09 19:03:54,115 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2828 GetRequests, 2669 SyntacticMatches, 1 SemanticMatches, 158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7527 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=6680, Invalid=18760, Unknown=0, NotChecked=0, Total=25440 [2018-12-09 19:03:54,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1545 states. [2018-12-09 19:03:54,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1545 to 1535. [2018-12-09 19:03:54,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1535 states. [2018-12-09 19:03:54,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1535 states to 1535 states and 1542 transitions. [2018-12-09 19:03:54,135 INFO L78 Accepts]: Start accepts. Automaton has 1535 states and 1542 transitions. Word has length 1360 [2018-12-09 19:03:54,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:54,136 INFO L480 AbstractCegarLoop]: Abstraction has 1535 states and 1542 transitions. [2018-12-09 19:03:54,136 INFO L481 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-12-09 19:03:54,136 INFO L276 IsEmpty]: Start isEmpty. Operand 1535 states and 1542 transitions. [2018-12-09 19:03:54,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1366 [2018-12-09 19:03:54,149 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:54,149 INFO L402 BasicCegarLoop]: trace histogram [230, 229, 229, 229, 229, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:54,150 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:54,150 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:54,150 INFO L82 PathProgramCache]: Analyzing trace with hash -1160826203, now seen corresponding path program 51 times [2018-12-09 19:03:54,150 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:54,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:54,151 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:54,151 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:54,151 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:54,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:03:54,965 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 22074 proven. 1084 refuted. 0 times theorem prover too weak. 114138 trivial. 0 not checked. [2018-12-09 19:03:54,965 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:54,965 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:03:54,965 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:03:54,966 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:03:54,966 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:03:54,966 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:03:54,971 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:03:54,971 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:03:55,751 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:03:55,751 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:03:55,765 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:03:56,460 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 21717 proven. 990 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-09 19:03:56,460 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:03:57,348 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 21717 proven. 990 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-09 19:03:57,367 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:03:57,367 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 22, 22] total 71 [2018-12-09 19:03:57,367 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:03:57,368 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-12-09 19:03:57,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-12-09 19:03:57,368 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=771, Invalid=4341, Unknown=0, NotChecked=0, Total=5112 [2018-12-09 19:03:57,368 INFO L87 Difference]: Start difference. First operand 1535 states and 1542 transitions. Second operand 51 states. [2018-12-09 19:03:59,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:03:59,248 INFO L93 Difference]: Finished difference Result 1794 states and 1807 transitions. [2018-12-09 19:03:59,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-12-09 19:03:59,248 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 1365 [2018-12-09 19:03:59,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:03:59,250 INFO L225 Difference]: With dead ends: 1794 [2018-12-09 19:03:59,250 INFO L226 Difference]: Without dead ends: 1794 [2018-12-09 19:03:59,251 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2783 GetRequests, 2688 SyntacticMatches, 0 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2260 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1497, Invalid=7815, Unknown=0, NotChecked=0, Total=9312 [2018-12-09 19:03:59,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1794 states. [2018-12-09 19:03:59,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1794 to 1765. [2018-12-09 19:03:59,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1765 states. [2018-12-09 19:03:59,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 1777 transitions. [2018-12-09 19:03:59,265 INFO L78 Accepts]: Start accepts. Automaton has 1765 states and 1777 transitions. Word has length 1365 [2018-12-09 19:03:59,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:03:59,266 INFO L480 AbstractCegarLoop]: Abstraction has 1765 states and 1777 transitions. [2018-12-09 19:03:59,266 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-12-09 19:03:59,266 INFO L276 IsEmpty]: Start isEmpty. Operand 1765 states and 1777 transitions. [2018-12-09 19:03:59,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1477 [2018-12-09 19:03:59,280 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:03:59,280 INFO L402 BasicCegarLoop]: trace histogram [250, 249, 249, 249, 249, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:03:59,281 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:03:59,281 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:03:59,281 INFO L82 PathProgramCache]: Analyzing trace with hash 1797808493, now seen corresponding path program 52 times [2018-12-09 19:03:59,281 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:03:59,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:59,282 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:03:59,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:03:59,282 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:03:59,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:00,532 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 42649 proven. 4900 refuted. 0 times theorem prover too weak. 114479 trivial. 0 not checked. [2018-12-09 19:04:00,532 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:00,532 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:00,532 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:00,532 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:00,532 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:00,532 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:00,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:04:00,540 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:04:00,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:00,757 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:02,113 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 63908 proven. 874 refuted. 0 times theorem prover too weak. 97246 trivial. 0 not checked. [2018-12-09 19:04:02,113 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:03,765 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 44588 proven. 2817 refuted. 0 times theorem prover too weak. 114623 trivial. 0 not checked. [2018-12-09 19:04:03,780 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:03,781 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 42, 42] total 109 [2018-12-09 19:04:03,781 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:03,781 INFO L459 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-12-09 19:04:03,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-12-09 19:04:03,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1860, Invalid=9912, Unknown=0, NotChecked=0, Total=11772 [2018-12-09 19:04:03,782 INFO L87 Difference]: Start difference. First operand 1765 states and 1777 transitions. Second operand 89 states. [2018-12-09 19:04:07,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:07,646 INFO L93 Difference]: Finished difference Result 1555 states and 1560 transitions. [2018-12-09 19:04:07,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 106 states. [2018-12-09 19:04:07,646 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 1476 [2018-12-09 19:04:07,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:07,649 INFO L225 Difference]: With dead ends: 1555 [2018-12-09 19:04:07,649 INFO L226 Difference]: Without dead ends: 1546 [2018-12-09 19:04:07,650 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3081 GetRequests, 2873 SyntacticMatches, 21 SemanticMatches, 187 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13985 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=5595, Invalid=29937, Unknown=0, NotChecked=0, Total=35532 [2018-12-09 19:04:07,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1546 states. [2018-12-09 19:04:07,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1546 to 1539. [2018-12-09 19:04:07,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2018-12-09 19:04:07,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 1544 transitions. [2018-12-09 19:04:07,658 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 1544 transitions. Word has length 1476 [2018-12-09 19:04:07,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:07,658 INFO L480 AbstractCegarLoop]: Abstraction has 1539 states and 1544 transitions. [2018-12-09 19:04:07,658 INFO L481 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-12-09 19:04:07,658 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 1544 transitions. [2018-12-09 19:04:07,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1482 [2018-12-09 19:04:07,667 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:07,667 INFO L402 BasicCegarLoop]: trace histogram [251, 250, 250, 250, 250, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:07,667 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:07,667 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:07,667 INFO L82 PathProgramCache]: Analyzing trace with hash -667535262, now seen corresponding path program 53 times [2018-12-09 19:04:07,668 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:07,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:07,668 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:04:07,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:07,668 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:07,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:08,939 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 45553 proven. 3153 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-09 19:04:08,939 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:08,939 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:08,939 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:08,939 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:08,939 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:08,939 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:08,945 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:04:08,945 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:04:09,407 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-12-09 19:04:09,407 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:04:09,416 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:10,415 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 44563 proven. 3153 refuted. 0 times theorem prover too weak. 115579 trivial. 0 not checked. [2018-12-09 19:04:10,415 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:11,962 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 44482 proven. 3234 refuted. 0 times theorem prover too weak. 115579 trivial. 0 not checked. [2018-12-09 19:04:11,977 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:11,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 30, 30] total 103 [2018-12-09 19:04:11,978 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:11,978 INFO L459 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-12-09 19:04:11,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-12-09 19:04:11,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2203, Invalid=8303, Unknown=0, NotChecked=0, Total=10506 [2018-12-09 19:04:11,979 INFO L87 Difference]: Start difference. First operand 1539 states and 1544 transitions. Second operand 74 states. [2018-12-09 19:04:14,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:14,004 INFO L93 Difference]: Finished difference Result 1671 states and 1678 transitions. [2018-12-09 19:04:14,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-12-09 19:04:14,004 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1481 [2018-12-09 19:04:14,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:14,007 INFO L225 Difference]: With dead ends: 1671 [2018-12-09 19:04:14,007 INFO L226 Difference]: Without dead ends: 1671 [2018-12-09 19:04:14,008 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3075 GetRequests, 2909 SyntacticMatches, 1 SemanticMatches, 165 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8269 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=7267, Invalid=20455, Unknown=0, NotChecked=0, Total=27722 [2018-12-09 19:04:14,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1671 states. [2018-12-09 19:04:14,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1671 to 1661. [2018-12-09 19:04:14,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1661 states. [2018-12-09 19:04:14,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1661 states to 1661 states and 1668 transitions. [2018-12-09 19:04:14,016 INFO L78 Accepts]: Start accepts. Automaton has 1661 states and 1668 transitions. Word has length 1481 [2018-12-09 19:04:14,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:14,017 INFO L480 AbstractCegarLoop]: Abstraction has 1661 states and 1668 transitions. [2018-12-09 19:04:14,017 INFO L481 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-12-09 19:04:14,017 INFO L276 IsEmpty]: Start isEmpty. Operand 1661 states and 1668 transitions. [2018-12-09 19:04:14,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1487 [2018-12-09 19:04:14,027 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:14,027 INFO L402 BasicCegarLoop]: trace histogram [252, 251, 251, 251, 251, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:14,027 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:14,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:14,027 INFO L82 PathProgramCache]: Analyzing trace with hash 9778855, now seen corresponding path program 54 times [2018-12-09 19:04:14,028 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:14,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:14,028 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:04:14,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:14,028 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:14,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:14,905 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25151 proven. 1201 refuted. 0 times theorem prover too weak. 138215 trivial. 0 not checked. [2018-12-09 19:04:14,905 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:14,905 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:14,905 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:14,905 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:14,905 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:14,905 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:14,911 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:04:14,911 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:04:15,951 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:04:15,951 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:04:15,968 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:16,754 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25050 proven. 1092 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-09 19:04:16,754 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:17,750 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25050 proven. 1092 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-09 19:04:17,769 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:17,770 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 23, 23] total 71 [2018-12-09 19:04:17,770 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:17,770 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-09 19:04:17,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-09 19:04:17,771 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=804, Invalid=4308, Unknown=0, NotChecked=0, Total=5112 [2018-12-09 19:04:17,771 INFO L87 Difference]: Start difference. First operand 1661 states and 1668 transitions. Second operand 50 states. [2018-12-09 19:04:19,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:19,711 INFO L93 Difference]: Finished difference Result 1930 states and 1943 transitions. [2018-12-09 19:04:19,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-12-09 19:04:19,712 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 1486 [2018-12-09 19:04:19,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:19,714 INFO L225 Difference]: With dead ends: 1930 [2018-12-09 19:04:19,714 INFO L226 Difference]: Without dead ends: 1930 [2018-12-09 19:04:19,714 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3024 GetRequests, 2928 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2305 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1502, Invalid=8004, Unknown=0, NotChecked=0, Total=9506 [2018-12-09 19:04:19,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1930 states. [2018-12-09 19:04:19,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1930 to 1901. [2018-12-09 19:04:19,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1901 states. [2018-12-09 19:04:19,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1901 states to 1901 states and 1913 transitions. [2018-12-09 19:04:19,723 INFO L78 Accepts]: Start accepts. Automaton has 1901 states and 1913 transitions. Word has length 1486 [2018-12-09 19:04:19,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:19,723 INFO L480 AbstractCegarLoop]: Abstraction has 1901 states and 1913 transitions. [2018-12-09 19:04:19,724 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-09 19:04:19,724 INFO L276 IsEmpty]: Start isEmpty. Operand 1901 states and 1913 transitions. [2018-12-09 19:04:19,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1603 [2018-12-09 19:04:19,734 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:19,734 INFO L402 BasicCegarLoop]: trace histogram [273, 272, 272, 272, 272, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:19,735 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:19,735 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:19,735 INFO L82 PathProgramCache]: Analyzing trace with hash 1962499760, now seen corresponding path program 55 times [2018-12-09 19:04:19,735 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:19,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:19,735 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:04:19,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:19,735 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:19,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:21,177 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 49214 proven. 5407 refuted. 0 times theorem prover too weak. 138309 trivial. 0 not checked. [2018-12-09 19:04:21,177 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:21,177 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:21,178 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:21,178 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:21,178 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:21,178 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:21,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:04:21,184 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:04:21,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:21,416 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:22,988 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 73783 proven. 970 refuted. 0 times theorem prover too weak. 118177 trivial. 0 not checked. [2018-12-09 19:04:22,988 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:24,841 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 51365 proven. 3115 refuted. 0 times theorem prover too weak. 138450 trivial. 0 not checked. [2018-12-09 19:04:24,856 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:24,857 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 44, 44] total 114 [2018-12-09 19:04:24,857 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:24,857 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-12-09 19:04:24,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-12-09 19:04:24,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2036, Invalid=10846, Unknown=0, NotChecked=0, Total=12882 [2018-12-09 19:04:24,858 INFO L87 Difference]: Start difference. First operand 1901 states and 1913 transitions. Second operand 93 states. [2018-12-09 19:04:27,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:27,393 INFO L93 Difference]: Finished difference Result 1681 states and 1686 transitions. [2018-12-09 19:04:27,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-12-09 19:04:27,393 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1602 [2018-12-09 19:04:27,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:27,395 INFO L225 Difference]: With dead ends: 1681 [2018-12-09 19:04:27,395 INFO L226 Difference]: Without dead ends: 1672 [2018-12-09 19:04:27,397 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3339 GetRequests, 3121 SyntacticMatches, 22 SemanticMatches, 196 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15420 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=6135, Invalid=32871, Unknown=0, NotChecked=0, Total=39006 [2018-12-09 19:04:27,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1672 states. [2018-12-09 19:04:27,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1672 to 1665. [2018-12-09 19:04:27,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1665 states. [2018-12-09 19:04:27,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1665 states to 1665 states and 1670 transitions. [2018-12-09 19:04:27,405 INFO L78 Accepts]: Start accepts. Automaton has 1665 states and 1670 transitions. Word has length 1602 [2018-12-09 19:04:27,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:27,405 INFO L480 AbstractCegarLoop]: Abstraction has 1665 states and 1670 transitions. [2018-12-09 19:04:27,405 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-12-09 19:04:27,405 INFO L276 IsEmpty]: Start isEmpty. Operand 1665 states and 1670 transitions. [2018-12-09 19:04:27,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1608 [2018-12-09 19:04:27,415 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:27,416 INFO L402 BasicCegarLoop]: trace histogram [274, 273, 273, 273, 273, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:27,416 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:27,416 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:27,416 INFO L82 PathProgramCache]: Analyzing trace with hash -1747254261, now seen corresponding path program 56 times [2018-12-09 19:04:27,416 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:27,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:27,417 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:04:27,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:27,417 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:27,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:28,899 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 52420 proven. 3468 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-09 19:04:28,899 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:28,899 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:28,899 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:28,899 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:28,900 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:28,900 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:28,905 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:04:28,905 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:04:29,458 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-12-09 19:04:29,458 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:04:29,469 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:30,583 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 28595 proven. 1199 refuted. 0 times theorem prover too weak. 164519 trivial. 0 not checked. [2018-12-09 19:04:30,583 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:31,778 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 28595 proven. 1199 refuted. 0 times theorem prover too weak. 164519 trivial. 0 not checked. [2018-12-09 19:04:31,794 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:31,794 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 25, 25] total 87 [2018-12-09 19:04:31,794 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:31,795 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-12-09 19:04:31,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-12-09 19:04:31,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1180, Invalid=6302, Unknown=0, NotChecked=0, Total=7482 [2018-12-09 19:04:31,795 INFO L87 Difference]: Start difference. First operand 1665 states and 1670 transitions. Second operand 76 states. [2018-12-09 19:04:33,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:33,914 INFO L93 Difference]: Finished difference Result 1810 states and 1818 transitions. [2018-12-09 19:04:33,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-09 19:04:33,914 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1607 [2018-12-09 19:04:33,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:33,916 INFO L225 Difference]: With dead ends: 1810 [2018-12-09 19:04:33,916 INFO L226 Difference]: Without dead ends: 1810 [2018-12-09 19:04:33,917 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3333 GetRequests, 3167 SyntacticMatches, 13 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6283 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=5733, Invalid=18137, Unknown=0, NotChecked=0, Total=23870 [2018-12-09 19:04:33,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1810 states. [2018-12-09 19:04:33,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1810 to 1797. [2018-12-09 19:04:33,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1797 states. [2018-12-09 19:04:33,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1797 states to 1797 states and 1805 transitions. [2018-12-09 19:04:33,926 INFO L78 Accepts]: Start accepts. Automaton has 1797 states and 1805 transitions. Word has length 1607 [2018-12-09 19:04:33,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:33,926 INFO L480 AbstractCegarLoop]: Abstraction has 1797 states and 1805 transitions. [2018-12-09 19:04:33,926 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-12-09 19:04:33,926 INFO L276 IsEmpty]: Start isEmpty. Operand 1797 states and 1805 transitions. [2018-12-09 19:04:33,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1618 [2018-12-09 19:04:33,937 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:33,937 INFO L402 BasicCegarLoop]: trace histogram [276, 275, 275, 275, 275, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:33,937 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:33,937 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:33,937 INFO L82 PathProgramCache]: Analyzing trace with hash -1712352251, now seen corresponding path program 57 times [2018-12-09 19:04:33,937 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:33,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:33,938 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:04:33,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:33,938 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:34,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:35,299 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31275 proven. 1347 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-09 19:04:35,300 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:35,300 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:35,300 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:35,300 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:35,300 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:35,300 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:35,306 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:04:35,307 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:04:35,507 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:04:35,507 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:04:35,520 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:36,937 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31106 proven. 4393 refuted. 0 times theorem prover too weak. 161595 trivial. 0 not checked. [2018-12-09 19:04:36,937 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:38,269 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31106 proven. 4393 refuted. 0 times theorem prover too weak. 161595 trivial. 0 not checked. [2018-12-09 19:04:38,285 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:38,286 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 53, 53] total 82 [2018-12-09 19:04:38,286 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:38,286 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-12-09 19:04:38,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-12-09 19:04:38,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1306, Invalid=5336, Unknown=0, NotChecked=0, Total=6642 [2018-12-09 19:04:38,287 INFO L87 Difference]: Start difference. First operand 1797 states and 1805 transitions. Second operand 79 states. [2018-12-09 19:04:39,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:39,792 INFO L93 Difference]: Finished difference Result 2061 states and 2073 transitions. [2018-12-09 19:04:39,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-09 19:04:39,792 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1617 [2018-12-09 19:04:39,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:39,794 INFO L225 Difference]: With dead ends: 2061 [2018-12-09 19:04:39,795 INFO L226 Difference]: Without dead ends: 2061 [2018-12-09 19:04:39,795 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3330 GetRequests, 3154 SyntacticMatches, 49 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5413 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3582, Invalid=12930, Unknown=0, NotChecked=0, Total=16512 [2018-12-09 19:04:39,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2061 states. [2018-12-09 19:04:39,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2061 to 2047. [2018-12-09 19:04:39,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2047 states. [2018-12-09 19:04:39,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 2059 transitions. [2018-12-09 19:04:39,806 INFO L78 Accepts]: Start accepts. Automaton has 2047 states and 2059 transitions. Word has length 1617 [2018-12-09 19:04:39,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:39,807 INFO L480 AbstractCegarLoop]: Abstraction has 2047 states and 2059 transitions. [2018-12-09 19:04:39,807 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-12-09 19:04:39,807 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 2059 transitions. [2018-12-09 19:04:39,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1734 [2018-12-09 19:04:39,818 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:39,818 INFO L402 BasicCegarLoop]: trace histogram [297, 296, 296, 296, 296, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:39,818 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:39,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:39,818 INFO L82 PathProgramCache]: Analyzing trace with hash -1388841432, now seen corresponding path program 58 times [2018-12-09 19:04:39,818 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:39,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:39,819 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:04:39,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:39,819 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:39,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:41,410 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 56421 proven. 5939 refuted. 0 times theorem prover too weak. 165673 trivial. 0 not checked. [2018-12-09 19:04:41,411 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:41,411 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:41,411 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:41,411 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:41,411 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:41,411 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:41,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:04:41,419 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:04:41,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:41,686 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:43,448 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 84624 proven. 1071 refuted. 0 times theorem prover too weak. 142338 trivial. 0 not checked. [2018-12-09 19:04:43,448 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:45,543 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 58795 proven. 3428 refuted. 0 times theorem prover too weak. 165810 trivial. 0 not checked. [2018-12-09 19:04:45,559 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:45,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 46, 46] total 119 [2018-12-09 19:04:45,560 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:45,561 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-12-09 19:04:45,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-12-09 19:04:45,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2220, Invalid=11822, Unknown=0, NotChecked=0, Total=14042 [2018-12-09 19:04:45,562 INFO L87 Difference]: Start difference. First operand 2047 states and 2059 transitions. Second operand 97 states. [2018-12-09 19:04:48,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:48,250 INFO L93 Difference]: Finished difference Result 1812 states and 1817 transitions. [2018-12-09 19:04:48,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 116 states. [2018-12-09 19:04:48,251 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 1733 [2018-12-09 19:04:48,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:48,254 INFO L225 Difference]: With dead ends: 1812 [2018-12-09 19:04:48,254 INFO L226 Difference]: Without dead ends: 1803 [2018-12-09 19:04:48,257 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3607 GetRequests, 3379 SyntacticMatches, 23 SemanticMatches, 205 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16925 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=6700, Invalid=35942, Unknown=0, NotChecked=0, Total=42642 [2018-12-09 19:04:48,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1803 states. [2018-12-09 19:04:48,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1803 to 1796. [2018-12-09 19:04:48,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1796 states. [2018-12-09 19:04:48,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1796 states to 1796 states and 1801 transitions. [2018-12-09 19:04:48,268 INFO L78 Accepts]: Start accepts. Automaton has 1796 states and 1801 transitions. Word has length 1733 [2018-12-09 19:04:48,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:48,269 INFO L480 AbstractCegarLoop]: Abstraction has 1796 states and 1801 transitions. [2018-12-09 19:04:48,269 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-12-09 19:04:48,269 INFO L276 IsEmpty]: Start isEmpty. Operand 1796 states and 1801 transitions. [2018-12-09 19:04:48,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1739 [2018-12-09 19:04:48,284 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:48,285 INFO L402 BasicCegarLoop]: trace histogram [298, 297, 297, 297, 297, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:48,285 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:48,285 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:48,286 INFO L82 PathProgramCache]: Analyzing trace with hash -1675122425, now seen corresponding path program 59 times [2018-12-09 19:04:48,286 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:48,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:48,286 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:04:48,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:48,286 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:48,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:49,903 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 59944 proven. 3798 refuted. 0 times theorem prover too weak. 165795 trivial. 0 not checked. [2018-12-09 19:04:49,903 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:49,903 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:49,904 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:49,904 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:49,904 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:49,904 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:49,910 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:04:49,910 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:04:50,679 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-12-09 19:04:50,679 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:04:50,690 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:04:51,896 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 32586 proven. 1311 refuted. 0 times theorem prover too weak. 195640 trivial. 0 not checked. [2018-12-09 19:04:51,897 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:04:53,226 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 32586 proven. 1311 refuted. 0 times theorem prover too weak. 195640 trivial. 0 not checked. [2018-12-09 19:04:53,242 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:04:53,242 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 26, 26] total 89 [2018-12-09 19:04:53,242 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:04:53,243 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-12-09 19:04:53,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-12-09 19:04:53,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1227, Invalid=6605, Unknown=0, NotChecked=0, Total=7832 [2018-12-09 19:04:53,243 INFO L87 Difference]: Start difference. First operand 1796 states and 1801 transitions. Second operand 79 states. [2018-12-09 19:04:57,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:04:57,719 INFO L93 Difference]: Finished difference Result 1946 states and 1954 transitions. [2018-12-09 19:04:57,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-12-09 19:04:57,720 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1738 [2018-12-09 19:04:57,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:04:57,724 INFO L225 Difference]: With dead ends: 1946 [2018-12-09 19:04:57,725 INFO L226 Difference]: Without dead ends: 1946 [2018-12-09 19:04:57,726 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3600 GetRequests, 3427 SyntacticMatches, 15 SemanticMatches, 158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6850 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=6075, Invalid=19365, Unknown=0, NotChecked=0, Total=25440 [2018-12-09 19:04:57,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1946 states. [2018-12-09 19:04:57,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1946 to 1933. [2018-12-09 19:04:57,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1933 states. [2018-12-09 19:04:57,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1933 states to 1933 states and 1941 transitions. [2018-12-09 19:04:57,739 INFO L78 Accepts]: Start accepts. Automaton has 1933 states and 1941 transitions. Word has length 1738 [2018-12-09 19:04:57,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:04:57,740 INFO L480 AbstractCegarLoop]: Abstraction has 1933 states and 1941 transitions. [2018-12-09 19:04:57,740 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-12-09 19:04:57,740 INFO L276 IsEmpty]: Start isEmpty. Operand 1933 states and 1941 transitions. [2018-12-09 19:04:57,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1749 [2018-12-09 19:04:57,753 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:04:57,753 INFO L402 BasicCegarLoop]: trace histogram [300, 299, 299, 299, 299, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:04:57,753 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:04:57,753 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:04:57,753 INFO L82 PathProgramCache]: Analyzing trace with hash 1749257613, now seen corresponding path program 60 times [2018-12-09 19:04:57,753 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:04:57,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:57,754 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:04:57,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:04:57,754 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:04:57,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:04:59,261 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35503 proven. 1477 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-09 19:04:59,261 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:59,261 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:04:59,261 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:04:59,262 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:04:59,262 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:04:59,262 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:04:59,268 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:04:59,268 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:04:59,485 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:04:59,485 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:04:59,499 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:01,109 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35327 proven. 4789 refuted. 0 times theorem prover too weak. 192444 trivial. 0 not checked. [2018-12-09 19:05:01,109 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:05:02,530 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35327 proven. 4789 refuted. 0 times theorem prover too weak. 192444 trivial. 0 not checked. [2018-12-09 19:05:02,547 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:05:02,547 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 55, 55] total 85 [2018-12-09 19:05:02,547 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:05:02,548 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-12-09 19:05:02,548 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-12-09 19:05:02,548 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1409, Invalid=5731, Unknown=0, NotChecked=0, Total=7140 [2018-12-09 19:05:02,548 INFO L87 Difference]: Start difference. First operand 1933 states and 1941 transitions. Second operand 82 states. [2018-12-09 19:05:04,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:05:04,364 INFO L93 Difference]: Finished difference Result 2207 states and 2219 transitions. [2018-12-09 19:05:04,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-12-09 19:05:04,364 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 1748 [2018-12-09 19:05:04,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:05:04,367 INFO L225 Difference]: With dead ends: 2207 [2018-12-09 19:05:04,367 INFO L226 Difference]: Without dead ends: 2207 [2018-12-09 19:05:04,368 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3596 GetRequests, 3413 SyntacticMatches, 51 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5841 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=3878, Invalid=13944, Unknown=0, NotChecked=0, Total=17822 [2018-12-09 19:05:04,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2207 states. [2018-12-09 19:05:04,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2207 to 2193. [2018-12-09 19:05:04,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2193 states. [2018-12-09 19:05:04,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2193 states to 2193 states and 2205 transitions. [2018-12-09 19:05:04,377 INFO L78 Accepts]: Start accepts. Automaton has 2193 states and 2205 transitions. Word has length 1748 [2018-12-09 19:05:04,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:05:04,378 INFO L480 AbstractCegarLoop]: Abstraction has 2193 states and 2205 transitions. [2018-12-09 19:05:04,378 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-12-09 19:05:04,378 INFO L276 IsEmpty]: Start isEmpty. Operand 2193 states and 2205 transitions. [2018-12-09 19:05:04,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1870 [2018-12-09 19:05:04,390 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:05:04,391 INFO L402 BasicCegarLoop]: trace histogram [322, 321, 321, 321, 321, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:05:04,391 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:05:04,391 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:05:04,391 INFO L82 PathProgramCache]: Analyzing trace with hash -299998901, now seen corresponding path program 61 times [2018-12-09 19:05:04,391 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:05:04,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:04,391 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:05:04,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:04,392 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:05:04,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:06,186 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 64300 proven. 6496 refuted. 0 times theorem prover too weak. 196904 trivial. 0 not checked. [2018-12-09 19:05:06,186 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:06,186 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:05:06,186 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:05:06,187 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:05:06,187 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:06,187 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:05:06,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:05:06,193 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:05:06,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:06,468 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:08,404 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 96476 proven. 1177 refuted. 0 times theorem prover too weak. 170047 trivial. 0 not checked. [2018-12-09 19:05:08,404 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:05:10,680 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 66908 proven. 3756 refuted. 0 times theorem prover too weak. 197036 trivial. 0 not checked. [2018-12-09 19:05:10,697 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:05:10,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 48, 48] total 124 [2018-12-09 19:05:10,697 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:05:10,698 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-12-09 19:05:10,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-12-09 19:05:10,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2412, Invalid=12840, Unknown=0, NotChecked=0, Total=15252 [2018-12-09 19:05:10,699 INFO L87 Difference]: Start difference. First operand 2193 states and 2205 transitions. Second operand 101 states. [2018-12-09 19:05:13,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:05:13,259 INFO L93 Difference]: Finished difference Result 1948 states and 1953 transitions. [2018-12-09 19:05:13,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-12-09 19:05:13,259 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 1869 [2018-12-09 19:05:13,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:05:13,261 INFO L225 Difference]: With dead ends: 1948 [2018-12-09 19:05:13,261 INFO L226 Difference]: Without dead ends: 1939 [2018-12-09 19:05:13,263 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3885 GetRequests, 3647 SyntacticMatches, 24 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18500 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=7290, Invalid=39150, Unknown=0, NotChecked=0, Total=46440 [2018-12-09 19:05:13,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1939 states. [2018-12-09 19:05:13,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1939 to 1932. [2018-12-09 19:05:13,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1932 states. [2018-12-09 19:05:13,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1932 states to 1932 states and 1937 transitions. [2018-12-09 19:05:13,271 INFO L78 Accepts]: Start accepts. Automaton has 1932 states and 1937 transitions. Word has length 1869 [2018-12-09 19:05:13,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:05:13,272 INFO L480 AbstractCegarLoop]: Abstraction has 1932 states and 1937 transitions. [2018-12-09 19:05:13,272 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-12-09 19:05:13,272 INFO L276 IsEmpty]: Start isEmpty. Operand 1932 states and 1937 transitions. [2018-12-09 19:05:13,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1875 [2018-12-09 19:05:13,284 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:05:13,284 INFO L402 BasicCegarLoop]: trace histogram [323, 322, 322, 322, 322, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:05:13,284 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:05:13,284 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:05:13,285 INFO L82 PathProgramCache]: Analyzing trace with hash 754168784, now seen corresponding path program 62 times [2018-12-09 19:05:13,285 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:05:13,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:13,285 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:05:13,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:13,285 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:05:13,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:15,110 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 68155 proven. 4143 refuted. 0 times theorem prover too weak. 197032 trivial. 0 not checked. [2018-12-09 19:05:15,110 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:15,110 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:05:15,110 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:05:15,111 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:05:15,111 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:15,111 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:05:15,117 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:05:15,117 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:05:15,804 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-12-09 19:05:15,804 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:05:15,816 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:17,155 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 36931 proven. 1428 refuted. 0 times theorem prover too weak. 230971 trivial. 0 not checked. [2018-12-09 19:05:17,155 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:05:18,621 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 36931 proven. 1428 refuted. 0 times theorem prover too weak. 230971 trivial. 0 not checked. [2018-12-09 19:05:18,638 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:05:18,638 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 27, 27] total 91 [2018-12-09 19:05:18,638 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:05:18,639 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-12-09 19:05:18,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-12-09 19:05:18,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=6914, Unknown=0, NotChecked=0, Total=8190 [2018-12-09 19:05:18,639 INFO L87 Difference]: Start difference. First operand 1932 states and 1937 transitions. Second operand 82 states. [2018-12-09 19:05:20,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:05:20,996 INFO L93 Difference]: Finished difference Result 2087 states and 2095 transitions. [2018-12-09 19:05:20,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-09 19:05:20,996 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 1874 [2018-12-09 19:05:20,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:05:20,998 INFO L225 Difference]: With dead ends: 2087 [2018-12-09 19:05:20,999 INFO L226 Difference]: Without dead ends: 2087 [2018-12-09 19:05:21,000 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3877 GetRequests, 3697 SyntacticMatches, 17 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7440 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=6427, Invalid=20633, Unknown=0, NotChecked=0, Total=27060 [2018-12-09 19:05:21,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2087 states. [2018-12-09 19:05:21,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2087 to 2074. [2018-12-09 19:05:21,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2074 states. [2018-12-09 19:05:21,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2074 states to 2074 states and 2082 transitions. [2018-12-09 19:05:21,009 INFO L78 Accepts]: Start accepts. Automaton has 2074 states and 2082 transitions. Word has length 1874 [2018-12-09 19:05:21,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:05:21,010 INFO L480 AbstractCegarLoop]: Abstraction has 2074 states and 2082 transitions. [2018-12-09 19:05:21,010 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-12-09 19:05:21,010 INFO L276 IsEmpty]: Start isEmpty. Operand 2074 states and 2082 transitions. [2018-12-09 19:05:21,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1885 [2018-12-09 19:05:21,023 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:05:21,023 INFO L402 BasicCegarLoop]: trace histogram [325, 324, 324, 324, 324, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:05:21,023 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:05:21,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:05:21,024 INFO L82 PathProgramCache]: Analyzing trace with hash 1694558474, now seen corresponding path program 63 times [2018-12-09 19:05:21,024 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:05:21,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:21,024 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:05:21,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:21,024 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:05:21,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:22,729 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 40095 proven. 1613 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-09 19:05:22,729 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:22,729 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:05:22,730 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:05:22,730 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:05:22,730 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:22,730 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:05:22,736 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:05:22,736 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:05:22,969 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:05:22,969 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:05:22,984 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:24,737 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 39912 proven. 5202 refuted. 0 times theorem prover too weak. 227491 trivial. 0 not checked. [2018-12-09 19:05:24,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:05:26,328 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 39912 proven. 5202 refuted. 0 times theorem prover too weak. 227491 trivial. 0 not checked. [2018-12-09 19:05:26,344 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:05:26,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 57, 57] total 88 [2018-12-09 19:05:26,345 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:05:26,345 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-12-09 19:05:26,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-12-09 19:05:26,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1516, Invalid=6140, Unknown=0, NotChecked=0, Total=7656 [2018-12-09 19:05:26,346 INFO L87 Difference]: Start difference. First operand 2074 states and 2082 transitions. Second operand 85 states. [2018-12-09 19:05:27,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:05:27,961 INFO L93 Difference]: Finished difference Result 2358 states and 2370 transitions. [2018-12-09 19:05:27,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-09 19:05:27,961 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1884 [2018-12-09 19:05:27,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:05:27,964 INFO L225 Difference]: With dead ends: 2358 [2018-12-09 19:05:27,964 INFO L226 Difference]: Without dead ends: 2358 [2018-12-09 19:05:27,964 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3872 GetRequests, 3682 SyntacticMatches, 53 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6285 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=4186, Invalid=14996, Unknown=0, NotChecked=0, Total=19182 [2018-12-09 19:05:27,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2358 states. [2018-12-09 19:05:27,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2358 to 2344. [2018-12-09 19:05:27,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2344 states. [2018-12-09 19:05:27,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2344 states to 2344 states and 2356 transitions. [2018-12-09 19:05:27,975 INFO L78 Accepts]: Start accepts. Automaton has 2344 states and 2356 transitions. Word has length 1884 [2018-12-09 19:05:27,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:05:27,976 INFO L480 AbstractCegarLoop]: Abstraction has 2344 states and 2356 transitions. [2018-12-09 19:05:27,976 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-12-09 19:05:27,976 INFO L276 IsEmpty]: Start isEmpty. Operand 2344 states and 2356 transitions. [2018-12-09 19:05:27,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2011 [2018-12-09 19:05:27,990 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:05:27,990 INFO L402 BasicCegarLoop]: trace histogram [348, 347, 347, 347, 347, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:05:27,990 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:05:27,991 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:05:27,991 INFO L82 PathProgramCache]: Analyzing trace with hash -455283635, now seen corresponding path program 64 times [2018-12-09 19:05:27,991 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:05:27,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:27,991 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:05:27,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:27,991 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:05:28,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:29,985 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 72881 proven. 7078 refuted. 0 times theorem prover too weak. 232350 trivial. 0 not checked. [2018-12-09 19:05:29,985 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:29,985 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:05:29,985 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:05:29,985 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:05:29,985 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:29,985 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:05:29,991 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:05:29,991 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:05:30,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:30,298 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:32,501 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 109384 proven. 1288 refuted. 0 times theorem prover too weak. 201637 trivial. 0 not checked. [2018-12-09 19:05:32,501 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:05:35,040 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 75734 proven. 4099 refuted. 0 times theorem prover too weak. 232476 trivial. 0 not checked. [2018-12-09 19:05:35,056 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:05:35,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 50, 50] total 129 [2018-12-09 19:05:35,057 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:05:35,057 INFO L459 AbstractCegarLoop]: Interpolant automaton has 105 states [2018-12-09 19:05:35,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 105 interpolants. [2018-12-09 19:05:35,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2612, Invalid=13900, Unknown=0, NotChecked=0, Total=16512 [2018-12-09 19:05:35,058 INFO L87 Difference]: Start difference. First operand 2344 states and 2356 transitions. Second operand 105 states. [2018-12-09 19:05:38,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:05:38,307 INFO L93 Difference]: Finished difference Result 2089 states and 2094 transitions. [2018-12-09 19:05:38,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2018-12-09 19:05:38,307 INFO L78 Accepts]: Start accepts. Automaton has 105 states. Word has length 2010 [2018-12-09 19:05:38,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:05:38,310 INFO L225 Difference]: With dead ends: 2089 [2018-12-09 19:05:38,310 INFO L226 Difference]: Without dead ends: 2080 [2018-12-09 19:05:38,312 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4173 GetRequests, 3925 SyntacticMatches, 25 SemanticMatches, 223 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20145 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=7905, Invalid=42495, Unknown=0, NotChecked=0, Total=50400 [2018-12-09 19:05:38,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2080 states. [2018-12-09 19:05:38,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2080 to 2073. [2018-12-09 19:05:38,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2073 states. [2018-12-09 19:05:38,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2073 states to 2073 states and 2078 transitions. [2018-12-09 19:05:38,320 INFO L78 Accepts]: Start accepts. Automaton has 2073 states and 2078 transitions. Word has length 2010 [2018-12-09 19:05:38,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:05:38,321 INFO L480 AbstractCegarLoop]: Abstraction has 2073 states and 2078 transitions. [2018-12-09 19:05:38,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 105 states. [2018-12-09 19:05:38,321 INFO L276 IsEmpty]: Start isEmpty. Operand 2073 states and 2078 transitions. [2018-12-09 19:05:38,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2016 [2018-12-09 19:05:38,335 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:05:38,335 INFO L402 BasicCegarLoop]: trace histogram [349, 348, 348, 348, 348, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:05:38,336 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:05:38,336 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:05:38,336 INFO L82 PathProgramCache]: Analyzing trace with hash -2048382334, now seen corresponding path program 65 times [2018-12-09 19:05:38,336 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:05:38,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:38,336 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:05:38,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:38,336 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:05:38,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:40,401 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 77083 proven. 4503 refuted. 0 times theorem prover too weak. 232484 trivial. 0 not checked. [2018-12-09 19:05:40,402 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:40,402 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:05:40,402 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:05:40,402 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:05:40,402 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:40,402 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:05:40,408 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:05:40,408 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:05:41,521 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-12-09 19:05:41,521 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:05:41,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:43,144 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 75655 proven. 4503 refuted. 0 times theorem prover too weak. 233912 trivial. 0 not checked. [2018-12-09 19:05:43,144 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:05:45,372 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 75558 proven. 4600 refuted. 0 times theorem prover too weak. 233912 trivial. 0 not checked. [2018-12-09 19:05:45,389 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:05:45,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 34, 34] total 119 [2018-12-09 19:05:45,390 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:05:45,391 INFO L459 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-12-09 19:05:45,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-12-09 19:05:45,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2861, Invalid=11181, Unknown=0, NotChecked=0, Total=14042 [2018-12-09 19:05:45,392 INFO L87 Difference]: Start difference. First operand 2073 states and 2078 transitions. Second operand 86 states. [2018-12-09 19:05:47,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:05:47,566 INFO L93 Difference]: Finished difference Result 2225 states and 2232 transitions. [2018-12-09 19:05:47,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-12-09 19:05:47,567 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 2015 [2018-12-09 19:05:47,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:05:47,569 INFO L225 Difference]: With dead ends: 2225 [2018-12-09 19:05:47,569 INFO L226 Difference]: Without dead ends: 2225 [2018-12-09 19:05:47,571 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4163 GetRequests, 3969 SyntacticMatches, 1 SemanticMatches, 193 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11617 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=9785, Invalid=28045, Unknown=0, NotChecked=0, Total=37830 [2018-12-09 19:05:47,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2225 states. [2018-12-09 19:05:47,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2225 to 2215. [2018-12-09 19:05:47,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2215 states. [2018-12-09 19:05:47,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2215 states to 2215 states and 2222 transitions. [2018-12-09 19:05:47,580 INFO L78 Accepts]: Start accepts. Automaton has 2215 states and 2222 transitions. Word has length 2015 [2018-12-09 19:05:47,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:05:47,581 INFO L480 AbstractCegarLoop]: Abstraction has 2215 states and 2222 transitions. [2018-12-09 19:05:47,581 INFO L481 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-12-09 19:05:47,581 INFO L276 IsEmpty]: Start isEmpty. Operand 2215 states and 2222 transitions. [2018-12-09 19:05:47,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2021 [2018-12-09 19:05:47,595 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:05:47,595 INFO L402 BasicCegarLoop]: trace histogram [350, 349, 349, 349, 349, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:05:47,595 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:05:47,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:05:47,596 INFO L82 PathProgramCache]: Analyzing trace with hash 1794680711, now seen corresponding path program 66 times [2018-12-09 19:05:47,596 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:05:47,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:47,596 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:05:47,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:47,596 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:05:47,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:49,040 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41893 proven. 1729 refuted. 0 times theorem prover too weak. 272214 trivial. 0 not checked. [2018-12-09 19:05:49,040 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:49,040 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:05:49,041 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:05:49,041 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:05:49,041 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:49,041 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:05:49,047 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:05:49,047 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:05:49,725 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:05:49,725 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:05:49,748 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:51,110 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41772 proven. 1550 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2018-12-09 19:05:51,110 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:05:52,706 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41772 proven. 1550 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2018-12-09 19:05:52,728 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:05:52,728 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 27, 27] total 83 [2018-12-09 19:05:52,728 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:05:52,729 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-12-09 19:05:52,729 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-12-09 19:05:52,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=986, Invalid=5986, Unknown=0, NotChecked=0, Total=6972 [2018-12-09 19:05:52,729 INFO L87 Difference]: Start difference. First operand 2215 states and 2222 transitions. Second operand 58 states. [2018-12-09 19:05:54,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:05:54,717 INFO L93 Difference]: Finished difference Result 2524 states and 2537 transitions. [2018-12-09 19:05:54,717 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-12-09 19:05:54,717 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 2020 [2018-12-09 19:05:54,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:05:54,720 INFO L225 Difference]: With dead ends: 2524 [2018-12-09 19:05:54,720 INFO L226 Difference]: Without dead ends: 2524 [2018-12-09 19:05:54,721 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4100 GetRequests, 3988 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3087 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1780, Invalid=11102, Unknown=0, NotChecked=0, Total=12882 [2018-12-09 19:05:54,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2524 states. [2018-12-09 19:05:54,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2524 to 2495. [2018-12-09 19:05:54,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2495 states. [2018-12-09 19:05:54,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2495 states to 2495 states and 2507 transitions. [2018-12-09 19:05:54,731 INFO L78 Accepts]: Start accepts. Automaton has 2495 states and 2507 transitions. Word has length 2020 [2018-12-09 19:05:54,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:05:54,732 INFO L480 AbstractCegarLoop]: Abstraction has 2495 states and 2507 transitions. [2018-12-09 19:05:54,732 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-12-09 19:05:54,732 INFO L276 IsEmpty]: Start isEmpty. Operand 2495 states and 2507 transitions. [2018-12-09 19:05:54,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2157 [2018-12-09 19:05:54,749 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:05:54,749 INFO L402 BasicCegarLoop]: trace histogram [375, 374, 374, 374, 374, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:05:54,749 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:05:54,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:05:54,750 INFO L82 PathProgramCache]: Analyzing trace with hash 1596582736, now seen corresponding path program 67 times [2018-12-09 19:05:54,750 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:05:54,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:54,750 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:05:54,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:05:54,750 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:05:54,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:56,987 INFO L134 CoverageAnalysis]: Checked inductivity of 362253 backedges. 82194 proven. 7685 refuted. 0 times theorem prover too weak. 272374 trivial. 0 not checked. [2018-12-09 19:05:56,987 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:56,987 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:05:56,987 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:05:56,987 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:05:56,987 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:05:56,987 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:05:56,993 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:05:56,993 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:05:57,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:05:57,312 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:05:59,691 INFO L134 CoverageAnalysis]: Checked inductivity of 362253 backedges. 123393 proven. 1404 refuted. 0 times theorem prover too weak. 237456 trivial. 0 not checked. [2018-12-09 19:05:59,691 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:06:02,507 INFO L134 CoverageAnalysis]: Checked inductivity of 362253 backedges. 85303 proven. 4457 refuted. 0 times theorem prover too weak. 272493 trivial. 0 not checked. [2018-12-09 19:06:02,524 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:06:02,524 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 52, 52] total 134 [2018-12-09 19:06:02,524 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:06:02,525 INFO L459 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-12-09 19:06:02,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-12-09 19:06:02,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2820, Invalid=15002, Unknown=0, NotChecked=0, Total=17822 [2018-12-09 19:06:02,526 INFO L87 Difference]: Start difference. First operand 2495 states and 2507 transitions. Second operand 109 states. [2018-12-09 19:06:07,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:06:07,024 INFO L93 Difference]: Finished difference Result 2235 states and 2240 transitions. [2018-12-09 19:06:07,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-12-09 19:06:07,025 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2156 [2018-12-09 19:06:07,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:06:07,027 INFO L225 Difference]: With dead ends: 2235 [2018-12-09 19:06:07,027 INFO L226 Difference]: Without dead ends: 2226 [2018-12-09 19:06:07,029 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4471 GetRequests, 4213 SyntacticMatches, 26 SemanticMatches, 232 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21860 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=8545, Invalid=45977, Unknown=0, NotChecked=0, Total=54522 [2018-12-09 19:06:07,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2226 states. [2018-12-09 19:06:07,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2226 to 2219. [2018-12-09 19:06:07,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2219 states. [2018-12-09 19:06:07,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2219 states to 2219 states and 2224 transitions. [2018-12-09 19:06:07,038 INFO L78 Accepts]: Start accepts. Automaton has 2219 states and 2224 transitions. Word has length 2156 [2018-12-09 19:06:07,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:06:07,038 INFO L480 AbstractCegarLoop]: Abstraction has 2219 states and 2224 transitions. [2018-12-09 19:06:07,038 INFO L481 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-12-09 19:06:07,038 INFO L276 IsEmpty]: Start isEmpty. Operand 2219 states and 2224 transitions. [2018-12-09 19:06:07,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2162 [2018-12-09 19:06:07,054 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:06:07,054 INFO L402 BasicCegarLoop]: trace histogram [376, 375, 375, 375, 375, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:06:07,055 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:06:07,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:06:07,055 INFO L82 PathProgramCache]: Analyzing trace with hash 567594603, now seen corresponding path program 68 times [2018-12-09 19:06:07,055 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:06:07,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:07,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:06:07,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:07,056 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:06:07,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:06:09,291 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 86758 proven. 4878 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2018-12-09 19:06:09,291 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:09,291 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:06:09,291 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:06:09,291 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:06:09,291 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:09,291 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:06:09,298 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:06:09,298 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:06:10,926 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-12-09 19:06:10,927 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:06:10,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:06:12,594 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 46743 proven. 1677 refuted. 0 times theorem prover too weak. 315730 trivial. 0 not checked. [2018-12-09 19:06:12,594 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:06:14,385 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 46743 proven. 1677 refuted. 0 times theorem prover too weak. 315730 trivial. 0 not checked. [2018-12-09 19:06:14,402 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:06:14,402 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 29, 29] total 95 [2018-12-09 19:06:14,403 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:06:14,403 INFO L459 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-12-09 19:06:14,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-12-09 19:06:14,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1380, Invalid=7550, Unknown=0, NotChecked=0, Total=8930 [2018-12-09 19:06:14,404 INFO L87 Difference]: Start difference. First operand 2219 states and 2224 transitions. Second operand 88 states. [2018-12-09 19:06:19,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:06:19,322 INFO L93 Difference]: Finished difference Result 2384 states and 2392 transitions. [2018-12-09 19:06:19,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-12-09 19:06:19,322 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2161 [2018-12-09 19:06:19,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:06:19,325 INFO L225 Difference]: With dead ends: 2384 [2018-12-09 19:06:19,325 INFO L226 Difference]: Without dead ends: 2384 [2018-12-09 19:06:19,327 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4461 GetRequests, 4267 SyntacticMatches, 21 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8689 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=7161, Invalid=23289, Unknown=0, NotChecked=0, Total=30450 [2018-12-09 19:06:19,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2384 states. [2018-12-09 19:06:19,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2384 to 2371. [2018-12-09 19:06:19,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2371 states. [2018-12-09 19:06:19,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2371 states to 2371 states and 2379 transitions. [2018-12-09 19:06:19,339 INFO L78 Accepts]: Start accepts. Automaton has 2371 states and 2379 transitions. Word has length 2161 [2018-12-09 19:06:19,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:06:19,339 INFO L480 AbstractCegarLoop]: Abstraction has 2371 states and 2379 transitions. [2018-12-09 19:06:19,339 INFO L481 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-12-09 19:06:19,339 INFO L276 IsEmpty]: Start isEmpty. Operand 2371 states and 2379 transitions. [2018-12-09 19:06:19,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2172 [2018-12-09 19:06:19,356 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:06:19,357 INFO L402 BasicCegarLoop]: trace histogram [378, 377, 377, 377, 377, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:06:19,357 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:06:19,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:06:19,357 INFO L82 PathProgramCache]: Analyzing trace with hash 1011103077, now seen corresponding path program 69 times [2018-12-09 19:06:19,357 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:06:19,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:19,358 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:06:19,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:19,358 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:06:19,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:06:21,444 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50431 proven. 1903 refuted. 0 times theorem prover too weak. 315625 trivial. 0 not checked. [2018-12-09 19:06:21,444 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:21,444 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:06:21,444 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:06:21,445 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:06:21,445 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:21,445 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:06:21,451 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:06:21,451 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:06:21,723 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:06:21,723 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:06:21,741 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:06:23,912 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50234 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2018-12-09 19:06:23,912 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:06:25,858 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50234 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2018-12-09 19:06:25,875 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:06:25,876 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 61, 61] total 94 [2018-12-09 19:06:25,876 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:06:25,876 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-12-09 19:06:25,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-12-09 19:06:25,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1742, Invalid=7000, Unknown=0, NotChecked=0, Total=8742 [2018-12-09 19:06:25,877 INFO L87 Difference]: Start difference. First operand 2371 states and 2379 transitions. Second operand 91 states. [2018-12-09 19:06:28,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:06:28,684 INFO L93 Difference]: Finished difference Result 2675 states and 2687 transitions. [2018-12-09 19:06:28,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-12-09 19:06:28,684 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2171 [2018-12-09 19:06:28,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:06:28,688 INFO L225 Difference]: With dead ends: 2675 [2018-12-09 19:06:28,688 INFO L226 Difference]: Without dead ends: 2675 [2018-12-09 19:06:28,689 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4454 GetRequests, 4250 SyntacticMatches, 57 SemanticMatches, 147 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7221 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=4838, Invalid=17214, Unknown=0, NotChecked=0, Total=22052 [2018-12-09 19:06:28,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2675 states. [2018-12-09 19:06:28,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2675 to 2661. [2018-12-09 19:06:28,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2661 states. [2018-12-09 19:06:28,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2661 states to 2661 states and 2673 transitions. [2018-12-09 19:06:28,701 INFO L78 Accepts]: Start accepts. Automaton has 2661 states and 2673 transitions. Word has length 2171 [2018-12-09 19:06:28,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:06:28,702 INFO L480 AbstractCegarLoop]: Abstraction has 2661 states and 2673 transitions. [2018-12-09 19:06:28,702 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-12-09 19:06:28,702 INFO L276 IsEmpty]: Start isEmpty. Operand 2661 states and 2673 transitions. [2018-12-09 19:06:28,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2308 [2018-12-09 19:06:28,722 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:06:28,722 INFO L402 BasicCegarLoop]: trace histogram [403, 402, 402, 402, 402, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:06:28,722 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:06:28,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:06:28,723 INFO L82 PathProgramCache]: Analyzing trace with hash -706640056, now seen corresponding path program 70 times [2018-12-09 19:06:28,723 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:06:28,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:28,724 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:06:28,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:28,724 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:06:28,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:06:31,192 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 92269 proven. 8317 refuted. 0 times theorem prover too weak. 317354 trivial. 0 not checked. [2018-12-09 19:06:31,193 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:31,193 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:06:31,193 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:06:31,193 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:06:31,193 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:31,193 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:06:31,199 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:06:31,199 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:06:31,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:06:31,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:06:34,181 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 138548 proven. 1525 refuted. 0 times theorem prover too weak. 277867 trivial. 0 not checked. [2018-12-09 19:06:34,182 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:06:37,302 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 95645 proven. 4830 refuted. 0 times theorem prover too weak. 317465 trivial. 0 not checked. [2018-12-09 19:06:37,319 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:06:37,320 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 54, 54] total 139 [2018-12-09 19:06:37,320 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:06:37,320 INFO L459 AbstractCegarLoop]: Interpolant automaton has 113 states [2018-12-09 19:06:37,321 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2018-12-09 19:06:37,321 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3036, Invalid=16146, Unknown=0, NotChecked=0, Total=19182 [2018-12-09 19:06:37,321 INFO L87 Difference]: Start difference. First operand 2661 states and 2673 transitions. Second operand 113 states. [2018-12-09 19:06:41,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:06:41,276 INFO L93 Difference]: Finished difference Result 2386 states and 2391 transitions. [2018-12-09 19:06:41,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 136 states. [2018-12-09 19:06:41,276 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 2307 [2018-12-09 19:06:41,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:06:41,279 INFO L225 Difference]: With dead ends: 2386 [2018-12-09 19:06:41,279 INFO L226 Difference]: Without dead ends: 2377 [2018-12-09 19:06:41,281 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4779 GetRequests, 4511 SyntacticMatches, 27 SemanticMatches, 241 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23645 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=9210, Invalid=49596, Unknown=0, NotChecked=0, Total=58806 [2018-12-09 19:06:41,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2018-12-09 19:06:41,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 2370. [2018-12-09 19:06:41,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2370 states. [2018-12-09 19:06:41,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2370 states to 2370 states and 2375 transitions. [2018-12-09 19:06:41,290 INFO L78 Accepts]: Start accepts. Automaton has 2370 states and 2375 transitions. Word has length 2307 [2018-12-09 19:06:41,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:06:41,291 INFO L480 AbstractCegarLoop]: Abstraction has 2370 states and 2375 transitions. [2018-12-09 19:06:41,291 INFO L481 AbstractCegarLoop]: Interpolant automaton has 113 states. [2018-12-09 19:06:41,291 INFO L276 IsEmpty]: Start isEmpty. Operand 2370 states and 2375 transitions. [2018-12-09 19:06:41,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2313 [2018-12-09 19:06:41,309 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:06:41,309 INFO L402 BasicCegarLoop]: trace histogram [404, 403, 403, 403, 403, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:06:41,309 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:06:41,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:06:41,310 INFO L82 PathProgramCache]: Analyzing trace with hash 1323482343, now seen corresponding path program 71 times [2018-12-09 19:06:41,310 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:06:41,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:41,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:06:41,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:41,310 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:06:41,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:06:43,791 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 97210 proven. 5268 refuted. 0 times theorem prover too weak. 317500 trivial. 0 not checked. [2018-12-09 19:06:43,791 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:43,791 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:06:43,791 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:06:43,791 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:06:43,791 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:43,791 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:06:43,797 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:06:43,797 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:06:45,562 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-12-09 19:06:45,562 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:06:45,576 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:06:47,570 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 95533 proven. 5268 refuted. 0 times theorem prover too weak. 319177 trivial. 0 not checked. [2018-12-09 19:06:47,570 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:06:50,248 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 95428 proven. 5373 refuted. 0 times theorem prover too weak. 319177 trivial. 0 not checked. [2018-12-09 19:06:50,265 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:06:50,266 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 36, 36] total 127 [2018-12-09 19:06:50,266 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:06:50,266 INFO L459 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-12-09 19:06:50,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-12-09 19:06:50,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3196, Invalid=12806, Unknown=0, NotChecked=0, Total=16002 [2018-12-09 19:06:50,267 INFO L87 Difference]: Start difference. First operand 2370 states and 2375 transitions. Second operand 92 states. [2018-12-09 19:06:53,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:06:53,003 INFO L93 Difference]: Finished difference Result 2532 states and 2539 transitions. [2018-12-09 19:06:53,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-12-09 19:06:53,003 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2312 [2018-12-09 19:06:53,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:06:53,006 INFO L225 Difference]: With dead ends: 2532 [2018-12-09 19:06:53,006 INFO L226 Difference]: Without dead ends: 2532 [2018-12-09 19:06:53,008 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4767 GetRequests, 4559 SyntacticMatches, 1 SemanticMatches, 207 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13519 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=11146, Invalid=32326, Unknown=0, NotChecked=0, Total=43472 [2018-12-09 19:06:53,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2532 states. [2018-12-09 19:06:53,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2532 to 2522. [2018-12-09 19:06:53,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2522 states. [2018-12-09 19:06:53,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2522 states to 2522 states and 2529 transitions. [2018-12-09 19:06:53,019 INFO L78 Accepts]: Start accepts. Automaton has 2522 states and 2529 transitions. Word has length 2312 [2018-12-09 19:06:53,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:06:53,020 INFO L480 AbstractCegarLoop]: Abstraction has 2522 states and 2529 transitions. [2018-12-09 19:06:53,020 INFO L481 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-12-09 19:06:53,020 INFO L276 IsEmpty]: Start isEmpty. Operand 2522 states and 2529 transitions. [2018-12-09 19:06:53,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2318 [2018-12-09 19:06:53,039 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:06:53,039 INFO L402 BasicCegarLoop]: trace histogram [405, 404, 404, 404, 404, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:06:53,039 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:06:53,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:06:53,040 INFO L82 PathProgramCache]: Analyzing trace with hash 1696940994, now seen corresponding path program 72 times [2018-12-09 19:06:53,040 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:06:53,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:53,040 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:06:53,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:06:53,040 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:06:53,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:06:54,860 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52508 proven. 2029 refuted. 0 times theorem prover too weak. 367484 trivial. 0 not checked. [2018-12-09 19:06:54,860 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:54,860 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:06:54,861 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:06:54,861 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:06:54,861 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:06:54,861 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:06:54,867 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:06:54,867 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:06:55,720 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:06:55,720 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:06:55,746 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:06:57,409 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52377 proven. 1809 refuted. 0 times theorem prover too weak. 367835 trivial. 0 not checked. [2018-12-09 19:06:57,409 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:06:59,401 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52377 proven. 1809 refuted. 0 times theorem prover too weak. 367835 trivial. 0 not checked. [2018-12-09 19:06:59,424 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:06:59,424 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 29, 29] total 89 [2018-12-09 19:06:59,424 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:06:59,425 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-09 19:06:59,425 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-09 19:06:59,425 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1071, Invalid=6939, Unknown=0, NotChecked=0, Total=8010 [2018-12-09 19:06:59,425 INFO L87 Difference]: Start difference. First operand 2522 states and 2529 transitions. Second operand 62 states. [2018-12-09 19:07:01,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:07:01,718 INFO L93 Difference]: Finished difference Result 2851 states and 2864 transitions. [2018-12-09 19:07:01,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-12-09 19:07:01,718 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2317 [2018-12-09 19:07:01,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:07:01,722 INFO L225 Difference]: With dead ends: 2851 [2018-12-09 19:07:01,722 INFO L226 Difference]: Without dead ends: 2851 [2018-12-09 19:07:01,722 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4698 GetRequests, 4578 SyntacticMatches, 0 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3508 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1901, Invalid=12861, Unknown=0, NotChecked=0, Total=14762 [2018-12-09 19:07:01,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2851 states. [2018-12-09 19:07:01,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2851 to 2822. [2018-12-09 19:07:01,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2822 states. [2018-12-09 19:07:01,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2822 states to 2822 states and 2834 transitions. [2018-12-09 19:07:01,735 INFO L78 Accepts]: Start accepts. Automaton has 2822 states and 2834 transitions. Word has length 2317 [2018-12-09 19:07:01,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:07:01,736 INFO L480 AbstractCegarLoop]: Abstraction has 2822 states and 2834 transitions. [2018-12-09 19:07:01,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-09 19:07:01,736 INFO L276 IsEmpty]: Start isEmpty. Operand 2822 states and 2834 transitions. [2018-12-09 19:07:01,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2464 [2018-12-09 19:07:01,756 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:07:01,757 INFO L402 BasicCegarLoop]: trace histogram [432, 431, 431, 431, 431, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:07:01,757 INFO L423 AbstractCegarLoop]: === Iteration 88 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:07:01,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:07:01,757 INFO L82 PathProgramCache]: Analyzing trace with hash -1831952213, now seen corresponding path program 73 times [2018-12-09 19:07:01,757 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:07:01,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:01,758 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:07:01,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:01,758 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:07:01,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:07:04,517 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 103136 proven. 8974 refuted. 0 times theorem prover too weak. 367683 trivial. 0 not checked. [2018-12-09 19:07:04,517 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:04,517 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:07:04,517 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:07:04,517 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:07:04,517 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:04,517 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:07:04,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:07:04,524 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:07:04,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:07:04,888 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:07:07,824 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 154894 proven. 1651 refuted. 0 times theorem prover too weak. 323248 trivial. 0 not checked. [2018-12-09 19:07:07,825 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:07:11,218 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 106790 proven. 5218 refuted. 0 times theorem prover too weak. 367785 trivial. 0 not checked. [2018-12-09 19:07:11,235 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:07:11,235 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 56, 56] total 144 [2018-12-09 19:07:11,235 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:07:11,236 INFO L459 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-12-09 19:07:11,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-12-09 19:07:11,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3260, Invalid=17332, Unknown=0, NotChecked=0, Total=20592 [2018-12-09 19:07:11,237 INFO L87 Difference]: Start difference. First operand 2822 states and 2834 transitions. Second operand 117 states. [2018-12-09 19:07:19,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:07:19,098 INFO L93 Difference]: Finished difference Result 2542 states and 2547 transitions. [2018-12-09 19:07:19,098 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 141 states. [2018-12-09 19:07:19,098 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2463 [2018-12-09 19:07:19,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:07:19,101 INFO L225 Difference]: With dead ends: 2542 [2018-12-09 19:07:19,101 INFO L226 Difference]: Without dead ends: 2533 [2018-12-09 19:07:19,103 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5097 GetRequests, 4819 SyntacticMatches, 28 SemanticMatches, 250 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25500 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=9900, Invalid=53352, Unknown=0, NotChecked=0, Total=63252 [2018-12-09 19:07:19,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2533 states. [2018-12-09 19:07:19,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2533 to 2526. [2018-12-09 19:07:19,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2526 states. [2018-12-09 19:07:19,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2526 states to 2526 states and 2531 transitions. [2018-12-09 19:07:19,113 INFO L78 Accepts]: Start accepts. Automaton has 2526 states and 2531 transitions. Word has length 2463 [2018-12-09 19:07:19,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:07:19,114 INFO L480 AbstractCegarLoop]: Abstraction has 2526 states and 2531 transitions. [2018-12-09 19:07:19,114 INFO L481 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-12-09 19:07:19,114 INFO L276 IsEmpty]: Start isEmpty. Operand 2526 states and 2531 transitions. [2018-12-09 19:07:19,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2469 [2018-12-09 19:07:19,134 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:07:19,134 INFO L402 BasicCegarLoop]: trace histogram [433, 432, 432, 432, 432, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:07:19,134 INFO L423 AbstractCegarLoop]: === Iteration 89 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:07:19,134 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:07:19,134 INFO L82 PathProgramCache]: Analyzing trace with hash 154747760, now seen corresponding path program 74 times [2018-12-09 19:07:19,135 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:07:19,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:19,135 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:07:19,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:19,135 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:07:19,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:07:21,918 INFO L134 CoverageAnalysis]: Checked inductivity of 481977 backedges. 108469 proven. 5673 refuted. 0 times theorem prover too weak. 367835 trivial. 0 not checked. [2018-12-09 19:07:21,918 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:21,918 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:07:21,918 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:07:21,918 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:07:21,918 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:21,918 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:07:21,927 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:07:21,927 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:07:23,928 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-12-09 19:07:23,929 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:07:23,943 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:07:26,188 INFO L134 CoverageAnalysis]: Checked inductivity of 481977 backedges. 106660 proven. 5673 refuted. 0 times theorem prover too weak. 369644 trivial. 0 not checked. [2018-12-09 19:07:26,188 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:07:29,134 INFO L134 CoverageAnalysis]: Checked inductivity of 481977 backedges. 106551 proven. 5782 refuted. 0 times theorem prover too weak. 369644 trivial. 0 not checked. [2018-12-09 19:07:29,152 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:07:29,153 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 37, 37] total 131 [2018-12-09 19:07:29,153 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:07:29,153 INFO L459 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-12-09 19:07:29,154 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-12-09 19:07:29,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3365, Invalid=13665, Unknown=0, NotChecked=0, Total=17030 [2018-12-09 19:07:29,155 INFO L87 Difference]: Start difference. First operand 2526 states and 2531 transitions. Second operand 95 states. [2018-12-09 19:07:31,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:07:31,583 INFO L93 Difference]: Finished difference Result 2693 states and 2700 transitions. [2018-12-09 19:07:31,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-12-09 19:07:31,584 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 2468 [2018-12-09 19:07:31,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:07:31,588 INFO L225 Difference]: With dead ends: 2693 [2018-12-09 19:07:31,588 INFO L226 Difference]: Without dead ends: 2693 [2018-12-09 19:07:31,590 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5084 GetRequests, 4869 SyntacticMatches, 1 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14527 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=11852, Invalid=34588, Unknown=0, NotChecked=0, Total=46440 [2018-12-09 19:07:31,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2693 states. [2018-12-09 19:07:31,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2693 to 2683. [2018-12-09 19:07:31,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2683 states. [2018-12-09 19:07:31,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2683 states to 2683 states and 2690 transitions. [2018-12-09 19:07:31,601 INFO L78 Accepts]: Start accepts. Automaton has 2683 states and 2690 transitions. Word has length 2468 [2018-12-09 19:07:31,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:07:31,603 INFO L480 AbstractCegarLoop]: Abstraction has 2683 states and 2690 transitions. [2018-12-09 19:07:31,603 INFO L481 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-12-09 19:07:31,603 INFO L276 IsEmpty]: Start isEmpty. Operand 2683 states and 2690 transitions. [2018-12-09 19:07:31,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2474 [2018-12-09 19:07:31,625 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:07:31,625 INFO L402 BasicCegarLoop]: trace histogram [434, 433, 433, 433, 433, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:07:31,625 INFO L423 AbstractCegarLoop]: === Iteration 90 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:07:31,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:07:31,626 INFO L82 PathProgramCache]: Analyzing trace with hash -169898907, now seen corresponding path program 75 times [2018-12-09 19:07:31,626 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:07:31,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:31,627 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:07:31,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:31,627 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:07:31,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:07:33,764 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58810 proven. 2188 refuted. 0 times theorem prover too weak. 423168 trivial. 0 not checked. [2018-12-09 19:07:33,764 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:33,764 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:07:33,765 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:07:33,765 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:07:33,765 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:33,765 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:07:33,771 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:07:33,771 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:07:36,481 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:07:36,481 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:07:36,510 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:07:38,389 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58293 proven. 1946 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2018-12-09 19:07:38,389 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:07:40,679 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58293 proven. 1946 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2018-12-09 19:07:40,703 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:07:40,704 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 30, 30] total 95 [2018-12-09 19:07:40,704 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:07:40,704 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-12-09 19:07:40,704 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-12-09 19:07:40,705 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1127, Invalid=7993, Unknown=0, NotChecked=0, Total=9120 [2018-12-09 19:07:40,705 INFO L87 Difference]: Start difference. First operand 2683 states and 2690 transitions. Second operand 67 states. [2018-12-09 19:07:43,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:07:43,476 INFO L93 Difference]: Finished difference Result 3022 states and 3035 transitions. [2018-12-09 19:07:43,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-12-09 19:07:43,477 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 2473 [2018-12-09 19:07:43,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:07:43,480 INFO L225 Difference]: With dead ends: 3022 [2018-12-09 19:07:43,480 INFO L226 Difference]: Without dead ends: 3022 [2018-12-09 19:07:43,480 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5015 GetRequests, 4888 SyntacticMatches, 0 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3960 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=2053, Invalid=14459, Unknown=0, NotChecked=0, Total=16512 [2018-12-09 19:07:43,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3022 states. [2018-12-09 19:07:43,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3022 to 2993. [2018-12-09 19:07:43,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2993 states. [2018-12-09 19:07:43,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2993 states to 2993 states and 3005 transitions. [2018-12-09 19:07:43,493 INFO L78 Accepts]: Start accepts. Automaton has 2993 states and 3005 transitions. Word has length 2473 [2018-12-09 19:07:43,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:07:43,493 INFO L480 AbstractCegarLoop]: Abstraction has 2993 states and 3005 transitions. [2018-12-09 19:07:43,493 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-12-09 19:07:43,493 INFO L276 IsEmpty]: Start isEmpty. Operand 2993 states and 3005 transitions. [2018-12-09 19:07:43,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2625 [2018-12-09 19:07:43,516 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:07:43,516 INFO L402 BasicCegarLoop]: trace histogram [462, 461, 461, 461, 461, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:07:43,516 INFO L423 AbstractCegarLoop]: === Iteration 91 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:07:43,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:07:43,517 INFO L82 PathProgramCache]: Analyzing trace with hash -603003347, now seen corresponding path program 76 times [2018-12-09 19:07:43,517 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:07:43,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:43,517 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:07:43,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:07:43,517 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:07:43,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:07:46,553 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 114825 proven. 9656 refuted. 0 times theorem prover too weak. 423769 trivial. 0 not checked. [2018-12-09 19:07:46,553 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:46,553 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:07:46,553 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:07:46,553 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:07:46,553 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:07:46,553 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:07:46,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:07:46,561 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:07:46,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:07:46,972 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:07:50,197 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 172476 proven. 1782 refuted. 0 times theorem prover too weak. 373992 trivial. 0 not checked. [2018-12-09 19:07:50,197 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:07:53,884 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 118768 proven. 5621 refuted. 0 times theorem prover too weak. 423861 trivial. 0 not checked. [2018-12-09 19:07:53,901 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:07:53,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 58, 58] total 149 [2018-12-09 19:07:53,902 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:07:53,902 INFO L459 AbstractCegarLoop]: Interpolant automaton has 121 states [2018-12-09 19:07:53,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 121 interpolants. [2018-12-09 19:07:53,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3492, Invalid=18560, Unknown=0, NotChecked=0, Total=22052 [2018-12-09 19:07:53,903 INFO L87 Difference]: Start difference. First operand 2993 states and 3005 transitions. Second operand 121 states. [2018-12-09 19:08:01,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:08:01,331 INFO L93 Difference]: Finished difference Result 2703 states and 2708 transitions. [2018-12-09 19:08:01,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2018-12-09 19:08:01,332 INFO L78 Accepts]: Start accepts. Automaton has 121 states. Word has length 2624 [2018-12-09 19:08:01,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:08:01,334 INFO L225 Difference]: With dead ends: 2703 [2018-12-09 19:08:01,334 INFO L226 Difference]: Without dead ends: 2694 [2018-12-09 19:08:01,336 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5425 GetRequests, 5137 SyntacticMatches, 29 SemanticMatches, 259 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27425 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=10615, Invalid=57245, Unknown=0, NotChecked=0, Total=67860 [2018-12-09 19:08:01,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2694 states. [2018-12-09 19:08:01,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2694 to 2687. [2018-12-09 19:08:01,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2687 states. [2018-12-09 19:08:01,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2687 states to 2687 states and 2692 transitions. [2018-12-09 19:08:01,347 INFO L78 Accepts]: Start accepts. Automaton has 2687 states and 2692 transitions. Word has length 2624 [2018-12-09 19:08:01,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:08:01,347 INFO L480 AbstractCegarLoop]: Abstraction has 2687 states and 2692 transitions. [2018-12-09 19:08:01,347 INFO L481 AbstractCegarLoop]: Interpolant automaton has 121 states. [2018-12-09 19:08:01,347 INFO L276 IsEmpty]: Start isEmpty. Operand 2687 states and 2692 transitions. [2018-12-09 19:08:01,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2630 [2018-12-09 19:08:01,370 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:08:01,370 INFO L402 BasicCegarLoop]: trace histogram [463, 462, 462, 462, 462, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:08:01,370 INFO L423 AbstractCegarLoop]: === Iteration 92 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:08:01,370 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:08:01,371 INFO L82 PathProgramCache]: Analyzing trace with hash 1430424994, now seen corresponding path program 77 times [2018-12-09 19:08:01,371 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:08:01,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:01,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:08:01,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:01,371 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:08:01,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:08:04,431 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 120565 proven. 6093 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2018-12-09 19:08:04,431 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:04,431 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:08:04,432 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:08:04,432 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:08:04,432 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:04,432 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:08:04,437 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:08:04,437 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:08:06,352 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-12-09 19:08:06,353 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:08:06,369 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:08:08,838 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 118619 proven. 6093 refuted. 0 times theorem prover too weak. 425873 trivial. 0 not checked. [2018-12-09 19:08:08,839 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:08:12,139 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 118506 proven. 6206 refuted. 0 times theorem prover too weak. 425873 trivial. 0 not checked. [2018-12-09 19:08:12,157 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:08:12,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 38, 38] total 135 [2018-12-09 19:08:12,158 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:08:12,159 INFO L459 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-12-09 19:08:12,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-12-09 19:08:12,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3535, Invalid=14555, Unknown=0, NotChecked=0, Total=18090 [2018-12-09 19:08:12,159 INFO L87 Difference]: Start difference. First operand 2687 states and 2692 transitions. Second operand 98 states. [2018-12-09 19:08:14,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:08:14,791 INFO L93 Difference]: Finished difference Result 2859 states and 2866 transitions. [2018-12-09 19:08:14,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-12-09 19:08:14,791 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 2629 [2018-12-09 19:08:14,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:08:14,794 INFO L225 Difference]: With dead ends: 2859 [2018-12-09 19:08:14,794 INFO L226 Difference]: Without dead ends: 2859 [2018-12-09 19:08:14,796 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5411 GetRequests, 5189 SyntacticMatches, 1 SemanticMatches, 221 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15573 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=12575, Invalid=36931, Unknown=0, NotChecked=0, Total=49506 [2018-12-09 19:08:14,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2859 states. [2018-12-09 19:08:14,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2859 to 2849. [2018-12-09 19:08:14,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2849 states. [2018-12-09 19:08:14,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2849 states to 2849 states and 2856 transitions. [2018-12-09 19:08:14,815 INFO L78 Accepts]: Start accepts. Automaton has 2849 states and 2856 transitions. Word has length 2629 [2018-12-09 19:08:14,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:08:14,816 INFO L480 AbstractCegarLoop]: Abstraction has 2849 states and 2856 transitions. [2018-12-09 19:08:14,816 INFO L481 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-12-09 19:08:14,816 INFO L276 IsEmpty]: Start isEmpty. Operand 2849 states and 2856 transitions. [2018-12-09 19:08:14,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2635 [2018-12-09 19:08:14,850 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:08:14,850 INFO L402 BasicCegarLoop]: trace histogram [464, 463, 463, 463, 463, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:08:14,850 INFO L423 AbstractCegarLoop]: === Iteration 93 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:08:14,850 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:08:14,850 INFO L82 PathProgramCache]: Analyzing trace with hash 2134165351, now seen corresponding path program 78 times [2018-12-09 19:08:14,850 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:08:14,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:14,851 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:08:14,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:14,851 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:08:15,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:08:17,141 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64779 proven. 2353 refuted. 0 times theorem prover too weak. 485793 trivial. 0 not checked. [2018-12-09 19:08:17,141 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:17,141 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:08:17,141 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:08:17,141 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:08:17,141 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:17,141 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:08:17,150 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:08:17,151 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:08:18,244 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:08:18,244 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:08:18,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:08:20,332 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64638 proven. 2088 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-09 19:08:20,332 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:08:22,797 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64638 proven. 2088 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-09 19:08:22,822 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:08:22,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 31, 31] total 95 [2018-12-09 19:08:22,823 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:08:22,823 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-12-09 19:08:22,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-12-09 19:08:22,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1152, Invalid=7968, Unknown=0, NotChecked=0, Total=9120 [2018-12-09 19:08:22,824 INFO L87 Difference]: Start difference. First operand 2849 states and 2856 transitions. Second operand 66 states. [2018-12-09 19:08:25,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:08:25,914 INFO L93 Difference]: Finished difference Result 3198 states and 3211 transitions. [2018-12-09 19:08:25,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-12-09 19:08:25,914 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 2634 [2018-12-09 19:08:25,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:08:25,919 INFO L225 Difference]: With dead ends: 3198 [2018-12-09 19:08:25,919 INFO L226 Difference]: Without dead ends: 3198 [2018-12-09 19:08:25,920 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5336 GetRequests, 5208 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3949 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=2010, Invalid=14760, Unknown=0, NotChecked=0, Total=16770 [2018-12-09 19:08:25,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3198 states. [2018-12-09 19:08:25,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3198 to 3169. [2018-12-09 19:08:25,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3169 states. [2018-12-09 19:08:25,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3169 states to 3169 states and 3181 transitions. [2018-12-09 19:08:25,935 INFO L78 Accepts]: Start accepts. Automaton has 3169 states and 3181 transitions. Word has length 2634 [2018-12-09 19:08:25,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:08:25,936 INFO L480 AbstractCegarLoop]: Abstraction has 3169 states and 3181 transitions. [2018-12-09 19:08:25,937 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-12-09 19:08:25,937 INFO L276 IsEmpty]: Start isEmpty. Operand 3169 states and 3181 transitions. [2018-12-09 19:08:25,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2791 [2018-12-09 19:08:25,964 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:08:25,965 INFO L402 BasicCegarLoop]: trace histogram [493, 492, 492, 492, 492, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:08:25,965 INFO L423 AbstractCegarLoop]: === Iteration 94 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:08:25,965 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:08:25,965 INFO L82 PathProgramCache]: Analyzing trace with hash -356784400, now seen corresponding path program 79 times [2018-12-09 19:08:25,966 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:08:25,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:25,966 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:08:25,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:25,966 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:08:26,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:08:29,333 INFO L134 CoverageAnalysis]: Checked inductivity of 623764 backedges. 127366 proven. 10363 refuted. 0 times theorem prover too weak. 486035 trivial. 0 not checked. [2018-12-09 19:08:29,334 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:29,334 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:08:29,334 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:08:29,334 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:08:29,334 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:29,334 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:08:29,339 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:08:29,340 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:08:29,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:08:29,777 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:08:33,296 INFO L134 CoverageAnalysis]: Checked inductivity of 623764 backedges. 191339 proven. 1918 refuted. 0 times theorem prover too weak. 430507 trivial. 0 not checked. [2018-12-09 19:08:33,296 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:08:37,345 INFO L134 CoverageAnalysis]: Checked inductivity of 623764 backedges. 131609 proven. 6039 refuted. 0 times theorem prover too weak. 486116 trivial. 0 not checked. [2018-12-09 19:08:37,363 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:08:37,363 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 60, 60] total 154 [2018-12-09 19:08:37,363 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:08:37,364 INFO L459 AbstractCegarLoop]: Interpolant automaton has 125 states [2018-12-09 19:08:37,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2018-12-09 19:08:37,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3732, Invalid=19830, Unknown=0, NotChecked=0, Total=23562 [2018-12-09 19:08:37,365 INFO L87 Difference]: Start difference. First operand 3169 states and 3181 transitions. Second operand 125 states. [2018-12-09 19:08:42,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:08:42,446 INFO L93 Difference]: Finished difference Result 2869 states and 2874 transitions. [2018-12-09 19:08:42,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-12-09 19:08:42,447 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 2790 [2018-12-09 19:08:42,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:08:42,450 INFO L225 Difference]: With dead ends: 2869 [2018-12-09 19:08:42,450 INFO L226 Difference]: Without dead ends: 2860 [2018-12-09 19:08:42,453 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5763 GetRequests, 5465 SyntacticMatches, 30 SemanticMatches, 268 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29420 ImplicationChecksByTransitivity, 6.2s TimeCoverageRelationStatistics Valid=11355, Invalid=61275, Unknown=0, NotChecked=0, Total=72630 [2018-12-09 19:08:42,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2860 states. [2018-12-09 19:08:42,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2860 to 2853. [2018-12-09 19:08:42,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2853 states. [2018-12-09 19:08:42,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2853 states to 2853 states and 2858 transitions. [2018-12-09 19:08:42,465 INFO L78 Accepts]: Start accepts. Automaton has 2853 states and 2858 transitions. Word has length 2790 [2018-12-09 19:08:42,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:08:42,466 INFO L480 AbstractCegarLoop]: Abstraction has 2853 states and 2858 transitions. [2018-12-09 19:08:42,466 INFO L481 AbstractCegarLoop]: Interpolant automaton has 125 states. [2018-12-09 19:08:42,466 INFO L276 IsEmpty]: Start isEmpty. Operand 2853 states and 2858 transitions. [2018-12-09 19:08:42,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2796 [2018-12-09 19:08:42,492 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:08:42,492 INFO L402 BasicCegarLoop]: trace histogram [494, 493, 493, 493, 493, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:08:42,492 INFO L423 AbstractCegarLoop]: === Iteration 95 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:08:42,492 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:08:42,493 INFO L82 PathProgramCache]: Analyzing trace with hash 945686987, now seen corresponding path program 80 times [2018-12-09 19:08:42,493 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:08:42,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:42,493 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:08:42,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:42,493 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:08:42,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:08:45,865 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 133528 proven. 6528 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-09 19:08:45,866 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:45,866 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:08:45,866 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:08:45,866 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:08:45,866 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:08:45,866 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:08:45,871 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:08:45,872 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:08:50,595 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-12-09 19:08:50,595 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:08:50,611 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:08:53,380 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 131440 proven. 6528 refuted. 0 times theorem prover too weak. 488287 trivial. 0 not checked. [2018-12-09 19:08:53,380 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:08:56,869 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 131323 proven. 6645 refuted. 0 times theorem prover too weak. 488287 trivial. 0 not checked. [2018-12-09 19:08:56,887 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:08:56,888 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 39, 39] total 139 [2018-12-09 19:08:56,888 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:08:56,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-12-09 19:08:56,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-12-09 19:08:56,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3706, Invalid=15476, Unknown=0, NotChecked=0, Total=19182 [2018-12-09 19:08:56,889 INFO L87 Difference]: Start difference. First operand 2853 states and 2858 transitions. Second operand 101 states. [2018-12-09 19:08:59,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:08:59,508 INFO L93 Difference]: Finished difference Result 3030 states and 3037 transitions. [2018-12-09 19:08:59,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-12-09 19:08:59,508 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2795 [2018-12-09 19:08:59,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:08:59,512 INFO L225 Difference]: With dead ends: 3030 [2018-12-09 19:08:59,512 INFO L226 Difference]: Without dead ends: 3030 [2018-12-09 19:08:59,515 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5748 GetRequests, 5519 SyntacticMatches, 1 SemanticMatches, 228 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16657 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=13315, Invalid=39355, Unknown=0, NotChecked=0, Total=52670 [2018-12-09 19:08:59,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3030 states. [2018-12-09 19:08:59,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3030 to 3020. [2018-12-09 19:08:59,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3020 states. [2018-12-09 19:08:59,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3020 states to 3020 states and 3027 transitions. [2018-12-09 19:08:59,530 INFO L78 Accepts]: Start accepts. Automaton has 3020 states and 3027 transitions. Word has length 2795 [2018-12-09 19:08:59,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:08:59,531 INFO L480 AbstractCegarLoop]: Abstraction has 3020 states and 3027 transitions. [2018-12-09 19:08:59,531 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-12-09 19:08:59,531 INFO L276 IsEmpty]: Start isEmpty. Operand 3020 states and 3027 transitions. [2018-12-09 19:08:59,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2801 [2018-12-09 19:08:59,557 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:08:59,558 INFO L402 BasicCegarLoop]: trace histogram [495, 494, 494, 494, 494, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:08:59,558 INFO L423 AbstractCegarLoop]: === Iteration 96 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:08:59,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:08:59,558 INFO L82 PathProgramCache]: Analyzing trace with hash 601825130, now seen corresponding path program 81 times [2018-12-09 19:08:59,558 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:08:59,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:59,558 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:08:59,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:08:59,559 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:08:59,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:09:02,162 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71715 proven. 2524 refuted. 0 times theorem prover too weak. 554512 trivial. 0 not checked. [2018-12-09 19:09:02,163 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:02,163 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:09:02,163 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:09:02,163 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:09:02,163 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:02,163 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:09:02,169 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:09:02,169 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:09:09,480 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:09:09,480 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:09:09,515 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:09:11,779 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71427 proven. 2235 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-09 19:09:11,779 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:09:14,539 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71427 proven. 2235 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-09 19:09:14,567 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:09:14,567 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 32, 32] total 99 [2018-12-09 19:09:14,567 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:09:14,568 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-09 19:09:14,568 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-09 19:09:14,568 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1195, Invalid=8705, Unknown=0, NotChecked=0, Total=9900 [2018-12-09 19:09:14,568 INFO L87 Difference]: Start difference. First operand 3020 states and 3027 transitions. Second operand 69 states. [2018-12-09 19:09:17,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:09:17,360 INFO L93 Difference]: Finished difference Result 3379 states and 3392 transitions. [2018-12-09 19:09:17,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-12-09 19:09:17,360 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 2800 [2018-12-09 19:09:17,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:09:17,363 INFO L225 Difference]: With dead ends: 3379 [2018-12-09 19:09:17,364 INFO L226 Difference]: Without dead ends: 3379 [2018-12-09 19:09:17,364 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5671 GetRequests, 5538 SyntacticMatches, 0 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4264 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=2094, Invalid=15996, Unknown=0, NotChecked=0, Total=18090 [2018-12-09 19:09:17,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3379 states. [2018-12-09 19:09:17,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3379 to 3350. [2018-12-09 19:09:17,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3350 states. [2018-12-09 19:09:17,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3350 states to 3350 states and 3362 transitions. [2018-12-09 19:09:17,378 INFO L78 Accepts]: Start accepts. Automaton has 3350 states and 3362 transitions. Word has length 2800 [2018-12-09 19:09:17,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:09:17,379 INFO L480 AbstractCegarLoop]: Abstraction has 3350 states and 3362 transitions. [2018-12-09 19:09:17,379 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-09 19:09:17,380 INFO L276 IsEmpty]: Start isEmpty. Operand 3350 states and 3362 transitions. [2018-12-09 19:09:17,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2962 [2018-12-09 19:09:17,409 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:09:17,409 INFO L402 BasicCegarLoop]: trace histogram [525, 524, 524, 524, 524, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:09:17,409 INFO L423 AbstractCegarLoop]: === Iteration 97 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:09:17,409 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:09:17,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1148647064, now seen corresponding path program 82 times [2018-12-09 19:09:17,409 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:09:17,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:09:17,410 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:09:17,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:09:17,410 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:09:17,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:09:21,104 INFO L134 CoverageAnalysis]: Checked inductivity of 706803 backedges. 140789 proven. 11095 refuted. 0 times theorem prover too weak. 554919 trivial. 0 not checked. [2018-12-09 19:09:21,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:21,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:09:21,105 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:09:21,105 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:09:21,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:21,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:09:21,111 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:09:21,111 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:09:21,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:09:21,549 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:09:25,426 INFO L134 CoverageAnalysis]: Checked inductivity of 706803 backedges. 211528 proven. 2059 refuted. 0 times theorem prover too weak. 493216 trivial. 0 not checked. [2018-12-09 19:09:25,426 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:09:29,859 INFO L134 CoverageAnalysis]: Checked inductivity of 706803 backedges. 145343 proven. 6472 refuted. 0 times theorem prover too weak. 554988 trivial. 0 not checked. [2018-12-09 19:09:29,876 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:09:29,877 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 62, 62] total 159 [2018-12-09 19:09:29,877 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:09:29,878 INFO L459 AbstractCegarLoop]: Interpolant automaton has 129 states [2018-12-09 19:09:29,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 129 interpolants. [2018-12-09 19:09:29,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3980, Invalid=21142, Unknown=0, NotChecked=0, Total=25122 [2018-12-09 19:09:29,879 INFO L87 Difference]: Start difference. First operand 3350 states and 3362 transitions. Second operand 129 states. [2018-12-09 19:09:33,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:09:33,684 INFO L93 Difference]: Finished difference Result 3040 states and 3045 transitions. [2018-12-09 19:09:33,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 156 states. [2018-12-09 19:09:33,684 INFO L78 Accepts]: Start accepts. Automaton has 129 states. Word has length 2961 [2018-12-09 19:09:33,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:09:33,688 INFO L225 Difference]: With dead ends: 3040 [2018-12-09 19:09:33,688 INFO L226 Difference]: Without dead ends: 3031 [2018-12-09 19:09:33,691 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6111 GetRequests, 5803 SyntacticMatches, 31 SemanticMatches, 277 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31485 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=12120, Invalid=65442, Unknown=0, NotChecked=0, Total=77562 [2018-12-09 19:09:33,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3031 states. [2018-12-09 19:09:33,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3031 to 3024. [2018-12-09 19:09:33,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3024 states. [2018-12-09 19:09:33,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3024 states to 3024 states and 3029 transitions. [2018-12-09 19:09:33,702 INFO L78 Accepts]: Start accepts. Automaton has 3024 states and 3029 transitions. Word has length 2961 [2018-12-09 19:09:33,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:09:33,703 INFO L480 AbstractCegarLoop]: Abstraction has 3024 states and 3029 transitions. [2018-12-09 19:09:33,703 INFO L481 AbstractCegarLoop]: Interpolant automaton has 129 states. [2018-12-09 19:09:33,703 INFO L276 IsEmpty]: Start isEmpty. Operand 3024 states and 3029 transitions. [2018-12-09 19:09:33,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2967 [2018-12-09 19:09:33,732 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:09:33,732 INFO L402 BasicCegarLoop]: trace histogram [526, 525, 525, 525, 525, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:09:33,732 INFO L423 AbstractCegarLoop]: === Iteration 98 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:09:33,732 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:09:33,732 INFO L82 PathProgramCache]: Analyzing trace with hash -643366969, now seen corresponding path program 83 times [2018-12-09 19:09:33,732 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:09:33,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:09:33,733 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:09:33,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:09:33,733 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:09:33,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:09:37,474 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 147388 proven. 6978 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-09 19:09:37,474 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:37,474 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:09:37,475 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:09:37,475 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:09:37,475 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:37,475 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:09:37,481 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:09:37,481 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:09:41,240 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 32 check-sat command(s) [2018-12-09 19:09:41,240 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:09:41,258 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:09:44,064 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 78518 proven. 2387 refuted. 0 times theorem prover too weak. 628550 trivial. 0 not checked. [2018-12-09 19:09:44,064 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:09:46,925 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 78518 proven. 2387 refuted. 0 times theorem prover too weak. 628550 trivial. 0 not checked. [2018-12-09 19:09:46,944 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:09:46,944 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 34, 34] total 105 [2018-12-09 19:09:46,944 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:09:46,945 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-12-09 19:09:46,945 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-12-09 19:09:46,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1674, Invalid=9246, Unknown=0, NotChecked=0, Total=10920 [2018-12-09 19:09:46,946 INFO L87 Difference]: Start difference. First operand 3024 states and 3029 transitions. Second operand 103 states. [2018-12-09 19:09:51,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:09:51,713 INFO L93 Difference]: Finished difference Result 3214 states and 3222 transitions. [2018-12-09 19:09:51,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2018-12-09 19:09:51,713 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 2966 [2018-12-09 19:09:51,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:09:51,716 INFO L225 Difference]: With dead ends: 3214 [2018-12-09 19:09:51,716 INFO L226 Difference]: Without dead ends: 3214 [2018-12-09 19:09:51,718 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6096 GetRequests, 5867 SyntacticMatches, 31 SemanticMatches, 198 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12218 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=9168, Invalid=30632, Unknown=0, NotChecked=0, Total=39800 [2018-12-09 19:09:51,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3214 states. [2018-12-09 19:09:51,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3214 to 3201. [2018-12-09 19:09:51,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3201 states. [2018-12-09 19:09:51,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3201 states to 3201 states and 3209 transitions. [2018-12-09 19:09:51,730 INFO L78 Accepts]: Start accepts. Automaton has 3201 states and 3209 transitions. Word has length 2966 [2018-12-09 19:09:51,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:09:51,731 INFO L480 AbstractCegarLoop]: Abstraction has 3201 states and 3209 transitions. [2018-12-09 19:09:51,731 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-12-09 19:09:51,731 INFO L276 IsEmpty]: Start isEmpty. Operand 3201 states and 3209 transitions. [2018-12-09 19:09:51,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2977 [2018-12-09 19:09:51,777 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:09:51,778 INFO L402 BasicCegarLoop]: trace histogram [528, 527, 527, 527, 527, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:09:51,778 INFO L423 AbstractCegarLoop]: === Iteration 99 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:09:51,778 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:09:51,778 INFO L82 PathProgramCache]: Analyzing trace with hash -310569395, now seen corresponding path program 84 times [2018-12-09 19:09:51,778 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:09:51,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:09:51,779 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:09:51,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:09:51,779 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:09:52,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:09:55,284 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83691 proven. 2733 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2018-12-09 19:09:55,284 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:55,284 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:09:55,284 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:09:55,284 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:09:55,284 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:09:55,285 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:09:55,290 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 19:09:55,290 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 19:09:55,669 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 19:09:55,669 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:09:55,694 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:09:59,211 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83459 proven. 8569 refuted. 0 times theorem prover too weak. 622746 trivial. 0 not checked. [2018-12-09 19:09:59,212 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:10:02,427 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83459 proven. 8569 refuted. 0 times theorem prover too weak. 622746 trivial. 0 not checked. [2018-12-09 19:10:02,445 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:10:02,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 71, 71] total 109 [2018-12-09 19:10:02,445 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:10:02,446 INFO L459 AbstractCegarLoop]: Interpolant automaton has 106 states [2018-12-09 19:10:02,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 106 interpolants. [2018-12-09 19:10:02,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2377, Invalid=9395, Unknown=0, NotChecked=0, Total=11772 [2018-12-09 19:10:02,447 INFO L87 Difference]: Start difference. First operand 3201 states and 3209 transitions. Second operand 106 states. [2018-12-09 19:10:04,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:10:04,823 INFO L93 Difference]: Finished difference Result 3555 states and 3567 transitions. [2018-12-09 19:10:04,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2018-12-09 19:10:04,823 INFO L78 Accepts]: Start accepts. Automaton has 106 states. Word has length 2976 [2018-12-09 19:10:04,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:10:04,828 INFO L225 Difference]: With dead ends: 3555 [2018-12-09 19:10:04,828 INFO L226 Difference]: Without dead ends: 3555 [2018-12-09 19:10:04,830 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6084 GetRequests, 5845 SyntacticMatches, 67 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9841 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=6678, Invalid=23424, Unknown=0, NotChecked=0, Total=30102 [2018-12-09 19:10:04,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states. [2018-12-09 19:10:04,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3541. [2018-12-09 19:10:04,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3541 states. [2018-12-09 19:10:04,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3541 states to 3541 states and 3553 transitions. [2018-12-09 19:10:04,847 INFO L78 Accepts]: Start accepts. Automaton has 3541 states and 3553 transitions. Word has length 2976 [2018-12-09 19:10:04,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:10:04,848 INFO L480 AbstractCegarLoop]: Abstraction has 3541 states and 3553 transitions. [2018-12-09 19:10:04,848 INFO L481 AbstractCegarLoop]: Interpolant automaton has 106 states. [2018-12-09 19:10:04,848 INFO L276 IsEmpty]: Start isEmpty. Operand 3541 states and 3553 transitions. [2018-12-09 19:10:04,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3138 [2018-12-09 19:10:04,882 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:10:04,883 INFO L402 BasicCegarLoop]: trace histogram [558, 557, 557, 557, 557, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:10:04,883 INFO L423 AbstractCegarLoop]: === Iteration 100 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:10:04,883 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:10:04,883 INFO L82 PathProgramCache]: Analyzing trace with hash -182742773, now seen corresponding path program 85 times [2018-12-09 19:10:04,883 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:10:04,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:10:04,884 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:10:04,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:10:04,884 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:10:05,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:10:08,967 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 155124 proven. 11852 refuted. 0 times theorem prover too weak. 630874 trivial. 0 not checked. [2018-12-09 19:10:08,967 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:10:08,967 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:10:08,967 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:10:08,967 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:10:08,967 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:10:08,967 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:10:08,974 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:10:08,974 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:10:09,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:10:09,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:10:13,744 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 233088 proven. 2205 refuted. 0 times theorem prover too weak. 562557 trivial. 0 not checked. [2018-12-09 19:10:13,744 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:10:18,602 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 160000 proven. 6920 refuted. 0 times theorem prover too weak. 630930 trivial. 0 not checked. [2018-12-09 19:10:18,620 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:10:18,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 64, 64] total 164 [2018-12-09 19:10:18,622 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:10:18,623 INFO L459 AbstractCegarLoop]: Interpolant automaton has 133 states [2018-12-09 19:10:18,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 133 interpolants. [2018-12-09 19:10:18,624 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4236, Invalid=22496, Unknown=0, NotChecked=0, Total=26732 [2018-12-09 19:10:18,624 INFO L87 Difference]: Start difference. First operand 3541 states and 3553 transitions. Second operand 133 states. [2018-12-09 19:10:23,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:10:23,817 INFO L93 Difference]: Finished difference Result 3216 states and 3221 transitions. [2018-12-09 19:10:23,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2018-12-09 19:10:23,818 INFO L78 Accepts]: Start accepts. Automaton has 133 states. Word has length 3137 [2018-12-09 19:10:23,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:10:23,820 INFO L225 Difference]: With dead ends: 3216 [2018-12-09 19:10:23,820 INFO L226 Difference]: Without dead ends: 3207 [2018-12-09 19:10:23,822 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6469 GetRequests, 6151 SyntacticMatches, 32 SemanticMatches, 286 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33620 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=12910, Invalid=69746, Unknown=0, NotChecked=0, Total=82656 [2018-12-09 19:10:23,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3207 states. [2018-12-09 19:10:23,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3207 to 3200. [2018-12-09 19:10:23,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3200 states. [2018-12-09 19:10:23,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3200 states to 3200 states and 3205 transitions. [2018-12-09 19:10:23,835 INFO L78 Accepts]: Start accepts. Automaton has 3200 states and 3205 transitions. Word has length 3137 [2018-12-09 19:10:23,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:10:23,836 INFO L480 AbstractCegarLoop]: Abstraction has 3200 states and 3205 transitions. [2018-12-09 19:10:23,836 INFO L481 AbstractCegarLoop]: Interpolant automaton has 133 states. [2018-12-09 19:10:23,836 INFO L276 IsEmpty]: Start isEmpty. Operand 3200 states and 3205 transitions. [2018-12-09 19:10:23,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3143 [2018-12-09 19:10:23,868 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:10:23,868 INFO L402 BasicCegarLoop]: trace histogram [559, 558, 558, 558, 558, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:10:23,868 INFO L423 AbstractCegarLoop]: === Iteration 101 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:10:23,868 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:10:23,869 INFO L82 PathProgramCache]: Analyzing trace with hash -1867759088, now seen corresponding path program 86 times [2018-12-09 19:10:23,869 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:10:23,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:10:23,869 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:10:23,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:10:23,869 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:10:24,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:10:28,010 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 162175 proven. 7443 refuted. 0 times theorem prover too weak. 631050 trivial. 0 not checked. [2018-12-09 19:10:28,010 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:10:28,010 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:10:28,010 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 19:10:28,010 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 19:10:28,010 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:10:28,010 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:10:28,016 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 19:10:28,016 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 19:10:32,347 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-12-09 19:10:32,347 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 19:10:32,368 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:10:35,689 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 159788 proven. 7443 refuted. 0 times theorem prover too weak. 633437 trivial. 0 not checked. [2018-12-09 19:10:35,689 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:10:39,760 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 159663 proven. 7568 refuted. 0 times theorem prover too weak. 633437 trivial. 0 not checked. [2018-12-09 19:10:39,779 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 19:10:39,780 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 41, 41] total 142 [2018-12-09 19:10:39,780 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 19:10:39,780 INFO L459 AbstractCegarLoop]: Interpolant automaton has 107 states [2018-12-09 19:10:39,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2018-12-09 19:10:39,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3964, Invalid=16058, Unknown=0, NotChecked=0, Total=20022 [2018-12-09 19:10:39,781 INFO L87 Difference]: Start difference. First operand 3200 states and 3205 transitions. Second operand 107 states. [2018-12-09 19:10:42,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:10:42,684 INFO L93 Difference]: Finished difference Result 3387 states and 3394 transitions. [2018-12-09 19:10:42,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2018-12-09 19:10:42,684 INFO L78 Accepts]: Start accepts. Automaton has 107 states. Word has length 3142 [2018-12-09 19:10:42,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:10:42,688 INFO L225 Difference]: With dead ends: 3387 [2018-12-09 19:10:42,688 INFO L226 Difference]: Without dead ends: 3387 [2018-12-09 19:10:42,690 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6452 GetRequests, 6209 SyntacticMatches, 6 SemanticMatches, 237 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18963 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=14033, Invalid=42849, Unknown=0, NotChecked=0, Total=56882 [2018-12-09 19:10:42,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3387 states. [2018-12-09 19:10:42,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3387 to 3377. [2018-12-09 19:10:42,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3377 states. [2018-12-09 19:10:42,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3377 states to 3377 states and 3384 transitions. [2018-12-09 19:10:42,703 INFO L78 Accepts]: Start accepts. Automaton has 3377 states and 3384 transitions. Word has length 3142 [2018-12-09 19:10:42,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:10:42,704 INFO L480 AbstractCegarLoop]: Abstraction has 3377 states and 3384 transitions. [2018-12-09 19:10:42,704 INFO L481 AbstractCegarLoop]: Interpolant automaton has 107 states. [2018-12-09 19:10:42,704 INFO L276 IsEmpty]: Start isEmpty. Operand 3377 states and 3384 transitions. [2018-12-09 19:10:42,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3148 [2018-12-09 19:10:42,736 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:10:42,736 INFO L402 BasicCegarLoop]: trace histogram [560, 559, 559, 559, 559, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:10:42,736 INFO L423 AbstractCegarLoop]: === Iteration 102 === [fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2018-12-09 19:10:42,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:10:42,737 INFO L82 PathProgramCache]: Analyzing trace with hash -486718779, now seen corresponding path program 87 times [2018-12-09 19:10:42,737 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:10:42,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:10:42,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 19:10:42,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:10:42,737 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:10:43,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 19:10:44,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 19:10:44,931 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 19:10:45,210 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 07:10:45 BoogieIcfgContainer [2018-12-09 19:10:45,210 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 19:10:45,210 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 19:10:45,210 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 19:10:45,210 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 19:10:45,211 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 07:01:50" (3/4) ... [2018-12-09 19:10:45,212 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-09 19:10:45,477 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_91770219-5bfe-49c5-97bf-d35acb7e3935/bin-2019/utaipan/witness.graphml [2018-12-09 19:10:45,477 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 19:10:45,478 INFO L168 Benchmark]: Toolchain (without parser) took 535447.39 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 957.8 MB in the beginning and 1.1 GB in the end (delta: -101.5 MB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. [2018-12-09 19:10:45,479 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 19:10:45,479 INFO L168 Benchmark]: CACSL2BoogieTranslator took 129.11 ms. Allocated memory is still 1.0 GB. Free memory was 957.8 MB in the beginning and 947.0 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-12-09 19:10:45,479 INFO L168 Benchmark]: Boogie Procedure Inliner took 13.81 ms. Allocated memory is still 1.0 GB. Free memory is still 947.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 19:10:45,479 INFO L168 Benchmark]: Boogie Preprocessor took 44.10 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 115.3 MB). Free memory was 947.0 MB in the beginning and 1.1 GB in the end (delta: -163.6 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. [2018-12-09 19:10:45,480 INFO L168 Benchmark]: RCFGBuilder took 152.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 22.5 MB). Peak memory consumption was 22.5 MB. Max. memory is 11.5 GB. [2018-12-09 19:10:45,480 INFO L168 Benchmark]: TraceAbstraction took 534837.55 ms. Allocated memory was 1.1 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -54.2 MB). Peak memory consumption was 3.8 GB. Max. memory is 11.5 GB. [2018-12-09 19:10:45,480 INFO L168 Benchmark]: Witness Printer took 267.12 ms. Allocated memory is still 5.0 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 83.0 MB). Peak memory consumption was 83.0 MB. Max. memory is 11.5 GB. [2018-12-09 19:10:45,481 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 129.11 ms. Allocated memory is still 1.0 GB. Free memory was 957.8 MB in the beginning and 947.0 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 13.81 ms. Allocated memory is still 1.0 GB. Free memory is still 947.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.10 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 115.3 MB). Free memory was 947.0 MB in the beginning and 1.1 GB in the end (delta: -163.6 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 152.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 22.5 MB). Peak memory consumption was 22.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 534837.55 ms. Allocated memory was 1.1 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -54.2 MB). Peak memory consumption was 3.8 GB. Max. memory is 11.5 GB. * Witness Printer took 267.12 ms. Allocated memory is still 5.0 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 83.0 MB). Peak memory consumption was 83.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] char mask[32]; [L26] i = 0 VAL [b={157:0}, i=0, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=0, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=148, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=162, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L20] return i; VAL [\old(size)=1, \result=2, b={140:0}, b={140:0}, i=2, size=1] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=2, i=0, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=2, i=0, mask={140:0}] [L26] i++ VAL [b={157:0}, i=1, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=1, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=148, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=162, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=143, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L20] return i; VAL [\old(size)=2, \result=3, b={140:0}, b={140:0}, i=3, size=2] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=3, i=1, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=3, i=1, mask={140:0}] [L26] i++ VAL [b={157:0}, i=2, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=2, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=148, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=162, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=143, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=131, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L20] return i; VAL [\old(size)=3, \result=4, b={140:0}, b={140:0}, i=4, size=3] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=4, i=2, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=4, i=2, mask={140:0}] [L26] i++ VAL [b={157:0}, i=3, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=3, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=148, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=162, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=143, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=131, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=130, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L20] return i; VAL [\old(size)=4, \result=5, b={140:0}, b={140:0}, i=5, size=4] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=5, i=3, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=5, i=3, mask={140:0}] [L26] i++ VAL [b={157:0}, i=4, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=4, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=148, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=162, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=143, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=131, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=130, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=139, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L20] return i; VAL [\old(size)=5, \result=6, b={140:0}, b={140:0}, i=6, size=5] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=6, i=4, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=6, i=4, mask={140:0}] [L26] i++ VAL [b={157:0}, i=5, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=5, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=148, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=162, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=143, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=131, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=130, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=139, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=129, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L20] return i; VAL [\old(size)=6, \result=7, b={140:0}, b={140:0}, i=7, size=6] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=7, i=5, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=7, i=5, mask={140:0}] [L26] i++ VAL [b={157:0}, i=6, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=6, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=148, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=162, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=143, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=131, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=130, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=139, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=129, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=149, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L20] return i; VAL [\old(size)=7, \result=8, b={140:0}, b={140:0}, i=8, size=7] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=8, i=6, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=8, i=6, mask={140:0}] [L26] i++ VAL [b={157:0}, i=7, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=7, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=148, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=162, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=143, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=131, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=130, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=139, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=129, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=149, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=155, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L20] return i; VAL [\old(size)=8, \result=9, b={140:0}, b={140:0}, i=9, size=8] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=9, i=7, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=9, i=7, mask={140:0}] [L26] i++ VAL [b={157:0}, i=8, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=8, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=148, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=162, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=143, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=131, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=130, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=139, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=129, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=149, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=155, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=135, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L20] return i; VAL [\old(size)=9, \result=10, b={140:0}, b={140:0}, i=10, size=9] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=10, i=8, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=10, i=8, mask={140:0}] [L26] i++ VAL [b={157:0}, i=9, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=9, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=148, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=162, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=143, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=131, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=130, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=139, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=129, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=149, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=155, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=135, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L20] return i; VAL [\old(size)=10, \result=11, b={140:0}, b={140:0}, i=11, size=10] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=11, i=9, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=11, i=9, mask={140:0}] [L26] i++ VAL [b={157:0}, i=10, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=10, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=148, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=162, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=143, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=131, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=130, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=139, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=129, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=149, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=155, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=135, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=146, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L20] return i; VAL [\old(size)=11, \result=12, b={140:0}, b={140:0}, i=12, size=11] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=12, i=10, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=12, i=10, mask={140:0}] [L26] i++ VAL [b={157:0}, i=11, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=11, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=148, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=162, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=143, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=131, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=130, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=139, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=129, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=149, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=155, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=135, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=146, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=151, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L20] return i; VAL [\old(size)=12, \result=13, b={140:0}, b={140:0}, i=13, size=12] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=13, i=11, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=13, i=11, mask={140:0}] [L26] i++ VAL [b={157:0}, i=12, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=12, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=148, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=162, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=143, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=131, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=130, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=139, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=129, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=149, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=155, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=135, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=146, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=151, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=158, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L20] return i; VAL [\old(size)=13, \result=14, b={140:0}, b={140:0}, i=14, size=13] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=14, i=12, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=14, i=12, mask={140:0}] [L26] i++ VAL [b={157:0}, i=13, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=13, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=148, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=162, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=143, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=131, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=130, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=139, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=129, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=149, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=155, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=135, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=146, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=151, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=158, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=154, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L20] return i; VAL [\old(size)=14, \result=15, b={140:0}, b={140:0}, i=15, size=14] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=15, i=13, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=15, i=13, mask={140:0}] [L26] i++ VAL [b={157:0}, i=14, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=14, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=148, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=162, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=143, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=131, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=130, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=139, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=129, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=149, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=155, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=135, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=146, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=151, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=158, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=154, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=136, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L20] return i; VAL [\old(size)=15, \result=16, b={140:0}, b={140:0}, i=16, size=15] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=16, i=14, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=16, i=14, mask={140:0}] [L26] i++ VAL [b={157:0}, i=15, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=15, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=148, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=162, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=143, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=131, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=130, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=139, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=129, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=149, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=155, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=135, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=146, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=151, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=158, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=154, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=136, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=138, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L20] return i; VAL [\old(size)=16, \result=17, b={140:0}, b={140:0}, i=17, size=16] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=17, i=15, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=17, i=15, mask={140:0}] [L26] i++ VAL [b={157:0}, i=16, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=16, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=148, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=162, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=143, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=131, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=130, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=139, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=129, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=149, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=155, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=135, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=146, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=151, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=158, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=154, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=136, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=138, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=152, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L20] return i; VAL [\old(size)=17, \result=18, b={140:0}, b={140:0}, i=18, size=17] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=18, i=16, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=18, i=16, mask={140:0}] [L26] i++ VAL [b={157:0}, i=17, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=17, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=148, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=162, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=143, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=131, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=130, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=139, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=129, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=149, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=155, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=135, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=146, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=151, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=158, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=154, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=136, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=138, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=152, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=141, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L20] return i; VAL [\old(size)=18, \result=19, b={140:0}, b={140:0}, i=19, size=18] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=19, i=17, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=19, i=17, mask={140:0}] [L26] i++ VAL [b={157:0}, i=18, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=18, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=148, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=162, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=143, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=131, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=130, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=139, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=129, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=149, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=155, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=135, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=146, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=151, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=158, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=154, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=136, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=138, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=152, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=141, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=132, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L20] return i; VAL [\old(size)=19, \result=20, b={140:0}, b={140:0}, i=20, size=19] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=20, i=18, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=20, i=18, mask={140:0}] [L26] i++ VAL [b={157:0}, i=19, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=19, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=148, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=162, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=143, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=131, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=130, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=139, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=129, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=149, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=155, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=135, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=146, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=151, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=158, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=154, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=136, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=138, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=152, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=141, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=132, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=133, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L20] return i; VAL [\old(size)=20, \result=21, b={140:0}, b={140:0}, i=21, size=20] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=21, i=19, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=21, i=19, mask={140:0}] [L26] i++ VAL [b={157:0}, i=20, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=20, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=148, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=162, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=143, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=131, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=130, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=139, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=129, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=149, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=155, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=135, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=146, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=151, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=158, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=154, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=136, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=138, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=152, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=141, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=132, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=133, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=137, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L20] return i; VAL [\old(size)=21, \result=22, b={140:0}, b={140:0}, i=22, size=21] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=22, i=20, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=22, i=20, mask={140:0}] [L26] i++ VAL [b={157:0}, i=21, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=21, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=148, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=162, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=143, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=131, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=130, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=139, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=129, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=149, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=155, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=135, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=146, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=151, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=158, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=154, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=136, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=138, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=152, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=141, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=132, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=133, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=137, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=159, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L20] return i; VAL [\old(size)=22, \result=23, b={140:0}, b={140:0}, i=23, size=22] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=23, i=21, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=23, i=21, mask={140:0}] [L26] i++ VAL [b={157:0}, i=22, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=22, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=148, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=162, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=143, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=131, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=130, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=139, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=129, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=149, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=155, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=135, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=146, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=151, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=158, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=154, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=136, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=138, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=152, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=141, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=132, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=133, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=137, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=159, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=163, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L20] return i; VAL [\old(size)=23, \result=24, b={140:0}, b={140:0}, i=24, size=23] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=24, i=22, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=24, i=22, mask={140:0}] [L26] i++ VAL [b={157:0}, i=23, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=23, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=148, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=162, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=143, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=131, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=130, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=139, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=129, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=149, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=155, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=135, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=146, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=151, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=158, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=154, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=136, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=138, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=152, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=141, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=132, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=133, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=137, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=159, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=163, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=144, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L20] return i; VAL [\old(size)=24, \result=25, b={140:0}, b={140:0}, i=25, size=24] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=25, i=23, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=25, i=23, mask={140:0}] [L26] i++ VAL [b={157:0}, i=24, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=24, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=148, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=162, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=143, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=131, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=130, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=139, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=129, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=149, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=155, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=135, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=146, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=151, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=158, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=154, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=136, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=138, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=152, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=141, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=132, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=133, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=137, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=159, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=163, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=144, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=153, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L20] return i; VAL [\old(size)=25, \result=26, b={140:0}, b={140:0}, i=26, size=25] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=26, i=24, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=26, i=24, mask={140:0}] [L26] i++ VAL [b={157:0}, i=25, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=25, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=148, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=162, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=143, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=131, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=130, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=139, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=129, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=149, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=155, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=135, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=146, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=151, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=158, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=154, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=136, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=138, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=152, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=141, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=132, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=133, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=137, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=159, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=163, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=144, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=153, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=145, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L20] return i; VAL [\old(size)=26, \result=27, b={140:0}, b={140:0}, i=27, size=26] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=27, i=25, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=27, i=25, mask={140:0}] [L26] i++ VAL [b={157:0}, i=26, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=26, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=148, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=162, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=143, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=131, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=130, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=139, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=129, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=149, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=155, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=135, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=146, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=151, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=158, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=154, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=136, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=138, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=152, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=141, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=132, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=133, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=137, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=159, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=163, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=144, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=153, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=145, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=164, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L20] return i; VAL [\old(size)=27, \result=28, b={140:0}, b={140:0}, i=28, size=27] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=28, i=26, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=28, i=26, mask={140:0}] [L26] i++ VAL [b={157:0}, i=27, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=27, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=148, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=162, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=143, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=131, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=130, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=139, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=129, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=149, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=155, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=135, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=146, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=151, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=158, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=154, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=136, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=138, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=152, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=141, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=132, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=133, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=137, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=159, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=163, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=144, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=153, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=145, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=164, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=160, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L20] return i; VAL [\old(size)=28, \result=29, b={140:0}, b={140:0}, i=29, size=28] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=29, i=27, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=29, i=27, mask={140:0}] [L26] i++ VAL [b={157:0}, i=28, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=28, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=148, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=162, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=143, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=131, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=130, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=139, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=129, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=149, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=155, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=135, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=146, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=151, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=158, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=154, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=136, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=138, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=152, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=141, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=132, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=133, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=137, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=159, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=163, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=144, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=153, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=145, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=164, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=160, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=142, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L20] return i; VAL [\old(size)=29, \result=30, b={140:0}, b={140:0}, i=30, size=29] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=30, i=28, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=30, i=28, mask={140:0}] [L26] i++ VAL [b={157:0}, i=29, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=29, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=148, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=162, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=143, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=131, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=130, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=139, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=129, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=149, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=155, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=135, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=146, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=151, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=158, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=154, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=136, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=138, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=152, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=141, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=132, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=133, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=137, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=159, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=163, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=144, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=153, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=145, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=164, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=160, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=142, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=161, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L20] return i; VAL [\old(size)=30, \result=31, b={140:0}, b={140:0}, i=31, size=30] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=31, i=29, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=31, i=29, mask={140:0}] [L26] i++ VAL [b={157:0}, i=30, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=30, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=148, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=162, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=143, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=131, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=130, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=139, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=129, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=149, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=155, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=135, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=146, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=151, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=158, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=154, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=136, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=138, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=152, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=141, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=132, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=133, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=137, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=159, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=163, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=144, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=153, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=145, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=164, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=160, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=142, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=161, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=134, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L20] return i; VAL [\old(size)=31, \result=32, b={140:0}, b={140:0}, i=32, size=31] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=32, i=30, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=32, i=30, mask={140:0}] [L26] i++ VAL [b={157:0}, i=31, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=31, mask={140:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=148, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=162, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=143, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=131, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=130, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=139, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=129, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=149, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=155, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=135, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=150, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=146, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=151, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=158, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=154, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=136, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=138, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=152, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=141, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=132, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=133, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=137, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=159, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=163, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=144, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=153, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=145, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=164, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=160, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=142, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=161, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=134, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 40 locations, 8 error locations. UNSAFE Result, 534.8s OverallTime, 102 OverallIterations, 560 TraceHistogramMax, 163.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3148 SDtfs, 77223 SDslu, 52128 SDs, 0 SdLazy, 243961 SolverSat, 13353 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 65.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 229303 GetRequests, 216982 SyntacticMatches, 1066 SemanticMatches, 11255 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 634503 ImplicationChecksByTransitivity, 200.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3541occurred in iteration=99, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.5s AbstIntTime, 5 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 101 MinimizatonAttempts, 1444 StatesRemovedByMinimization, 98 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 4.0s SsaConstructionTime, 53.9s SatisfiabilityAnalysisTime, 251.6s InterpolantComputationTime, 224889 NumberOfCodeBlocks, 201360 NumberOfCodeBlocksAsserted, 734 NumberOfCheckSat, 332235 ConstructedInterpolants, 45 QuantifiedInterpolants, 938387608 SizeOfPredicates, 271 NumberOfNonLiveVariables, 221457 ConjunctsInSsa, 2975 ConjunctsInUnsatCore, 287 InterpolantComputations, 8 PerfectInterpolantSequences, 49038250/49603719 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...