./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-08 17:52:24,687 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-08 17:52:24,688 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-08 17:52:24,694 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-08 17:52:24,694 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-08 17:52:24,695 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-08 17:52:24,695 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-08 17:52:24,696 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-08 17:52:24,697 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-08 17:52:24,698 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-08 17:52:24,698 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-08 17:52:24,698 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-08 17:52:24,699 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-08 17:52:24,699 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-08 17:52:24,700 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-08 17:52:24,701 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-08 17:52:24,701 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-08 17:52:24,702 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-08 17:52:24,703 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-08 17:52:24,704 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-08 17:52:24,704 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-08 17:52:24,705 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-08 17:52:24,706 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-08 17:52:24,706 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-08 17:52:24,706 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-08 17:52:24,707 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-08 17:52:24,707 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-08 17:52:24,708 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-08 17:52:24,708 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-08 17:52:24,709 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-08 17:52:24,709 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-08 17:52:24,710 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-08 17:52:24,710 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-08 17:52:24,710 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-08 17:52:24,711 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-08 17:52:24,711 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-08 17:52:24,711 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-12-08 17:52:24,718 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-08 17:52:24,719 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-08 17:52:24,719 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-08 17:52:24,719 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-08 17:52:24,720 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-08 17:52:24,720 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-08 17:52:24,720 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-08 17:52:24,720 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-08 17:52:24,720 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-08 17:52:24,720 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-08 17:52:24,720 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-08 17:52:24,721 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-08 17:52:24,721 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-08 17:52:24,721 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-08 17:52:24,721 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-08 17:52:24,721 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-08 17:52:24,721 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-08 17:52:24,722 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-08 17:52:24,722 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-08 17:52:24,722 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-08 17:52:24,722 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-08 17:52:24,722 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-08 17:52:24,722 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-08 17:52:24,722 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-08 17:52:24,723 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-08 17:52:24,723 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-08 17:52:24,723 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-08 17:52:24,723 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-08 17:52:24,723 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-08 17:52:24,723 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-08 17:52:24,723 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-08 17:52:24,723 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-08 17:52:24,724 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-08 17:52:24,724 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-08 17:52:24,724 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-08 17:52:24,724 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-08 17:52:24,724 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2018-12-08 17:52:24,741 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-08 17:52:24,747 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-08 17:52:24,749 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-08 17:52:24,750 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-08 17:52:24,750 INFO L276 PluginConnector]: CDTParser initialized [2018-12-08 17:52:24,751 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-12-08 17:52:24,783 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/data/43f196b6c/520294d675444c598943e0d860a7e3e5/FLAG2c0f930c0 [2018-12-08 17:52:25,170 INFO L307 CDTParser]: Found 1 translation units. [2018-12-08 17:52:25,170 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-12-08 17:52:25,174 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/data/43f196b6c/520294d675444c598943e0d860a7e3e5/FLAG2c0f930c0 [2018-12-08 17:52:25,182 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/data/43f196b6c/520294d675444c598943e0d860a7e3e5 [2018-12-08 17:52:25,184 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-08 17:52:25,185 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-08 17:52:25,186 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-08 17:52:25,186 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-08 17:52:25,188 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-08 17:52:25,188 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,190 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@22096c3e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25, skipping insertion in model container [2018-12-08 17:52:25,190 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,194 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-08 17:52:25,208 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-08 17:52:25,310 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 17:52:25,313 INFO L191 MainTranslator]: Completed pre-run [2018-12-08 17:52:25,333 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 17:52:25,343 INFO L195 MainTranslator]: Completed translation [2018-12-08 17:52:25,343 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25 WrapperNode [2018-12-08 17:52:25,343 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-08 17:52:25,344 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-08 17:52:25,344 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-08 17:52:25,344 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-08 17:52:25,349 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,353 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,357 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-08 17:52:25,357 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-08 17:52:25,357 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-08 17:52:25,358 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-08 17:52:25,393 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,394 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,395 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,395 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,399 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,404 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,405 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... [2018-12-08 17:52:25,407 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-08 17:52:25,407 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-08 17:52:25,407 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-08 17:52:25,407 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-08 17:52:25,408 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-08 17:52:25,440 INFO L130 BoogieDeclarations]: Found specification of procedure P_1 [2018-12-08 17:52:25,440 INFO L138 BoogieDeclarations]: Found implementation of procedure P_1 [2018-12-08 17:52:25,440 INFO L130 BoogieDeclarations]: Found specification of procedure write_data [2018-12-08 17:52:25,440 INFO L138 BoogieDeclarations]: Found implementation of procedure write_data [2018-12-08 17:52:25,440 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-08 17:52:25,440 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-08 17:52:25,440 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-08 17:52:25,441 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-08 17:52:25,441 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-08 17:52:25,441 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-08 17:52:25,441 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-08 17:52:25,441 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-08 17:52:25,441 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-08 17:52:25,441 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-08 17:52:25,441 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-08 17:52:25,442 INFO L130 BoogieDeclarations]: Found specification of procedure is_P_1_triggered [2018-12-08 17:52:25,442 INFO L138 BoogieDeclarations]: Found implementation of procedure is_P_1_triggered [2018-12-08 17:52:25,442 INFO L130 BoogieDeclarations]: Found specification of procedure read_data [2018-12-08 17:52:25,442 INFO L138 BoogieDeclarations]: Found implementation of procedure read_data [2018-12-08 17:52:25,442 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-08 17:52:25,442 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-08 17:52:25,442 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-08 17:52:25,442 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-08 17:52:25,442 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-08 17:52:25,443 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-08 17:52:25,443 INFO L130 BoogieDeclarations]: Found specification of procedure C_1 [2018-12-08 17:52:25,443 INFO L138 BoogieDeclarations]: Found implementation of procedure C_1 [2018-12-08 17:52:25,443 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-08 17:52:25,443 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-08 17:52:25,443 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-08 17:52:25,443 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-08 17:52:25,443 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-08 17:52:25,443 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-08 17:52:25,444 INFO L130 BoogieDeclarations]: Found specification of procedure is_C_1_triggered [2018-12-08 17:52:25,444 INFO L138 BoogieDeclarations]: Found implementation of procedure is_C_1_triggered [2018-12-08 17:52:25,444 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-08 17:52:25,444 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-08 17:52:25,676 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-08 17:52:25,677 INFO L280 CfgBuilder]: Removed 4 assue(true) statements. [2018-12-08 17:52:25,677 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 05:52:25 BoogieIcfgContainer [2018-12-08 17:52:25,677 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-08 17:52:25,678 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-08 17:52:25,678 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-08 17:52:25,681 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-08 17:52:25,681 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 08.12 05:52:25" (1/3) ... [2018-12-08 17:52:25,682 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5242b4fb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.12 05:52:25, skipping insertion in model container [2018-12-08 17:52:25,682 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 05:52:25" (2/3) ... [2018-12-08 17:52:25,682 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5242b4fb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.12 05:52:25, skipping insertion in model container [2018-12-08 17:52:25,682 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 05:52:25" (3/3) ... [2018-12-08 17:52:25,683 INFO L112 eAbstractionObserver]: Analyzing ICFG kundu1_false-unreach-call_false-termination.cil.c [2018-12-08 17:52:25,689 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-08 17:52:25,695 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-08 17:52:25,704 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-08 17:52:25,727 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-08 17:52:25,727 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-08 17:52:25,727 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-08 17:52:25,727 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-08 17:52:25,727 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-08 17:52:25,727 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-08 17:52:25,727 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-08 17:52:25,727 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-08 17:52:25,742 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states. [2018-12-08 17:52:25,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-08 17:52:25,749 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:25,750 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:25,752 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:25,756 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:25,756 INFO L82 PathProgramCache]: Analyzing trace with hash -1385664965, now seen corresponding path program 1 times [2018-12-08 17:52:25,757 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:25,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:25,786 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:25,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:25,787 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:25,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:25,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:25,905 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:25,906 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 17:52:25,906 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:25,909 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 17:52:25,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 17:52:25,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:25,918 INFO L87 Difference]: Start difference. First operand 150 states. Second operand 4 states. [2018-12-08 17:52:26,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:26,009 INFO L93 Difference]: Finished difference Result 282 states and 384 transitions. [2018-12-08 17:52:26,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 17:52:26,011 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-12-08 17:52:26,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:26,018 INFO L225 Difference]: With dead ends: 282 [2018-12-08 17:52:26,018 INFO L226 Difference]: Without dead ends: 140 [2018-12-08 17:52:26,020 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:26,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-12-08 17:52:26,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-12-08 17:52:26,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-12-08 17:52:26,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 179 transitions. [2018-12-08 17:52:26,054 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 179 transitions. Word has length 72 [2018-12-08 17:52:26,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:26,056 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 179 transitions. [2018-12-08 17:52:26,056 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 17:52:26,056 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 179 transitions. [2018-12-08 17:52:26,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-08 17:52:26,058 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:26,058 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:26,059 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:26,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:26,059 INFO L82 PathProgramCache]: Analyzing trace with hash -1426339715, now seen corresponding path program 1 times [2018-12-08 17:52:26,059 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:26,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,060 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:26,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,060 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:26,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:26,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:26,136 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:26,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 17:52:26,137 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:26,138 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 17:52:26,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 17:52:26,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:26,139 INFO L87 Difference]: Start difference. First operand 140 states and 179 transitions. Second operand 4 states. [2018-12-08 17:52:26,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:26,264 INFO L93 Difference]: Finished difference Result 373 states and 490 transitions. [2018-12-08 17:52:26,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 17:52:26,265 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-12-08 17:52:26,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:26,266 INFO L225 Difference]: With dead ends: 373 [2018-12-08 17:52:26,267 INFO L226 Difference]: Without dead ends: 253 [2018-12-08 17:52:26,268 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:26,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2018-12-08 17:52:26,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 238. [2018-12-08 17:52:26,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-12-08 17:52:26,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 301 transitions. [2018-12-08 17:52:26,286 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 301 transitions. Word has length 72 [2018-12-08 17:52:26,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:26,286 INFO L480 AbstractCegarLoop]: Abstraction has 238 states and 301 transitions. [2018-12-08 17:52:26,286 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 17:52:26,286 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 301 transitions. [2018-12-08 17:52:26,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 17:52:26,287 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:26,288 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:26,288 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:26,288 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:26,288 INFO L82 PathProgramCache]: Analyzing trace with hash 1691683492, now seen corresponding path program 1 times [2018-12-08 17:52:26,288 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:26,288 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,289 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:26,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,289 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:26,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:26,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:26,342 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:26,342 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 17:52:26,342 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:26,343 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 17:52:26,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 17:52:26,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:26,343 INFO L87 Difference]: Start difference. First operand 238 states and 301 transitions. Second operand 4 states. [2018-12-08 17:52:26,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:26,478 INFO L93 Difference]: Finished difference Result 573 states and 746 transitions. [2018-12-08 17:52:26,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 17:52:26,478 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2018-12-08 17:52:26,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:26,481 INFO L225 Difference]: With dead ends: 573 [2018-12-08 17:52:26,481 INFO L226 Difference]: Without dead ends: 355 [2018-12-08 17:52:26,483 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:26,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2018-12-08 17:52:26,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 339. [2018-12-08 17:52:26,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 339 states. [2018-12-08 17:52:26,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339 states to 339 states and 428 transitions. [2018-12-08 17:52:26,515 INFO L78 Accepts]: Start accepts. Automaton has 339 states and 428 transitions. Word has length 73 [2018-12-08 17:52:26,515 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:26,516 INFO L480 AbstractCegarLoop]: Abstraction has 339 states and 428 transitions. [2018-12-08 17:52:26,516 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 17:52:26,516 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 428 transitions. [2018-12-08 17:52:26,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 17:52:26,517 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:26,517 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:26,517 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:26,518 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:26,518 INFO L82 PathProgramCache]: Analyzing trace with hash -73133117, now seen corresponding path program 1 times [2018-12-08 17:52:26,518 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:26,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,519 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:26,519 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,519 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:26,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:26,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:26,587 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:26,587 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 17:52:26,587 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:26,587 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 17:52:26,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 17:52:26,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 17:52:26,588 INFO L87 Difference]: Start difference. First operand 339 states and 428 transitions. Second operand 6 states. [2018-12-08 17:52:26,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:26,619 INFO L93 Difference]: Finished difference Result 688 states and 882 transitions. [2018-12-08 17:52:26,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 17:52:26,620 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-08 17:52:26,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:26,621 INFO L225 Difference]: With dead ends: 688 [2018-12-08 17:52:26,621 INFO L226 Difference]: Without dead ends: 369 [2018-12-08 17:52:26,622 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-08 17:52:26,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2018-12-08 17:52:26,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 354. [2018-12-08 17:52:26,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-12-08 17:52:26,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 443 transitions. [2018-12-08 17:52:26,640 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 443 transitions. Word has length 73 [2018-12-08 17:52:26,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:26,640 INFO L480 AbstractCegarLoop]: Abstraction has 354 states and 443 transitions. [2018-12-08 17:52:26,640 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 17:52:26,640 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 443 transitions. [2018-12-08 17:52:26,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 17:52:26,641 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:26,641 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:26,641 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:26,641 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:26,642 INFO L82 PathProgramCache]: Analyzing trace with hash -1444940415, now seen corresponding path program 1 times [2018-12-08 17:52:26,642 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:26,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:26,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,642 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:26,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:26,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:26,692 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:26,692 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 17:52:26,692 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:26,692 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 17:52:26,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 17:52:26,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 17:52:26,693 INFO L87 Difference]: Start difference. First operand 354 states and 443 transitions. Second operand 6 states. [2018-12-08 17:52:26,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:26,732 INFO L93 Difference]: Finished difference Result 702 states and 887 transitions. [2018-12-08 17:52:26,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 17:52:26,732 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-08 17:52:26,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:26,734 INFO L225 Difference]: With dead ends: 702 [2018-12-08 17:52:26,735 INFO L226 Difference]: Without dead ends: 368 [2018-12-08 17:52:26,736 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-08 17:52:26,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states. [2018-12-08 17:52:26,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 364. [2018-12-08 17:52:26,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2018-12-08 17:52:26,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 452 transitions. [2018-12-08 17:52:26,750 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 452 transitions. Word has length 73 [2018-12-08 17:52:26,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:26,750 INFO L480 AbstractCegarLoop]: Abstraction has 364 states and 452 transitions. [2018-12-08 17:52:26,750 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 17:52:26,750 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 452 transitions. [2018-12-08 17:52:26,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 17:52:26,751 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:26,751 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:26,752 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:26,752 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:26,752 INFO L82 PathProgramCache]: Analyzing trace with hash -1422308161, now seen corresponding path program 1 times [2018-12-08 17:52:26,752 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:26,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:26,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,753 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:26,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:26,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:26,830 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:26,830 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 17:52:26,830 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:26,830 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 17:52:26,830 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 17:52:26,830 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 17:52:26,831 INFO L87 Difference]: Start difference. First operand 364 states and 452 transitions. Second operand 6 states. [2018-12-08 17:52:26,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:26,905 INFO L93 Difference]: Finished difference Result 926 states and 1173 transitions. [2018-12-08 17:52:26,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-08 17:52:26,905 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-08 17:52:26,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:26,908 INFO L225 Difference]: With dead ends: 926 [2018-12-08 17:52:26,908 INFO L226 Difference]: Without dead ends: 583 [2018-12-08 17:52:26,909 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-08 17:52:26,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states. [2018-12-08 17:52:26,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 570. [2018-12-08 17:52:26,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2018-12-08 17:52:26,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 714 transitions. [2018-12-08 17:52:26,934 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 714 transitions. Word has length 73 [2018-12-08 17:52:26,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:26,935 INFO L480 AbstractCegarLoop]: Abstraction has 570 states and 714 transitions. [2018-12-08 17:52:26,935 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 17:52:26,935 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 714 transitions. [2018-12-08 17:52:26,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-08 17:52:26,936 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:26,936 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:26,936 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:26,936 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:26,936 INFO L82 PathProgramCache]: Analyzing trace with hash -1577822909, now seen corresponding path program 1 times [2018-12-08 17:52:26,936 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:26,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,937 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:26,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:26,937 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:26,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:26,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:26,977 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:26,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 17:52:26,978 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:26,978 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 17:52:26,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 17:52:26,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-08 17:52:26,978 INFO L87 Difference]: Start difference. First operand 570 states and 714 transitions. Second operand 6 states. [2018-12-08 17:52:27,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:27,423 INFO L93 Difference]: Finished difference Result 1162 states and 1558 transitions. [2018-12-08 17:52:27,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-08 17:52:27,423 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 86 [2018-12-08 17:52:27,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:27,426 INFO L225 Difference]: With dead ends: 1162 [2018-12-08 17:52:27,426 INFO L226 Difference]: Without dead ends: 824 [2018-12-08 17:52:27,427 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2018-12-08 17:52:27,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 824 states. [2018-12-08 17:52:27,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 824 to 771. [2018-12-08 17:52:27,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 771 states. [2018-12-08 17:52:27,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 771 states and 1019 transitions. [2018-12-08 17:52:27,454 INFO L78 Accepts]: Start accepts. Automaton has 771 states and 1019 transitions. Word has length 86 [2018-12-08 17:52:27,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:27,454 INFO L480 AbstractCegarLoop]: Abstraction has 771 states and 1019 transitions. [2018-12-08 17:52:27,454 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 17:52:27,454 INFO L276 IsEmpty]: Start isEmpty. Operand 771 states and 1019 transitions. [2018-12-08 17:52:27,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-08 17:52:27,455 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:27,455 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:27,455 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:27,456 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:27,456 INFO L82 PathProgramCache]: Analyzing trace with hash -627422246, now seen corresponding path program 1 times [2018-12-08 17:52:27,456 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:27,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:27,457 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:27,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:27,457 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:27,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:27,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 17:52:27,531 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:27,531 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-12-08 17:52:27,531 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:27,531 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-08 17:52:27,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-08 17:52:27,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-12-08 17:52:27,532 INFO L87 Difference]: Start difference. First operand 771 states and 1019 transitions. Second operand 8 states. [2018-12-08 17:52:28,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:28,332 INFO L93 Difference]: Finished difference Result 1991 states and 2867 transitions. [2018-12-08 17:52:28,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-12-08 17:52:28,332 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 90 [2018-12-08 17:52:28,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:28,336 INFO L225 Difference]: With dead ends: 1991 [2018-12-08 17:52:28,337 INFO L226 Difference]: Without dead ends: 1466 [2018-12-08 17:52:28,338 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=138, Unknown=0, NotChecked=0, Total=182 [2018-12-08 17:52:28,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2018-12-08 17:52:28,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1355. [2018-12-08 17:52:28,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1355 states. [2018-12-08 17:52:28,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1882 transitions. [2018-12-08 17:52:28,384 INFO L78 Accepts]: Start accepts. Automaton has 1355 states and 1882 transitions. Word has length 90 [2018-12-08 17:52:28,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:28,384 INFO L480 AbstractCegarLoop]: Abstraction has 1355 states and 1882 transitions. [2018-12-08 17:52:28,384 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-08 17:52:28,384 INFO L276 IsEmpty]: Start isEmpty. Operand 1355 states and 1882 transitions. [2018-12-08 17:52:28,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-12-08 17:52:28,385 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:28,385 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:28,385 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:28,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:28,385 INFO L82 PathProgramCache]: Analyzing trace with hash 1334723078, now seen corresponding path program 1 times [2018-12-08 17:52:28,385 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:28,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:28,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:28,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:28,386 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:28,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:28,406 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-08 17:52:28,406 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:28,406 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:28,407 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 93 with the following transitions: [2018-12-08 17:52:28,408 INFO L205 CegarAbsIntRunner]: [0], [2], [7], [10], [15], [17], [47], [50], [59], [60], [75], [78], [84], [88], [89], [99], [101], [103], [104], [121], [126], [131], [132], [144], [153], [156], [159], [174], [178], [181], [193], [196], [198], [201], [217], [221], [226], [229], [242], [243], [244], [258], [260], [290], [307], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [346], [347], [348], [352], [353], [356], [357], [358], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [392], [393], [394] [2018-12-08 17:52:28,430 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:28,430 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:28,547 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-08 17:52:28,548 INFO L272 AbstractInterpreter]: Visited 63 different actions 63 times. Never merged. Never widened. Performed 523 root evaluator evaluations with a maximum evaluation depth of 3. Performed 523 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 38 variables. [2018-12-08 17:52:28,553 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:28,553 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-08 17:52:28,652 INFO L227 lantSequenceWeakener]: Weakened 71 states. On average, predicates are now at 81.91% of their original sizes. [2018-12-08 17:52:28,652 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-08 17:52:28,839 INFO L418 sIntCurrentIteration]: We unified 91 AI predicates to 91 [2018-12-08 17:52:28,839 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-08 17:52:28,840 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 17:52:28,840 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [24] imperfect sequences [3] total 25 [2018-12-08 17:52:28,840 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:28,840 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-12-08 17:52:28,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-12-08 17:52:28,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=469, Unknown=0, NotChecked=0, Total=552 [2018-12-08 17:52:28,841 INFO L87 Difference]: Start difference. First operand 1355 states and 1882 transitions. Second operand 24 states. [2018-12-08 17:52:30,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:30,274 INFO L93 Difference]: Finished difference Result 2651 states and 3713 transitions. [2018-12-08 17:52:30,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-12-08 17:52:30,275 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 92 [2018-12-08 17:52:30,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:30,278 INFO L225 Difference]: With dead ends: 2651 [2018-12-08 17:52:30,278 INFO L226 Difference]: Without dead ends: 1312 [2018-12-08 17:52:30,282 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 106 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 265 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=260, Invalid=1222, Unknown=0, NotChecked=0, Total=1482 [2018-12-08 17:52:30,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1312 states. [2018-12-08 17:52:30,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1312 to 1308. [2018-12-08 17:52:30,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1308 states. [2018-12-08 17:52:30,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1308 states to 1308 states and 1810 transitions. [2018-12-08 17:52:30,321 INFO L78 Accepts]: Start accepts. Automaton has 1308 states and 1810 transitions. Word has length 92 [2018-12-08 17:52:30,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:30,322 INFO L480 AbstractCegarLoop]: Abstraction has 1308 states and 1810 transitions. [2018-12-08 17:52:30,322 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-12-08 17:52:30,322 INFO L276 IsEmpty]: Start isEmpty. Operand 1308 states and 1810 transitions. [2018-12-08 17:52:30,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-12-08 17:52:30,323 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:30,323 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:30,323 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:30,323 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:30,323 INFO L82 PathProgramCache]: Analyzing trace with hash 872719042, now seen corresponding path program 1 times [2018-12-08 17:52:30,324 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:30,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:30,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:30,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:30,324 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:30,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:30,350 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-08 17:52:30,351 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:30,351 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:30,351 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 94 with the following transitions: [2018-12-08 17:52:30,351 INFO L205 CegarAbsIntRunner]: [0], [2], [7], [10], [15], [17], [47], [50], [59], [60], [75], [78], [84], [88], [89], [99], [101], [103], [104], [121], [126], [131], [132], [144], [153], [156], [159], [165], [171], [174], [178], [181], [193], [196], [198], [201], [217], [221], [226], [229], [242], [243], [244], [258], [260], [290], [307], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [346], [347], [348], [352], [353], [356], [357], [358], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [392], [393], [394] [2018-12-08 17:52:30,353 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:30,354 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:30,408 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-08 17:52:30,408 INFO L272 AbstractInterpreter]: Visited 75 different actions 88 times. Merged at 7 different actions 7 times. Never widened. Performed 781 root evaluator evaluations with a maximum evaluation depth of 3. Performed 781 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 39 variables. [2018-12-08 17:52:30,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:30,411 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-08 17:52:30,477 INFO L227 lantSequenceWeakener]: Weakened 86 states. On average, predicates are now at 83.08% of their original sizes. [2018-12-08 17:52:30,478 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-08 17:52:30,695 INFO L418 sIntCurrentIteration]: We unified 92 AI predicates to 92 [2018-12-08 17:52:30,696 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-08 17:52:30,696 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 17:52:30,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [3] total 32 [2018-12-08 17:52:30,696 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:30,696 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-08 17:52:30,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-08 17:52:30,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=180, Invalid=750, Unknown=0, NotChecked=0, Total=930 [2018-12-08 17:52:30,697 INFO L87 Difference]: Start difference. First operand 1308 states and 1810 transitions. Second operand 31 states. [2018-12-08 17:52:33,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:33,802 INFO L93 Difference]: Finished difference Result 2735 states and 4054 transitions. [2018-12-08 17:52:33,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-08 17:52:33,802 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 93 [2018-12-08 17:52:33,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:33,806 INFO L225 Difference]: With dead ends: 2735 [2018-12-08 17:52:33,806 INFO L226 Difference]: Without dead ends: 1708 [2018-12-08 17:52:33,809 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 128 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1351 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=720, Invalid=3702, Unknown=0, NotChecked=0, Total=4422 [2018-12-08 17:52:33,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1708 states. [2018-12-08 17:52:33,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1708 to 1633. [2018-12-08 17:52:33,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1633 states. [2018-12-08 17:52:33,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1633 states to 1633 states and 2280 transitions. [2018-12-08 17:52:33,866 INFO L78 Accepts]: Start accepts. Automaton has 1633 states and 2280 transitions. Word has length 93 [2018-12-08 17:52:33,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:33,866 INFO L480 AbstractCegarLoop]: Abstraction has 1633 states and 2280 transitions. [2018-12-08 17:52:33,866 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-08 17:52:33,866 INFO L276 IsEmpty]: Start isEmpty. Operand 1633 states and 2280 transitions. [2018-12-08 17:52:33,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-12-08 17:52:33,867 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:33,867 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:33,867 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:33,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:33,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1839079452, now seen corresponding path program 1 times [2018-12-08 17:52:33,867 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:33,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:33,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:33,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:33,868 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:33,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:33,918 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-08 17:52:33,919 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:33,919 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:33,919 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 97 with the following transitions: [2018-12-08 17:52:33,919 INFO L205 CegarAbsIntRunner]: [0], [2], [7], [10], [15], [17], [20], [36], [39], [46], [47], [50], [59], [60], [61], [64], [66], [71], [74], [75], [78], [84], [88], [89], [99], [101], [103], [104], [121], [126], [131], [132], [144], [153], [156], [159], [165], [168], [187], [243], [244], [258], [260], [290], [307], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [352], [353], [354], [355], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [392], [393], [394] [2018-12-08 17:52:33,920 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:33,920 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:33,940 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-08 17:52:33,940 INFO L272 AbstractInterpreter]: Visited 77 different actions 77 times. Never merged. Never widened. Performed 624 root evaluator evaluations with a maximum evaluation depth of 3. Performed 624 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 38 variables. [2018-12-08 17:52:33,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:33,941 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-08 17:52:33,981 INFO L227 lantSequenceWeakener]: Weakened 91 states. On average, predicates are now at 82.44% of their original sizes. [2018-12-08 17:52:33,981 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-08 17:52:34,192 INFO L418 sIntCurrentIteration]: We unified 95 AI predicates to 95 [2018-12-08 17:52:34,192 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-08 17:52:34,192 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 17:52:34,192 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [34] imperfect sequences [8] total 40 [2018-12-08 17:52:34,192 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:34,193 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-12-08 17:52:34,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-12-08 17:52:34,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=223, Invalid=899, Unknown=0, NotChecked=0, Total=1122 [2018-12-08 17:52:34,193 INFO L87 Difference]: Start difference. First operand 1633 states and 2280 transitions. Second operand 34 states. [2018-12-08 17:52:35,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:35,931 INFO L93 Difference]: Finished difference Result 3272 states and 4614 transitions. [2018-12-08 17:52:35,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-08 17:52:35,931 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 96 [2018-12-08 17:52:35,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:35,938 INFO L225 Difference]: With dead ends: 3272 [2018-12-08 17:52:35,938 INFO L226 Difference]: Without dead ends: 1735 [2018-12-08 17:52:35,944 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 116 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 797 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=551, Invalid=2419, Unknown=0, NotChecked=0, Total=2970 [2018-12-08 17:52:35,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1735 states. [2018-12-08 17:52:36,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1735 to 1724. [2018-12-08 17:52:36,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1724 states. [2018-12-08 17:52:36,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1724 states to 1724 states and 2397 transitions. [2018-12-08 17:52:36,039 INFO L78 Accepts]: Start accepts. Automaton has 1724 states and 2397 transitions. Word has length 96 [2018-12-08 17:52:36,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:36,039 INFO L480 AbstractCegarLoop]: Abstraction has 1724 states and 2397 transitions. [2018-12-08 17:52:36,039 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-12-08 17:52:36,039 INFO L276 IsEmpty]: Start isEmpty. Operand 1724 states and 2397 transitions. [2018-12-08 17:52:36,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-12-08 17:52:36,040 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:36,040 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:36,041 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:36,041 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:36,041 INFO L82 PathProgramCache]: Analyzing trace with hash 10359417, now seen corresponding path program 1 times [2018-12-08 17:52:36,041 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:36,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:36,042 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:36,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:36,042 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:36,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:36,123 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-08 17:52:36,123 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:36,123 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:36,123 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 105 with the following transitions: [2018-12-08 17:52:36,123 INFO L205 CegarAbsIntRunner]: [0], [2], [7], [10], [15], [17], [20], [36], [39], [46], [47], [50], [59], [60], [61], [64], [66], [71], [74], [75], [78], [84], [88], [89], [99], [101], [103], [104], [121], [126], [131], [132], [144], [153], [156], [159], [165], [168], [178], [181], [193], [196], [215], [240], [242], [243], [244], [258], [260], [290], [307], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [352], [353], [354], [355], [356], [357], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [392], [393], [394] [2018-12-08 17:52:36,125 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:36,125 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:36,143 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-08 17:52:36,144 INFO L272 AbstractInterpreter]: Visited 82 different actions 82 times. Never merged. Never widened. Performed 670 root evaluator evaluations with a maximum evaluation depth of 3. Performed 670 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 39 variables. [2018-12-08 17:52:36,145 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:36,145 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-08 17:52:36,216 INFO L227 lantSequenceWeakener]: Weakened 96 states. On average, predicates are now at 81.25% of their original sizes. [2018-12-08 17:52:36,216 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-08 17:52:36,472 INFO L418 sIntCurrentIteration]: We unified 103 AI predicates to 103 [2018-12-08 17:52:36,472 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-08 17:52:36,472 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 17:52:36,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [35] imperfect sequences [9] total 42 [2018-12-08 17:52:36,472 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:36,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-08 17:52:36,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-08 17:52:36,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=226, Invalid=964, Unknown=0, NotChecked=0, Total=1190 [2018-12-08 17:52:36,473 INFO L87 Difference]: Start difference. First operand 1724 states and 2397 transitions. Second operand 35 states. [2018-12-08 17:52:38,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:38,976 INFO L93 Difference]: Finished difference Result 3413 states and 4810 transitions. [2018-12-08 17:52:38,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-08 17:52:38,976 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 104 [2018-12-08 17:52:38,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:38,980 INFO L225 Difference]: With dead ends: 3413 [2018-12-08 17:52:38,981 INFO L226 Difference]: Without dead ends: 1876 [2018-12-08 17:52:38,984 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 124 GetRequests, 70 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 789 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=540, Invalid=2540, Unknown=0, NotChecked=0, Total=3080 [2018-12-08 17:52:38,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1876 states. [2018-12-08 17:52:39,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1876 to 1851. [2018-12-08 17:52:39,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1851 states. [2018-12-08 17:52:39,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1851 states to 1851 states and 2559 transitions. [2018-12-08 17:52:39,055 INFO L78 Accepts]: Start accepts. Automaton has 1851 states and 2559 transitions. Word has length 104 [2018-12-08 17:52:39,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:39,055 INFO L480 AbstractCegarLoop]: Abstraction has 1851 states and 2559 transitions. [2018-12-08 17:52:39,056 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-08 17:52:39,056 INFO L276 IsEmpty]: Start isEmpty. Operand 1851 states and 2559 transitions. [2018-12-08 17:52:39,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-08 17:52:39,057 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:39,057 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:39,057 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:39,057 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:39,057 INFO L82 PathProgramCache]: Analyzing trace with hash -368152824, now seen corresponding path program 1 times [2018-12-08 17:52:39,057 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:39,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:39,058 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:39,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:39,058 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:39,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:39,117 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 22 proven. 9 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-08 17:52:39,117 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:39,117 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:39,117 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 117 with the following transitions: [2018-12-08 17:52:39,117 INFO L205 CegarAbsIntRunner]: [0], [2], [7], [10], [15], [17], [20], [36], [39], [46], [47], [50], [59], [60], [61], [64], [66], [71], [74], [75], [78], [84], [88], [89], [99], [101], [103], [104], [121], [126], [131], [132], [144], [153], [156], [159], [165], [168], [171], [178], [181], [187], [193], [196], [217], [221], [242], [243], [244], [258], [260], [290], [307], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [352], [353], [354], [355], [356], [357], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [392], [393], [394] [2018-12-08 17:52:39,118 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:39,118 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:39,191 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-08 17:52:39,191 INFO L272 AbstractInterpreter]: Visited 90 different actions 226 times. Merged at 12 different actions 40 times. Never widened. Performed 2964 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2964 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 9 fixpoints after 4 different actions. Largest state had 39 variables. [2018-12-08 17:52:39,194 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:39,195 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-08 17:52:39,195 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:39,195 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 17:52:39,203 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:39,204 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-08 17:52:39,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:39,258 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 17:52:39,286 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-08 17:52:39,287 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-08 17:52:39,361 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-08 17:52:39,383 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-08 17:52:39,383 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [8] total 11 [2018-12-08 17:52:39,383 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:39,384 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 17:52:39,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 17:52:39,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-12-08 17:52:39,384 INFO L87 Difference]: Start difference. First operand 1851 states and 2559 transitions. Second operand 3 states. [2018-12-08 17:52:39,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:39,521 INFO L93 Difference]: Finished difference Result 4528 states and 6429 transitions. [2018-12-08 17:52:39,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 17:52:39,521 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 116 [2018-12-08 17:52:39,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:39,530 INFO L225 Difference]: With dead ends: 4528 [2018-12-08 17:52:39,530 INFO L226 Difference]: Without dead ends: 2835 [2018-12-08 17:52:39,536 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 241 GetRequests, 231 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-12-08 17:52:39,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2835 states. [2018-12-08 17:52:39,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2835 to 2825. [2018-12-08 17:52:39,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2825 states. [2018-12-08 17:52:39,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2825 states to 2825 states and 3600 transitions. [2018-12-08 17:52:39,622 INFO L78 Accepts]: Start accepts. Automaton has 2825 states and 3600 transitions. Word has length 116 [2018-12-08 17:52:39,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:39,622 INFO L480 AbstractCegarLoop]: Abstraction has 2825 states and 3600 transitions. [2018-12-08 17:52:39,622 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 17:52:39,623 INFO L276 IsEmpty]: Start isEmpty. Operand 2825 states and 3600 transitions. [2018-12-08 17:52:39,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-12-08 17:52:39,625 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:39,625 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:39,625 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:39,625 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:39,626 INFO L82 PathProgramCache]: Analyzing trace with hash 1530986996, now seen corresponding path program 1 times [2018-12-08 17:52:39,626 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:39,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:39,626 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:39,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:39,626 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:39,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:39,695 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 23 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-12-08 17:52:39,695 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:39,695 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:39,695 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 171 with the following transitions: [2018-12-08 17:52:39,695 INFO L205 CegarAbsIntRunner]: [0], [2], [5], [7], [10], [15], [17], [20], [36], [39], [46], [47], [50], [52], [55], [59], [60], [61], [64], [66], [71], [74], [75], [78], [84], [88], [89], [92], [95], [99], [101], [103], [104], [121], [126], [131], [132], [133], [135], [138], [142], [143], [144], [153], [156], [159], [161], [165], [168], [178], [184], [192], [243], [244], [258], [260], [262], [264], [269], [277], [280], [285], [290], [307], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [350], [351], [352], [353], [354], [355], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [373], [374], [375], [376], [377], [378], [379], [380], [381], [382], [383], [390], [391], [392], [393], [394] [2018-12-08 17:52:39,696 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:39,696 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:39,718 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-08 17:52:39,718 INFO L272 AbstractInterpreter]: Visited 83 different actions 98 times. Merged at 8 different actions 8 times. Never widened. Performed 812 root evaluator evaluations with a maximum evaluation depth of 3. Performed 812 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 39 variables. [2018-12-08 17:52:39,719 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:39,720 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-08 17:52:39,775 INFO L227 lantSequenceWeakener]: Weakened 106 states. On average, predicates are now at 78.79% of their original sizes. [2018-12-08 17:52:39,776 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-08 17:52:40,079 INFO L418 sIntCurrentIteration]: We unified 169 AI predicates to 169 [2018-12-08 17:52:40,079 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-08 17:52:40,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 17:52:40,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [41] imperfect sequences [10] total 49 [2018-12-08 17:52:40,079 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:40,079 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-08 17:52:40,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-08 17:52:40,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=1386, Unknown=0, NotChecked=0, Total=1640 [2018-12-08 17:52:40,080 INFO L87 Difference]: Start difference. First operand 2825 states and 3600 transitions. Second operand 41 states. [2018-12-08 17:52:42,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:42,763 INFO L93 Difference]: Finished difference Result 5637 states and 7174 transitions. [2018-12-08 17:52:42,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-12-08 17:52:42,764 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 170 [2018-12-08 17:52:42,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:42,770 INFO L225 Difference]: With dead ends: 5637 [2018-12-08 17:52:42,770 INFO L226 Difference]: Without dead ends: 2926 [2018-12-08 17:52:42,774 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 200 GetRequests, 130 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1558 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=801, Invalid=4311, Unknown=0, NotChecked=0, Total=5112 [2018-12-08 17:52:42,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2926 states. [2018-12-08 17:52:42,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2926 to 2901. [2018-12-08 17:52:42,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2901 states. [2018-12-08 17:52:42,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2901 states to 2901 states and 3646 transitions. [2018-12-08 17:52:42,856 INFO L78 Accepts]: Start accepts. Automaton has 2901 states and 3646 transitions. Word has length 170 [2018-12-08 17:52:42,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:42,857 INFO L480 AbstractCegarLoop]: Abstraction has 2901 states and 3646 transitions. [2018-12-08 17:52:42,857 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-08 17:52:42,857 INFO L276 IsEmpty]: Start isEmpty. Operand 2901 states and 3646 transitions. [2018-12-08 17:52:42,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-12-08 17:52:42,859 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:42,859 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:42,859 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:42,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:42,859 INFO L82 PathProgramCache]: Analyzing trace with hash -1748206503, now seen corresponding path program 1 times [2018-12-08 17:52:42,859 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:42,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:42,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:42,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:42,860 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:42,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:42,895 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 115 trivial. 0 not checked. [2018-12-08 17:52:42,895 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:42,895 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 17:52:42,895 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:42,895 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 17:52:42,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 17:52:42,895 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:42,896 INFO L87 Difference]: Start difference. First operand 2901 states and 3646 transitions. Second operand 4 states. [2018-12-08 17:52:43,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:43,013 INFO L93 Difference]: Finished difference Result 4917 states and 6241 transitions. [2018-12-08 17:52:43,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 17:52:43,014 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 186 [2018-12-08 17:52:43,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:43,020 INFO L225 Difference]: With dead ends: 4917 [2018-12-08 17:52:43,020 INFO L226 Difference]: Without dead ends: 2475 [2018-12-08 17:52:43,024 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:43,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2475 states. [2018-12-08 17:52:43,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2475 to 2475. [2018-12-08 17:52:43,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2475 states. [2018-12-08 17:52:43,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2475 states to 2475 states and 3096 transitions. [2018-12-08 17:52:43,092 INFO L78 Accepts]: Start accepts. Automaton has 2475 states and 3096 transitions. Word has length 186 [2018-12-08 17:52:43,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:43,092 INFO L480 AbstractCegarLoop]: Abstraction has 2475 states and 3096 transitions. [2018-12-08 17:52:43,092 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 17:52:43,092 INFO L276 IsEmpty]: Start isEmpty. Operand 2475 states and 3096 transitions. [2018-12-08 17:52:43,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-12-08 17:52:43,094 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:43,094 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:43,095 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:43,095 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:43,095 INFO L82 PathProgramCache]: Analyzing trace with hash -524905367, now seen corresponding path program 1 times [2018-12-08 17:52:43,095 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:43,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:43,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:43,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:43,095 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:43,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:43,172 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 32 proven. 40 refuted. 0 times theorem prover too weak. 116 trivial. 0 not checked. [2018-12-08 17:52:43,172 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:43,173 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:43,173 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 225 with the following transitions: [2018-12-08 17:52:43,173 INFO L205 CegarAbsIntRunner]: [0], [2], [5], [7], [10], [15], [17], [20], [36], [39], [46], [47], [50], [52], [55], [59], [60], [61], [64], [66], [71], [74], [75], [78], [84], [88], [89], [92], [95], [99], [101], [103], [104], [121], [126], [129], [130], [131], [132], [133], [135], [138], [142], [143], [144], [153], [156], [159], [161], [165], [168], [171], [178], [181], [187], [192], [193], [196], [217], [221], [242], [243], [244], [258], [260], [262], [264], [269], [272], [280], [285], [290], [296], [304], [306], [307], [310], [315], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [350], [351], [352], [353], [354], [355], [356], [357], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [373], [374], [375], [376], [377], [378], [379], [380], [381], [382], [383], [384], [385], [386], [387], [388], [389], [390], [391], [392], [393], [394] [2018-12-08 17:52:43,174 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:43,174 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:43,243 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-08 17:52:43,243 INFO L272 AbstractInterpreter]: Visited 96 different actions 241 times. Merged at 12 different actions 40 times. Never widened. Performed 2991 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2991 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 9 fixpoints after 4 different actions. Largest state had 39 variables. [2018-12-08 17:52:43,244 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:43,244 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-08 17:52:43,245 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:43,245 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 17:52:43,253 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:43,253 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-08 17:52:43,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:43,320 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 17:52:43,378 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 136 proven. 0 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-08 17:52:43,379 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-08 17:52:43,495 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 43 proven. 9 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-12-08 17:52:43,520 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-08 17:52:43,520 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [9, 4] total 12 [2018-12-08 17:52:43,520 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:43,521 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 17:52:43,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 17:52:43,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2018-12-08 17:52:43,521 INFO L87 Difference]: Start difference. First operand 2475 states and 3096 transitions. Second operand 3 states. [2018-12-08 17:52:43,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:43,597 INFO L93 Difference]: Finished difference Result 5556 states and 7164 transitions. [2018-12-08 17:52:43,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 17:52:43,598 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 224 [2018-12-08 17:52:43,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:43,604 INFO L225 Difference]: With dead ends: 5556 [2018-12-08 17:52:43,604 INFO L226 Difference]: Without dead ends: 3221 [2018-12-08 17:52:43,609 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 458 GetRequests, 447 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2018-12-08 17:52:43,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3221 states. [2018-12-08 17:52:43,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3221 to 3213. [2018-12-08 17:52:43,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3213 states. [2018-12-08 17:52:43,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3213 states to 3213 states and 3912 transitions. [2018-12-08 17:52:43,691 INFO L78 Accepts]: Start accepts. Automaton has 3213 states and 3912 transitions. Word has length 224 [2018-12-08 17:52:43,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:43,691 INFO L480 AbstractCegarLoop]: Abstraction has 3213 states and 3912 transitions. [2018-12-08 17:52:43,691 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 17:52:43,692 INFO L276 IsEmpty]: Start isEmpty. Operand 3213 states and 3912 transitions. [2018-12-08 17:52:43,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-12-08 17:52:43,695 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:43,696 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:43,696 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:43,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:43,696 INFO L82 PathProgramCache]: Analyzing trace with hash 1261166181, now seen corresponding path program 1 times [2018-12-08 17:52:43,696 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:43,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:43,697 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:43,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:43,697 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:43,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:43,757 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 46 proven. 10 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-12-08 17:52:43,757 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:43,757 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:43,757 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 225 with the following transitions: [2018-12-08 17:52:43,757 INFO L205 CegarAbsIntRunner]: [0], [2], [5], [7], [10], [15], [17], [20], [36], [39], [46], [47], [50], [52], [57], [59], [60], [61], [64], [66], [71], [74], [75], [78], [84], [88], [89], [92], [95], [99], [101], [103], [104], [121], [126], [129], [130], [131], [132], [133], [135], [138], [142], [143], [144], [153], [156], [159], [161], [165], [168], [171], [178], [181], [187], [192], [193], [196], [217], [221], [242], [243], [244], [258], [260], [262], [264], [269], [272], [280], [285], [290], [296], [304], [306], [307], [310], [315], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [350], [351], [352], [353], [354], [355], [356], [357], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [373], [374], [375], [376], [377], [378], [379], [380], [381], [382], [383], [384], [385], [386], [387], [388], [389], [390], [391], [392], [393], [394] [2018-12-08 17:52:43,759 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:43,759 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:43,855 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-08 17:52:43,855 INFO L272 AbstractInterpreter]: Visited 123 different actions 346 times. Merged at 28 different actions 57 times. Never widened. Performed 3796 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3796 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 14 fixpoints after 7 different actions. Largest state had 39 variables. [2018-12-08 17:52:43,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:43,858 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-08 17:52:43,859 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:43,859 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 17:52:43,867 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:43,867 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-08 17:52:43,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:43,929 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 17:52:43,957 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 144 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-12-08 17:52:43,957 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-08 17:52:44,064 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 46 proven. 10 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-12-08 17:52:44,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-08 17:52:44,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 4 [2018-12-08 17:52:44,079 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:44,080 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 17:52:44,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 17:52:44,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:44,080 INFO L87 Difference]: Start difference. First operand 3213 states and 3912 transitions. Second operand 3 states. [2018-12-08 17:52:44,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:44,190 INFO L93 Difference]: Finished difference Result 6422 states and 8027 transitions. [2018-12-08 17:52:44,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 17:52:44,190 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 224 [2018-12-08 17:52:44,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:44,198 INFO L225 Difference]: With dead ends: 6422 [2018-12-08 17:52:44,198 INFO L226 Difference]: Without dead ends: 3365 [2018-12-08 17:52:44,203 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 444 SyntacticMatches, 5 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 17:52:44,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3365 states. [2018-12-08 17:52:44,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3365 to 3359. [2018-12-08 17:52:44,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3359 states. [2018-12-08 17:52:44,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3359 states to 3359 states and 4026 transitions. [2018-12-08 17:52:44,305 INFO L78 Accepts]: Start accepts. Automaton has 3359 states and 4026 transitions. Word has length 224 [2018-12-08 17:52:44,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:44,305 INFO L480 AbstractCegarLoop]: Abstraction has 3359 states and 4026 transitions. [2018-12-08 17:52:44,305 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 17:52:44,306 INFO L276 IsEmpty]: Start isEmpty. Operand 3359 states and 4026 transitions. [2018-12-08 17:52:44,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-12-08 17:52:44,309 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:44,309 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:44,309 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:44,310 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:44,310 INFO L82 PathProgramCache]: Analyzing trace with hash 2068698656, now seen corresponding path program 1 times [2018-12-08 17:52:44,310 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:44,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:44,311 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:44,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:44,311 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:44,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:44,379 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 163 trivial. 0 not checked. [2018-12-08 17:52:44,379 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:44,379 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 17:52:44,379 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:44,379 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 17:52:44,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 17:52:44,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 17:52:44,380 INFO L87 Difference]: Start difference. First operand 3359 states and 4026 transitions. Second operand 5 states. [2018-12-08 17:52:44,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:44,924 INFO L93 Difference]: Finished difference Result 9912 states and 12797 transitions. [2018-12-08 17:52:44,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-08 17:52:44,924 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 226 [2018-12-08 17:52:44,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:44,943 INFO L225 Difference]: With dead ends: 9912 [2018-12-08 17:52:44,943 INFO L226 Difference]: Without dead ends: 6846 [2018-12-08 17:52:44,950 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-08 17:52:44,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6846 states. [2018-12-08 17:52:45,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6846 to 5791. [2018-12-08 17:52:45,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5791 states. [2018-12-08 17:52:45,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5791 states to 5791 states and 6943 transitions. [2018-12-08 17:52:45,130 INFO L78 Accepts]: Start accepts. Automaton has 5791 states and 6943 transitions. Word has length 226 [2018-12-08 17:52:45,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:45,131 INFO L480 AbstractCegarLoop]: Abstraction has 5791 states and 6943 transitions. [2018-12-08 17:52:45,131 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 17:52:45,131 INFO L276 IsEmpty]: Start isEmpty. Operand 5791 states and 6943 transitions. [2018-12-08 17:52:45,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-12-08 17:52:45,133 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:45,133 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:45,133 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:45,133 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:45,133 INFO L82 PathProgramCache]: Analyzing trace with hash -1328875362, now seen corresponding path program 1 times [2018-12-08 17:52:45,133 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:45,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:45,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:45,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:45,134 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:45,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:45,308 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 6 proven. 68 refuted. 0 times theorem prover too weak. 115 trivial. 0 not checked. [2018-12-08 17:52:45,308 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:45,308 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:45,308 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 227 with the following transitions: [2018-12-08 17:52:45,308 INFO L205 CegarAbsIntRunner]: [0], [2], [5], [7], [10], [15], [17], [20], [22], [25], [36], [39], [46], [47], [50], [52], [57], [59], [60], [61], [64], [66], [71], [74], [75], [78], [84], [88], [89], [92], [95], [97], [99], [101], [103], [104], [121], [126], [129], [130], [131], [132], [133], [135], [138], [142], [143], [144], [153], [156], [159], [161], [165], [168], [171], [178], [181], [187], [192], [193], [196], [217], [221], [242], [243], [244], [258], [260], [262], [264], [269], [272], [280], [285], [290], [296], [302], [306], [307], [310], [315], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [350], [351], [352], [353], [354], [355], [356], [357], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [373], [374], [375], [376], [377], [378], [379], [380], [381], [382], [383], [384], [385], [386], [387], [388], [389], [390], [391], [392], [393], [394] [2018-12-08 17:52:45,309 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:45,309 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:45,606 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-08 17:52:45,606 INFO L272 AbstractInterpreter]: Visited 139 different actions 874 times. Merged at 53 different actions 186 times. Never widened. Performed 11021 root evaluator evaluations with a maximum evaluation depth of 3. Performed 11021 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 50 fixpoints after 12 different actions. Largest state had 39 variables. [2018-12-08 17:52:45,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:45,611 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-08 17:52:45,611 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:45,611 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 17:52:45,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:45,620 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-08 17:52:45,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:45,678 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 17:52:45,771 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 97 proven. 34 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-12-08 17:52:45,772 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-08 17:52:45,933 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 152 trivial. 0 not checked. [2018-12-08 17:52:45,950 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-08 17:52:45,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 8, 8] total 17 [2018-12-08 17:52:45,951 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-08 17:52:45,951 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-08 17:52:45,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-08 17:52:45,951 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=230, Unknown=0, NotChecked=0, Total=272 [2018-12-08 17:52:45,951 INFO L87 Difference]: Start difference. First operand 5791 states and 6943 transitions. Second operand 15 states. [2018-12-08 17:52:47,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:47,920 INFO L93 Difference]: Finished difference Result 11194 states and 13811 transitions. [2018-12-08 17:52:47,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-08 17:52:47,920 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 226 [2018-12-08 17:52:47,921 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:47,934 INFO L225 Difference]: With dead ends: 11194 [2018-12-08 17:52:47,934 INFO L226 Difference]: Without dead ends: 6172 [2018-12-08 17:52:47,940 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 521 GetRequests, 468 SyntacticMatches, 10 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 467 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=1659, Unknown=0, NotChecked=0, Total=1980 [2018-12-08 17:52:47,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6172 states. [2018-12-08 17:52:48,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6172 to 6018. [2018-12-08 17:52:48,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6018 states. [2018-12-08 17:52:48,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6018 states to 6018 states and 7151 transitions. [2018-12-08 17:52:48,133 INFO L78 Accepts]: Start accepts. Automaton has 6018 states and 7151 transitions. Word has length 226 [2018-12-08 17:52:48,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:48,133 INFO L480 AbstractCegarLoop]: Abstraction has 6018 states and 7151 transitions. [2018-12-08 17:52:48,133 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-08 17:52:48,133 INFO L276 IsEmpty]: Start isEmpty. Operand 6018 states and 7151 transitions. [2018-12-08 17:52:48,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 326 [2018-12-08 17:52:48,137 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:48,138 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 7, 6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:48,138 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:48,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:48,138 INFO L82 PathProgramCache]: Analyzing trace with hash -275713700, now seen corresponding path program 1 times [2018-12-08 17:52:48,138 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:48,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:48,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:48,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:48,139 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:48,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:48,227 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 103 proven. 43 refuted. 0 times theorem prover too weak. 366 trivial. 0 not checked. [2018-12-08 17:52:48,227 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:48,227 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-08 17:52:48,228 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 326 with the following transitions: [2018-12-08 17:52:48,228 INFO L205 CegarAbsIntRunner]: [0], [2], [5], [7], [10], [15], [17], [20], [22], [25], [36], [39], [46], [47], [50], [52], [57], [59], [60], [61], [64], [66], [69], [71], [74], [75], [78], [84], [88], [89], [92], [95], [97], [99], [101], [103], [104], [121], [126], [129], [130], [131], [132], [133], [135], [138], [142], [143], [144], [153], [156], [159], [161], [165], [168], [171], [178], [181], [187], [192], [193], [196], [217], [221], [242], [243], [244], [258], [260], [262], [264], [269], [272], [277], [280], [285], [290], [296], [302], [306], [307], [310], [315], [317], [328], [330], [332], [333], [334], [335], [336], [337], [338], [339], [340], [341], [342], [346], [347], [348], [350], [351], [352], [353], [354], [355], [356], [357], [362], [363], [364], [365], [366], [367], [368], [369], [370], [371], [372], [373], [374], [375], [376], [377], [378], [379], [380], [381], [382], [383], [384], [385], [386], [387], [388], [389], [390], [391], [392], [393], [394] [2018-12-08 17:52:48,229 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-08 17:52:48,229 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-08 17:52:48,922 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-08 17:52:48,922 INFO L272 AbstractInterpreter]: Visited 141 different actions 2244 times. Merged at 59 different actions 673 times. Widened at 2 different actions 2 times. Performed 26149 root evaluator evaluations with a maximum evaluation depth of 3. Performed 26149 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 182 fixpoints after 20 different actions. Largest state had 39 variables. [2018-12-08 17:52:48,924 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:48,924 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-08 17:52:48,924 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 17:52:48,924 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 17:52:48,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:48,930 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-08 17:52:48,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:48,990 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 17:52:49,025 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 360 proven. 0 refuted. 0 times theorem prover too weak. 152 trivial. 0 not checked. [2018-12-08 17:52:49,025 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-08 17:52:49,146 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 419 trivial. 0 not checked. [2018-12-08 17:52:49,161 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-08 17:52:49,161 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [7] total 9 [2018-12-08 17:52:49,161 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:49,161 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 17:52:49,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 17:52:49,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-12-08 17:52:49,162 INFO L87 Difference]: Start difference. First operand 6018 states and 7151 transitions. Second operand 3 states. [2018-12-08 17:52:49,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:49,431 INFO L93 Difference]: Finished difference Result 15726 states and 18937 transitions. [2018-12-08 17:52:49,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 17:52:49,431 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 325 [2018-12-08 17:52:49,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:49,451 INFO L225 Difference]: With dead ends: 15726 [2018-12-08 17:52:49,452 INFO L226 Difference]: Without dead ends: 10493 [2018-12-08 17:52:49,459 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 657 GetRequests, 646 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-12-08 17:52:49,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10493 states. [2018-12-08 17:52:49,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10493 to 10430. [2018-12-08 17:52:49,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10430 states. [2018-12-08 17:52:49,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10430 states to 10430 states and 12338 transitions. [2018-12-08 17:52:49,808 INFO L78 Accepts]: Start accepts. Automaton has 10430 states and 12338 transitions. Word has length 325 [2018-12-08 17:52:49,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:49,808 INFO L480 AbstractCegarLoop]: Abstraction has 10430 states and 12338 transitions. [2018-12-08 17:52:49,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 17:52:49,808 INFO L276 IsEmpty]: Start isEmpty. Operand 10430 states and 12338 transitions. [2018-12-08 17:52:49,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 326 [2018-12-08 17:52:49,814 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:49,814 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 7, 6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:49,814 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:49,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:49,815 INFO L82 PathProgramCache]: Analyzing trace with hash 150840798, now seen corresponding path program 1 times [2018-12-08 17:52:49,815 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:49,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:49,815 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:49,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:49,815 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:49,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 17:52:49,875 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 57 proven. 0 refuted. 0 times theorem prover too weak. 455 trivial. 0 not checked. [2018-12-08 17:52:49,875 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 17:52:49,875 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 17:52:49,875 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-08 17:52:49,876 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 17:52:49,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 17:52:49,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 17:52:49,876 INFO L87 Difference]: Start difference. First operand 10430 states and 12338 transitions. Second operand 5 states. [2018-12-08 17:52:50,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 17:52:50,362 INFO L93 Difference]: Finished difference Result 15835 states and 18824 transitions. [2018-12-08 17:52:50,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-08 17:52:50,362 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 325 [2018-12-08 17:52:50,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 17:52:50,376 INFO L225 Difference]: With dead ends: 15835 [2018-12-08 17:52:50,376 INFO L226 Difference]: Without dead ends: 6091 [2018-12-08 17:52:50,385 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-08 17:52:50,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6091 states. [2018-12-08 17:52:50,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6091 to 5949. [2018-12-08 17:52:50,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5949 states. [2018-12-08 17:52:50,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5949 states to 5949 states and 6875 transitions. [2018-12-08 17:52:50,575 INFO L78 Accepts]: Start accepts. Automaton has 5949 states and 6875 transitions. Word has length 325 [2018-12-08 17:52:50,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 17:52:50,575 INFO L480 AbstractCegarLoop]: Abstraction has 5949 states and 6875 transitions. [2018-12-08 17:52:50,575 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 17:52:50,575 INFO L276 IsEmpty]: Start isEmpty. Operand 5949 states and 6875 transitions. [2018-12-08 17:52:50,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-12-08 17:52:50,579 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 17:52:50,579 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 17:52:50,579 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 17:52:50,579 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 17:52:50,579 INFO L82 PathProgramCache]: Analyzing trace with hash -1394352896, now seen corresponding path program 1 times [2018-12-08 17:52:50,579 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-08 17:52:50,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:50,580 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 17:52:50,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 17:52:50,580 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-08 17:52:50,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 17:52:50,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 17:52:50,668 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-08 17:52:50,769 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 08.12 05:52:50 BoogieIcfgContainer [2018-12-08 17:52:50,769 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-08 17:52:50,769 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-08 17:52:50,769 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-08 17:52:50,769 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-08 17:52:50,770 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 05:52:25" (3/4) ... [2018-12-08 17:52:50,771 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-08 17:52:50,865 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_8b42f51a-6fb9-4eeb-83cb-40a6b94723c6/bin-2019/utaipan/witness.graphml [2018-12-08 17:52:50,865 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-08 17:52:50,866 INFO L168 Benchmark]: Toolchain (without parser) took 25681.45 ms. Allocated memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: 900.2 MB). Free memory was 962.4 MB in the beginning and 875.3 MB in the end (delta: 87.2 MB). Peak memory consumption was 987.4 MB. Max. memory is 11.5 GB. [2018-12-08 17:52:50,867 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 982.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-08 17:52:50,867 INFO L168 Benchmark]: CACSL2BoogieTranslator took 157.73 ms. Allocated memory is still 1.0 GB. Free memory was 962.4 MB in the beginning and 946.3 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-08 17:52:50,867 INFO L168 Benchmark]: Boogie Procedure Inliner took 13.55 ms. Allocated memory is still 1.0 GB. Free memory is still 946.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-08 17:52:50,867 INFO L168 Benchmark]: Boogie Preprocessor took 49.30 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 95.4 MB). Free memory was 946.3 MB in the beginning and 1.1 GB in the end (delta: -144.3 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. [2018-12-08 17:52:50,867 INFO L168 Benchmark]: RCFGBuilder took 270.43 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 30.5 MB). Peak memory consumption was 30.5 MB. Max. memory is 11.5 GB. [2018-12-08 17:52:50,868 INFO L168 Benchmark]: TraceAbstraction took 25091.05 ms. Allocated memory was 1.1 GB in the beginning and 1.9 GB in the end (delta: 804.8 MB). Free memory was 1.1 GB in the beginning and 896.0 MB in the end (delta: 164.2 MB). Peak memory consumption was 969.0 MB. Max. memory is 11.5 GB. [2018-12-08 17:52:50,868 INFO L168 Benchmark]: Witness Printer took 96.23 ms. Allocated memory is still 1.9 GB. Free memory was 896.0 MB in the beginning and 875.3 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 11.5 GB. [2018-12-08 17:52:50,869 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 982.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 157.73 ms. Allocated memory is still 1.0 GB. Free memory was 962.4 MB in the beginning and 946.3 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 13.55 ms. Allocated memory is still 1.0 GB. Free memory is still 946.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 49.30 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 95.4 MB). Free memory was 946.3 MB in the beginning and 1.1 GB in the end (delta: -144.3 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 270.43 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 30.5 MB). Peak memory consumption was 30.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 25091.05 ms. Allocated memory was 1.1 GB in the beginning and 1.9 GB in the end (delta: 804.8 MB). Free memory was 1.1 GB in the beginning and 896.0 MB in the end (delta: 164.2 MB). Peak memory consumption was 969.0 MB. Max. memory is 11.5 GB. * Witness Printer took 96.23 ms. Allocated memory is still 1.9 GB. Free memory was 896.0 MB in the beginning and 875.3 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [\old(C_1_ev)=76, \old(C_1_i)=68, \old(C_1_pc)=81, \old(C_1_pr)=78, \old(C_1_st)=80, \old(data_0)=74, \old(data_1)=67, \old(e)=66, \old(i)=70, \old(max_loop)=79, \old(num)=69, \old(P_1_ev)=71, \old(P_1_i)=77, \old(P_1_pc)=72, \old(P_1_st)=75, \old(timer)=73, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L504] CALL init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L504] RET init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L505] CALL start_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L428] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] CALL init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] RET init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L430] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L431] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_P_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_C_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=0] [L431] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L432] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___2=1] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=1, tmp___2=1] [L301] CALL C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L128] char c ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L301] RET C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, c=65, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0, tmp___0=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L56] CALL error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 22 procedures, 150 locations, 1 error locations. UNSAFE Result, 25.0s OverallTime, 22 OverallIterations, 10 TraceHistogramMax, 17.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5423 SDtfs, 7446 SDslu, 15561 SDs, 0 SdLazy, 10454 SolverSat, 2728 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.4s Time, PredicateUnifierStatistics: 10 DeclaredPredicates, 3105 GetRequests, 2675 SyntacticMatches, 24 SemanticMatches, 406 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5279 ImplicationChecksByTransitivity, 3.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=10430occurred in iteration=20, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 1.5s AbstIntTime, 10 AbstIntIterations, 5 AbstIntStrong, 0.9841293955598787 AbsIntWeakeningRatio, 0.7381818181818182 AbsIntAvgWeakeningVarsNumRemoved, 18.85090909090909 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.7s AutomataMinimizationTime, 21 MinimizatonAttempts, 1805 StatesRemovedByMinimization, 19 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.8s InterpolantComputationTime, 4494 NumberOfCodeBlocks, 4494 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 5218 ConstructedInterpolants, 0 QuantifiedInterpolants, 1782639 SizeOfPredicates, 5 NumberOfNonLiveVariables, 4329 ConjunctsInSsa, 30 ConjunctsInUnsatCore, 31 InterpolantComputations, 17 PerfectInterpolantSequences, 4093/4363 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...