./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c8989412e094655bcf4508d76eb9764ed06d0b34 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 19:38:03,332 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 19:38:03,333 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 19:38:03,339 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 19:38:03,339 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 19:38:03,340 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 19:38:03,341 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 19:38:03,341 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 19:38:03,342 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 19:38:03,343 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 19:38:03,343 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 19:38:03,343 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 19:38:03,344 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 19:38:03,344 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 19:38:03,345 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 19:38:03,345 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 19:38:03,346 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 19:38:03,346 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 19:38:03,347 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 19:38:03,348 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 19:38:03,349 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 19:38:03,349 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 19:38:03,350 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 19:38:03,350 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 19:38:03,351 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 19:38:03,351 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 19:38:03,352 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 19:38:03,352 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 19:38:03,353 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 19:38:03,353 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 19:38:03,353 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 19:38:03,354 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 19:38:03,354 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 19:38:03,354 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 19:38:03,354 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 19:38:03,355 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 19:38:03,355 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-12-09 19:38:03,362 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 19:38:03,362 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 19:38:03,363 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 19:38:03,363 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 19:38:03,363 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-09 19:38:03,363 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-09 19:38:03,363 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-09 19:38:03,363 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-09 19:38:03,363 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-09 19:38:03,363 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-09 19:38:03,364 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-09 19:38:03,364 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-09 19:38:03,364 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-09 19:38:03,364 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 19:38:03,364 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-09 19:38:03,364 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-09 19:38:03,365 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-09 19:38:03,365 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 19:38:03,366 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-09 19:38:03,366 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 19:38:03,367 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-09 19:38:03,367 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-09 19:38:03,367 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c8989412e094655bcf4508d76eb9764ed06d0b34 [2018-12-09 19:38:03,384 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 19:38:03,391 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 19:38:03,393 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 19:38:03,394 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 19:38:03,394 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 19:38:03,395 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c [2018-12-09 19:38:03,442 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/data/16821ae31/3c0c3c637ba24e23a32af275821b21f7/FLAGb44718c32 [2018-12-09 19:38:03,889 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 19:38:03,889 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c [2018-12-09 19:38:03,897 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/data/16821ae31/3c0c3c637ba24e23a32af275821b21f7/FLAGb44718c32 [2018-12-09 19:38:03,906 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/data/16821ae31/3c0c3c637ba24e23a32af275821b21f7 [2018-12-09 19:38:03,909 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 19:38:03,910 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-09 19:38:03,910 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 19:38:03,911 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 19:38:03,913 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 19:38:03,914 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 07:38:03" (1/1) ... [2018-12-09 19:38:03,916 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6a8209d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:03, skipping insertion in model container [2018-12-09 19:38:03,917 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 07:38:03" (1/1) ... [2018-12-09 19:38:03,922 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 19:38:03,947 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 19:38:04,067 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 19:38:04,070 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 19:38:04,099 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 19:38:04,109 INFO L195 MainTranslator]: Completed translation [2018-12-09 19:38:04,110 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04 WrapperNode [2018-12-09 19:38:04,110 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 19:38:04,110 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-09 19:38:04,110 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-09 19:38:04,111 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-09 19:38:04,146 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,150 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,154 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-09 19:38:04,155 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 19:38:04,155 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 19:38:04,155 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 19:38:04,161 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,161 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,162 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,162 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,167 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,174 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,175 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... [2018-12-09 19:38:04,177 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 19:38:04,177 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 19:38:04,177 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 19:38:04,178 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 19:38:04,178 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 19:38:04,208 INFO L130 BoogieDeclarations]: Found specification of procedure read [2018-12-09 19:38:04,208 INFO L138 BoogieDeclarations]: Found implementation of procedure read [2018-12-09 19:38:04,209 INFO L130 BoogieDeclarations]: Found specification of procedure write_back [2018-12-09 19:38:04,209 INFO L138 BoogieDeclarations]: Found implementation of procedure write_back [2018-12-09 19:38:04,209 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 19:38:04,209 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 19:38:04,209 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-09 19:38:04,209 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-09 19:38:04,209 INFO L130 BoogieDeclarations]: Found specification of procedure compute2 [2018-12-09 19:38:04,209 INFO L138 BoogieDeclarations]: Found implementation of procedure compute2 [2018-12-09 19:38:04,209 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 19:38:04,209 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 19:38:04,209 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-09 19:38:04,209 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-09 19:38:04,209 INFO L130 BoogieDeclarations]: Found specification of procedure compute1 [2018-12-09 19:38:04,209 INFO L138 BoogieDeclarations]: Found implementation of procedure compute1 [2018-12-09 19:38:04,210 INFO L130 BoogieDeclarations]: Found specification of procedure write_loop [2018-12-09 19:38:04,210 INFO L138 BoogieDeclarations]: Found implementation of procedure write_loop [2018-12-09 19:38:04,210 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-09 19:38:04,210 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-09 19:38:04,210 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 19:38:04,210 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 19:38:04,493 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 19:38:04,493 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-12-09 19:38:04,493 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 07:38:04 BoogieIcfgContainer [2018-12-09 19:38:04,493 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 19:38:04,494 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 19:38:04,494 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 19:38:04,495 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 19:38:04,496 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 07:38:03" (1/3) ... [2018-12-09 19:38:04,496 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@495c909f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 07:38:04, skipping insertion in model container [2018-12-09 19:38:04,496 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 07:38:04" (2/3) ... [2018-12-09 19:38:04,497 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@495c909f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 07:38:04, skipping insertion in model container [2018-12-09 19:38:04,497 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 07:38:04" (3/3) ... [2018-12-09 19:38:04,498 INFO L112 eAbstractionObserver]: Analyzing ICFG toy2_false-unreach-call_false-termination.cil.c [2018-12-09 19:38:04,503 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 19:38:04,508 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-09 19:38:04,517 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-09 19:38:04,538 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 19:38:04,538 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-09 19:38:04,538 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 19:38:04,538 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 19:38:04,538 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 19:38:04,538 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 19:38:04,538 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 19:38:04,538 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 19:38:04,552 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states. [2018-12-09 19:38:04,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:04,556 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:04,557 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:04,558 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:04,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:04,561 INFO L82 PathProgramCache]: Analyzing trace with hash 1787110337, now seen corresponding path program 1 times [2018-12-09 19:38:04,562 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:04,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:04,589 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:04,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:04,590 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:04,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:04,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:04,694 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:04,694 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:04,694 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:04,698 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:04,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:04,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:04,709 INFO L87 Difference]: Start difference. First operand 158 states. Second operand 3 states. [2018-12-09 19:38:04,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:04,741 INFO L93 Difference]: Finished difference Result 298 states and 509 transitions. [2018-12-09 19:38:04,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:04,742 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2018-12-09 19:38:04,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:04,751 INFO L225 Difference]: With dead ends: 298 [2018-12-09 19:38:04,751 INFO L226 Difference]: Without dead ends: 149 [2018-12-09 19:38:04,754 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:04,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-12-09 19:38:04,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-12-09 19:38:04,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-12-09 19:38:04,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 241 transitions. [2018-12-09 19:38:04,781 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 241 transitions. Word has length 46 [2018-12-09 19:38:04,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:04,782 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 241 transitions. [2018-12-09 19:38:04,782 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:04,782 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 241 transitions. [2018-12-09 19:38:04,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:04,783 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:04,783 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:04,783 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:04,783 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:04,783 INFO L82 PathProgramCache]: Analyzing trace with hash 1714723779, now seen corresponding path program 1 times [2018-12-09 19:38:04,783 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:04,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:04,784 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:04,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:04,784 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:04,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:04,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:04,837 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:04,837 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:04,837 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:04,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:04,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:04,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:04,838 INFO L87 Difference]: Start difference. First operand 149 states and 241 transitions. Second operand 3 states. [2018-12-09 19:38:04,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:04,868 INFO L93 Difference]: Finished difference Result 281 states and 458 transitions. [2018-12-09 19:38:04,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:04,868 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2018-12-09 19:38:04,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:04,869 INFO L225 Difference]: With dead ends: 281 [2018-12-09 19:38:04,869 INFO L226 Difference]: Without dead ends: 149 [2018-12-09 19:38:04,870 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:04,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-12-09 19:38:04,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-12-09 19:38:04,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-12-09 19:38:04,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 233 transitions. [2018-12-09 19:38:04,878 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 233 transitions. Word has length 46 [2018-12-09 19:38:04,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:04,878 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 233 transitions. [2018-12-09 19:38:04,878 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:04,878 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 233 transitions. [2018-12-09 19:38:04,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:04,879 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:04,879 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:04,879 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:04,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:04,879 INFO L82 PathProgramCache]: Analyzing trace with hash 1171834943, now seen corresponding path program 1 times [2018-12-09 19:38:04,879 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:04,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:04,880 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:04,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:04,880 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:04,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:04,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:04,924 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:04,924 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:04,924 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:04,924 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:04,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:04,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:04,925 INFO L87 Difference]: Start difference. First operand 149 states and 233 transitions. Second operand 4 states. [2018-12-09 19:38:05,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:05,049 INFO L93 Difference]: Finished difference Result 383 states and 603 transitions. [2018-12-09 19:38:05,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:38:05,049 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-12-09 19:38:05,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:05,051 INFO L225 Difference]: With dead ends: 383 [2018-12-09 19:38:05,052 INFO L226 Difference]: Without dead ends: 252 [2018-12-09 19:38:05,053 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:05,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-12-09 19:38:05,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 149. [2018-12-09 19:38:05,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-12-09 19:38:05,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 231 transitions. [2018-12-09 19:38:05,071 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 231 transitions. Word has length 46 [2018-12-09 19:38:05,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:05,071 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 231 transitions. [2018-12-09 19:38:05,071 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:05,071 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 231 transitions. [2018-12-09 19:38:05,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:05,073 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:05,073 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:05,073 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:05,073 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:05,073 INFO L82 PathProgramCache]: Analyzing trace with hash 1873434817, now seen corresponding path program 1 times [2018-12-09 19:38:05,074 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:05,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:05,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,075 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:05,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:05,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:05,113 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:05,113 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:05,113 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:05,114 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:05,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:05,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:05,114 INFO L87 Difference]: Start difference. First operand 149 states and 231 transitions. Second operand 4 states. [2018-12-09 19:38:05,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:05,224 INFO L93 Difference]: Finished difference Result 418 states and 654 transitions. [2018-12-09 19:38:05,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:38:05,224 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-12-09 19:38:05,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:05,226 INFO L225 Difference]: With dead ends: 418 [2018-12-09 19:38:05,226 INFO L226 Difference]: Without dead ends: 289 [2018-12-09 19:38:05,226 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:05,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2018-12-09 19:38:05,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 165. [2018-12-09 19:38:05,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-12-09 19:38:05,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 253 transitions. [2018-12-09 19:38:05,237 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 253 transitions. Word has length 46 [2018-12-09 19:38:05,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:05,237 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 253 transitions. [2018-12-09 19:38:05,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:05,237 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 253 transitions. [2018-12-09 19:38:05,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:05,238 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:05,238 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:05,239 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:05,239 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:05,239 INFO L82 PathProgramCache]: Analyzing trace with hash -1035329085, now seen corresponding path program 1 times [2018-12-09 19:38:05,239 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:05,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:05,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,240 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:05,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:05,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:05,266 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:05,266 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:05,266 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:05,267 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:05,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:05,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:05,267 INFO L87 Difference]: Start difference. First operand 165 states and 253 transitions. Second operand 4 states. [2018-12-09 19:38:05,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:05,389 INFO L93 Difference]: Finished difference Result 503 states and 772 transitions. [2018-12-09 19:38:05,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:38:05,390 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-12-09 19:38:05,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:05,392 INFO L225 Difference]: With dead ends: 503 [2018-12-09 19:38:05,392 INFO L226 Difference]: Without dead ends: 369 [2018-12-09 19:38:05,392 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:05,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2018-12-09 19:38:05,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 352. [2018-12-09 19:38:05,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2018-12-09 19:38:05,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 540 transitions. [2018-12-09 19:38:05,416 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 540 transitions. Word has length 46 [2018-12-09 19:38:05,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:05,416 INFO L480 AbstractCegarLoop]: Abstraction has 352 states and 540 transitions. [2018-12-09 19:38:05,416 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:05,417 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 540 transitions. [2018-12-09 19:38:05,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:05,418 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:05,418 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:05,419 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:05,419 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:05,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1544802175, now seen corresponding path program 1 times [2018-12-09 19:38:05,419 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:05,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,420 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:05,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,420 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:05,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:05,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:05,491 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:05,491 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 19:38:05,491 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:05,491 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:38:05,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:38:05,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:05,492 INFO L87 Difference]: Start difference. First operand 352 states and 540 transitions. Second operand 5 states. [2018-12-09 19:38:05,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:05,677 INFO L93 Difference]: Finished difference Result 974 states and 1524 transitions. [2018-12-09 19:38:05,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:38:05,677 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2018-12-09 19:38:05,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:05,680 INFO L225 Difference]: With dead ends: 974 [2018-12-09 19:38:05,680 INFO L226 Difference]: Without dead ends: 654 [2018-12-09 19:38:05,681 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:38:05,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-12-09 19:38:05,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 525. [2018-12-09 19:38:05,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 525 states. [2018-12-09 19:38:05,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 804 transitions. [2018-12-09 19:38:05,717 INFO L78 Accepts]: Start accepts. Automaton has 525 states and 804 transitions. Word has length 46 [2018-12-09 19:38:05,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:05,718 INFO L480 AbstractCegarLoop]: Abstraction has 525 states and 804 transitions. [2018-12-09 19:38:05,718 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:38:05,718 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 804 transitions. [2018-12-09 19:38:05,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:05,719 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:05,719 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:05,719 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:05,719 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:05,720 INFO L82 PathProgramCache]: Analyzing trace with hash -1914487912, now seen corresponding path program 1 times [2018-12-09 19:38:05,720 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:05,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:05,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:05,721 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:05,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:05,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:05,800 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:05,800 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 19:38:05,800 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:05,800 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:38:05,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:38:05,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:05,801 INFO L87 Difference]: Start difference. First operand 525 states and 804 transitions. Second operand 5 states. [2018-12-09 19:38:05,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:05,979 INFO L93 Difference]: Finished difference Result 2028 states and 3129 transitions. [2018-12-09 19:38:05,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:38:05,979 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2018-12-09 19:38:05,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:05,983 INFO L225 Difference]: With dead ends: 2028 [2018-12-09 19:38:05,983 INFO L226 Difference]: Without dead ends: 1544 [2018-12-09 19:38:05,984 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:38:05,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1544 states. [2018-12-09 19:38:06,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1544 to 587. [2018-12-09 19:38:06,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 587 states. [2018-12-09 19:38:06,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 901 transitions. [2018-12-09 19:38:06,017 INFO L78 Accepts]: Start accepts. Automaton has 587 states and 901 transitions. Word has length 46 [2018-12-09 19:38:06,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:06,017 INFO L480 AbstractCegarLoop]: Abstraction has 587 states and 901 transitions. [2018-12-09 19:38:06,017 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:38:06,017 INFO L276 IsEmpty]: Start isEmpty. Operand 587 states and 901 transitions. [2018-12-09 19:38:06,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:06,017 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:06,018 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:06,018 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:06,018 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:06,018 INFO L82 PathProgramCache]: Analyzing trace with hash 605189396, now seen corresponding path program 1 times [2018-12-09 19:38:06,018 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:06,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,019 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:06,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,019 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:06,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:06,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:06,041 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:06,041 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:06,041 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:06,042 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:06,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:06,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:06,042 INFO L87 Difference]: Start difference. First operand 587 states and 901 transitions. Second operand 4 states. [2018-12-09 19:38:06,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:06,194 INFO L93 Difference]: Finished difference Result 1686 states and 2621 transitions. [2018-12-09 19:38:06,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:38:06,195 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-12-09 19:38:06,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:06,197 INFO L225 Difference]: With dead ends: 1686 [2018-12-09 19:38:06,198 INFO L226 Difference]: Without dead ends: 1137 [2018-12-09 19:38:06,199 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:06,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1137 states. [2018-12-09 19:38:06,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1137 to 1121. [2018-12-09 19:38:06,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-12-09 19:38:06,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1731 transitions. [2018-12-09 19:38:06,248 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1731 transitions. Word has length 46 [2018-12-09 19:38:06,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:06,248 INFO L480 AbstractCegarLoop]: Abstraction has 1121 states and 1731 transitions. [2018-12-09 19:38:06,248 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:06,248 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1731 transitions. [2018-12-09 19:38:06,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:06,248 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:06,249 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:06,249 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:06,249 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:06,249 INFO L82 PathProgramCache]: Analyzing trace with hash 1027891222, now seen corresponding path program 1 times [2018-12-09 19:38:06,249 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:06,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,249 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:06,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,249 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:06,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:06,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:06,286 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:06,286 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:06,286 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:06,286 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:06,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:06,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:06,287 INFO L87 Difference]: Start difference. First operand 1121 states and 1731 transitions. Second operand 4 states. [2018-12-09 19:38:06,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:06,451 INFO L93 Difference]: Finished difference Result 2615 states and 4073 transitions. [2018-12-09 19:38:06,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:38:06,451 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-12-09 19:38:06,452 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:06,456 INFO L225 Difference]: With dead ends: 2615 [2018-12-09 19:38:06,457 INFO L226 Difference]: Without dead ends: 1597 [2018-12-09 19:38:06,460 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:06,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1597 states. [2018-12-09 19:38:06,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1597 to 1590. [2018-12-09 19:38:06,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2018-12-09 19:38:06,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 2433 transitions. [2018-12-09 19:38:06,526 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 2433 transitions. Word has length 46 [2018-12-09 19:38:06,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:06,526 INFO L480 AbstractCegarLoop]: Abstraction has 1590 states and 2433 transitions. [2018-12-09 19:38:06,526 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:06,526 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 2433 transitions. [2018-12-09 19:38:06,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 19:38:06,527 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:06,527 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:06,528 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:06,528 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:06,528 INFO L82 PathProgramCache]: Analyzing trace with hash -560456680, now seen corresponding path program 1 times [2018-12-09 19:38:06,528 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:06,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,529 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:06,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,529 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:06,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:06,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:06,554 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:06,554 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:06,554 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:06,554 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:06,554 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:06,554 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:06,554 INFO L87 Difference]: Start difference. First operand 1590 states and 2433 transitions. Second operand 3 states. [2018-12-09 19:38:06,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:06,665 INFO L93 Difference]: Finished difference Result 3289 states and 5113 transitions. [2018-12-09 19:38:06,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:06,665 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2018-12-09 19:38:06,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:06,670 INFO L225 Difference]: With dead ends: 3289 [2018-12-09 19:38:06,670 INFO L226 Difference]: Without dead ends: 1749 [2018-12-09 19:38:06,673 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:06,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1749 states. [2018-12-09 19:38:06,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1749 to 1709. [2018-12-09 19:38:06,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1709 states. [2018-12-09 19:38:06,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1709 states to 1709 states and 2589 transitions. [2018-12-09 19:38:06,759 INFO L78 Accepts]: Start accepts. Automaton has 1709 states and 2589 transitions. Word has length 46 [2018-12-09 19:38:06,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:06,759 INFO L480 AbstractCegarLoop]: Abstraction has 1709 states and 2589 transitions. [2018-12-09 19:38:06,760 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:06,760 INFO L276 IsEmpty]: Start isEmpty. Operand 1709 states and 2589 transitions. [2018-12-09 19:38:06,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-12-09 19:38:06,762 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:06,762 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:06,762 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:06,762 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:06,762 INFO L82 PathProgramCache]: Analyzing trace with hash 1832125989, now seen corresponding path program 1 times [2018-12-09 19:38:06,763 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:06,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,763 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:06,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:06,763 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:06,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:06,823 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 19 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-12-09 19:38:06,823 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:38:06,823 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:38:06,824 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 81 with the following transitions: [2018-12-09 19:38:06,825 INFO L205 CegarAbsIntRunner]: [45], [46], [74], [83], [87], [113], [116], [135], [148], [161], [174], [225], [228], [230], [233], [235], [238], [242], [251], [253], [264], [276], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [674], [678], [681], [682], [691], [693], [695], [696], [697], [699] [2018-12-09 19:38:06,855 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:38:06,855 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:38:07,013 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 19:38:07,014 INFO L272 AbstractInterpreter]: Visited 46 different actions 46 times. Never merged. Never widened. Performed 464 root evaluator evaluations with a maximum evaluation depth of 3. Performed 464 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 64 variables. [2018-12-09 19:38:07,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:07,027 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 19:38:07,191 INFO L227 lantSequenceWeakener]: Weakened 60 states. On average, predicates are now at 83.38% of their original sizes. [2018-12-09 19:38:07,191 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 19:38:07,387 INFO L418 sIntCurrentIteration]: We unified 79 AI predicates to 79 [2018-12-09 19:38:07,387 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 19:38:07,388 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:38:07,388 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [24] imperfect sequences [7] total 29 [2018-12-09 19:38:07,388 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:07,389 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-12-09 19:38:07,389 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-12-09 19:38:07,389 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=439, Unknown=0, NotChecked=0, Total=552 [2018-12-09 19:38:07,389 INFO L87 Difference]: Start difference. First operand 1709 states and 2589 transitions. Second operand 24 states. [2018-12-09 19:38:10,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:10,399 INFO L93 Difference]: Finished difference Result 4163 states and 6486 transitions. [2018-12-09 19:38:10,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-09 19:38:10,399 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 80 [2018-12-09 19:38:10,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:10,408 INFO L225 Difference]: With dead ends: 4163 [2018-12-09 19:38:10,408 INFO L226 Difference]: Without dead ends: 2463 [2018-12-09 19:38:10,413 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 90 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=280, Invalid=910, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 19:38:10,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2463 states. [2018-12-09 19:38:10,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2463 to 2387. [2018-12-09 19:38:10,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2387 states. [2018-12-09 19:38:10,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2387 states to 2387 states and 3592 transitions. [2018-12-09 19:38:10,524 INFO L78 Accepts]: Start accepts. Automaton has 2387 states and 3592 transitions. Word has length 80 [2018-12-09 19:38:10,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:10,524 INFO L480 AbstractCegarLoop]: Abstraction has 2387 states and 3592 transitions. [2018-12-09 19:38:10,524 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-12-09 19:38:10,524 INFO L276 IsEmpty]: Start isEmpty. Operand 2387 states and 3592 transitions. [2018-12-09 19:38:10,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-12-09 19:38:10,527 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:10,528 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:10,528 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:10,528 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:10,528 INFO L82 PathProgramCache]: Analyzing trace with hash 864775335, now seen corresponding path program 1 times [2018-12-09 19:38:10,528 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:10,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:10,529 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:10,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:10,529 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:10,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:10,557 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-12-09 19:38:10,557 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:10,557 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:10,557 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:10,557 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:10,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:10,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:10,558 INFO L87 Difference]: Start difference. First operand 2387 states and 3592 transitions. Second operand 4 states. [2018-12-09 19:38:10,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:10,744 INFO L93 Difference]: Finished difference Result 6280 states and 9514 transitions. [2018-12-09 19:38:10,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:38:10,744 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 80 [2018-12-09 19:38:10,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:10,753 INFO L225 Difference]: With dead ends: 6280 [2018-12-09 19:38:10,753 INFO L226 Difference]: Without dead ends: 4072 [2018-12-09 19:38:10,757 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:10,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4072 states. [2018-12-09 19:38:10,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4072 to 4069. [2018-12-09 19:38:10,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4069 states. [2018-12-09 19:38:10,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4069 states to 4069 states and 6149 transitions. [2018-12-09 19:38:10,929 INFO L78 Accepts]: Start accepts. Automaton has 4069 states and 6149 transitions. Word has length 80 [2018-12-09 19:38:10,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:10,929 INFO L480 AbstractCegarLoop]: Abstraction has 4069 states and 6149 transitions. [2018-12-09 19:38:10,929 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:10,929 INFO L276 IsEmpty]: Start isEmpty. Operand 4069 states and 6149 transitions. [2018-12-09 19:38:10,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-12-09 19:38:10,933 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:10,933 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:10,933 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:10,933 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:10,933 INFO L82 PathProgramCache]: Analyzing trace with hash -172006164, now seen corresponding path program 1 times [2018-12-09 19:38:10,933 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:10,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:10,934 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:10,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:10,934 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:10,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:10,993 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 19 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-12-09 19:38:10,993 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:38:10,993 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:38:10,993 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 88 with the following transitions: [2018-12-09 19:38:10,994 INFO L205 CegarAbsIntRunner]: [45], [46], [74], [83], [87], [113], [116], [126], [129], [135], [148], [161], [174], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [264], [276], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [674], [678], [681], [682], [683], [684], [691], [693], [695], [696], [697], [699] [2018-12-09 19:38:10,995 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:38:10,995 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:38:11,026 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 19:38:11,026 INFO L272 AbstractInterpreter]: Visited 55 different actions 55 times. Never merged. Never widened. Performed 541 root evaluator evaluations with a maximum evaluation depth of 3. Performed 541 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 65 variables. [2018-12-09 19:38:11,038 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:11,038 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 19:38:11,104 INFO L227 lantSequenceWeakener]: Weakened 69 states. On average, predicates are now at 83.77% of their original sizes. [2018-12-09 19:38:11,104 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 19:38:11,391 INFO L418 sIntCurrentIteration]: We unified 86 AI predicates to 86 [2018-12-09 19:38:11,391 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 19:38:11,391 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:38:11,392 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [7] total 33 [2018-12-09 19:38:11,392 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:11,392 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-09 19:38:11,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-09 19:38:11,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=630, Unknown=0, NotChecked=0, Total=756 [2018-12-09 19:38:11,392 INFO L87 Difference]: Start difference. First operand 4069 states and 6149 transitions. Second operand 28 states. [2018-12-09 19:38:15,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:15,891 INFO L93 Difference]: Finished difference Result 5500 states and 8314 transitions. [2018-12-09 19:38:15,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-09 19:38:15,891 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 87 [2018-12-09 19:38:15,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:15,899 INFO L225 Difference]: With dead ends: 5500 [2018-12-09 19:38:15,899 INFO L226 Difference]: Without dead ends: 4217 [2018-12-09 19:38:15,901 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 99 GetRequests, 60 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 352 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=307, Invalid=1333, Unknown=0, NotChecked=0, Total=1640 [2018-12-09 19:38:15,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4217 states. [2018-12-09 19:38:16,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4217 to 4103. [2018-12-09 19:38:16,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4103 states. [2018-12-09 19:38:16,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4103 states to 4103 states and 6187 transitions. [2018-12-09 19:38:16,064 INFO L78 Accepts]: Start accepts. Automaton has 4103 states and 6187 transitions. Word has length 87 [2018-12-09 19:38:16,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:16,065 INFO L480 AbstractCegarLoop]: Abstraction has 4103 states and 6187 transitions. [2018-12-09 19:38:16,065 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-09 19:38:16,065 INFO L276 IsEmpty]: Start isEmpty. Operand 4103 states and 6187 transitions. [2018-12-09 19:38:16,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-12-09 19:38:16,069 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:16,069 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:16,069 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:16,069 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:16,069 INFO L82 PathProgramCache]: Analyzing trace with hash 746661019, now seen corresponding path program 1 times [2018-12-09 19:38:16,069 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:16,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:16,070 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:16,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:16,070 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:16,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:16,110 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 19 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-12-09 19:38:16,110 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:38:16,110 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:38:16,111 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 90 with the following transitions: [2018-12-09 19:38:16,111 INFO L205 CegarAbsIntRunner]: [45], [46], [74], [83], [87], [113], [116], [126], [132], [135], [139], [145], [148], [152], [155], [161], [174], [225], [228], [230], [233], [235], [238], [242], [251], [253], [264], [276], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [649], [665], [667], [673], [674], [678], [681], [682], [687], [688], [691], [693], [695], [696], [697], [699] [2018-12-09 19:38:16,112 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:38:16,112 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:38:16,140 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 19:38:16,140 INFO L272 AbstractInterpreter]: Visited 61 different actions 63 times. Merged at 2 different actions 2 times. Never widened. Performed 567 root evaluator evaluations with a maximum evaluation depth of 3. Performed 567 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 67 variables. [2018-12-09 19:38:16,146 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:16,146 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 19:38:16,210 INFO L227 lantSequenceWeakener]: Weakened 75 states. On average, predicates are now at 83.42% of their original sizes. [2018-12-09 19:38:16,210 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 19:38:16,448 INFO L418 sIntCurrentIteration]: We unified 88 AI predicates to 88 [2018-12-09 19:38:16,448 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 19:38:16,448 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:38:16,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [7] total 37 [2018-12-09 19:38:16,448 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:16,448 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 19:38:16,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 19:38:16,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=839, Unknown=0, NotChecked=0, Total=992 [2018-12-09 19:38:16,449 INFO L87 Difference]: Start difference. First operand 4103 states and 6187 transitions. Second operand 32 states. [2018-12-09 19:38:23,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:23,091 INFO L93 Difference]: Finished difference Result 8967 states and 13901 transitions. [2018-12-09 19:38:23,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-12-09 19:38:23,091 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 89 [2018-12-09 19:38:23,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:23,109 INFO L225 Difference]: With dead ends: 8967 [2018-12-09 19:38:23,109 INFO L226 Difference]: Without dead ends: 6402 [2018-12-09 19:38:23,121 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 101 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 499 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=359, Invalid=1621, Unknown=0, NotChecked=0, Total=1980 [2018-12-09 19:38:23,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6402 states. [2018-12-09 19:38:23,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6402 to 6072. [2018-12-09 19:38:23,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6072 states. [2018-12-09 19:38:23,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6072 states to 6072 states and 9159 transitions. [2018-12-09 19:38:23,461 INFO L78 Accepts]: Start accepts. Automaton has 6072 states and 9159 transitions. Word has length 89 [2018-12-09 19:38:23,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:23,462 INFO L480 AbstractCegarLoop]: Abstraction has 6072 states and 9159 transitions. [2018-12-09 19:38:23,462 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 19:38:23,462 INFO L276 IsEmpty]: Start isEmpty. Operand 6072 states and 9159 transitions. [2018-12-09 19:38:23,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-12-09 19:38:23,467 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:23,467 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:23,467 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:23,467 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:23,467 INFO L82 PathProgramCache]: Analyzing trace with hash -1693034259, now seen corresponding path program 1 times [2018-12-09 19:38:23,467 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:23,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:23,468 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:23,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:23,468 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:23,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:23,528 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 19:38:23,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:23,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 19:38:23,528 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:23,529 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:38:23,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:38:23,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:23,529 INFO L87 Difference]: Start difference. First operand 6072 states and 9159 transitions. Second operand 5 states. [2018-12-09 19:38:23,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:23,957 INFO L93 Difference]: Finished difference Result 14686 states and 22641 transitions. [2018-12-09 19:38:23,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 19:38:23,957 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 104 [2018-12-09 19:38:23,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:23,977 INFO L225 Difference]: With dead ends: 14686 [2018-12-09 19:38:23,977 INFO L226 Difference]: Without dead ends: 9332 [2018-12-09 19:38:23,991 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-12-09 19:38:23,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9332 states. [2018-12-09 19:38:24,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9332 to 8704. [2018-12-09 19:38:24,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8704 states. [2018-12-09 19:38:24,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8704 states to 8704 states and 12979 transitions. [2018-12-09 19:38:24,361 INFO L78 Accepts]: Start accepts. Automaton has 8704 states and 12979 transitions. Word has length 104 [2018-12-09 19:38:24,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:24,361 INFO L480 AbstractCegarLoop]: Abstraction has 8704 states and 12979 transitions. [2018-12-09 19:38:24,361 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:38:24,361 INFO L276 IsEmpty]: Start isEmpty. Operand 8704 states and 12979 transitions. [2018-12-09 19:38:24,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-12-09 19:38:24,370 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:24,370 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:24,370 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:24,370 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:24,370 INFO L82 PathProgramCache]: Analyzing trace with hash -1969943531, now seen corresponding path program 1 times [2018-12-09 19:38:24,370 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:24,370 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:24,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:24,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:24,371 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:24,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:24,406 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-09 19:38:24,406 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:24,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:24,407 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:24,407 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:24,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:24,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:24,407 INFO L87 Difference]: Start difference. First operand 8704 states and 12979 transitions. Second operand 4 states. [2018-12-09 19:38:24,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:24,788 INFO L93 Difference]: Finished difference Result 15700 states and 23534 transitions. [2018-12-09 19:38:24,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:38:24,788 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 112 [2018-12-09 19:38:24,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:24,803 INFO L225 Difference]: With dead ends: 15700 [2018-12-09 19:38:24,803 INFO L226 Difference]: Without dead ends: 7643 [2018-12-09 19:38:24,814 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:24,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7643 states. [2018-12-09 19:38:25,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7643 to 4840. [2018-12-09 19:38:25,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4840 states. [2018-12-09 19:38:25,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4840 states to 4840 states and 7172 transitions. [2018-12-09 19:38:25,103 INFO L78 Accepts]: Start accepts. Automaton has 4840 states and 7172 transitions. Word has length 112 [2018-12-09 19:38:25,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:25,103 INFO L480 AbstractCegarLoop]: Abstraction has 4840 states and 7172 transitions. [2018-12-09 19:38:25,103 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:25,103 INFO L276 IsEmpty]: Start isEmpty. Operand 4840 states and 7172 transitions. [2018-12-09 19:38:25,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-12-09 19:38:25,108 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:25,108 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:25,108 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:25,108 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:25,108 INFO L82 PathProgramCache]: Analyzing trace with hash 1765457489, now seen corresponding path program 1 times [2018-12-09 19:38:25,108 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:25,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:25,109 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:25,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:25,109 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:25,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:25,133 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-09 19:38:25,133 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:25,134 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:25,134 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:25,134 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:25,134 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:25,134 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:25,134 INFO L87 Difference]: Start difference. First operand 4840 states and 7172 transitions. Second operand 4 states. [2018-12-09 19:38:25,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:25,350 INFO L93 Difference]: Finished difference Result 7646 states and 11438 transitions. [2018-12-09 19:38:25,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:38:25,350 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 112 [2018-12-09 19:38:25,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:25,356 INFO L225 Difference]: With dead ends: 7646 [2018-12-09 19:38:25,356 INFO L226 Difference]: Without dead ends: 4085 [2018-12-09 19:38:25,359 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:25,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4085 states. [2018-12-09 19:38:25,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4085 to 4085. [2018-12-09 19:38:25,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4085 states. [2018-12-09 19:38:25,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4085 states to 4085 states and 6075 transitions. [2018-12-09 19:38:25,563 INFO L78 Accepts]: Start accepts. Automaton has 4085 states and 6075 transitions. Word has length 112 [2018-12-09 19:38:25,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:25,563 INFO L480 AbstractCegarLoop]: Abstraction has 4085 states and 6075 transitions. [2018-12-09 19:38:25,563 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:25,563 INFO L276 IsEmpty]: Start isEmpty. Operand 4085 states and 6075 transitions. [2018-12-09 19:38:25,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-12-09 19:38:25,565 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:25,565 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:25,566 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:25,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:25,566 INFO L82 PathProgramCache]: Analyzing trace with hash 270685587, now seen corresponding path program 1 times [2018-12-09 19:38:25,566 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:25,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:25,566 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:25,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:25,566 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:25,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:25,601 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 19:38:25,601 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:25,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:25,601 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:25,602 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:25,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:25,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:25,602 INFO L87 Difference]: Start difference. First operand 4085 states and 6075 transitions. Second operand 3 states. [2018-12-09 19:38:25,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:25,906 INFO L93 Difference]: Finished difference Result 9576 states and 14551 transitions. [2018-12-09 19:38:25,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:25,907 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2018-12-09 19:38:25,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:25,914 INFO L225 Difference]: With dead ends: 9576 [2018-12-09 19:38:25,914 INFO L226 Difference]: Without dead ends: 5676 [2018-12-09 19:38:25,920 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:25,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5676 states. [2018-12-09 19:38:26,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5676 to 5667. [2018-12-09 19:38:26,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5667 states. [2018-12-09 19:38:26,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5667 states to 5667 states and 8450 transitions. [2018-12-09 19:38:26,245 INFO L78 Accepts]: Start accepts. Automaton has 5667 states and 8450 transitions. Word has length 127 [2018-12-09 19:38:26,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:26,245 INFO L480 AbstractCegarLoop]: Abstraction has 5667 states and 8450 transitions. [2018-12-09 19:38:26,245 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:26,245 INFO L276 IsEmpty]: Start isEmpty. Operand 5667 states and 8450 transitions. [2018-12-09 19:38:26,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-12-09 19:38:26,249 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:26,250 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:26,250 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:26,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:26,250 INFO L82 PathProgramCache]: Analyzing trace with hash -722579885, now seen corresponding path program 1 times [2018-12-09 19:38:26,250 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:26,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:26,250 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:26,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:26,251 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:26,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:26,283 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 19:38:26,283 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:26,283 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:26,283 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:26,283 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:26,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:26,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:26,284 INFO L87 Difference]: Start difference. First operand 5667 states and 8450 transitions. Second operand 3 states. [2018-12-09 19:38:26,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:26,732 INFO L93 Difference]: Finished difference Result 13683 states and 20773 transitions. [2018-12-09 19:38:26,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:26,732 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2018-12-09 19:38:26,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:26,744 INFO L225 Difference]: With dead ends: 13683 [2018-12-09 19:38:26,744 INFO L226 Difference]: Without dead ends: 8201 [2018-12-09 19:38:26,754 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:26,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8201 states. [2018-12-09 19:38:27,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8201 to 8174. [2018-12-09 19:38:27,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8174 states. [2018-12-09 19:38:27,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8174 states to 8174 states and 12122 transitions. [2018-12-09 19:38:27,220 INFO L78 Accepts]: Start accepts. Automaton has 8174 states and 12122 transitions. Word has length 127 [2018-12-09 19:38:27,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:27,220 INFO L480 AbstractCegarLoop]: Abstraction has 8174 states and 12122 transitions. [2018-12-09 19:38:27,220 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:27,220 INFO L276 IsEmpty]: Start isEmpty. Operand 8174 states and 12122 transitions. [2018-12-09 19:38:27,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-12-09 19:38:27,228 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:27,228 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:27,228 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:27,228 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:27,229 INFO L82 PathProgramCache]: Analyzing trace with hash -867223331, now seen corresponding path program 1 times [2018-12-09 19:38:27,229 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:27,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:27,229 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:27,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:27,229 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:27,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:27,296 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 6 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-09 19:38:27,296 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:38:27,297 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:38:27,297 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 134 with the following transitions: [2018-12-09 19:38:27,297 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [126], [129], [135], [139], [142], [148], [152], [155], [161], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [264], [276], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [485], [487], [492], [498], [502], [510], [514], [520], [523], [552], [564], [576], [582], [586], [594], [598], [606], [610], [616], [649], [665], [667], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:38:27,298 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:38:27,298 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:38:27,323 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 19:38:27,324 INFO L272 AbstractInterpreter]: Visited 86 different actions 89 times. Merged at 2 different actions 2 times. Never widened. Performed 724 root evaluator evaluations with a maximum evaluation depth of 3. Performed 724 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 67 variables. [2018-12-09 19:38:27,325 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:27,325 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 19:38:27,400 INFO L227 lantSequenceWeakener]: Weakened 105 states. On average, predicates are now at 78.14% of their original sizes. [2018-12-09 19:38:27,400 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 19:38:27,769 INFO L418 sIntCurrentIteration]: We unified 132 AI predicates to 132 [2018-12-09 19:38:27,769 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 19:38:27,769 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:38:27,769 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [38] imperfect sequences [9] total 45 [2018-12-09 19:38:27,769 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:27,770 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-09 19:38:27,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-09 19:38:27,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=1260, Unknown=0, NotChecked=0, Total=1406 [2018-12-09 19:38:27,770 INFO L87 Difference]: Start difference. First operand 8174 states and 12122 transitions. Second operand 38 states. [2018-12-09 19:38:37,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:37,529 INFO L93 Difference]: Finished difference Result 15070 states and 22466 transitions. [2018-12-09 19:38:37,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-09 19:38:37,530 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 133 [2018-12-09 19:38:37,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:37,542 INFO L225 Difference]: With dead ends: 15070 [2018-12-09 19:38:37,542 INFO L226 Difference]: Without dead ends: 8348 [2018-12-09 19:38:37,554 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 149 GetRequests, 96 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 764 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=355, Invalid=2615, Unknown=0, NotChecked=0, Total=2970 [2018-12-09 19:38:37,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8348 states. [2018-12-09 19:38:38,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8348 to 8265. [2018-12-09 19:38:38,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8265 states. [2018-12-09 19:38:38,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8265 states to 8265 states and 12217 transitions. [2018-12-09 19:38:38,071 INFO L78 Accepts]: Start accepts. Automaton has 8265 states and 12217 transitions. Word has length 133 [2018-12-09 19:38:38,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:38,071 INFO L480 AbstractCegarLoop]: Abstraction has 8265 states and 12217 transitions. [2018-12-09 19:38:38,071 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-09 19:38:38,071 INFO L276 IsEmpty]: Start isEmpty. Operand 8265 states and 12217 transitions. [2018-12-09 19:38:38,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-12-09 19:38:38,079 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:38,079 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:38,079 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:38,079 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:38,079 INFO L82 PathProgramCache]: Analyzing trace with hash 1647304349, now seen corresponding path program 1 times [2018-12-09 19:38:38,079 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:38,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:38,080 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:38,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:38,080 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:38,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:38,115 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 19:38:38,115 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:38,115 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:38,115 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:38,115 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:38,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:38,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:38,116 INFO L87 Difference]: Start difference. First operand 8265 states and 12217 transitions. Second operand 3 states. [2018-12-09 19:38:38,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:38,637 INFO L93 Difference]: Finished difference Result 16848 states and 25374 transitions. [2018-12-09 19:38:38,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:38,637 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2018-12-09 19:38:38,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:38,650 INFO L225 Difference]: With dead ends: 16848 [2018-12-09 19:38:38,650 INFO L226 Difference]: Without dead ends: 8859 [2018-12-09 19:38:38,667 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:38,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8859 states. [2018-12-09 19:38:39,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8859 to 8815. [2018-12-09 19:38:39,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8815 states. [2018-12-09 19:38:39,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8815 states to 8815 states and 12726 transitions. [2018-12-09 19:38:39,183 INFO L78 Accepts]: Start accepts. Automaton has 8815 states and 12726 transitions. Word has length 133 [2018-12-09 19:38:39,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:39,183 INFO L480 AbstractCegarLoop]: Abstraction has 8815 states and 12726 transitions. [2018-12-09 19:38:39,183 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:39,183 INFO L276 IsEmpty]: Start isEmpty. Operand 8815 states and 12726 transitions. [2018-12-09 19:38:39,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-12-09 19:38:39,190 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:39,190 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:39,191 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:39,191 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:39,191 INFO L82 PathProgramCache]: Analyzing trace with hash 1482975989, now seen corresponding path program 1 times [2018-12-09 19:38:39,191 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:39,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:39,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:39,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:39,192 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:39,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:39,222 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 19:38:39,222 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:39,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:39,222 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:39,223 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:39,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:39,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:39,223 INFO L87 Difference]: Start difference. First operand 8815 states and 12726 transitions. Second operand 3 states. [2018-12-09 19:38:39,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:39,852 INFO L93 Difference]: Finished difference Result 18176 states and 26719 transitions. [2018-12-09 19:38:39,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:39,852 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 135 [2018-12-09 19:38:39,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:39,866 INFO L225 Difference]: With dead ends: 18176 [2018-12-09 19:38:39,866 INFO L226 Difference]: Without dead ends: 9637 [2018-12-09 19:38:39,881 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:39,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9637 states. [2018-12-09 19:38:40,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9637 to 9321. [2018-12-09 19:38:40,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9321 states. [2018-12-09 19:38:40,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9321 states to 9321 states and 13165 transitions. [2018-12-09 19:38:40,448 INFO L78 Accepts]: Start accepts. Automaton has 9321 states and 13165 transitions. Word has length 135 [2018-12-09 19:38:40,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:40,448 INFO L480 AbstractCegarLoop]: Abstraction has 9321 states and 13165 transitions. [2018-12-09 19:38:40,448 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:40,448 INFO L276 IsEmpty]: Start isEmpty. Operand 9321 states and 13165 transitions. [2018-12-09 19:38:40,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-12-09 19:38:40,456 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:40,456 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:40,456 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:40,456 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:40,456 INFO L82 PathProgramCache]: Analyzing trace with hash 1633215901, now seen corresponding path program 1 times [2018-12-09 19:38:40,456 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:40,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:40,456 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:40,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:40,457 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:40,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:40,491 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 19:38:40,491 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:40,491 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:40,491 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:40,492 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:40,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:40,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:40,492 INFO L87 Difference]: Start difference. First operand 9321 states and 13165 transitions. Second operand 3 states. [2018-12-09 19:38:41,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:41,493 INFO L93 Difference]: Finished difference Result 25542 states and 37765 transitions. [2018-12-09 19:38:41,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:41,493 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2018-12-09 19:38:41,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:41,516 INFO L225 Difference]: With dead ends: 25542 [2018-12-09 19:38:41,517 INFO L226 Difference]: Without dead ends: 16515 [2018-12-09 19:38:41,540 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:41,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16515 states. [2018-12-09 19:38:42,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16515 to 16152. [2018-12-09 19:38:42,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16152 states. [2018-12-09 19:38:42,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16152 states to 16152 states and 23058 transitions. [2018-12-09 19:38:42,536 INFO L78 Accepts]: Start accepts. Automaton has 16152 states and 23058 transitions. Word has length 137 [2018-12-09 19:38:42,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:42,537 INFO L480 AbstractCegarLoop]: Abstraction has 16152 states and 23058 transitions. [2018-12-09 19:38:42,537 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:42,537 INFO L276 IsEmpty]: Start isEmpty. Operand 16152 states and 23058 transitions. [2018-12-09 19:38:42,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-12-09 19:38:42,557 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:42,557 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:42,557 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:42,557 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:42,557 INFO L82 PathProgramCache]: Analyzing trace with hash 687619000, now seen corresponding path program 1 times [2018-12-09 19:38:42,557 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:42,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:42,557 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:42,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:42,558 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:42,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:42,591 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-09 19:38:42,591 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:42,591 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 19:38:42,591 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:42,591 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:38:42,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:38:42,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:42,592 INFO L87 Difference]: Start difference. First operand 16152 states and 23058 transitions. Second operand 5 states. [2018-12-09 19:38:44,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:44,668 INFO L93 Difference]: Finished difference Result 48520 states and 72446 transitions. [2018-12-09 19:38:44,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:38:44,669 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 138 [2018-12-09 19:38:44,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:44,754 INFO L225 Difference]: With dead ends: 48520 [2018-12-09 19:38:44,755 INFO L226 Difference]: Without dead ends: 32400 [2018-12-09 19:38:44,789 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 8 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:38:44,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32400 states. [2018-12-09 19:38:46,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32400 to 28621. [2018-12-09 19:38:46,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28621 states. [2018-12-09 19:38:46,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28621 states to 28621 states and 42530 transitions. [2018-12-09 19:38:46,853 INFO L78 Accepts]: Start accepts. Automaton has 28621 states and 42530 transitions. Word has length 138 [2018-12-09 19:38:46,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:46,853 INFO L480 AbstractCegarLoop]: Abstraction has 28621 states and 42530 transitions. [2018-12-09 19:38:46,853 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:38:46,853 INFO L276 IsEmpty]: Start isEmpty. Operand 28621 states and 42530 transitions. [2018-12-09 19:38:46,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-12-09 19:38:46,894 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:46,894 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:46,895 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:46,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:46,895 INFO L82 PathProgramCache]: Analyzing trace with hash -1430929100, now seen corresponding path program 1 times [2018-12-09 19:38:46,895 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:46,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:46,896 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:46,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:46,896 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:46,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:46,934 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 19:38:46,934 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:46,935 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:46,935 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:46,935 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:46,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:46,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:46,935 INFO L87 Difference]: Start difference. First operand 28621 states and 42530 transitions. Second operand 3 states. [2018-12-09 19:38:48,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:48,858 INFO L93 Difference]: Finished difference Result 43398 states and 66798 transitions. [2018-12-09 19:38:48,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:48,859 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 138 [2018-12-09 19:38:48,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:48,917 INFO L225 Difference]: With dead ends: 43398 [2018-12-09 19:38:48,917 INFO L226 Difference]: Without dead ends: 28361 [2018-12-09 19:38:48,979 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:48,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28361 states. [2018-12-09 19:38:50,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28361 to 27961. [2018-12-09 19:38:50,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27961 states. [2018-12-09 19:38:50,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27961 states to 27961 states and 41350 transitions. [2018-12-09 19:38:50,976 INFO L78 Accepts]: Start accepts. Automaton has 27961 states and 41350 transitions. Word has length 138 [2018-12-09 19:38:50,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:50,976 INFO L480 AbstractCegarLoop]: Abstraction has 27961 states and 41350 transitions. [2018-12-09 19:38:50,976 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:50,976 INFO L276 IsEmpty]: Start isEmpty. Operand 27961 states and 41350 transitions. [2018-12-09 19:38:51,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-12-09 19:38:51,017 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:51,017 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:51,017 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:51,017 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:51,017 INFO L82 PathProgramCache]: Analyzing trace with hash 1140089527, now seen corresponding path program 1 times [2018-12-09 19:38:51,017 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:51,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:51,018 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:51,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:51,018 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:51,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:51,072 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 13 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 19:38:51,072 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:38:51,072 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:38:51,072 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 141 with the following transitions: [2018-12-09 19:38:51,073 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [126], [129], [132], [139], [142], [145], [152], [155], [161], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [485], [487], [492], [498], [504], [510], [514], [520], [523], [544], [549], [556], [561], [568], [573], [582], [588], [594], [600], [606], [610], [616], [649], [665], [667], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:38:51,074 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:38:51,074 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:38:51,446 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:38:51,446 INFO L272 AbstractInterpreter]: Visited 117 different actions 849 times. Merged at 52 different actions 258 times. Never widened. Performed 13665 root evaluator evaluations with a maximum evaluation depth of 3. Performed 13665 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 52 fixpoints after 16 different actions. Largest state had 67 variables. [2018-12-09 19:38:51,447 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:51,448 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:38:51,448 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:38:51,448 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:38:51,455 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:51,455 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:38:51,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:51,523 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:38:51,556 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 19:38:51,556 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:38:51,603 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 19:38:51,626 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:38:51,626 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [7] total 9 [2018-12-09 19:38:51,627 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:51,627 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:51,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:51,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:38:51,627 INFO L87 Difference]: Start difference. First operand 27961 states and 41350 transitions. Second operand 3 states. [2018-12-09 19:38:53,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:53,608 INFO L93 Difference]: Finished difference Result 51753 states and 78516 transitions. [2018-12-09 19:38:53,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:38:53,609 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 140 [2018-12-09 19:38:53,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:53,665 INFO L225 Difference]: With dead ends: 51753 [2018-12-09 19:38:53,665 INFO L226 Difference]: Without dead ends: 18954 [2018-12-09 19:38:53,777 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 289 GetRequests, 282 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:38:53,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18954 states. [2018-12-09 19:38:55,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18954 to 18727. [2018-12-09 19:38:55,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18727 states. [2018-12-09 19:38:55,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18727 states to 18727 states and 26809 transitions. [2018-12-09 19:38:55,081 INFO L78 Accepts]: Start accepts. Automaton has 18727 states and 26809 transitions. Word has length 140 [2018-12-09 19:38:55,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:55,082 INFO L480 AbstractCegarLoop]: Abstraction has 18727 states and 26809 transitions. [2018-12-09 19:38:55,082 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:38:55,082 INFO L276 IsEmpty]: Start isEmpty. Operand 18727 states and 26809 transitions. [2018-12-09 19:38:55,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-12-09 19:38:55,103 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:55,103 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:55,104 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:55,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:55,104 INFO L82 PathProgramCache]: Analyzing trace with hash 1008698240, now seen corresponding path program 1 times [2018-12-09 19:38:55,104 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:55,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:55,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:55,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:55,104 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:55,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:55,138 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:38:55,138 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:55,138 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:38:55,138 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:55,139 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:38:55,139 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:38:55,139 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:38:55,139 INFO L87 Difference]: Start difference. First operand 18727 states and 26809 transitions. Second operand 4 states. [2018-12-09 19:38:57,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:38:57,104 INFO L93 Difference]: Finished difference Result 38242 states and 54980 transitions. [2018-12-09 19:38:57,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:38:57,105 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 152 [2018-12-09 19:38:57,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:38:57,169 INFO L225 Difference]: With dead ends: 38242 [2018-12-09 19:38:57,170 INFO L226 Difference]: Without dead ends: 26004 [2018-12-09 19:38:57,209 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 19:38:57,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26004 states. [2018-12-09 19:38:58,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26004 to 24239. [2018-12-09 19:38:58,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24239 states. [2018-12-09 19:38:58,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24239 states to 24239 states and 34375 transitions. [2018-12-09 19:38:58,986 INFO L78 Accepts]: Start accepts. Automaton has 24239 states and 34375 transitions. Word has length 152 [2018-12-09 19:38:58,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:38:58,987 INFO L480 AbstractCegarLoop]: Abstraction has 24239 states and 34375 transitions. [2018-12-09 19:38:58,987 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:38:58,987 INFO L276 IsEmpty]: Start isEmpty. Operand 24239 states and 34375 transitions. [2018-12-09 19:38:59,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-12-09 19:38:59,017 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:38:59,017 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:38:59,017 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:38:59,017 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:38:59,017 INFO L82 PathProgramCache]: Analyzing trace with hash -1999893820, now seen corresponding path program 1 times [2018-12-09 19:38:59,017 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:38:59,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:59,018 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:38:59,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:38:59,018 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:38:59,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:38:59,040 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-09 19:38:59,040 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:38:59,040 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:38:59,040 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:38:59,041 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:38:59,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:38:59,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:38:59,041 INFO L87 Difference]: Start difference. First operand 24239 states and 34375 transitions. Second operand 3 states. [2018-12-09 19:39:01,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:01,328 INFO L93 Difference]: Finished difference Result 52255 states and 76123 transitions. [2018-12-09 19:39:01,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:39:01,328 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 161 [2018-12-09 19:39:01,329 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:01,409 INFO L225 Difference]: With dead ends: 52255 [2018-12-09 19:39:01,410 INFO L226 Difference]: Without dead ends: 29581 [2018-12-09 19:39:01,492 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:39:01,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29581 states. [2018-12-09 19:39:03,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29581 to 29546. [2018-12-09 19:39:03,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29546 states. [2018-12-09 19:39:03,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29546 states to 29546 states and 41447 transitions. [2018-12-09 19:39:03,898 INFO L78 Accepts]: Start accepts. Automaton has 29546 states and 41447 transitions. Word has length 161 [2018-12-09 19:39:03,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:03,898 INFO L480 AbstractCegarLoop]: Abstraction has 29546 states and 41447 transitions. [2018-12-09 19:39:03,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:39:03,898 INFO L276 IsEmpty]: Start isEmpty. Operand 29546 states and 41447 transitions. [2018-12-09 19:39:03,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-09 19:39:03,937 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:03,937 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:03,937 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:03,937 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:03,937 INFO L82 PathProgramCache]: Analyzing trace with hash 2051198295, now seen corresponding path program 1 times [2018-12-09 19:39:03,937 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:03,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:03,938 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:03,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:03,938 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:03,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:03,975 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-09 19:39:03,976 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:03,976 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:03,976 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 163 with the following transitions: [2018-12-09 19:39:03,976 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [119], [126], [129], [132], [135], [139], [142], [145], [148], [152], [155], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [502], [508], [514], [520], [523], [544], [549], [556], [561], [568], [573], [580], [586], [594], [598], [604], [610], [618], [621], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:03,978 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:03,978 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:04,039 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 19:39:04,040 INFO L272 AbstractInterpreter]: Visited 72 different actions 132 times. Merged at 11 different actions 24 times. Never widened. Performed 2653 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2653 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 3 fixpoints after 1 different actions. Largest state had 68 variables. [2018-12-09 19:39:04,041 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:04,041 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 19:39:04,119 INFO L227 lantSequenceWeakener]: Weakened 96 states. On average, predicates are now at 78.51% of their original sizes. [2018-12-09 19:39:04,119 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 19:39:04,526 INFO L418 sIntCurrentIteration]: We unified 161 AI predicates to 161 [2018-12-09 19:39:04,526 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 19:39:04,526 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:39:04,526 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [42] imperfect sequences [5] total 45 [2018-12-09 19:39:04,526 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:04,527 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-12-09 19:39:04,527 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-12-09 19:39:04,527 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=1510, Unknown=0, NotChecked=0, Total=1722 [2018-12-09 19:39:04,527 INFO L87 Difference]: Start difference. First operand 29546 states and 41447 transitions. Second operand 42 states. [2018-12-09 19:39:13,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:13,252 INFO L93 Difference]: Finished difference Result 56383 states and 79243 transitions. [2018-12-09 19:39:13,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-12-09 19:39:13,252 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 162 [2018-12-09 19:39:13,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:13,338 INFO L225 Difference]: With dead ends: 56383 [2018-12-09 19:39:13,338 INFO L226 Difference]: Without dead ends: 30096 [2018-12-09 19:39:13,412 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 196 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1822 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=815, Invalid=5037, Unknown=0, NotChecked=0, Total=5852 [2018-12-09 19:39:13,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30096 states. [2018-12-09 19:39:15,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30096 to 29888. [2018-12-09 19:39:15,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29888 states. [2018-12-09 19:39:15,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29888 states to 29888 states and 41687 transitions. [2018-12-09 19:39:15,774 INFO L78 Accepts]: Start accepts. Automaton has 29888 states and 41687 transitions. Word has length 162 [2018-12-09 19:39:15,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:15,775 INFO L480 AbstractCegarLoop]: Abstraction has 29888 states and 41687 transitions. [2018-12-09 19:39:15,775 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-12-09 19:39:15,775 INFO L276 IsEmpty]: Start isEmpty. Operand 29888 states and 41687 transitions. [2018-12-09 19:39:15,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-09 19:39:15,822 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:15,822 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:15,822 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:15,822 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:15,822 INFO L82 PathProgramCache]: Analyzing trace with hash -1085250615, now seen corresponding path program 1 times [2018-12-09 19:39:15,822 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:15,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:15,823 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:15,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:15,823 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:15,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:15,856 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 40 proven. 9 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 19:39:15,856 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:15,856 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:15,856 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 163 with the following transitions: [2018-12-09 19:39:15,857 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [92], [94], [99], [104], [109], [113], [116], [122], [126], [129], [132], [139], [142], [145], [148], [152], [155], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [502], [508], [514], [520], [523], [544], [549], [556], [561], [568], [571], [580], [586], [594], [598], [604], [610], [616], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:15,858 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:15,858 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:15,895 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 19:39:15,895 INFO L272 AbstractInterpreter]: Visited 71 different actions 96 times. Merged at 7 different actions 12 times. Never widened. Performed 1569 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1569 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 68 variables. [2018-12-09 19:39:15,897 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:15,897 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 19:39:15,962 INFO L227 lantSequenceWeakener]: Weakened 96 states. On average, predicates are now at 77.9% of their original sizes. [2018-12-09 19:39:15,962 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 19:39:16,271 INFO L418 sIntCurrentIteration]: We unified 161 AI predicates to 161 [2018-12-09 19:39:16,271 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 19:39:16,271 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:39:16,271 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [38] imperfect sequences [5] total 41 [2018-12-09 19:39:16,271 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:16,271 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-09 19:39:16,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-09 19:39:16,272 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=162, Invalid=1244, Unknown=0, NotChecked=0, Total=1406 [2018-12-09 19:39:16,272 INFO L87 Difference]: Start difference. First operand 29888 states and 41687 transitions. Second operand 38 states. [2018-12-09 19:39:21,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:21,791 INFO L93 Difference]: Finished difference Result 51443 states and 72427 transitions. [2018-12-09 19:39:21,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-09 19:39:21,791 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 162 [2018-12-09 19:39:21,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:21,874 INFO L225 Difference]: With dead ends: 51443 [2018-12-09 19:39:21,875 INFO L226 Difference]: Without dead ends: 29610 [2018-12-09 19:39:21,951 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 180 GetRequests, 125 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 926 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=419, Invalid=2773, Unknown=0, NotChecked=0, Total=3192 [2018-12-09 19:39:21,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29610 states. [2018-12-09 19:39:24,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29610 to 29546. [2018-12-09 19:39:24,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29546 states. [2018-12-09 19:39:24,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29546 states to 29546 states and 41187 transitions. [2018-12-09 19:39:24,311 INFO L78 Accepts]: Start accepts. Automaton has 29546 states and 41187 transitions. Word has length 162 [2018-12-09 19:39:24,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:24,311 INFO L480 AbstractCegarLoop]: Abstraction has 29546 states and 41187 transitions. [2018-12-09 19:39:24,311 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-09 19:39:24,311 INFO L276 IsEmpty]: Start isEmpty. Operand 29546 states and 41187 transitions. [2018-12-09 19:39:24,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 164 [2018-12-09 19:39:24,346 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:24,346 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:24,346 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:24,346 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:24,347 INFO L82 PathProgramCache]: Analyzing trace with hash 868301488, now seen corresponding path program 1 times [2018-12-09 19:39:24,347 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:24,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:24,347 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:24,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:24,347 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:24,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:24,385 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 19:39:24,386 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:24,386 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:24,386 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 164 with the following transitions: [2018-12-09 19:39:24,386 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [119], [126], [129], [132], [135], [139], [142], [145], [148], [152], [155], [158], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [502], [508], [514], [520], [523], [544], [549], [556], [561], [568], [571], [580], [586], [594], [598], [604], [610], [618], [621], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:24,387 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:24,387 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:24,518 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:39:24,518 INFO L272 AbstractInterpreter]: Visited 92 different actions 326 times. Merged at 23 different actions 79 times. Never widened. Performed 5348 root evaluator evaluations with a maximum evaluation depth of 3. Performed 5348 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 25 fixpoints after 10 different actions. Largest state had 68 variables. [2018-12-09 19:39:24,526 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:24,526 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:39:24,526 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:24,527 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:39:24,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:24,533 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:39:24,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:24,605 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:39:24,620 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 50 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 19:39:24,620 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:39:24,646 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 49 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-09 19:39:24,661 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:39:24,661 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [5] total 6 [2018-12-09 19:39:24,661 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:24,662 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:39:24,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:39:24,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:39:24,662 INFO L87 Difference]: Start difference. First operand 29546 states and 41187 transitions. Second operand 3 states. [2018-12-09 19:39:26,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:26,025 INFO L93 Difference]: Finished difference Result 45113 states and 63906 transitions. [2018-12-09 19:39:26,025 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:39:26,026 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 163 [2018-12-09 19:39:26,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:26,073 INFO L225 Difference]: With dead ends: 45113 [2018-12-09 19:39:26,073 INFO L226 Difference]: Without dead ends: 17902 [2018-12-09 19:39:26,165 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 328 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:39:26,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17902 states. [2018-12-09 19:39:27,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17902 to 17777. [2018-12-09 19:39:27,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17777 states. [2018-12-09 19:39:27,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17777 states to 17777 states and 23887 transitions. [2018-12-09 19:39:27,421 INFO L78 Accepts]: Start accepts. Automaton has 17777 states and 23887 transitions. Word has length 163 [2018-12-09 19:39:27,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:27,422 INFO L480 AbstractCegarLoop]: Abstraction has 17777 states and 23887 transitions. [2018-12-09 19:39:27,422 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:39:27,422 INFO L276 IsEmpty]: Start isEmpty. Operand 17777 states and 23887 transitions. [2018-12-09 19:39:27,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-09 19:39:27,437 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:27,437 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:27,438 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:27,438 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:27,438 INFO L82 PathProgramCache]: Analyzing trace with hash -111587477, now seen corresponding path program 1 times [2018-12-09 19:39:27,438 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:27,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:27,439 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:27,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:27,439 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:27,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:27,471 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 19:39:27,472 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:27,472 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:27,472 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 163 with the following transitions: [2018-12-09 19:39:27,472 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [119], [126], [129], [132], [135], [139], [142], [145], [148], [152], [155], [158], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [502], [508], [514], [520], [523], [544], [549], [556], [561], [568], [573], [580], [586], [594], [598], [604], [610], [616], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:27,474 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:27,474 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:27,581 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:39:27,582 INFO L272 AbstractInterpreter]: Visited 92 different actions 275 times. Merged at 23 different actions 62 times. Never widened. Performed 3960 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3960 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 22 fixpoints after 10 different actions. Largest state had 68 variables. [2018-12-09 19:39:27,583 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:27,583 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:39:27,583 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:27,583 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:39:27,589 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:27,589 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:39:27,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:27,649 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:39:27,660 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:39:27,660 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:39:27,683 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-12-09 19:39:27,698 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:39:27,698 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [5] total 6 [2018-12-09 19:39:27,698 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:27,699 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:39:27,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:39:27,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:39:27,699 INFO L87 Difference]: Start difference. First operand 17777 states and 23887 transitions. Second operand 3 states. [2018-12-09 19:39:28,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:28,770 INFO L93 Difference]: Finished difference Result 25898 states and 34635 transitions. [2018-12-09 19:39:28,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:39:28,770 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 162 [2018-12-09 19:39:28,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:28,798 INFO L225 Difference]: With dead ends: 25898 [2018-12-09 19:39:28,799 INFO L226 Difference]: Without dead ends: 15202 [2018-12-09 19:39:28,829 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 330 GetRequests, 326 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:39:28,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15202 states. [2018-12-09 19:39:29,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15202 to 14948. [2018-12-09 19:39:29,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14948 states. [2018-12-09 19:39:29,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14948 states to 14948 states and 19304 transitions. [2018-12-09 19:39:29,901 INFO L78 Accepts]: Start accepts. Automaton has 14948 states and 19304 transitions. Word has length 162 [2018-12-09 19:39:29,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:29,901 INFO L480 AbstractCegarLoop]: Abstraction has 14948 states and 19304 transitions. [2018-12-09 19:39:29,901 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:39:29,901 INFO L276 IsEmpty]: Start isEmpty. Operand 14948 states and 19304 transitions. [2018-12-09 19:39:29,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-12-09 19:39:29,911 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:29,911 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:29,911 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:29,912 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:29,912 INFO L82 PathProgramCache]: Analyzing trace with hash -1936365336, now seen corresponding path program 1 times [2018-12-09 19:39:29,912 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:29,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:29,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:29,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:29,912 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:29,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:29,960 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 19:39:29,960 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:29,960 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:29,960 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 165 with the following transitions: [2018-12-09 19:39:29,960 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [119], [126], [129], [132], [135], [139], [142], [145], [148], [152], [155], [158], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [502], [508], [514], [520], [523], [544], [549], [556], [561], [568], [573], [580], [586], [594], [600], [604], [610], [618], [623], [626], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:29,961 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:29,961 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:30,109 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:39:30,109 INFO L272 AbstractInterpreter]: Visited 92 different actions 346 times. Merged at 23 different actions 85 times. Never widened. Performed 6215 root evaluator evaluations with a maximum evaluation depth of 3. Performed 6215 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 27 fixpoints after 10 different actions. Largest state had 68 variables. [2018-12-09 19:39:30,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:30,110 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:39:30,110 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:30,110 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:39:30,116 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:30,116 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:39:30,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:30,182 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:39:30,199 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 49 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-09 19:39:30,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:39:30,230 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 19:39:30,245 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:39:30,246 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [5] total 6 [2018-12-09 19:39:30,246 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:30,246 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:39:30,246 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:39:30,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:39:30,246 INFO L87 Difference]: Start difference. First operand 14948 states and 19304 transitions. Second operand 3 states. [2018-12-09 19:39:30,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:30,798 INFO L93 Difference]: Finished difference Result 21358 states and 27329 transitions. [2018-12-09 19:39:30,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:39:30,798 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 164 [2018-12-09 19:39:30,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:30,809 INFO L225 Difference]: With dead ends: 21358 [2018-12-09 19:39:30,809 INFO L226 Difference]: Without dead ends: 7527 [2018-12-09 19:39:30,832 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 334 GetRequests, 330 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 19:39:30,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7527 states. [2018-12-09 19:39:31,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7527 to 7206. [2018-12-09 19:39:31,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7206 states. [2018-12-09 19:39:31,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7206 states to 7206 states and 8597 transitions. [2018-12-09 19:39:31,321 INFO L78 Accepts]: Start accepts. Automaton has 7206 states and 8597 transitions. Word has length 164 [2018-12-09 19:39:31,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:31,321 INFO L480 AbstractCegarLoop]: Abstraction has 7206 states and 8597 transitions. [2018-12-09 19:39:31,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:39:31,321 INFO L276 IsEmpty]: Start isEmpty. Operand 7206 states and 8597 transitions. [2018-12-09 19:39:31,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-09 19:39:31,325 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:31,325 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:31,325 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:31,325 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:31,325 INFO L82 PathProgramCache]: Analyzing trace with hash 332313197, now seen corresponding path program 1 times [2018-12-09 19:39:31,325 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:31,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:31,326 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:31,326 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:31,326 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:31,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:31,363 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 19:39:31,363 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:31,363 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:31,363 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 163 with the following transitions: [2018-12-09 19:39:31,364 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [119], [126], [129], [132], [135], [139], [142], [145], [148], [152], [155], [158], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [502], [508], [514], [520], [523], [544], [549], [556], [561], [568], [573], [580], [586], [594], [600], [604], [610], [616], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:31,365 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:31,365 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:31,488 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:39:31,488 INFO L272 AbstractInterpreter]: Visited 92 different actions 305 times. Merged at 23 different actions 74 times. Never widened. Performed 4807 root evaluator evaluations with a maximum evaluation depth of 3. Performed 4807 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 24 fixpoints after 9 different actions. Largest state had 68 variables. [2018-12-09 19:39:31,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:31,490 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:39:31,490 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:31,490 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:39:31,530 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:31,530 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:39:31,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:31,591 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:39:31,618 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:39:31,618 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:39:31,671 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-12-09 19:39:31,686 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-09 19:39:31,686 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4, 4] imperfect sequences [5] total 9 [2018-12-09 19:39:31,686 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:31,687 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:39:31,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:39:31,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:39:31,687 INFO L87 Difference]: Start difference. First operand 7206 states and 8597 transitions. Second operand 4 states. [2018-12-09 19:39:32,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:32,113 INFO L93 Difference]: Finished difference Result 10603 states and 12735 transitions. [2018-12-09 19:39:32,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:39:32,114 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 162 [2018-12-09 19:39:32,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:32,122 INFO L225 Difference]: With dead ends: 10603 [2018-12-09 19:39:32,123 INFO L226 Difference]: Without dead ends: 5377 [2018-12-09 19:39:32,128 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 324 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-12-09 19:39:32,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5377 states. [2018-12-09 19:39:32,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5377 to 4585. [2018-12-09 19:39:32,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4585 states. [2018-12-09 19:39:32,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4585 states to 4585 states and 5456 transitions. [2018-12-09 19:39:32,442 INFO L78 Accepts]: Start accepts. Automaton has 4585 states and 5456 transitions. Word has length 162 [2018-12-09 19:39:32,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:32,442 INFO L480 AbstractCegarLoop]: Abstraction has 4585 states and 5456 transitions. [2018-12-09 19:39:32,442 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:39:32,442 INFO L276 IsEmpty]: Start isEmpty. Operand 4585 states and 5456 transitions. [2018-12-09 19:39:32,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2018-12-09 19:39:32,444 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:32,445 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:32,445 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:32,445 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:32,445 INFO L82 PathProgramCache]: Analyzing trace with hash 2076745615, now seen corresponding path program 1 times [2018-12-09 19:39:32,445 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:32,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:32,445 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:32,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:32,445 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:32,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:32,488 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 40 proven. 9 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-09 19:39:32,488 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:32,488 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:32,488 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 168 with the following transitions: [2018-12-09 19:39:32,488 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [92], [94], [99], [104], [109], [113], [116], [122], [126], [129], [132], [139], [142], [145], [148], [152], [155], [158], [161], [165], [168], [174], [179], [184], [187], [198], [200], [204], [215], [217], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [504], [508], [514], [520], [523], [544], [549], [556], [561], [568], [573], [580], [588], [594], [600], [604], [610], [616], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:32,489 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:32,489 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:32,545 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:39:32,545 INFO L272 AbstractInterpreter]: Visited 82 different actions 143 times. Merged at 19 different actions 28 times. Never widened. Performed 2108 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2108 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 9 fixpoints after 6 different actions. Largest state had 68 variables. [2018-12-09 19:39:32,547 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:32,547 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:39:32,547 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:32,547 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:39:32,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:32,555 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:39:32,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:32,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:39:32,656 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 19:39:32,656 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:39:32,728 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 49 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-09 19:39:32,743 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 19:39:32,743 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2018-12-09 19:39:32,743 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:32,744 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:39:32,744 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:39:32,744 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:39:32,744 INFO L87 Difference]: Start difference. First operand 4585 states and 5456 transitions. Second operand 5 states. [2018-12-09 19:39:33,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:33,120 INFO L93 Difference]: Finished difference Result 8292 states and 9839 transitions. [2018-12-09 19:39:33,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:39:33,120 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 167 [2018-12-09 19:39:33,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:33,126 INFO L225 Difference]: With dead ends: 8292 [2018-12-09 19:39:33,126 INFO L226 Difference]: Without dead ends: 4293 [2018-12-09 19:39:33,130 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 340 GetRequests, 329 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:39:33,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4293 states. [2018-12-09 19:39:33,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4293 to 4094. [2018-12-09 19:39:33,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4094 states. [2018-12-09 19:39:33,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4094 states to 4094 states and 4813 transitions. [2018-12-09 19:39:33,401 INFO L78 Accepts]: Start accepts. Automaton has 4094 states and 4813 transitions. Word has length 167 [2018-12-09 19:39:33,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:33,402 INFO L480 AbstractCegarLoop]: Abstraction has 4094 states and 4813 transitions. [2018-12-09 19:39:33,402 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:39:33,402 INFO L276 IsEmpty]: Start isEmpty. Operand 4094 states and 4813 transitions. [2018-12-09 19:39:33,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-09 19:39:33,403 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:33,403 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:33,403 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:33,404 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:33,404 INFO L82 PathProgramCache]: Analyzing trace with hash 502944881, now seen corresponding path program 1 times [2018-12-09 19:39:33,404 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:33,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:33,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:33,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:33,404 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:33,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:33,434 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 41 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 19:39:33,435 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:33,435 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:33,435 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 163 with the following transitions: [2018-12-09 19:39:33,435 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [119], [126], [129], [132], [135], [139], [142], [145], [148], [152], [155], [158], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [504], [508], [514], [520], [523], [544], [549], [556], [561], [568], [573], [580], [588], [594], [600], [604], [610], [616], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:33,436 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:33,436 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:33,557 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:39:33,557 INFO L272 AbstractInterpreter]: Visited 92 different actions 295 times. Merged at 23 different actions 68 times. Never widened. Performed 4698 root evaluator evaluations with a maximum evaluation depth of 3. Performed 4698 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 26 fixpoints after 11 different actions. Largest state had 68 variables. [2018-12-09 19:39:33,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:33,558 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:39:33,558 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:33,558 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:39:33,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:33,564 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:39:33,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:33,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:39:33,656 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 19:39:33,657 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:39:33,732 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 19:39:33,746 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 19:39:33,747 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2018-12-09 19:39:33,747 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:33,747 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:39:33,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:39:33,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:39:33,747 INFO L87 Difference]: Start difference. First operand 4094 states and 4813 transitions. Second operand 5 states. [2018-12-09 19:39:34,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:34,132 INFO L93 Difference]: Finished difference Result 7273 states and 8590 transitions. [2018-12-09 19:39:34,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:39:34,133 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 162 [2018-12-09 19:39:34,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:34,138 INFO L225 Difference]: With dead ends: 7273 [2018-12-09 19:39:34,138 INFO L226 Difference]: Without dead ends: 3929 [2018-12-09 19:39:34,142 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 330 GetRequests, 319 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:39:34,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3929 states. [2018-12-09 19:39:34,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3929 to 3548. [2018-12-09 19:39:34,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3548 states. [2018-12-09 19:39:34,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3548 states to 3548 states and 4173 transitions. [2018-12-09 19:39:34,396 INFO L78 Accepts]: Start accepts. Automaton has 3548 states and 4173 transitions. Word has length 162 [2018-12-09 19:39:34,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:34,396 INFO L480 AbstractCegarLoop]: Abstraction has 3548 states and 4173 transitions. [2018-12-09 19:39:34,396 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:39:34,396 INFO L276 IsEmpty]: Start isEmpty. Operand 3548 states and 4173 transitions. [2018-12-09 19:39:34,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-12-09 19:39:34,398 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:34,398 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:34,398 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:34,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:34,398 INFO L82 PathProgramCache]: Analyzing trace with hash -1401112260, now seen corresponding path program 1 times [2018-12-09 19:39:34,398 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:34,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:34,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:34,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:34,399 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:34,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:34,426 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 42 proven. 8 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:39:34,426 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:34,426 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 19:39:34,426 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 175 with the following transitions: [2018-12-09 19:39:34,426 INFO L205 CegarAbsIntRunner]: [4], [7], [18], [20], [24], [27], [30], [37], [44], [45], [46], [47], [58], [62], [65], [72], [73], [74], [83], [87], [89], [94], [99], [104], [109], [113], [116], [119], [126], [129], [132], [135], [139], [142], [145], [152], [155], [161], [165], [168], [174], [179], [182], [198], [200], [224], [225], [228], [230], [233], [235], [238], [242], [251], [253], [256], [259], [268], [271], [278], [280], [285], [291], [292], [304], [308], [314], [320], [326], [334], [340], [346], [352], [358], [364], [376], [388], [400], [412], [424], [430], [436], [442], [448], [454], [460], [469], [471], [473], [476], [479], [483], [487], [492], [498], [504], [508], [514], [520], [523], [544], [549], [556], [561], [568], [573], [580], [588], [594], [600], [604], [610], [616], [649], [651], [654], [665], [667], [669], [673], [674], [678], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [693], [694], [695], [696], [697], [699] [2018-12-09 19:39:34,427 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 19:39:34,427 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 19:39:34,588 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 19:39:34,588 INFO L272 AbstractInterpreter]: Visited 90 different actions 409 times. Merged at 25 different actions 118 times. Widened at 1 different actions 1 times. Performed 6314 root evaluator evaluations with a maximum evaluation depth of 3. Performed 6314 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 30 fixpoints after 9 different actions. Largest state had 68 variables. [2018-12-09 19:39:34,590 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:34,590 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 19:39:34,590 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 19:39:34,590 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 19:39:34,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:34,596 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 19:39:34,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:34,659 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 19:39:34,689 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 43 proven. 8 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-12-09 19:39:34,689 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 19:39:34,759 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 50 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 19:39:34,774 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 19:39:34,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2018-12-09 19:39:34,774 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:34,774 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 19:39:34,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 19:39:34,774 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:39:34,774 INFO L87 Difference]: Start difference. First operand 3548 states and 4173 transitions. Second operand 5 states. [2018-12-09 19:39:34,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:34,999 INFO L93 Difference]: Finished difference Result 4645 states and 5414 transitions. [2018-12-09 19:39:34,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 19:39:34,999 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 174 [2018-12-09 19:39:34,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:35,002 INFO L225 Difference]: With dead ends: 4645 [2018-12-09 19:39:35,002 INFO L226 Difference]: Without dead ends: 1497 [2018-12-09 19:39:35,004 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 354 GetRequests, 343 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 19:39:35,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1497 states. [2018-12-09 19:39:35,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1497 to 1449. [2018-12-09 19:39:35,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1449 states. [2018-12-09 19:39:35,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1449 states to 1449 states and 1640 transitions. [2018-12-09 19:39:35,113 INFO L78 Accepts]: Start accepts. Automaton has 1449 states and 1640 transitions. Word has length 174 [2018-12-09 19:39:35,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:35,113 INFO L480 AbstractCegarLoop]: Abstraction has 1449 states and 1640 transitions. [2018-12-09 19:39:35,113 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 19:39:35,114 INFO L276 IsEmpty]: Start isEmpty. Operand 1449 states and 1640 transitions. [2018-12-09 19:39:35,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2018-12-09 19:39:35,114 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:35,115 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:35,115 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:35,115 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:35,115 INFO L82 PathProgramCache]: Analyzing trace with hash 1446702025, now seen corresponding path program 1 times [2018-12-09 19:39:35,115 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:35,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:35,115 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:35,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:35,115 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:35,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:35,151 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 92 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-12-09 19:39:35,151 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:39:35,151 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 19:39:35,151 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:35,151 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 19:39:35,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 19:39:35,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:39:35,152 INFO L87 Difference]: Start difference. First operand 1449 states and 1640 transitions. Second operand 4 states. [2018-12-09 19:39:35,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:35,295 INFO L93 Difference]: Finished difference Result 2106 states and 2400 transitions. [2018-12-09 19:39:35,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 19:39:35,295 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 230 [2018-12-09 19:39:35,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:35,297 INFO L225 Difference]: With dead ends: 2106 [2018-12-09 19:39:35,297 INFO L226 Difference]: Without dead ends: 1368 [2018-12-09 19:39:35,298 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 19:39:35,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1368 states. [2018-12-09 19:39:35,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1368 to 1368. [2018-12-09 19:39:35,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1368 states. [2018-12-09 19:39:35,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1368 states to 1368 states and 1530 transitions. [2018-12-09 19:39:35,430 INFO L78 Accepts]: Start accepts. Automaton has 1368 states and 1530 transitions. Word has length 230 [2018-12-09 19:39:35,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:35,430 INFO L480 AbstractCegarLoop]: Abstraction has 1368 states and 1530 transitions. [2018-12-09 19:39:35,430 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 19:39:35,430 INFO L276 IsEmpty]: Start isEmpty. Operand 1368 states and 1530 transitions. [2018-12-09 19:39:35,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-12-09 19:39:35,431 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:35,431 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:35,431 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:35,431 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:35,431 INFO L82 PathProgramCache]: Analyzing trace with hash -557378392, now seen corresponding path program 1 times [2018-12-09 19:39:35,431 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:35,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:35,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:35,432 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:35,432 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:35,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 19:39:35,461 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 85 proven. 0 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2018-12-09 19:39:35,461 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 19:39:35,461 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 19:39:35,461 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 19:39:35,462 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 19:39:35,462 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 19:39:35,462 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:39:35,462 INFO L87 Difference]: Start difference. First operand 1368 states and 1530 transitions. Second operand 3 states. [2018-12-09 19:39:35,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 19:39:35,567 INFO L93 Difference]: Finished difference Result 1997 states and 2248 transitions. [2018-12-09 19:39:35,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 19:39:35,567 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 233 [2018-12-09 19:39:35,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 19:39:35,569 INFO L225 Difference]: With dead ends: 1997 [2018-12-09 19:39:35,569 INFO L226 Difference]: Without dead ends: 1348 [2018-12-09 19:39:35,570 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 19:39:35,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1348 states. [2018-12-09 19:39:35,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1348 to 1322. [2018-12-09 19:39:35,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1322 states. [2018-12-09 19:39:35,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1322 states to 1322 states and 1468 transitions. [2018-12-09 19:39:35,670 INFO L78 Accepts]: Start accepts. Automaton has 1322 states and 1468 transitions. Word has length 233 [2018-12-09 19:39:35,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 19:39:35,670 INFO L480 AbstractCegarLoop]: Abstraction has 1322 states and 1468 transitions. [2018-12-09 19:39:35,670 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 19:39:35,670 INFO L276 IsEmpty]: Start isEmpty. Operand 1322 states and 1468 transitions. [2018-12-09 19:39:35,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-12-09 19:39:35,671 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 19:39:35,671 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 19:39:35,671 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 19:39:35,672 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 19:39:35,672 INFO L82 PathProgramCache]: Analyzing trace with hash 1383203622, now seen corresponding path program 1 times [2018-12-09 19:39:35,672 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 19:39:35,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:35,672 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 19:39:35,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 19:39:35,672 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 19:39:35,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 19:39:35,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 19:39:35,753 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 19:39:35,857 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 07:39:35 BoogieIcfgContainer [2018-12-09 19:39:35,857 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 19:39:35,857 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 19:39:35,857 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 19:39:35,857 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 19:39:35,858 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 07:38:04" (3/4) ... [2018-12-09 19:39:35,859 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-09 19:39:35,960 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_87d954a3-c1ca-425d-b60b-ce3e5b018db7/bin-2019/utaipan/witness.graphml [2018-12-09 19:39:35,961 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 19:39:35,961 INFO L168 Benchmark]: Toolchain (without parser) took 92052.22 ms. Allocated memory was 1.0 GB in the beginning and 4.7 GB in the end (delta: 3.7 GB). Free memory was 948.6 MB in the beginning and 3.8 GB in the end (delta: -2.9 GB). Peak memory consumption was 832.9 MB. Max. memory is 11.5 GB. [2018-12-09 19:39:35,962 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 19:39:35,962 INFO L168 Benchmark]: CACSL2BoogieTranslator took 199.49 ms. Allocated memory is still 1.0 GB. Free memory was 948.6 MB in the beginning and 932.5 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-09 19:39:35,962 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 126.9 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -189.3 MB). Peak memory consumption was 13.1 MB. Max. memory is 11.5 GB. [2018-12-09 19:39:35,962 INFO L168 Benchmark]: Boogie Preprocessor took 22.25 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 19:39:35,962 INFO L168 Benchmark]: RCFGBuilder took 315.89 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.1 MB). Peak memory consumption was 47.1 MB. Max. memory is 11.5 GB. [2018-12-09 19:39:35,963 INFO L168 Benchmark]: TraceAbstraction took 91363.07 ms. Allocated memory was 1.2 GB in the beginning and 4.7 GB in the end (delta: 3.6 GB). Free memory was 1.1 GB in the beginning and 3.9 GB in the end (delta: -2.8 GB). Peak memory consumption was 764.7 MB. Max. memory is 11.5 GB. [2018-12-09 19:39:35,963 INFO L168 Benchmark]: Witness Printer took 103.79 ms. Allocated memory is still 4.7 GB. Free memory was 3.9 GB in the beginning and 3.8 GB in the end (delta: 67.5 MB). Peak memory consumption was 67.5 MB. Max. memory is 11.5 GB. [2018-12-09 19:39:35,964 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 199.49 ms. Allocated memory is still 1.0 GB. Free memory was 948.6 MB in the beginning and 932.5 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 126.9 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -189.3 MB). Peak memory consumption was 13.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 22.25 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 315.89 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.1 MB). Peak memory consumption was 47.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 91363.07 ms. Allocated memory was 1.2 GB in the beginning and 4.7 GB in the end (delta: 3.6 GB). Free memory was 1.1 GB in the beginning and 3.9 GB in the end (delta: -2.8 GB). Peak memory consumption was 764.7 MB. Max. memory is 11.5 GB. * Witness Printer took 103.79 ms. Allocated memory is still 4.7 GB. Free memory was 3.9 GB in the beginning and 3.8 GB in the end (delta: 67.5 MB). Peak memory consumption was 67.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [\old(c)=17, \old(c1_i)=4, \old(c1_pc)=29, \old(c1_st)=24, \old(c2_i)=14, \old(c2_pc)=28, \old(c2_st)=25, \old(c_req_up)=30, \old(c_t)=20, \old(d)=23, \old(data)=18, \old(e_c)=11, \old(e_e)=31, \old(e_f)=21, \old(e_g)=10, \old(e_p_in)=8, \old(e_wl)=13, \old(p_in)=15, \old(p_out)=9, \old(processed)=16, \old(r_i)=26, \old(r_st)=7, \old(t_b)=12, \old(wb_i)=5, \old(wb_pc)=19, \old(wb_st)=3, \old(wl_i)=27, \old(wl_pc)=22, \old(wl_st)=6, c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L679] int __retres1 ; [L683] e_wl = 2 [L684] e_c = e_wl [L685] e_g = e_c [L686] e_f = e_g [L687] e_e = e_f [L688] wl_pc = 0 [L689] c1_pc = 0 [L690] c2_pc = 0 [L691] wb_pc = 0 [L692] wb_i = 1 [L693] c2_i = wb_i [L694] c1_i = c2_i [L695] wl_i = c1_i [L696] r_i = 0 [L697] c_req_up = 0 [L698] d = 0 [L699] c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=0, \old(e_e)=0, \old(e_f)=0, \old(e_g)=0, \old(e_wl)=0, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L700] CALL start_simulation() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L390] int kernel_st ; [L393] kernel_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L394] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L405] COND TRUE (int )wl_i == 1 [L406] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L410] COND TRUE (int )c1_i == 1 [L411] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )c2_i == 1 [L416] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )wb_i == 1 [L421] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND FALSE !((int )r_i == 1) [L428] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L463] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )c1_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L482] COND FALSE !((int )c2_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L491] COND FALSE !((int )wb_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L500] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L314] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L329] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L127] COND TRUE (int )c1_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L138] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L329] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L344] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L172] COND TRUE (int )c2_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L183] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L344] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L359] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L217] COND TRUE (int )wb_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L228] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L359] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L535] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L537] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L538] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L565] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L570] COND TRUE (int )e_wl == 0 [L571] e_wl = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L575] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L576] COND TRUE (int )e_wl == 1 [L577] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L593] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L594] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L602] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L603] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L611] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L612] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L620] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L630] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L635] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L640] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L645] COND TRUE (int )e_wl == 1 [L646] e_wl = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L650] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L314] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L329] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L127] COND FALSE !((int )c1_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L130] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L145] COND TRUE ! processed [L146] data += 1 [L147] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L148] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L149] COND TRUE (int )e_g == 1 [L150] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L157] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L138] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L329] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L344] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L172] COND FALSE !((int )c2_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L175] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L190] COND TRUE ! processed [L191] data += 1 [L192] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L193] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L194] COND TRUE (int )e_g == 1 [L195] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L183] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L344] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L359] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L217] COND FALSE !((int )wb_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L220] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L235] c_t = data [L236] c_req_up = 1 [L237] processed = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L228] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L359] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L535] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L537] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L538] COND TRUE (int )c_req_up == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L539] COND TRUE c != c_t [L540] c = c_t [L541] e_c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] c_req_up = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L565] COND TRUE (int )e_c == 0 [L566] e_c = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L570] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L575] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L583] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L593] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L594] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L602] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L603] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L611] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L612] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L620] COND TRUE (int )e_c == 1 [L621] r_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L630] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L635] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L640] COND TRUE (int )e_c == 1 [L641] e_c = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L645] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L650] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L653] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L656] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L337] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L352] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND TRUE (int )r_st == 0 [L369] tmp___3 = __VERIFIER_nondet_int() [L371] COND TRUE \read(tmp___3) [L373] r_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L374] CALL read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L249] d = c [L250] e_e = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L251] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L259] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L260] COND TRUE (int )e_e == 1 [L261] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L269] e_e = 2 [L270] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L374] RET read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L113] CALL error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 11 procedures, 158 locations, 1 error locations. UNSAFE Result, 91.3s OverallTime, 40 OverallIterations, 6 TraceHistogramMax, 60.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9772 SDtfs, 17615 SDslu, 22215 SDs, 0 SdLazy, 16309 SolverSat, 1711 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.6s Time, PredicateUnifierStatistics: 12 DeclaredPredicates, 3591 GetRequests, 3169 SyntacticMatches, 19 SemanticMatches, 403 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4639 ImplicationChecksByTransitivity, 3.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=29888occurred in iteration=29, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 1.6s AbstIntTime, 14 AbstIntIterations, 6 AbstIntStrong, 0.9920037373693199 AbsIntWeakeningRatio, 0.8345120226308345 AbsIntAvgWeakeningVarsNumRemoved, 28.087694483734087 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 23.6s AutomataMinimizationTime, 39 MinimizatonAttempts, 14813 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 6113 NumberOfCodeBlocks, 6113 NumberOfCodeBlocksAsserted, 48 NumberOfCheckSat, 7119 ConstructedInterpolants, 0 QuantifiedInterpolants, 1765758 SizeOfPredicates, 12 NumberOfNonLiveVariables, 8644 ConjunctsInSsa, 45 ConjunctsInUnsatCore, 55 InterpolantComputations, 38 PerfectInterpolantSequences, 2386/2519 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...